SY88303BL - Amplifier Microchip - Free user manual and instructions

USER MANUAL SY88303BL Microchip

3.3V, 3.2Gbps CML Limiting Post Amplifier with Wide Loss-of-Signal Detection Range

General Description

The SY88303BL low-power limiting post amplifiers are designed for use in fiber-optic receivers. These devices connect to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88303BL quantizes these signals and output CML-level waveforms.

The SY88303BL operates from a single +3.3V power supply, over temperatures ranging from -40°C to +85°C. With their wide bandwidth and high gain, signals with data rates up to 3.2Gbps, and as small as 10mV _PP , can be amplified to drive devices with CML/PECL inputs.

The device generates a loss-of-signal (LOS) open-collector TTL output. The LOS function is optimized to detect a wide input range, as shown in the typical operating characteristic curve on Page 6. A programmable loss-of-signal level-set pin (LOS _LVL ) sets the sensitivity of the input amplitude detection.

LOS asserts high if the input amplitude falls below the threshold sets by LOS_LVL and de-asserts low otherwise. The enable bar input (/EN) de-asserts the true output signal without removing the input signal. The LOS output can be fed back to the /EN input to maintain output stability under a loss-of-signal condition. Typically, 3.5dB LOS hysteresis is provided to prevent chattering.

Datasheet and support documentation can be found on Micrel's web site at: www.micrel.com.

Features

• Loss-of-signal detection circuit optimized to detect a wide input range
• Chatter-free Open-Collector TTL Loss-of-Signal (LOS) output
• Single 3.3V power supply
  • 155Mbps to 3.2Gbps operation
• Low-noise CML data outputs
• Programmable LOS level set (LOS _LVL )
  • Available in a tiny 10-pin EPAD-MSOP and 16-pin QFN package

Applications

• PON
• Gigabit Ethernet
  • 1X and 2X Fibre Channel
  • SONET/SDH: OC 3/12/24/48 – STM 1/4/8/16
  • High-gain line driver and line receiver

Markets

• FTTX
  • Optical transceivers
• Datacom/Telecom
• Low-gain TIA interface
• Long-reach FOM

Typical Application

VCC 4.75kΩ Jumper LOS /EN VCC GND From Transimpedance Amplifier 0.1μF DIN /DIN SY88303BL DOUT 0.1μF To /DOUT CDR VREF LOSLVL VCC 0.1μF VCC 5kΩ

Pin Configuration

/EN 1 DIN 2 /DIN 3 VREF 4 LOSLVL 5 10 VCC 9 DOUT 8 /DOUT 7 LOS 6 GND

10-Pin EPAD-MSOP (K10-2)

VCC /EN LOSLVL VCC 16 15 14 13 DIN 1 12 DOUT GND 2 11 GND GND 3 10 GND /DIN 4 9 /DOUT 5 6 7 8 VCC VREF LOS VCC

16-Pin QFN

Ordering Information

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY88303BLEY	K10-2	Industrial	303B with Pb-Free bar line indicator	Matte-SnPb-free
SY88303BLEYTR^(1)	K10-2	Industrial	303B with Pb-Free bar line indicator	Matte-SnPb-free
SY88303BLMG	QFN-16	Industrial	303B with Pb-Free bar line indicator	NiPdAuPb-free
SY88303BLMGTR^(1)	QFN-16	Industrial	303B with Pb-Free bar line indicator	NiPdAuPb-free

Note:
1. Tape and Reel.

Pin Description

Pin Number (MSOP)	Pin Number (QFN)	Pin Name	Type	Pin Function
1 15 /EN			TTL Input: Default is low.	Enable bar: De-asserts true data output when High.
2	1	DIN	Data Input	True data input with 50Ω termination to V_REF .
3	4	/DIN	Data Input	Complementary data input w50Ω termination to V_REF .
4 6 VREF				Reference Voltage: Placing a capacitor here to V_CC helps stabilize.
5 14 LOSLVL Input				Loss-of-Signal Level Set: A resistor from this pin to V_CC sets the threshold for the data input amplitude at which the LOS output will be asserted.
6 Exposed Pad	2, 3, 10, 11 Exposed Pad	GND	Ground	Device ground. Exposed pad must be connected to PCB ground plane.
7 7 LOS			Open Collector TTL Output	Loss-of-Signal: Asserts high when the data input amplitude falls below the threshold sets by LOS_VL . For proper operation, install an external 4.75kΩ pull-up resistor at this output.
8	9	/DOUT	CML Output	Complementary data output.
9	12	DOUT	CML Output	True data output.
10	5, 8, 13, 16	VCC	Power Supply	Positive power supply.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) 0V to +4.0V

Input Voltage (DIN, DIN) 0 to V_CC

Output Current (IOUT) Continuous....+50mA Surge....+100mA

/EN Voltage 0 to Vcc

V_REF Current -800 A to +500 A

LOS_LVL Voltage.... V_REF to V_CC

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) ......-65°C to +150°C

Operating Ratings ^(2)

Supply Voltage (Vcc)....+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Junction Temperature ( T_J )....-40°C to +125°C

Junction Thermal Resistance ^(3)

EPAD-MSOP

0 JA (Still-Air) 38°CW

JB 22°CW

QFN

θ JA (Still-Air) 61°CW

JB 38°CW

DC Electrical Characteristics

V_CC = 3.0V to 3.6V ; R_L = 50 to V_CC ; T_A = -40^ to +85^ ; typical values at V_CC = 3.3V , T_A = 25^ .

Symbol	Parameter	Condition	Min	Typ	Max	Units
I_CC	Power Supply Current	No output load		38	60	mA
V_LOSLVL	LOS_LVL Voltage		V_REF		V_CC	V
V_OH	CML Output HIGH Voltage		V_CC-0.020	V_CC-0.005	V_CC	V
V_OL	CML Output LOW Voltage		V_CC-0.475	V_CC-0.4	V_CC-0.350	V
V_OFFSET	Differential Output Offset				± 80	mV
V_REF	Reference Voltage		V_CC-1.48	V_CC-1.32	V_CC-1.16	V
Z_I	Single-Ended Input Impedance		40	50	60

TTL DC Electrical Characteristics

V_CC = 3.0V to 3.6V; T_A = -40^ to +85^.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	/EN Input HIGH Voltage		2.0			V
V_IL	/EN Input LOW Voltage				0.8	V
I_IH	/EN Input HIGH Current	V_IN = 2.7V V_IN = V_CC			20100	μAμA
I_IL	/EN Input LOW Current	V_IN = 0.5V	-300			μA
I_OH	LOS Output Leakage	V_OH = 3.6V			100	μA
V_OL	LOS Output LOW Level	I_OL = +4mA			0.5	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes the use of a 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device's most negative potential on the PCB.

AC Electrical Characteristics

V_CC = 3.0V to 3.6V ; R_L = 50 to V_CC ; T_A = -40^ to +85^ ; typical values at V_CC = 3.3V , T_A = +25^ .

Symbol	Parameter	Condition	Min	Typ	Max	Units
t_r, t_f Output Rise/Fall Time(20% to 80%)		Note 4		60	120	ps
t_JITTER Deterministic		Note 5		15		pS_PP
		Random	Note 6	5		pS_RMS
V_ID	Differential Input Voltage Swing	Figure 1	10		1800	mV_PP
V_OD	Differential Output Voltage Swing	V_ID ≥ 12mV_PP , Figure 1	700	800	950	mV_PP
T_OFF	LOS De-assert Time			2	10	μs
T_ON	LOS Assert Time			2	10	μs
LOS_DL	Low LOS De-assert Level	R = 15kΩ, Note 8		27		mV_PP
LOS_AL	Low LOS Assert Level	R = 15kΩ, Note 8		18		mV_PP
HYS_L	Low LOS Hysteresis	R = 15kΩ, Note 7		3.4		dB
LOS_DM	Medium LOS De-assert Level	R = 5kΩ, Note 8		53	80	mV_PP
LOS_AM	Medium LOS Assert Level	R = 5kΩ, Note 8	21	36		mV_PP
HYS_M	LOS Hysteresis	R = 5kΩ, Note 7	2	3.5	6	dB
LOS_DH	High LOS De-assert Level	R = 100Ω, Note 8		137	200	mV_PP
LOS_AH	High LOS Assert Level	R = 100Ω, Note 8	70	94		mV_PP
HYS_H	High LOS Hysteresis	R = 100Ω, Note 7	2	3.5	6	dB
B-3dB	3dB Bandwidth			2		GHz
A_V(Diff)	Differential Voltage Gain			39		dB
S_21	Single-ended Small-Signal Gain		26	33		dB

Notes:

1. Amplifier in limiting mode. Input is a 200MHz, 100mV _PP square wave.
2. Deterministic jitter measured using 3.2Gbps K28.5 pattern, V_ID = 10mV_PP
3. Random jitter measured using 3.2Gbps K28.7 pattern, V_ID = 10mV_PP .
4. This specification defines electrical hysteresis as 20log (LOS De-assert/LOS Assert). The ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2, depending upon the level of received optical power and ROSA characteristics. Based upon that ratio, the optical hysteresis corresponding to the electrical hysteresis range 2dB-6dB, shown in the AC characteristics table, will be 1dB-3dB Optical Hysteresis.
5. See "Typical Operating Characteristics" for a graph showing how to choose a particular R_LOSLVL for a particular LOS assert and its associated de-assert amplitude.

Typical Operating Characteristics

Functional Characteristics

Functional Block Diagram

graph TD
    DIN -->|50Ω| Lim["Limiting Amplifier"]
    DIN -->|50Ω| VREF
    DIN -->|50Ω| VCC
    DIN -->|50Ω| GND
    VREF --> LevelDetect
    VREF --> LevelDetect
    VCC --> LevelDetect
    GND --> LevelDetect
    LevelDetect --> OC-TTLBuffer
    OC-TTLBuffer --> LOS
    CMLBuffer --> DOUT
    TTLBuffer --> /DOUT
    TTLBuffer --> /EN
    LevelDetect --> LevelDetect
    2.8kΩ --> LevelDetect
    style DIN fill:#f9f,stroke:#333
    style VREF fill:#ccf,stroke:#333
    style VCC fill:#ccf,stroke:#333
    style GND fill:#ccf,stroke:#333
    style LOSLVL fill:#fff,stroke:#333
    style LOSLVL fill:#fff,stroke:#333
    style CMLBuffer fill:#cfc,stroke:#333
    style TTLBuffer fill:#cfc,stroke:#333
    style OC-TTLBuffer fill:#cfc,stroke:#333

Detailed Description

The SY88303BL low-power limiting post amplifiers operate from a single +3.3V power supply, over temperatures from -40^ to +85^ . Signals with data rates up to 3.2Gbps and as small as 10mV_PP can be amplified. Figure 1 shows the allowed input voltage swing. The SY88303BL generates a LOS output allowing feedback to /EN for output stability. LOS_LVL sets the sensitivity of the input amplitude detection.

Input Amplifier Buffer

Figure 2 shows a simplified schematic of the input stage. The high-sensitivity of the input amplifier allows signals as small as 10mVPP to be amplified. The input amplifier also allows input signals as large as 1800mVPP . Input signals below 12mVpp are linearly amplified with a typical 42dB differential voltage gain. Since it is a limiting amplifier, these devices output typically 800mVPP voltage-limited waveforms for input signals greater than 12mVPP . Applications requiring the SY88303BL to operate with strong signals should have the upstream TIA placed as close as possible to the devices' input pins. This ensures the best performance of the device.

Output Buffer

The SY88303BL CML output buffers are designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external 50Ω resistor to Vcc for each output pin provides this. Figure 3 shows a simplified schematic of the output stage.

Loss-of-Signal

The SY88303BL generates a chatter-free LOS open-collector TTL output, as shown in Figure 4. LOS is used to determine that the input amplitude is large enough to be considered a valid input. LOS asserts high if the input amplitude falls below the threshold sets by LOS_LVL and de-asserts low otherwise. LOS can be fed back to the enable bar (/EN) input to maintain output stability under a loss-of-signal condition. /EN de-asserts the true output signal without removing the input signals.

Loss-of-Signal Level Set

Programmable LOS level-set pin (LOS LVL ) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and LOS LVL set the voltage at LOS LVL . This voltage ranges from V_CC to V_REF . The external resistor creates a voltage divider between V_CC and V_REF , as shown in Figure 5.

Hysteresis

The SY88303BL typically provides 3.5dB LOS electrical hysteresis. By definition, a power ratio measured in dB is 10log (power ratio). Power is calculated as V^2_IN/R for an electrical signal. Hence, the same ratio can be stated as 20log (voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and therefore, the ratios change linearly. Thus, the optical hysteresis in dB is half the electrical hysteresis in dB given in the data sheet. Since the SY88303BL is an electrical device, this data sheet refers to hysteresis in electrical terms. With 3.5dB LOS hysteresis, a voltage factor of 1.5 is required to assert or de-assert LOS.

Figure 1. V_IS and V_ID

VCC VREF 50Ω 50Ω 0.1μF DIN 0.1μF /DIN AC-Coupling Capacitors VCC ESD STRUCTURE GND

Figure 2. Input Structure

VCC 50Ω 50Ω DOUT Z2 = 50Ω 0.1μF I/DOUT Z3 = 50Ω AC-Coupling Capacitors 16mA ESD STRUCTURE GND VCC 50Ω 50Ω

Figure 3. Output Structure

Pure electrical circuit lines without any symbols

Figure 4. LOS Output Structure

VCC RLOSLVL LOS LVL 2.8kΩ VREF

Figure 5. LOS_LVL Setting Circuit

Package Information

NOTES: 1. DIMENSIONS ARE IN MM (INCHES). 2. CONTROLLING DIMENSION: MM 3. DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS, EITHER OF WHICH SHALL NOT EXCEED 0.20 [0.008]

10-Pin EPAD-MSOP (K10-2)

Pin 1 Dot By Marking 3,000±0.050 3,000±0.050

TOP VIEW

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.550±0.050 Exp. DAP 0.400±0.050 1.550±0.050 Exp. DAP 0.230±0.050 0.500 Bsc 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

16-Pin QFN

Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane Heavy Copper Plane VEE VEE

PCB Thermal Consideration for 16-Pin QFN® Package (Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management, solder void has to be less than 50% of the epad area.

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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