SY88149CL - Amplifier Microchip - Free user manual and instructions

USER MANUAL SY88149CL Microchip

The SY88149CL is a high-sensitivity limiting post amplifier designed for use in fiber-optic receivers. These devices connect to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88149CL quantizes these signals and outputs PECL level waveforms.

The SY88149CL operates from a single +3.3V power supply, over temperatures ranging from -40°C to +85°C. With its wide bandwidth and high gain, signals with data rates up to 1.25Gbps, and as small as 5mV can be amplified to drive devices with PECL inputs.

The SY88149CL generates a high-gain signal-detect (SD) open-collector TTL output. The SD function has a high gain input stage for increased sensitivity. A programmable Signal Detect level set pin (SD) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SD _VL and de-asserts low otherwise. The enable input (EN) de-asserts the true output signal without removing the input signal. The SD output can be fed back to the EN input to maintain output stability under a loss-of-signal condition. Typically, 3.4dB SD hysteresis is provided to prevent chattering.

All support documentation can be found on Micrel's web site at: www.micrel.com.

Features

• Single 3.3V power supply
• Fast SD enable/disable time
  • 622Mbps to 1.25Gbps operation
• Low-noise PECL data outputs
• High-gain SD
• Chatter-free Open-Collector TTL signal detect (SD) output with internal 4.75kΩ pull-up resistor
• TTL EN input
• Programmable SD level set (SD _LVL )
  • Available in a tiny 10-pin MSOP package

Applications

• GE-PON/GPON/EPON
• Gigabit Ethernet
  • 1062Mbps Fibre Channel
  • OC-12/24 SONET/SDH
  • High-gain line driver and line receiver
• Low-gain TIA interface

Markets

• FTTH/FTTP
• Datacom/Telecom
  • Optical transceiver

Typical Application Circuit

From Transimpedance Amp. 0.1µF 0.1µF 50Ω 50Ω DIN /DIN GND SD EN VCC SY88149CL SDLVL VREF VCC 15kΩ 0.1µF 0.1µF DOUT → /DOUT → 130Ω 130Ω To CDR

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY88149CLKG	K10-1	Industrial	149C with Pb-Free bar line indicator	NiPdAu Pb-Free
SY88149CLKGTR^(1)	K10-1	Industrial	149C with Pb-Free bar line indicator	NiPdAu Pb-Free

Note:
1. Tape and Reel.

Pin Configuration

EN 1 DIN 2 /DIN 3 VREF 4 SDLVL 5 10 VCC 9 DCUT 8 /DOUT 7 SD 6 GND 10-Pin MSOP (K10-1)

Pin Description

Pin Number	Pin Name	Type	Pin Function
1	EN	TTL Input: Default is HIGH.	Enable: This input enables the outputs when it is HIGH. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open.
2	DIN	Data Input	True data input.
3	/DIN	Data Input	Complementary data input.
4	VREF		Reference voltage: Placing a capacitor here to V_CC helps stabilize SD_LVL .
5	SDLVL	Input	Signal Detect Level Set: a resistor from this pin to V_CC sets the threshold for the data input amplitude at which SD will be asserted.
6	GND	Ground	Device ground.
7	SD	Open-collector TTL output w/internal 4.75kΩ pull-up resistor	Signal-Detect asserts high when the data input amplitude rises above the threshold set by SD_LVL .
8	/DOUT	PECL Output	Complementary data output.
9	DOUT	PECL Output	True data output.
10	VCC	Power Supply	Positive power supply.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) 0V to +7.0V

Input Voltage (DIN, /DIN) 0 to _C

Output Current ( I_OUT )

Continuous....±50mA

Surge....±100mA

EN Voltage.... 0 to V _CC

V_REF Current....-800_A to +500_A

SD_LVL Voltage V_REF to V_CC

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_cc ) ....+3.0V to +3.6V

Ambient Temperature ( T_A ) -40^ to +85^

Junction Temperature (T _J )......-40°C to +125°C

Junction Thermal Resistance

MSOP ( _JA ) Still-air 113°C/W

DC Electrical Characteristics

V_CC = 3.0 to 3.6V; R_L = 50 to V_CC - 2V; T_A = -40^ to +85^, typical values at V_CC = 3.3V, T_A = 25^.

Symbol	Parameter	Condition	Min	Typ	Max	Units
I_CC	Power Supply Current	No output load		26	39	mA
SD_LVL	SD_LVL Voltage		V_REF		V_CC	V
V_OH	PECL Output HIGH Voltage		V_CC-1.085	V_CC-0.955	V_CC-0.880	V
V_OL	PECL Output LOW Voltage		V_CC-1.830	V_CC-1.705	V_CC-1.555	V
V_IHCMR	Common Mode Range		GND+2.0		V_CC	V
V_REF	Reference Voltage		V_CC-1.48	V_CC-1.32	V_CC-1.16	V

TTL DC Electrical Characteristics

V_CC = 3.0 to 3.6V; R_L = 50 to V_CC - 2V; T_A = -40^ to +85^, typical values at V_CC = 3.3V, T_A = 25^.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	EN Input HIGH Voltage		2.0			V
V_IL	EN Input LOW Voltage				0.8	V
I_IH	EN Input HIGH Current	V_IN = 2.7V V_IN = V_CC			20100	μAμA
I_IL	EN Input LOW Current	V_IN = 0.5V	-0.3			mA
V_OH	SD Output HIGH Level	V_CC ≥ 3.3V, I_OH-MAX < 160μA V_CC < 3.3V, I_OH-MAX < 160μA	2.42.0			VV
V_OL	SD Output LOW Level	I_OL = +2mA			0.5	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes the use of a 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device's most negative potential on the PCB.

AC Electrical Characteristics

$$ V _ {C C} = 3. 0 \mathrm{V} \text { to } 3. 6 \mathrm{V}; R _ {\text { LOAD }} = 5 0 \Omega \text { to } V _ {C C} - 2 \mathrm{V}; T _ {A} = - 4 0 ^ {\circ} \mathrm{C} \text { to } + 8 5 ^ {\circ} \mathrm{C}. $$

Symbol	Parameter	Condition	Min	Typ	Max	Units
t_r , t_f	Output Rise/Fall Time(20% to 80%)	Note 4			260	ps
t_JITTER	Deterministic	Note 5		15		p_sPP
	Random	Note 6		5		p_SRMS
V_ID	Differential Input Voltage Swing	Figure 1	5		1800	mV_PP
V_OD	Differential Output Voltage Swing	V_ID ≥ 18mV_PP Figure 1		1500		mV_PP
T_OFF	SD Release Time			100	500	ns
T_ON	SD Assert Time			100	500	ns
SD_AL	Low SD Assert Level	R_SDLVL=15kΩ, Note 8		3.4		mV_PP
SD_DL	Low SD De-assert Level	R_SDLVL=15kΩ, Note 8		2.3		mV_PP
HYSL	Low SD Hysteresis	R_SDLVL=15kΩ, Note 7		3.4		dB
SD_AM	Medium SD Assert Level	R_SDLVL=5kΩ, Note 8		6.2	8	mV_PP
SD_DM	Medium SD De-assert Level	R_SDLVL=5kΩ, Note 8	3	4.2		mV_PP
HYS_M	Medium SD Hysteresis	R_SDLVL=5kΩ, Note 7	2	3.4	5	dB
SD_AH	High SD Assert Level	R_SDLVL=100Ω, Note 8		16.4	20	mV_PP
SD_DH	High SD De-assert Level	R_SDLVL=100Ω, Note 8	8	10.8		mV_PP
HYSH	High SD Hysteresis	R_SDLVL=100Ω, Note 7	2	3.4	5	dB
B_-3dB	3dB Bandwidth			1		GHz
A_V(Diff)	Differential Voltage Gain			42		dB
S_21	Single-ended Small-Signal Gain			36		dB

Notes:

1. Amplifier in limiting mode. Input is a 200MHz square wave.
2. Deterministic jitter measured using 1.25Gbps K28.5 pattern, V_ID = 10mV_PP .
3. Random jitter measured using 1.25Gbps K28.7 pattern, V_ID = 10mV_PP .
4. This specification defines electrical hysteresis as 20(SD Assert/SD De-assert) . The ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and ROSA characteristics. Based upon that ratio, the optical hysteresis corresponding to the electrical hysteresis range 2dB-5dB, shown in the AC characteristics table, will be 1dB-4dB optical Hysteresis.
5. See "Typical Operating Characteristics" for a graph showing how to choose a particular R_SDLVL for a particular SD assert and its associated de-assert amplitude.

Typical Operating Characteristics

V_CC = 3.3V, T_A = 25^, R_L = 50 to V_CC - 2V, unless otherwise stated.

Functional Block Diagram

graph TD
    DIN --> LimitingAmplifier["Limiting Amplifier"]
    /DIN --> LimitingAmplifier
    VREF --> LevelDetect["Level Detect"]
    VCC --> LevelDetect
    GND --> LevelDetect
    SDLVL --> LevelDetect
    LimitingAmplifier --> PECLBuffer["PECL Buffer"]
    PECLBuffer --> DOUT["DOUT"]
    PECLBuffer --> /DOUT["/DOUT"]
    PECLBuffer --> EN["EN"]
    LevelDetect --> TTLBuffer["TTL Buffer"]
    TTLBuffer --> 4.75kΩ[4.75kΩ]
    LevelDetect --> OC-TTLBuffer["OC-TTL Buffer"]
    OC-TTLBuffer --> SD["SD"]
    4.75kΩ --> Vcc["Vcc"]

Detailed Description

The SY88149CL high-sensitivity limiting post amplifier operates from a single +3.3V power supply, over temperatures from -40°C to +85°C. Signals with data rates up to 1.25Gbps and as small as 5mV can be amplified. Figure 1 shows the allowed input voltage swing. The SY88149CL generates an SD output, allowing feedback to EN for output stability. SD _LVL sets the sensitivity of the input amplitude detection.

Input Amplifier/Buffer

Figure 2 shows a simplified schematic of the input stage. The high-sensitivity of the input amplifier allows signals as small as 5mVPP to be detected and amplified. The input amplifier allows input signals as large as 1800mVPP . Input signals are linearly amplified with a typically 42dB differential voltage gain. Since it is a limiting amplifier, the SY88149CL outputs typically 1500mVPP voltage-limited waveforms for input signals that are greater than 12mVPP . Applications requiring the SY88149CL to operate with high-gain should have the upstream TIA placed as close as possible to the SY88149CL's input pins. This ensures the best performance of the device.

Output Buffer

The SY88149CL's PECL output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external 50Ω resistor to Vcc-2V for each output pin provides this. Figure 3 shows a simplified schematic of the output stage.

Signal Detect

The SY88149CL generates a chatter-free Signal-Detect (SD) open-collector TTL output with internal 4.75kΩ pull-up resistor, as shown in Figure 4. SD is used to determine that the input amplitude is too small to be considered a valid input. SD asserts high if the input amplitude rises above threshold set by SDLVL and de-asserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a SDs of signal condition. EN de-asserts low the true output signal without removing the input signals. Typically, 3.4dB SD hysteresis is provided to prevent chattering.

Signal Detect Level Set

A programmable SD level set pin (SD LVL ) sets the threshold of the input amplitude detection. Connecting an external resistor between V CC and SD LVL sets the voltage at SD LVL . This voltage ranges from V CC to V REF . The external resistor creates a voltage divider between V CC and V REF , as shown in Figure 5.

Hysteresis

The SY88149CL provides typically 3.4dB SD electrical hysteresis. By definition, a power ratio measured in dB is 10log (power ratio). Power is calculated as V^2_IN/R for an electrical signal. Hence the same ratio can be stated as 20log (voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power and hence the ratios change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the data sheet. The SY88149CL is an electrical device; this data sheet refers to hysteresis in electrical terms. With 3.4dB SD hysteresis, a voltage factor of 1.5 is required to assert or de-assert SD.

Figure 1. VIS and VID Definition

VREF 50Ω 50Ω 0.1μF DIN 0.1μF /DIN AC-Coupling Capacitors VCC ESD STRUCTURE GND

Figure 2. Input Structure

VCC DOUT /DOUT GND ESD STRUCTURE

Figure 3. Output Structure

VCC 4.75kΩ SD

Figure 4. SD Output Structure

Figure 5. SD LVL Setting Circuit
Note: Recommended value for RSDLVL is 15kΩ or less.

Related Product and Support Documentation

Part Number	Function	Data Sheet Link
SY88933AL	3.3V/5V 1.25Gbps PECL High-Sensitivity Limiting Post Amplifier with TTL SD	http://www.micrel.com/product-info/sy88933al.shtml
Application Notes	Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers	http://www.micrel.com/product-info/app_hints+notes.shtml

Package Information

NOTES: 1. DIMENSIONS ARE IN MM (INCHES). 2. CONTROLLING DIMENSION: MM △ DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS, EITHER OF WHICH SHALL NOT EXCEED 0.20 [0.008] PER SIDE.

Rev. 00

10-Pin MSOP (K10-1)

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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