SY88773V - Amplifier Microchip - Free user manual and instructions

USER MANUAL SY88773V Microchip

■ Multi-rate up to 3.2Gbps operation
■ Wide gain-bandwidth product

• 38dB differential gain

- 2GHz 3dB bandwidth

■ Low noise 50Ω CML data outputs

• 800mV PP output swing
• 60ps edge rates
• 5ps (RMS) typ. random jitter
  • 15ps (PP) typ. deterministic jitter

■ Chatter-free, Loss-of-Signal (LOS) output

• 4.6dB electrical hysteresis
• OC-TTL output with internal 4.75kΩ pull-up resistor

■ Programmable LOS sensitivity using single external resistor
■ Integrated input bias reference
■ TTL /EN input allows feedback from LOS
■ Wide operating range

• Single 3.3V ±10% or 5V ±10% power supply
- -40°C to +85°C industrial temperature range

■ Available in tiny 10-pin EPAD-MSOP and 16-pin MLF™ packages

APPLICATIONS

■ 1.25Gbps and 2.5Gbps Gigabit Ethernet
■ 1.062Gbps and 2.125Gbps Fibre Channel
■ 155Mbps, 622Gbps, 1.25Gbps, and 2.5Gbps SONET/SDH
■ Gigabit interface converter (GBIC)
■ Small form factor (SFF) and small form factor pluggable (SFP) transceivers
■ Parallel 10G Ethernet
■ High-gain line driver and line receiver

DESCRIPTION

The SY88773V low-power, limiting post amplifier is designed for use in fiber optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88773V quantizes these signals and outputs typically 800mVpp voltage-limited waveforms.

The SY88773V operates from a single +3.3V ±10% or +5V ±10% power supply, over an industrial temperature range of -40°C to +85°C. With its wide bandwidth and high gain, signals with data rates up to 3.2Gbps and as small as 10mVpp can be amplified to drive devices with CML inputs or AC-coupled PECL inputs.

The SY88773V incorporates a loss-of-signal (LOS), open-collector TTL output with internal 4.75kΩ pull-up resistor. A programmable, loss-of-signal level set pin (LOSLVL) sets the sensitivity of the input amplitude detection. LOS asserts high if the input amplitude falls below the threshold set by LOSLVL and de-asserts low otherwise. LOS can be fed back to the enable (/EN) input to maintain output stability under a loss-of-signal condition. /EN de-asserts the true output signal without removing the input signal. Typically 4.6dB LOS hysteresis is provided to prevent chattering.

Please see Micrel's website at www.micrel.com for a complete selection of optical module ICs. The following table summarizes the differences between devices in Micrel's latest family of Limiting Amplifiers.

All support documentation can be found on Micrel's web site at www.micrel.com.

Part Number	Integrated 50Ω LOS Input Termination or	Active SD or HIGH	LOW GH Enable
SY88773V No	LOS LOW
SY88823V No	SD HIGH
SY88843V Yes	SD HIGH
SY88973V Yes	LOS LOW

Table 1. Limiting Amplifiers Selection Guide

TYPICAL PERFORMANCE

3.3V, 25°C, 10mV pp Input @3.2Gbps 2 ^31 -1 PRBS, R LOAD = 50Ω to V _CC

Output Swing (75mV/div.) TIME (50ps/div.)

Micro LeadFrame and MLF are trademarks of Amkor Technology

FUNCTIONAL BLOCK DIAGRAM

graph TD
    DIN --> LimitingAmplifier["Limiting Amplifier"]
    DIN --> /DIN["/DIN"]
    REF --> REFGenerator["REF Generator"]
    REF --> LevelDetect["Level Detect"]
    LevelDetect --> TTLBuffer["TTL Buffer"]
    LevelDetect --> OC-TTLBuffer["OC-TTL Buffer"]
    OC-TTLBuffer --> LOS["LOS"]
    LevelDetect --> VCC1["VCC 25kΩ"]
    LevelDetect --> VCC2["VCC"]
    LevelDetect --> 4.75kΩ[4.75kΩ]
    LevelDetect --> GND["GND"]
    VCC1 --> DOUT["DOUT"]
    VCC2 --> /EN["/EN"]
    style DIN fill:#f9f,stroke:#333
    style REF fill:#ccf,stroke:#333
    style LevelDetect fill:#cfc,stroke:#333
    style OC-TTLBuffer fill:#fcc,stroke:#333
    style LOS fill:#ffc,stroke:#333
    style VCC1 fill:#fff,stroke:#333
    style VCC2 fill:#fff,stroke:#333
    style GND fill:#fff,stroke:#333

PACKAGE/ORDERING INFORMATION

VCC /EN LOSLVL VCC 16 15 14 13 DIN 1 12 DOUT GND 2 11 GND GND 3 10 GND /DIN 4 9 /DOUT 5 6 7 8 VCC REF LOS VCC

16-Pin MLF (MLF-16)

/EN 1 DIN 2 /DIN 3 REF 4 LOSLVL 5 10 VCC 9 DOUT 8 /DOUT 7 LOS 6 GND

10-Pin EPAD-MSOP (K10-2)

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY88773VKI	K10-2	Industrial	773V	Sn-Pb
SY88773 VKITR^(2)	K10-2	Industrial	773V	Sn-Pb
SY88773VMI	MLF-16	Industrial	773V	Sn-Pb
SY88773 VMITR^(2)	MLF-16	Industrial	773V	Sn-Pb
SY88773 VEY^(3)	K10-2	Industrial	773V with Pb-Free bar-line indicator	Pb-Free Matte-Sn
SY88773 VEYTR^(2, 3)	K10-2	Industrial	773V with Pb-Free bar-line indicator	Pb-Free Matte-Sn
SY88773 VMG^(3)	MLF-16	Industrial	773V with Pb-Free bar-line indicator	Pb-Free NiPdAu
SY88773 VMGTR^(2, 3)	MLF-16	Industrial	773V with Pb-Free bar-line indicator	Pb-Free NiPdAu

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ C , DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.

PIN DESCRIPTION

Pin Number Pin (MSOP) (ML)	in Number F^TM Pin Name	Type Pin Function
1 15 /EN	TTL Input: Enable: De-asserts true data output when high. Default is high. Incorporates 25kΩ pull-up to VCC.
2, 3 1, 4 D	IN, /DIN Differential Differential Differential Data Input. Inputs must be biased to meet Data Input common-mode range.
4	6	REF		Reference Voltage: Bypass with 0.01°F low ESR capacitor from REF to VCC to stabilize LOSLVL and REF.
5	14	LOSLVL	Input: Default is maximum sensitivity.	Loss-of-Signal Level Set: A resistor from this pin to VCC sets the threshold for the data input amplitude at which the LOS output will be asserted.
6 Exposed Pad	2, 3, 10, 11 Exposed Pad	GND	Ground	Device Ground. Exposed pad must be soldered (or equivalent) to the same potential as the ground pins.
7	7	LOS	Open Collector TTL Output with internal 4.75kΩ pull-up resistor	Loss-of-Signal: Asserts high when the data input amplitude falls below the threshold set by LOSLVL.
8, 9	9, 12	DOUT, /DOUT	Differential CML Output	Differential Data Output.
10	5, 8, 13, 16	VCC	Power Supply	Positive Power Supply. Bypass with 0.1×F 0.01°F low ESR capacitors. 0.01°F capacitors should be as close as possible to VCC pins.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_CC ) 0V to +7.0V

/EN, LOSLVL Voltage ....0 to Vcc

REF Current ±1mA

LOS Current ±5mA

DOUT, /DOUT Current ....±25mA

DIN, /DIN Current ....±10mA

Storage Temperature ( T_S ) -65^ to +150^

Lead Temperature (soldering, 20 sec.) ....+260°C

Operating Ratings ^(2)

Supply Voltage ( V_CC ) ....+3.0V to +3.6V or ....+4.5V to +5.5V

Ambient Temperature ( T_A ) -40^ to +85^

Junction Temperature ( T_J ) -40^ to +120^

Package Thermal Resistance ^(3)

MLFTM

_JA (Still-Air)....61°C/W _JB ....38°C/W

EPAD-MSOP

_JA (Still-Air)....38°C/W _JB ....22°C/W

DC ELECTRICAL CHARACTERISTICS

V_CC = 3.0V to 3.6V or 4.5V to 5.5V , T_A = -40^ C to +85^ C ; typical values at V_CC = 3.3V , T_A = 25^ C .

Symbol Parameter Condition Min Typ Max Units
I_CC	Power Supply Current	3.3V, Note 45V, Note 4		2830	4245	mAmA
	Power Supply Current	3.3V, Note 55V, Note 5		4547	6265	mAmA
V_REF	REF Voltage			V_CC-1.3		V
V_LOSLVL	LOSLVL Voltage Range		V_REF		V_CC	V
V_OH	DOUT, /DOUT HIGH Voltage	Note 6	V_CC-0.020	V_CC-0.005	V_CC	V
V_OL	DOUT, /DOUT LOW Voltage	3.3V, Note 65V, Note 6	V_CC-0.475 V_CC-0.510	V_CC-0.400 V_CC-0.400	V_CC-0.350 V_CC-0.350	VV
V_OFFSET	Differential Output Offset	Note 6			±80	mV
Z_O	Single-Ended Output Impedance		40	50	60	Ω
V_IHCMR	Input Common Mode Range	Note 7	GND+2.15		V_CC	V

TTL DC ELECTRICAL CHARACTERISTICS

V_CC = 3.0V to 3.6V or 4.5V to 5.5V , T_A = -40^ C to +85^ C .

Symbol Parameter Condition Min Typ Max Units
V_OH	LOS Output HIGH Level	Sourcing 100 × A	2.4		V_CC	V
V_OL	LOS Output LOW Level	Sinking 2mA			0.5	V
V_IH	/EN Input HIGH Voltage		2.0			V
V_IL	/EN Input LOW Voltage				0.8	V
I_IH	/EN Input HIGH Current	V_IN = 2.7V V_IN = V_CC			20100	A A
I_IL	/EN Input LOW Current	V_IN = 0.5V	-0.3			mA

Notes:

1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes the use of 4-layer PCB. Exposed pad must be soldered (or equivalent) to the device's most negative potential on the PCB.
4. Excludes current of CML output stage. See "Detailed Description."
5. Total device current with no output load.
6. Output levels are based on a 50Ω to V _CC load impedance. If the load impedance is different, the output level will be changed. Amplifier is in limiting mode.
7. The V_IHCMR range is referenced to the most positive side of the differential input signal.

AC ELECTRICAL CHARACTERISTICS
V_CC = 3.0V to 3.6V or 4.5V to 5.5V , T_A = -40^ C to +85^ C , R_LOAD = 50 to V_CC ; typical values at V_CC = 3.3V , T_A = 25^ C .

Symbol Parameter Condition Min Typ Max Units
PSRR Power	Supply Rejection Ratio 35 dB
t_r, t_f	Output Rise/Fall Time Note 8 60 120 (20% to 80%)	ps
t_JITTER	Deterministic Note 9 15 ps Random 5 ps					PP RMS
V_ID	Differential Input Voltage Swing		10		1800	mV PP
V_OD	Differential Output Voltage Swing	3.3V, Note 8 5V, Note 8	700 700	800 800	950 1020	mV PP mV PP
HYS	LOS Hysteresis	Note 10	2	4.6	8	dB
t_OFF	LOS Release Time			0.1	0.5	S
t_ON	LOS Assert Time			0.2	0.5	S
V_SR	LOS Sensitivity Range	Note 11	10		35	mV PP
B_-3dB	-3dB Bandwidth			2.0		GHz
A_V(Diff)	Differential Voltage Gain		32	38 dB
S_21	Single-Ended Small-Signal Gain		26	32 dB

Notes:

1. Amplifier in limiting mode. Input is a 200MHz square wave, t_r < 300ps .
2. Deterministic jitter measured using 2.488Gbps K28.5 pattern, V_ID = 10mVPP . Random jitter measured using 2.488Gbps K28.7 pattern, VID = 10mV_PP .
3. Electrical signal.
4. This is the detectable range of input amplitudes that can assert LOS. The input amplitude to de-assert LOS is 2–8dB higher than the assert amplitude. See "Typical Operating Characteristics" for graphs showing how to choose a particular V_LOSLVL or R_LOSLVL for a particular LOS assert, and its associated de-assert, amplitude. If increased LOS sensitivity and hysteresis are required, an application note entitled "Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers" is available at http://www.micrel.com/product-info/app spreading+notes.shtml.

TYPICAL OPERATING CHARACTERISTICS

V_CC = 3.3V, T_A = 25^, R_LOAD = 50 to V_CC , unless otherwise stated.

10mVpp Input @3.2Gbps 2^31-1 PRBS Output Swing (75mV/div.) TIME (50ps/div.)

DETAILED DESCRIPTION

The SY88773V low-power, limiting post amplifier operates from a single +3.3V or +5V power supply, over temperatures from -40°C to +85°C. Signals with data rates up to 3.2Gbps and as small as 10mVpp can be amplified. Figure 1 shows the allowed input voltage swing. The SY88773V generates an LOS output, providing feedback to /EN for output stability. LOSLVL sets the sensitivity of the input amplitude detection.

Input Amplifier/Buffer

The SY88773V input is designed for V_REF as its nominal DC bias point. If AC-coupling to the SY88773V, REF can be used as the DC bias point by externally connecting the inputs through appropriate termination resistors to REF. If DC-coupling to the SY88773V, ensure the upstream device's output swing meets the SY88773V's common mode range. Figure 2 shows a simplified schematic of the input structure.

The high-sensitivity of the input amplifier detects and amplifies signals as small as 10mV_pp . The input amplifier allows input signals as large as 1800mV_pp . Input signals are linearly amplified with a typically 38dB differential voltage gain. Since it is a limiting amplifier, the SY88773V outputs typically 800mV_pp voltage-limited waveforms for input signals that are greater than 10mV_pp . Applications requiring the SY88773V to operate with high-gain should have the upstream TIA placed as close as possible to the SY88773V's input pins to ensure the device's best performance.

Output Buffer

The SY88773V's CML output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external 50Ω resistor to VCC or equivalent for each output pin provides appropriate output buffer termination. Figure 3 shows a simplified schematic of the output structure and includes an appropriate termination method. Of course, driving a downstream device with a CML input that is internally terminated with 50Ω to VCC eliminates the need for external termination. As noted in the previous section, the amplifier outputs, typically 800mVpp, waveforms across 25Ω total loads. The output buffer, thus, switches typically 16mA tail-current. Figure 4 shows the power supply current measurement which excludes the 16mA tail-current.

Loss-of-Signal

The SY88773V incorporates a chatter-free, LOS open-collector TTL output with internal 4.75kΩ pull-up resistor as shown in Figure 5. LOS is used to determine that the input amplitude is too small to be considered a valid input. LOS asserts high if the input amplitude falls below the threshold set by LOSLVL and de-asserts low otherwise. LOS can be fed back to the enable (/EN) input to maintain output stability under a loss-of-signal condition. /EN de-asserts low the true output signal without removing the input signals. Typically, 4.6dB LOS hysteresis is provided to prevent chattering.

Loss-of-Signal Level Set

A programmable, loss-of-signal level set pin sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and LOSLVL sets the voltage at LOSLVL. This voltage ranges from V_CC to V_REF . The external resistor creates a voltage divider between VCC and REF as shown in Figure 6. If desired, an appropriate external voltage may be applied rather than using a resistor. The relationship between V_LOSLVL and R_LOSLVL is given by:

$$ V _ {L O S L V L \overline {{C C}}} \forall 3 \quad . \frac {R _ {L O S L V L}}{R _ {L O S L V L} + 2 . 8} $$

where voltages are in volts and resistances are in kΩ.

The smaller the external resistor, which implies a smaller voltage difference from LOSLVL to VCC, the lower the LOS sensitivity. Hence, larger input amplitude is required to de-assert LOS. The "Typical Operating Characteristics" section contains graphs showing the relationship between the input amplitude detection sensitivity and V_LOSLVL or R_LOSLVL .

Hysteresis

The SY88773V provides typically 4.6dB LOS electrical hysteresis. By definition, a power ratio measured in dB is 10(power ratio) . Power is calculated as V^2_IN/R for an electrical signal. Hence, the same ratio can be stated as 20(voltage ratio) . While in linear mode, the electrical voltage input changes linearly with the optical power and, hence, the ratios change linearly. Therefore, the optical hysteresis in dB is half the electrical hysteresis in dB given in the datasheet. The SY88773V provides typically 2.3dB LOS optical hysteresis. As the SY88773V is an electrical device, this datasheet refers to hysteresis in electrical terms. With 4.6dB LOS hysteresis, a voltage factor of 1.7 is required to de-assert LOS.

Hysteresis and Sensitivity Improvement

If increased LOS sensitivity and hysteresis are required, an application note entitled “Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers” is available at http://www.micrel.com/product-info/app_hints+notes.shtml.

Figure 1. V_IS and V_ID Definition

DIN /DIN ESD STRUCTURE Vcc GND

Figure 2. Input Structure

VCC 50Ω 50Ω DOUT Z₀ = 50Ω /DOUT Z₀ = 50Ω AC-Coupling Capacitors 16mA GND ESD STRUCTURE VCC 50Ω 50Ω 0.1αF

Figure 3. Output Structure

VCC Icc 16mA 50Ω 50Ω ESD STRUCTURE 16mA GND

Figure 4. Power Supply Current Measurement

VCC 4.75kΩ LOS

Figure 5. LOS Output Structure

VCC R_LOSLVL LOSLVL 2.8kΩ REF

Figure 6. LOSLVL Setting Circuit

TYPICAL APPLICATIONS CIRCUIT

From Transimpedance Amp. 0.1×F 0.1×F 0.1×F DIN /DIN 50Ω50Ω GND VCC 100kΩ LOSLVL REF VCC 0.1×F 0.1×F DOUT /DOUT 0.1×F To CDR SY88773V

RELATED PRODUCT AND SUPPORT DOCUMENTATION

Part Number Function Data Sheet Link
SY88773V 3.3V/5V	3.2Gbps CML Low-Power, http://www.micrel.com/ Limiting Post Amplifier w/ TTL LOS	/_PDF/HBW/sy88773v.pdf
SY88823V 3.3V/5V	3.2Gbps CML Low-Power, http://www.micrel.com/ Limiting Post Amplifier w/ TTL SD	/_PDF/HBW/sy88823v.pdf
SY88843V 3.3V/5V	3.2Gbps CML Low-Power, http://www.micrel.com/ Limiting Post Amplifier w/ TTL SD	/_PDF/HBW/sy88843v.pdf
SY88973V 3.3V/5V	3.2Gbps CML Low-Power, http://www.micrel.com/ Limiting Post Amplifier w/ TTL LOS	/_PDF/HBW/sy88973v.pdf
Application Notes	Notes on Sensitivity and Hysteresis http://www.micrel.com/product-info/app_hints+notes.shtml in Micrel Post Amplifiers

10 LEAD EPAD-MSOP (K10-2)

NOTES 1. DIMENSIONS ARE IN MM (INCHES). 2. CONTROLLING DIMENSION: MM 3. DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS, EITHER OF WHICH SHALL NOT EXCEED 0.20 [0.008]

Rev.01

16-PIN MicroLEADFRAME™ (MLF-16)

Pin 1 Dot By Marking 3.000±0.050 3.000±0.050

TOP VIEW

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.550±0.050 Exp. DAP 0.400±0.050 1.550±0.050 Exp. DAP 0.500 Bsc 0.230±0.050 0.400±0.050 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane VEE VEE Heavy Copper Plane

PCB Thermal Consideration for 16-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 [phone] FAX + 1 [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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