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FTLD10CE3C - Composant optique Finisar - Free user manual and instructions

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USER MANUAL FTLD10CE3C Finisar

Product Specification

100GBASE-SR10 100m CXP Optical Transceiver Module

FTLD10CE3C

PRODUCT FEATURES

• 12-channel full-duplex transceiver module
• Hot Pluggable CXP form factor
- Multirate capability: 1Gb/s to 11.3Gb/s per channel
• Maximum link length of 100m on OM3 Multimode Fiber (MMF)
- Unretimed CPPI electrical interface
- Requires 3.3V power supply only
- Low power dissipation: < 3.5W
• Reliable VCSEL array technology
• Digital Diagnostics including Tx and Rx optical power monitoring
• Commercial operating case temperature range: 0°C to 70°C
• RoHS-6 Compliant (lead-free)

Finisar FTLD10CE3C - PRODUCT FEATURES - 1

natural_image Exterior view of a beige electronic device with a black connector and beige handle (no visible text or symbols)

APPLICATIONS

• Infiniband 12x SDR/DDR/QDR
• 100GBASE-SR10 100G Ethernet
- OTU4/OTU2e
- 12x 10GBASE-SR Ethernet (compatible)
- PCIe (Gen1/2/3)
- SATA3
- Proprietary protocols

Finisar's FTLD10CE3C second-generation CXP transceiver modules are designed for use in up to 136 Gigabit per second links over 12 duplex multimode fiber pairs. They are compliant with the IBTA CXP Specification ^1 , IEEE 802.3ba 100GBASE-SR10 and CPPI electrical interfaces ^2 . The transceiver is RoHS-6 compliant and lead-free per Directive 2002/95/EC ^3 , and Finisar Application Note AN-2038 ^4 . They support Tx/Rx optical power monitoring functionality. For applications up to 14 Gb/s per channel please contact Finisar.

PRODUCT SELECTION

FTLD10CE3C

E: Ethernet-compliant optical interface

3: Second generation product

C: Commercial temperature rate

I. Pin Descriptions

Bottom sideTop Side
I/O #NameContact LengthContact LengthNameI/O #
Receiver -- Top Card
C1GNDFinisar FTLD10CE3C - FTLD10CE3C - 1
C2RX1p
C3RX1n
C4GND
C5RX3p
C6RX3n
C7GND
C8RX5p
C9RX5n
C10GND
C11RX7p
C12RX7n
C13GND
C14RX9p
C15RX9n
C16GND
C17RX11p
C18RX11n
C19GND
C20PRSNT_L
C21Int_L/Reset_L
Transmitter -- Bottom Card
A1GNDCard EdgeGNDB1
A2TX1pTX0pB2
A3TX1nTX0nB3
A4GNDGNDB4
A5TX3pTX2pB5
A6TX3nTX2nB6
A7GNDGNDB7
A8TX5pTX4pB8
A9TX5nTX4nB9
A10GNDGNDB10
A11TX7pTX6pB11
A12TX7nTX6nB12
A13GNDGNDB13
A14TX9pTX8pB14
A15TX9nTX8nB15
A16GNDGNDB16
A17TX11pTX10pB17
A18TX11nTX10nB18
A19GNDGNDB19
A20SCLVCC3.3-TXB20
A21SDAVCC12-TXB21

Transmitter -- Bottom Card

A1GND
A2TX1p
A3TX1n
A4GND
A5TX3p
A6TX3n
A7GND
A8TX5p
A9TX5n
A10GND
A11TX7p
A12TX7n
A13GND
A14TX9p
A15TX9n
A16GND
A17TX11p
A18TX11n
A19GND
A20SCL
A21SDA

Figure 1 - CXP-compliant 84-pin connector

PinSymbolName/DescriptionNotes
A1GNDGround1
A2Tx1pTransmitter Non-Inverted Data Input
A3Tx1nTransmitter Inverted Data Input
A4GNDGround1
A5Tx3pTransmitter Non-Inverted Data Input
A6Tx3nTransmitter Inverted Data Input
A7GNDGround1
A8Tx5pTransmitter Non-Inverted Data Input
A9Tx5nTransmitter Inverted Data Input
A10GNDGround1
A11Tx7pTransmitter Non-Inverted Data Input
A12Tx7nTransmitter Inverted Data Input
A13GNDGround1
A14Tx9pTransmitter Non-Inverted Data Input
A15Tx9nTransmitter Inverted Data Input
A16GNDGround1
A17Tx11pTransmitter Non-Inverted Data Input
A18Tx11nTransmitter Inverted Data Input
A19GNDGround1
A20SCL2-wire serial interface clock
A21SDA2-wire serial interface data
B1GNDGround1
B2Tx0pTransmitter Non-Inverted Data Input
B3Tx0nTransmitter Inverted Data Input
B4GNDGround1
B5Tx2pTransmitter Non-Inverted Data Input
B6Tx2nTransmitter Inverted Data Input
B7GNDGround1
B8Tx4pTransmitter Non-Inverted Data Input
B9Tx4nTransmitter Inverted Data Input
B10GNDGround1
B11Tx6pTransmitter Non-Inverted Data Input
B12Tx6nTransmitter Inverted Data Input
B13GNDGround1
B14Tx8pTransmitter Non-Inverted Data Input
B15Tx8nTransmitter Inverted Data Input
B16GNDGround1
B17Tx10pTransmitter Non-Inverted Data Input
B18Tx10nTransmitter Inverted Data Input
B19GNDGround1
B20VCC3.3-TX+3.3 V Power supply transmitter
B21VCC12-TX+12.0 V Power supply transmitter - NOT CONNECTED2
C1GNDGround1
C2Rx1pReceiver Non-Inverted Data Output
C3Rx1nReceiver Inverted Data Output
C4GNDGround1
C5Rx3pReceiver Non-Inverted Data Output
C6Rx3nReceiver Inverted Data Output
C7GNDGround1
C8Rx5pReceiver Non-Inverted Data Output
C9Rx5nReceiver Inverted Data Output
C10GNDGround1
C11Rx7pReceiver Non-Inverted Data Output
C12Rx7nReceiver Inverted Data Output
C13GNDGround1
C14Rx9pReceiver Non-Inverted Data Output
C15Rx9nReceiver Inverted Data Output
C16GNDGround1
C17Rx11pReceiver Non-Inverted Data Output
C18Rx11nReceiver Inverted Data Output
C19GNDGround1
C20PRSNT_LModule Present
C21Int_L/Reset_LInterrupt / Reset
D1GNDGround1
D2Rx0pReceiver Non-Inverted Data Output
D3Rx0nReceiver Inverted Data Output
D4GNDGround1
D5Rx2pReceiver Non-Inverted Data Output
D6Rx2nReceiver Inverted Data Output
D7GNDGround1
D8Rx4pReceiver Non-Inverted Data Output
D9Rx4nReceiver Inverted Data Output
D10GNDGround1
D11Rx6pReceiver Non-Inverted Data Output
D12Rx6nReceiver Inverted Data Output
D13GNDGround1
D14Rx8pReceiver Non-Inverted Data Output
D15Rx8nReceiver Inverted Data Output
D16GNDGround1
D17Rx10pReceiver Non-Inverted Data Output
D18Rx10nReceiver Inverted Data Output
D19GNDGround1
D20Vcc3.3-RX+3.3 V Power supply receiver
D21Vcc12-RX+12.0 V Power supply receiver - NOT CONNECTED2

Notes

  1. Circuit ground is internally isolated from chassis ground.

  2. 12V power supply not required.

II. General Product Characteristics

ParameterValueUnitNotes
Module Form FactorCXP
Number of Lanes12 Tx and 12 Rx
Maximum Aggregate Data Rate135.816Gb/s
Maximum Data Rate per Lane11.318Gb/s
Protocols SupportedTypical applications include Infiniband DDR/QDR, 100GBASE-SR10 Ethernet, OTU4, OTU2e, PCIe-Gen1/2/3, 12x10GBASE-SR Ethernet
Electrical Interface and Pin-out84-pin edge connectorPin-out as defined by the CXP Specification
Optical Cable Type RequiredMultimode ribbon 24-fiber cable assembly, MPO connector
Maximum Power Consumption per End3.5WattsVaries with output voltage swing and pre-emphasis settings
Management InterfaceSerial, I2C-based, 400 kHz maximum frequencyAs defined by the CXP Specification
Data Rate SpecificationsSymbolMinTypMaxUnitsRef.
Bit Rate per LaneBR100011318Mb/sec1
Bit Error Ratio @10.3Gb/s per LaneBER1 10^-12 2
Bit Error Ratio @11.1Gb/s per LaneBER2 10^6 2
Bit Error Ratio @11.2Gb/s per LaneBER3 10^6 2
Bit Error Ratio @11.3Gb/s per LaneBER4 10^8 2
Link distance on OM3 MMFD1100meters
Link distance on OM4 MMFD2150meters

Notes:
1. Infiniband SDR/DDR/QDR, 100GBASE-SR10 100G Ethernet, OTU2e, OTU4, PCIe Gen1/2/3, 12x10GBASE-SR 10G Ethernet.
2. Tested with a PRBS 2 ^31 -1 test pattern.

III. Absolute Maximum Ratings

ParameterSymbolMinTypMaxUnitRef.
Maximum Supply Voltage V_cc1 , V_ccTx , V_ccRx -0.53.6V
Storage Temperature T_S -4085°C
Case Operating Temperature T_OP 070°C
Relative HumidityRH085%1

Notes:
1. Non-condensing.

IV. Electrical Characteristics (T OP = 0 to 70^,V_CC = 3.3± 5% Volts)

NOTE: The FTLD10CE3C requires that a CPPI-compliant CXP electrical connector be used on the host board in order to guarantee its electrical interface specification. Please check with your connector supplier.

ParameterSymbolMinTypMaxUnitRef.
Supply VoltageVcc1, VccTx, VccRx3.153.45V
Supply CurrentIcc8501000mA
Module Total PowerP3.5W1,7
Link Turn-On Time
Transmit turn-on time2000ms2
Transmitter (per Lane)
Single ended input voltage toleranceVinT-0.34.0V
Differential data input swingVin,pp1201200mVpp3
Differential input threshold50mV
AC common mode input voltage tolerance (RMS)15mV
Differential input return lossPer IEEE 802.3ba, Section 86A.4.1.1dB4
J2 Jitter ToleranceJt20.17UI
J9 Jitter ToleranceJt90.29UI
Data Dependent Pulse Width ShrinkageDDPWS0.07UI
Eye mask coordinates {X1, X2 Y1, Y2}0.11, 0.31 95, 350UI mV5
Receiver (per Lane)
Single-ended output voltage-0.34.0V
Differential data output swingVout,pp0800mVpp6.7
AC common mode output voltage (RMS)7.5mV
Termination mismatch at 1 MHx5%
Differential output return lossPer IEEE 802.3ba, Section 86A.4.2.1dB4
Common mode output return lossPer IEEE 802.3ba, Section 86A.4.2.2dB4
Output transition time, 20% to 80%28ps
J2 Jitter outputJo20.42UI
J9 Jitter outputJo90.65UI
Eye mask coordinates {X1, X2 Y1, Y2}0.29, 0.5 150, 425UI mV5
Power Supply Ripple TolerancePSR50mVpp

Notes:

  1. Maximum total power value is specified across the full temperature and voltage range.
  2. From power-on and end of any fault conditions.
  3. After internal AC coupling. Self-biasing 100Ω differential input.
  4. 10 MHz to 11.1 GHz range
  5. Hit ratio = 5 x 10E-5
  6. AC coupled with 100Ω differential output impedance.
  7. Settable in 4 discrete steps via the I2C interface. See Figure 2 for Vout settings.

Finisar FTLD10CE3C - Notes: - 1

radar | Time (UI) | Differential amplitude (mV) | | --------- | --------------------------- | | 0 | 0 | | X1 | 0 | | X2 | 0 | | 1-X2 | 0 | | 1-X1 | 0 | | 1 | -Y2 |

Figure 2 – Transmitter Input Differential Signal Mask

Finisar FTLD10CE3C - Notes: - 2

radar | Time (UI) | Differential amplitude (mV) | | --------- | --------------------------- | | 0 | 0 | | X1 | 0 | | X2 | 0 | | 1-X1 | 0 | | 1 | 0 |

Figure 3 – Receiver Output Differential Signal Mask

Receiver Output Amplitude Settings

CodeReceiver Output Amplitude (mV)Reference
1xxxbMinNominalMax
0111b650750850
0110b550650750
0101b450550650Default Setting
0100b350450550
0011b300400500
0010b250350450
0001b200300400
0000b150250350

Receiver Pre-Emphasis Settings

CodePre-emphasis (dB)Reference
0111b4.5 +/- 0.25
0110b4.0 +/- 0.5
0101b3.5 +/- 0.5
0100b3.0 +/-0.5
0011b2.5 +/- 0.5Default Setting
0010b2.0 +/- 0.5
0001b1.5 +/- 0.5
0000b0.5 +/- 0.25

Module-end, Typical Power Consumption

Power(mW)Pre-Emphasis
Code0000b0001b0010b0011b0100b0101b0110b0111b
RxOutput0000b20062006200920092009201320132013
0001b20092009200920132009201320132016
0010b20132013201320132013201620162020
0011b20162013201620162016202020202023
0100b20202016202020202020202020232023
0101b20232020202320232023202620262026
0110b20262026202620262026202620302030
0111b20262026203020302030203020332033

V. Optical Characteristics (T OP = 0 to 70°C, VCC = 3.3 ± 5% Volts)

ParameterSymbolMinTypMaxUnitRef.
Transmitter (per Lane)
Signaling Speed per Lane11.3GBd1
Center wavelength840860nm
RMS Spectral WidthSW0.65nm
Average Launch Power per Lane TXP_x -7.62.4dBm
Transmit OMA per LaneTxOMA-5.63.0dBm2
Difference in Power between any two lanes [OMA] DP_x 4.0dB
Peak Power per Lane PP_x 4.0dBm
Launch Power [OMA] minus TDP per LaneP-TDP-6.5dBm
TDP per LaneTDP3.5dBm
Optical Extinction RatioER3.0dB
Optical Return Loss ToleranceORL12dB
Encircled FluxFLX>86% at 19 um<30% at 4.5 umdBm
Average launch power of OFF transmitter, per lane-30dBm
Relative Intensity NoiseRIN-128dB/Hz3
Transmitter eye mask definition {X1, X2, X3, Y1, Y2, Y3}0.23, 0.34, 0.43, 0.27, 0.35, 0.4
Receiver (per Lane)
Signaling Speed per Lane11.3GBd4
Center wavelength840860nm
Damage ThresholdDT3.4dBm
Average Receive Power per Lane RXP_x -9.52.4dBm
Receive Power (OMA) per LaneRxOMA3.0dBm
Stressed Receiver Sensitivity (OMA) per LaneSRS-5.4dBm
Peak Power, per lane PP_x 4dBm
Receiver ReflectanceRfl-12dB
Vertical eye closure penalty, per lane1.9dB
Stressed eye J2 jitter, per Lane0.3UI
Stressed eye J9 jitter, per Lane0.47UI
OMA of each aggressor lane-0.4dBm
Receiver jitter tolerance [OMA], per Lane-5.4dBm
Rx jitter tolerance: Jitter frequency and p-p amplitude(75, 5)kHz, UI
(375, 1)kHz, UI
LOS De-Assert LOS_D -12.5dBm
LOS Assert LOS_A -30.0-15.5dBm
LOS Hysteresis1dB

Notes:
1. Transmitter consists of 12 lasers operating at a maximum rate of 11.3Gb/s each.
2. Even if TDP is <0.9dB, the OMA min must exceed this value.
3. RIN is scaled by 10*log (10/4) to maintain SNR outside of transmitter.
4. Receiver consists of 12 photodetectors operating at a maximum rate of 11.3Gb/s each.

VI. Memory Map and Control Registers

Compliant with the InfinibandSM Trade Association's InfiniBandTM Architectural Release 1.3, Volume 2, CXP Specification Release, November 6^th , 2012.

VII. Environmental Specifications

Finisar FTLD10CE3C transceiver modules have an operating temperature range from 0^ C to +70^ C case temperature.

Environmental SpecificationsSymbolMinTypMaxUnitsRef.
Case Operating Temperature T_op 070°C
Storage Temperature T_sto -575°C

VIII. Regulatory Compliance

Finisar FTLD10CE3C transceiver modules are RoHS-6 Compliant. Copies of certificates are available at Finisar Corporation upon request.

FTLD10CE3C transceiver modules are classified as Class 1 laser eye safety compliant per IEC 60825-1.

FeatureAgencyStandardCertificate Number
Laser Eye SafetyFDA/CDRHCDRH 21 CFR 1040 and Laser Notice 500620885-043
Laser Eye SafetyTÜVEN 60825-1: 2007, EN60825-2:2004+A1IEC 60825-1: 2007 ( 2^nd Edition)IEC 60825-2: 2010 ( 3^rd Edition)R72120958
Electrical SafetyTÜVEN 60950:2006+A11R72120958
Electrical SafetyUL/CSACLASS 3862.07CLASS 3862.872397145

Copies of the referenced certificates are available at Finisar Corporation upon request.

IX. Mechanical Specifications

The FTLD10CE3C transceiver module mechanical specifications are based on the CXP Specification.

62.3 13.5 23.9 21.2 19.7 28.45 82.2 9.81 14.0 (LATCHED)

Figure 3 - FTLD10CE3C mechanical drawing

Finisar Sunnyvale, CA 94089 FTLD10CE3C 100GBASE-SR10 MADE IN CHINA Class 1 21CFR1040.10 LN#50 6/2007 S/N: YY-WW

Figure 4 - FTLD10CE3C production-level product label

X. References

  1. Supplement to Infiniband Architecture Specification, Volume 2, Release 1.3., Annex A6: "12x Form-factor Pluggable (CXP) - Interface Specification for Cables, Active Cables, & Transceivers", November 6, 2012
  2. IEEE 802.3ba, PMD Type 100GBASE-SR10
  3. Directive 2002/95/EC of the European Council Parliament and of the Council, “on the restriction of the use of certain hazardous substances in electrical and electronic equipment”. January 27, 2003.
  4. “Application Note AN-2038: Finisar Implementation Of RoHS Compliant Transceivers”, Finisar Corporation.
  5. “Application Note AN-2085: CXP Transceiver EEPROM Mapping”, Finisar Corporation.

XI. For More Information

Finisar Corporation

1389 Moffett Park Drive

Sunnyvale, CA 94089-1133

Tel. 1-408-548-1000

Fax 1-408-541-6138

sales@finisar.com

www.finisar.com

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Product information

Brand : Finisar

Model : FTLD10CE3C

Category : Composant optique