CobraNet CM-2 - Professional audio equipment MediaMatrix - Free user manual and instructions

USER MANUAL CobraNet CM-2 MediaMatrix

Digital Audio Networking Processor

CobraNet™

Silicon Series

CS18100x, CS18101x, CS18102x, and CM-2

CS49610x, CS49611x, and CS49612x

Hardware User's Manual

Version 2.3

Preliminary Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Table of Contents

List of Figures......4

1.0 .Introduction .... 5
2.0 Features....6

2.1 CobraNet....6
2.2 CobraNet Interface....6
2.3 Host Interface....7
2.4 Asynchronous Serial Interface 7
2.5 Synchronous Serial Audio Interface....7
2.6 Audio Clock Interface....7
2.7 Audio Routing and Processing....7

3.0 Hardware....8

4.0 Pinout and Signal Descriptions 9

4.1 CS1810xx & CS4961xx Package Pinouts....10

4.1.1 CS1810xx/CS4961xx Pinout....10
4.1.2 CM-2 Connector Pinout.... 11

4.2 Signal Descriptions 12

4.2.1 Host Port Signals 12
4.2.2 Asynchronous Serial Port (UART Bridge) Signals ....12
4.2.3 Synchronous Serial (Audio) Signals.... 13
4.2.4 Audio Clock Signals ....13
4.2.5 Miscellaneous Signals....14
4.2.6 Power and Ground Signals 14
4.2.7 System Signals 15

4.3 Characteristics and Specifications....16

4.3.1 Absolute Maximum Ratings 16
4.3.2 Recommended Operating Conditions ....16
4.3.3 Digital DC Characteristics 16
4.3.4 Power Supply Characteristics ....16

5.0 Synchronization....17

5.1 Synchronization Modes....17

5.1.1 Internal Mode 18
5.1.2 External Word Clock Mode 18
5.1.3 External Master Clock Mode ....18

6.0 Digital Audio Interface....19

6.1 Digital Audio Interface Timing 20

6.1.1 Normal Mode Data Timing ....21
6.1.2 I²S Mode Data Timing....21
6.1.3 Standard Mode Data Timing 22

7.0 Host Management Interface (HMI)....23

7.1 Hardware....23
7.4 Protocol and Messages....28

7.4.1 Messages....28

7.4.1.1. Translate Address 29
7.4.1.2. Interrupt Acknowledge....29
7.4.1.3. Goto Packet.....29
7.4.1.4. Goto Translation....29
7.4.1.5. Packet Received 30
7.4.1.6. Packet Transmit 30
7.4.1.7. Goto Counters ....30

7.4.2 Status....31

7.4.3 Data....32

7.4.3.1. Region length 32
7.4.3.2. Writable Region....32
7.4.3.3. Translation Complete 32
7.4.3.4. Packet Transmission Complete....32
7.4.3.5. Received Packet Available 32
7.4.3.6. Message Togglebit ....32

8.0 HMI Reference Code 33

8.1 HMI Definitions....33
8.2 HMI Access Code 34
8.3 CM-1, CM-2 Auto-detection 36

9.0 Mechanical Drawings and Schematics 37

9.1 CM-2 Mechanical Drawings 38
9.2 CM-2 Schematics....44
9.3 CS1810xx/CS4961xx Package 51
9.4 Temperature Specifications 52

10.0 Ordering Information 53

10.1 Device Part Numbers....53
10.2 Device Part Numbering Scheme....53

List of Figures

Figure 1. CobraNet Data Services ....5

Figure 2. CobraNet Interface Hardware Block Diagram....8

Figure 3. Audio Clock Sub-system....17

Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x & CS18101x/CS49611x .... 19

Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x....19

Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1....20

Figure 7. Serial Port Data Timing Overview....20

Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x ....21

Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102x/CS49612x ....21

Figure 10. Audio Data Timing Detail - I²S Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x ....21

Figure 11. Audio Data Timing Detail - I²S Mode, 128FS - CS18102x & CS49612x....21

Figure 12. Audio Data Timing Detail - Standard Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x ....22

Figure 13. Audio Data Timing Detail - Standard Mode, 128FS - CS18102x/CS49612x 22

Figure 14. Host Port Read Cycle Timing - Motorola Mode 25

Figure 15. Host Port Write Cycle Timing - Motorola Mode....25

Figure 16. Parallal Control Port - Intel Mode Read Cycle 27

Figure 17. Parallel Control Port - Intel Mode Write Cycle ....27

Figure 18. CM-2 Module Assembly Drawing, Top 38

Figure 19. CM-2 Module Assembly Drawing, Bottom 39

Figure 20. General PCB Dimensions....40

Figure 21. Example Configuration, Side View....41

Figure 22. Faceplate Dimensions 42

Figure 23. Connector Detail 43

Figure 24. CM-2 RevF Schematic Page 1 of 7 44

Figure 25. CM-2 RevF Schematic Page 2 of 7 45

Figure 26. CM-2 RevF Schematic Page 3 of 7 46

Figure 27. CM-2 RevF Schematic Page 4 of 7 47

Figure 28. CM-2 RevF Schematic Page 5 of 7 48

Figure 29. CM-2 RevF Schematic Page 6 of 7 49

Figure 30. CM-2 RevF Schematic Page 7 of 7 ....50

Figure 31. 144-Pin LQFP Package Drawing....51

Figure 32. Device Part Numbering Explanation....53

1.0 Introduction

This document is intended to help hardware designers integrate the CobraNet™ interface into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x, CS49611x, and CS49612x members of the CobraNet™ Silicon Series of devices, where "x" is the ROM version (ROM ID). This document also describes the CM-2 module with schematics, mechanical drawings, etc.

CobraNet is a combination of hardware (the CobraNet interface), network protocol, and firmware. CobraNet operates on a switched Ethernet network and provides the following additional communications services.

• Isochronous (Audio) Data Transport
  • Sample Clock Distribution
  • Control and Monitoring Data Transport

The CobraNet interface performs synchronous-to-isochronous and isochronous-to-synchronous conversions as well as the data formatting required for transporting real-time digital audio over the network.

The CobraNet interface has provisions for carrying and utilizing control and monitoring data such as Simple Network Management Protocol (SNMP) through the same network connection as the audio. Standard data transport capabilities of Ethernet are shown here as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data communications and CobraNet applications can coexist on the same physical network.

Figure 1 illustrates the different data services available through the CobraNet system.

Ethernet Control Data Isochronous Data (Audio) Unregulated Traffic Clock

Figure 1. CobraNet Data Services

2.0 Features

2.1 CobraNet

• Real-time Digital Audio Distribution via Ethernet
- No Overall Limit on Network Channel Capacity
- Fully IEEE 802.3 Ethernet Standards Compliant
- Fiber optic and gigabit Ethernet variants are fully supported.
- Ethernet infrastructure can be used simultaneously for audio and data communications.
• Free CobraCAD™ Audio Network Design Tool
• High-quality Audio Sample Clock Delivery Over Ethernet
- Bit-transparent 16-, 20-, and 24-bit Audio Transport
• Professional 48-kHz and 96-kHz sample rate
- Select Latency as Low as 1.33ms
- Flexible Many-to-many Network Audio Routing Capabilities
- Reduced-cost, Improved-performance, Convergent Audio Distribution Infrastructure

2.2 CobraNet Interface

• 120 MIPS Customer-configurable Audio DSP
• Auto-negotiating 100Mbit Full-duplex Ethernet Connections
- Up to 32-channel Audio I/O Capability
- Implements CobraNet Protocol for real-time transport of audio over Ethernet.
- Local Management via 8-bit Parallel Host Port
- UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or RARP
- Remote Management via Simple Network Management Protocol (SNMP)
• Economical Three-chip Solution
• Available Module form factor allows for flexible integration into audio products.
• Non-volatile Storage of Configuration Parameters
- Safely Upgrade Firmware Over Ethernet Connection
• LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status
- Watchdog Timer Output for System Integrity Assurance
• Comprehensive Power-on Self-test (POST)
- Error and Fault Reporting and Logging Mechanisms

2.3 Host Interface

• 8-bit Data, 4-bit Address
• Virtual 24-bit Addressing with 32-bit Data
- Polled, Interrupt, and DMA Modes of Operation
- Configure and Monitor CobraNet Interface
• Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed

2.4 Asynchronous Serial Interface

• Full-duplex Capable
- 8-bit Data Format
• Supports all Standard Baud Rates

2.5 Synchronous Serial Audio Interface

• Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O
• 64FS (3.072 MHz) Bit Rate for CS18100x/CS49610x and CS18101x/CS49611x
  • 128FS (6.144 MHz) Bit Rate for CS18102x/CS49612x
• Accommodates Many Synchronous Serial Formats Including I ^2 S
  • 32-bit Data Resolution on All Audio I/O

2.6 Audio Clock Interface

• 5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface Design
  • Low-jitter Master Audio Clock Oscillator (24.576 MHz)
• Synchronize to Supplied Master and/or Sample Clock
• Sophisticated jitter attenuation assures network perturbations do not affect audio performance.

2.7 Audio Routing and Processing

• Single-channel Granularity in Routing From Synchronous Serial Audio Interface to CobraNet Network
• Two levels of inward audio routing affords flexibility in audio I/O interface design in the host system.
• Local Audio Loopback and Output Duplication Capability
• Peak-read Audio Metering with Ballistics

3.0 Hardware

Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture.

graph LR
    A["Clock"] --> B["VCXO"]
    C["Audio"] --> D["CS1810xx/CS4961xx"]
    E["Serial"] --> D
    F["Host"] --> D
    D --> G["Control"]
    H["Flash Memory"] --> I["Ethernet Controller"]
    I --> J["Ethernet Magnetics"]
    J --> K["Output"]
    style A fill:#fff,stroke:#333
    style C fill:#fff,stroke:#333
    style E fill:#fff,stroke:#333
    style F fill:#fff,stroke:#333
    style H fill:#fff,stroke:#333
    style I fill:#fff,stroke:#333
    style J fill:#fff,stroke:#333
    style K fill:#fff,stroke:#333

Figure 2. CobraNet Interface Hardware Block Diagram

Flash memory holds the CobraNet firmware and management interface variable settings.

The CS1810xx or CS4961xx network processor is the heart of the CobraNet interface. It implements the network protocol stacks and performs the synchronous-to-isochronous and isochronous-to-synchronous conversions. The network processor has a role in sample clock regeneration and performs all interactions with the host system.

The sample clock is generated by a voltage-controlled crystal oscillator (VCXO) controlled by the network processor. The VCXO frequency is carefully adjusted to achieve lock with the network clock.

The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast Ethernet standard. As per Ethernet requirements the interface is transformer isolated.

4.0 Pinout and Signal Descriptions

This section details the chip pinout and signal interfaces for each module and is divided as follows:

• "CS1810xx & CS4961xx Package Pinouts" on page 10
• "Host Port Signals" on page 12
• "Asynchronous Serial Port (UART Bridge) Signals" on page 12
• "Synchronous Serial (Audio) Signals" on page 13
  • "Audio Clock Signals" on page 13
  • "Miscellaneous Signals" on page 14
  • "Power and Ground Signals" on page 14
• "System Signals" on page 15

4.1 CS1810xx & CS4961xx Package Pinouts

4.1.1 CS1810xx/CS4961xx Pinout

Table 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces for these signals are expanded in the following sections.

Table 1. CS1810xx/CS4961xx Pin Assignments

Pin #	Pin Name	Pin #	Pin Name	Pin #	Pin Name	Pin #	Pin Name
1	VCXO_CTRL	37	DATA1	73	VDDIO	109	HADDR1
2	MCLK_SEL	38		74	ADDR10	110	HADDR0
3	DBDA	39	DATA0	75	ADDR14	111	HDATA7
4	DBCK	40	DATA15	76	GND	112	HDATA6
5	NC	41	DATA14	77	ADDR13	113	VDDIO
6	NC	42	DATA13	78	NC	114	HDATA5
7	NC	43	DATA12	79	NC	115	HDATA4
8	DAO_MCLK	44	VDDIO	80	NC	116	GND
9	TEST	45	DATA11	81	NC	117	HDATA3
10	VDDD	46	DATA10	82	ADDR15	118	HDATA2
11	HS3	47	GND	83	VDDD	119	VDDD
12	NC	48	DATA9	84	ADDR16	120	HDATA1
13	GND	49	DATA8	85	ADDR17	121	HDATA0
14	DAO2_LRCLK	50	NC	86	GND	122	GND
15	DAO1_DATA3	51	NC	87	ADDR18	123	XTAL_OUT
16	DAO1_DATA2/HS2	52	NC	88	ADDR19	124	XTO
17	DAO1_DATA1/HS1	53	NC	89		125	XTI
18	VDDIO	54	VDDD	90	1	126	GND_a
19	DAO1_DATA0/HS0	55	ADDR12	91	VDDIO	127	FILT2
20	DAO1_SCLK	56	ADDR11	92		128	FILT1
21	GND	57	GND	93		129	VDDA
22	DAO1_LRCLK	58	ADDR9	94	GND	130	VDDD
23	UART_TX_OE	59	ADDR8	95	WATCHDOG	131	DAI1_DATA3
24	VDDD	60	VDDIO	96	IOWAIT	132	DAI1_DATA2
25	UART_TXD	61	ADDR7	97	REFCLK_IN	133	GND
26	UART_RXD	62	ADDR6	98	VDDD	134	DAI1_DATA1
27	GND	63	GND	99	GPIO0	135	DAI1_DATA0
28	NC	64	ADDR5	100	GPIO1	136	VDDIO
29	DATA7	65	2	101	GND	137	DAI1_SCLK
30	DATA6	66	VDDD	102		138	DAI1_LRCLK
31	DATA5	67	ADDR4	103		139	GND
32	DATA4	68	ADDR3	104		140
33	VDDIO	69	GND	105	HADDR3	141	NC
34	DATA3	70	ADDR2	106	HADDR2	142	NC
35	DATA2	71	ADDR1	107	/W	143	IRQ1
36	GND	72	ADDR0	108	GPIO2	144	IRQ2

4.1.2 CM-2 Connector Pinout

Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The interfaces for these signals are expanded following the table.

Table 2. CM-2 Pin Assignments

Conn.	Pin #	Pin Name	Conn.	Pin #	Pin Name	Conn.	Pin #	Pin Name
J1/J2 A1	UART_RXD	J1/J2 B8 GND J3/J4	A15	DAI1_DATA3
J1/J2	A2	UART_TX_OE	J1/J2	B9	VCC_+3.3V	J3/J4	A16	RSVD3
J1/J2 A3	HACK		J1/J2 B10	GND J3/J4 A17	WATCHDOG
J1/J2 A4	HR/W		J1/J2 B11	VCC_+3.3V		J3/J4 A18	RSVD4
J1/J2 A5	HDS		J1/J2 B12	GND J3/J4 A19	AUX_POWER2
J1/J2 A6	HREQ		J1/J2	B13	VCC_+3.3V	J3/J4	A20	AUX_POWER0
J1/J2 A7	HEN		J1/J2 B14	GND J3/J4 B1 GND
J1/J2	A8	HADDR0	J1/J2	B15	VCC_+3.3V	J3/J4	B2	VCC_+3.3V
J1/J2 A9	HADDR1	J1/J2 B16	GND	J3/J4 B3	GND
J1/J2	A10	HADDR2	J1/J2	B17	VCC_+3.3V	J3/J4	B4	VCC_+3.3V
J1/J2	A11	HDATA0	J1/J2	B18	RSVD1	J3/J4	B5	GND
J1/J2	A12	HDATA1	J1/J2	B19	GND	J3/J4	B6	VCC_+3.3V
J1/J2	A13	HDATA2	J1/J2	B20	VCC_+3.3V	J3/J4	B7	GND
J1/J2	A14	HDATA3	J3/J4	A1	RSVD2	J3/J4	B8	VCC_+3.3V
J1/J2 A15	HDATA4		J3/J4 A2 MUTE			J3/J4 B9	GND
J1/J2	A16	HDATA5	J3/J4	A3	FS1	J3/J4	B10	VCC_+3.3V
J1/J2	A17	HDATA6	J3/J4	A4	MCLK_OUT	J3/J4	B11	GND
J1/J2 A18	HRESET		J3/J4 A5	MCLK_IN	J3/J4 B12	VCC_+3.3V
J1/J2	A19	HDATA7	J3/J4	A6	REFCLK_IN	J3/J4	B13	GND
J1/J2	A20	HADDR3	J3/J4	A7	DAO1_SCLK/DAI1_SCLK	J3/J4	B14	VCC_+3.3V
J1/J2	B1	UART_TXD	J3/J4	A8	DAO1_DATA0	J3/J4	B15	GND
J1/J2	B2	GND	J3/J4	A9	DAO1_DATA1	J3/J4	B16	GND
J1/J2	B3	VCC_+3.3V	J3/J4	A10	DAO1_DATA2	J3/J4	B17	VCC_+5V
J1/J2	B4	GND	J3/J4	A11	DAO1_DATA3	J3/J4	B18	VCC_+5V
J1/J2	B5	VCC_+3.3V	J3/J4	A12	DAI1_DATA0	J3/J4	B19	AUX_POWER3
J1/J2	B6	GND	J3/J4	A13	DAI1_DATA1	J3/J4	B20	AUX_POWER1
J1/J2 B7	VCC_+3.3V	J3/J4 A14	DATA2

4.2 Signal Descriptions

4.2.1 Host Port Signals

The host port is used to manage and monitor the CobraNet interface. Electrical operation and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this Manual.

The host port can operate in two modes in order to accommodate Motorola ^® or Intel ^® style interfaces. The default mode is Motorola. Intel mode is set via a firmware modification.

Table 2-1: Host Port Signals

Signal Description Direction			CM-2 Pin #	CS1810xx/ CS4961xx Pin #	Notes
HDATA[7:0]	Host Data	In/Out	J1:A19, A[17:11]	111, 112, 114, 115, 117, 118, 102, 121	Host port data.
HADDR[3:0]	Host Address	In	J1:A20, A[10:8]	105, 106, 109,110	Host port address.
HRW	Host Direction	In J1:A4		107 Host port transfer direction (Motorola mode).
HRD	Host Read	In	J1:A4	107	Host Read (Intel mode).
HREQ	Host Request	Out	J1:A6	140	Host port data request.
HACK	Host Alert	Out	J1:A3	102	Host port interrupt request.
HDS	Host Strobe	In	J1:A5	103	Host port strobe (Motorola mode).
HWR	Host Write	In	J1:A5	103	Host Write (Intel mode).
HEN Host	Enable In J1:A7		104	Host Port Enable.
HCS	Select	In	J1:A7	104	Select (Intel mode).

4.2.2 Asynchronous Serial Port (UART Bridge) Signals

Level-shifting drive circuits are typically required between these signals and any external connections.

Signal	Description	Direction	CM-2 Pin #	CS1810xx/ CS4961xx Pin #	Notes
UART_RXD	Asynchronous Serial Receive Data	In	J1:A1	26	Pull-up to VCC if unused.
UART_TXD	Asynchronous Serial Transmit Data	Out	J1:B1	25
UART_TX_OE	Transmit Drive Enable	Out	J1:A2	23	Enable transmit (active high) drive for two wire multi-drop interface.

4.2.3 Synchronous Serial (Audio) Signals

The synchronous serial interfaces are used to bring digital audio into and out of the system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing and format is described in "Digital Audio Interface" on page 19.

Signal Description Direction		CM-2 Pin #	CS1810xx/ CS4961xx Pin #	Notes
DAO1_SCLK Audio Bit Clock Out J3:A7 20				Synchronous serial bit clock.64 FS for CS18100x & CS49610x (2x1 channel)64 FS for CS18101x & CS49611x (2x4 channels)128 FS for CS18102x & CS49612x (4x4 channels)Typically tied to DAI1_SCLK.
DAO1_DATA[3:0]	Audio Output Data	Out	J3:A18, B18	Output synchronous serial audio data DAO1_DATA[3:1] not used for CS18100x & CS49610x.
DAI1_DATA[3:0]	Audio Input Data In		J3: A[15:12]	Input synchronous serial audio data DAI1_DATA[3:1] not used for CS18100x & CS49610x.
DAI1_SCLK	Audio Bit Clock	In	J4:A7	Should be tied to DAO1_SCLK.Synchronous serial bit clock.

4.2.4 Audio Clock Signals

See "Synchronization" on page 17 for an overview of synchronization modes and issues.

Signal	Description	Direction	CM-2 Pin #	CS1810xx/ CS4961xx Pin #	Notes
DAI1_LRCLK	Sample clock input	In		138	Should be tied to DAO1_LRCLK for all devices.
DAO1_LRCLK (FS1)	Sample clock output	Out	J3:A3	22	FS1 (word clock) for CS18100x/CS49610x and CS18101x/CS49611x.
DAO2_LRCLK (FS1)	Sample clock output	Out	J3:A3	14	FS1 (word clock) for CS18102x & CS49612x.
REFCLK_IN	Reference clock	In	J3:A6	97	Clock input for synchronizing network to an external clock source, for redundancy control and synchronization of FS divider chain to external source. See "Synchronization" on page 17 for more detail.
MCLK_IN	Master audio clock input	In	J3:A5	8*	For systems featuring multiple CobraNet interfaces operating off a common master clock. See "Synchronization" on page 17 for more detail.
MCLK_OUT	Master audio clock output	Out	J3:A4	8*	Low jitter 24.576 MHz master audio clock.

*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out implementation.

4.2.5 Miscellaneous Signals

Signal Description Direction			CM-2 Pin #	CS1810xx/ CS4961xx Pin #	Notes
Reset In		J1:A18		93	System reset (active low). 10 ns max rise time. 1 ms min assertion time.
WATCHDOG Watch Dog Out J3:A17 95					Toggles at 750 Hz nominal rate to indicate proper operation. Period duration in excess of 200 ms indicates hardware or software failure has occurred and the interface should be reset. Note that improper operation can also be indicated by short pulses (<100 ns).
	Interface Ready	Out J3:A2		92	Asserts (active low) during initialization and when a fault is detected or connection to the network is lost.
NC	No Connect	-	-	28, 50-53, 78-81, 141, 142

4.2.6 Power and Ground Signals

Signal	Description	CM-2 Pin #	CS1810xx/CS4961xx Pin #	Specification
VCC_+3V	System Digital +3.3 v	J1:B20, B17, B15, B13, B11, B9, B7, B5, B3J3:B14, B12, B10, B8, B6, B4, B2	N/A	3.3 ± 0.3v, 500 mA Typ., 750 mA Max.
VCC_+5V		J3;B[18:17]	N/A	Backwards Compatibility
VDDD		N/A	10, 24, 54, 66, 83, 98, 119, 130	+1.8 V @ 500mA Typ. for Core Logic
VDDIO		N/A	18, 33, 44, 60, 73, 91, 113, 136	+3.3 V @ 120mA Typ. for I/O Logic
VDDA		N/A	129	Filtered +1.8 V @ 10mA Typ.
AUX_POWER [3-0]		J3:B[20:19], A[20:19]	N/A
GND	Digital Ground	J1:B19, B16, B14, B12, B10, B8, B6, B4, B2J3:B16, B15, B13, B11, B9, B7, B5, B3, B1	13, 21, 27, 36, 47, 57, 63, 69, 76, 86, 94, 101, 116, 122, 126, 133, 139

4.2.7 System Signals

Use these CS1810xx/CS4961xx signals strictly in the manner described in CM-2 Schematics (Section 9.2 on page 44). Each signal is briefly described below.

Signal Description		CS1810xx/CS4961xx Pin #
VCXO_CTRL A Delta-sigma DAC Output for Controlling the On-board VCXO 1
MCLK_SEL Control Signal for Selecting MCLK Sources 2
DBDA, DBCK I2C Debugger Interface 3, 4
TEST	Used for testing during manufacturing. Keep grounded for normal operation.	9
DATA[15:0] Data Bus for Flash & Ethernet Controller(s)		29-32, 34, 35, 37, 39-43, 45, 46, 48, 49
ADDR[19:0] Address Bus for Flash & Ethernet Controller(s)		55, 56, 58, 59, 61, 62, 64, 67, 68, 70-72, 74, 75, 77, 82, 84, 85, 87, 88
WE	Write Enable for Flash and Ethernet Controller(s)	38
1	Chip Select for Flash Memory Device	90
2	Chip Select for Ethernet Controller(s)	65
	Output Enable	89
IOWAIT	Wait State Signal from Ethernet Controller(s)	96
GPIO[2:0]	General-purpose I/O Signals	99, 100, 108
XTI	Reference Clock Input / Crystal Oscillator Input	125
XTO	Crystal Oscillator Output	124
XTAL_OUT	A Buffered Version of XTI	123
FILT2, FILT1	PLL Loop Filter	127, 128
DAO_MCLK	MCLK Input	8
HS[3:0]	CS1810xx/CS4961xx Boot Mode Selection	11, 16, 17, 19

4.3 Characteristics and Specifications

4.3.1 Absolute Maximum Ratings

Parameter	Symbol	Min	Max	Unit
DC power supplies: Core supply	VDD	-0.3	2.0	V
	VDDA	-0.3	2.0	V
	VDDIO	-0.3	5.0	V
		-	0.3	V
Input current, any pin except supplies I	in	-	+	/
Input voltage on FILT1, FILT2	V_filt		2.0	V
Input voltage on I/O pins	V_inio	-	5.0	V
Storage temperature	T_stg	-65 150	°C

Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

4.3.2 Recommended Operating Conditions

Parameter		Symbol	Min	Typ	Max	Unit
DC power supplies:	Core supply	VDD	1.71	1.8	1.89	V
	PLL supply	VDDA	1.71	1.8	1.89	V
	I/O supply	VDDIO	3.13	3.3	3.46	V
	|VDDA – VDD|				0.3	V
Ambient operating temperature		T_A		-		°C
	- CQ		0		+ 70
	- DQ		- 40		+ 85

4.3.3 Digital DC Characteristics

(measurements performed under static conditions.)

Parameter	Symbol	Min	Typ	Max	Unit
High-level input voltage	V_IH	2.0	-	-	V
Low-level input voltage, except XTI	V_IL	-	-	0.8	V
Low-level input voltage, XTI	V_ILXTI	-	-	0.6	V
Input Hysteresis	V_hys		0.3		V
High-level output voltage at I_O = -8.0 mA_O = -16.0 mA	V_OH	VDDIO * 0.9	-	-	V
Low-level output voltage at I_O = 8.0 mA_O = -16.0 mA	V_OL	-	-	VDDIO * 0.1	V
Input leakage current (all pins without internal pull-up resistors except XTI)	I_IN	-	-	5	μA
Input leakage current (pins with internal pull-up resistors, XTI)	I_IN-PU	-	-	50	μA

4.3.4 Power Supply Characteristics

(measurements performed under operating conditions))

Parameter	Min	Typ	Max	Unit
Power supply current:Core and I/O operating: VDD (Note 1)	-	500	-	mA
PLL operating: VDDA	-	10	-	mA
With external memory and most ports operating: VDDIO	-	120	-	mA

NOTES:1. Dependent on application firmware and DSP clock speed.

5.0 Synchronization

Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design (CM-2). This circuitry allows the synchronization modes documented below to be achieved. Modes are distinguished by different settings of the multiplexors and software elements.

graph TD
    A["DAC"] --> B["VCXO 24.576 MHz"]
    B --> C["Sample Phase Counter"]
    C --> D["Audio Clock Generator"]
    D --> E["FS1"]
    D --> F["SLCK"]
    G["MCLK_IN"] --> C
    H["MCLK_SEL"] --> C
    I["MCLK_SEL"] --> C
    J["RefClkEnable"] --> C
    K["RefClkPolarity"] --> C
    L["REFCLK_IN"] --> C
    M["BeatReceived"] --> N["Phase Detector"]
    N --> O["Loop Filter"]
    P["External Hardware Component (CM2)"] --> N
    Q["Internal Hardware Component (CS1810xx, CS4961xx)"] --> N
    R["Software Component"] --> N
    S["MCLK_OUT"] --> D

Figure 3. Audio Clock Sub-system

5.1 Synchronization Modes

Clock synchronization mode for conductor and performer roles is independently selectable via management interface variables syncConductorClock and syncPerformerClock. The role (conductor or performer) is determined by the network environment including the conductor priority setting of the device and the other devices on the network. It is possible to ensure you will never assume the conductor role by selecting a conductor priority of zero. However, it is not reasonable to assume that by setting a high conductor priority, you will always assume the conductor role. For more information, refer to CobraNet Programmer's Reference Manual.

The following synchronization modes are further described below:

• "Internal Mode" on page 18
• "External Word Clock Mode" on page 18
• "External Master Clock Mode" on page 18

5.1.1 Internal Mode

All CobraNet clocks are derived from the onboard VCXO. The master clock generated by the VCXO is available to external circuits via the master clock output.

Conductor—The VCXO is "parked" according to the syncClockTrim setting.

Performer—The VCXO is “steered” to match the clock transmitted by the Conductor.

5.1.2 External Word Clock Mode

All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an external clock supplied to the reference clock input. The clock supplied can be any integral division of the sample clock in the range of 750Hz to 48kHz.

External synchronization lock range: ±5 s . This specification indicates drift or wander between the supplied clock and the generated network clock at the conductor. Absolute phase difference between the supplied reference clock and generated sample clock is dependant on network topology.

Conductor—This mode gives a means for synchronizing an entire CobraNet network to an external clock.

Performer—The interface disregards the fine timing information delivered over the network from the conductor. Coarse timing information from the conductor is still used; fine timing information is instead supplied by the reference clock. The external clock source must be synchronous with the network conductor. This mode is useful in installations where a house sync source is readily available.

5.1.3 External Master Clock Mode

The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a "hard" synchronization mode. The supplied clock is used directly by the CobraNet interface for all timing. This mode is primarily useful for devices with multiple CobraNet interfaces sharing a common master audio clock. The supplied clock must be 24.576 MHz. The supplied clock must have a ±37 ppm precision.

Conductor—The entire network is synchronized to the supplied master clock.

Performer—The node will initially lock to the network clock and will “jam sync” via the supplied master clock. The external clock source must be synchronous with the network conductor.

6.0 Digital Audio Interface

The CS18101x/CS49611x, CS18102x/CS49612x, and CM-2 support four bi-directional synchronous serial interfaces. The CS18100x & CS49610x support one bi-directional synchronous serial interface. All interfaces operate in master mode with DAO1_SCLK as the bit clock and FS1 as the frame clock. A sample period worth of synchronous serial data includes two (or four) audio channels. CobraNet supports two synchronous serial bit rates: 48 Khz and 96 KHz. However, 96 kHz sample rate is not available when using CS18102x/CS49612x with 16X16 channels. Bit rate is selected by the modeRateControl variable. All synchronous serial interfaces operate from a common clock at the same bit rate.

FS1 DAO1_DATA0 / DAI1_DATA0 1 2 *DAO 1_D ATA1 / DAI1_DATA1 3 4 *DAO 1_D ATA2 / DAI1_DATA2 5 6 *DAO 1_D ATA3 / DAI1_DATA3 7 8

* Not present in CS18100x or CS49610x.

Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x & CS18101x/CS49611x

FS1 DAO1_DATA0 / DAI1_DATA0 1 2 3 4 DAO1_DATA1 / DAI1_DATA1 5 6 7 8 DAO1_DATA2 / DAI1_DATA2 9 10 11 12 DAO1_DATA3 / DAI1_DATA3 13 14 15 16

Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x

Default channel ordering is shown above. Note that the first channel always begins after the rising or falling edge of FS1 (depending on the mode).

DAI1_SCLK period depends on the sample rate selected. Up to 32 significant bits are received and buffered by the DSP for synchronous inputs. Up to 32 significant bits are transmitted by the DSP for synchronous outputs. Bit 31 is always the most significant (sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits 15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic recommends driving unused LS bits to zero.

Although data is always transmitted and received with a 32-bit resolution by the synchronous serial ports, the resolution of the data transferred to/from the Ethernet may be less. Incoming audio data is truncated to the selected resolution. Unused least significant bits on outgoing data is zero filled.

6.1 Digital Audio Interface Timing

MCLK_OUT DAO1_SCLK FS1 0 - 5ns 0 - 10ns

Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1

An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows a MCLK_OUT edge by 0.0 to 10.0ns.

Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends on power up timing.

DAO1_SCLK DAI1_DATAx DAO1_DATAx ≥5ns ≥0ns 0 - 12ns

Figure 7. Serial Port Data Timing Overview

Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the edge of DAO1_SCLK.

6.1.1 Normal Mode Data Timing

DAI1_SCLK FS1 DAI1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23

Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

DAI1_SCLK FS1 DAI1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 2: DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 22 21 20 19 18 17 16 15 14 13-12-11-10-9-8-7-6-5-4-3-2-1-0 Unused 2:

Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102x/CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The figure above shows 24-bit audio data.

The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge.

6.1.2 I ^2 S Mode Data Timing

DAI1_SCLK FS1 DAI1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23

Figure 10. Audio Data Timing Detail - I²S Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

DAI1_SCLK FS1 DAI1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 2 DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 22 21 20 19 18 17 16 15 14 13-12-11-10-9-8-7-6-5-4-3-2-1-0 Unused 2

Figure 11. Audio Data Timing Detail - I²S Mode, 128FS - CS18102x & CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The figure above shows 24-bit audio data.

The MSB is left justified and arrives one bit period following FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge.

6.1.3 Standard Mode Data Timing

DAI1_SCLK FS1 DAI1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23

Figure 12. Audio Data Timing Detail - Standard Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

DAI1_SCLK FS1 DAI1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 2 DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused 23 22 21 20 19 18 17 16 15 14 13-12-11-10-9-8-7-6-5-4-3-2-1-0 Unused 2

Figure 13. Audio Data Timing Detail - Standard Mode, 128FS - CS18102x/CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The figure above shows 24-bit audio data.

The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge.

7.0 Host Management Interface (HMI)

7.1 Hardware

The host port is 8 bits wide with 4 bits of addressing. Ten of the 16 addressable registers are implemented. The upper two registers can be used to configure and retrieve the status on the host port hardware. However, only the first 8 are essential for normal HMI communications. It is therefore feasible, in most applications, to utilize only the first 3 address bits and tie the most significant bit (A3) low.

Host port hardware supports Intel ^® (little-endian), Motorola ^® , and Motorola multiplexed bus (big-endian) protocols. Standard CobraNet firmware configures the port in the Motorola, big-endian mode.

The host port memory map is shown in Table 3. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34.

Host Address Register
0 Message A (MS)
1 Message B
2 Message C
3 Message D (LS)
4 Data A (MS)
5 Data B
6 Data C
7 Data D (LS)
8 Control
9 Status

Table 3. Host port memory map

The message and data registers provide separate bi-directional data conduits between the host processor and the CS1810xx/CS4961xx. A 32-bit word of data is transferred to the CS1810xx/CS4961xx when the host writes the D message or data register after presumably previously writing the A, B, and C registers with valid data. Data is transferred from the CS1810xx/CS4961xx following a read of the D message or data register. Again, presumably the A, B, and C registers are read previously.

Two additional hardware signals are associated with the host port: HACK and HREQ. Both are outputs to the host.

HACK may be wired to an interrupt request input on the host. HACK can be made to assert (logic 0) on specific events as specified by the hackEnable MI variable. HACK is deasserted (logic 1) by issuance of the Acknowledge Interrupt message (see "Messages" below).

HREQ may be wired to a host interrupt or DMA request input. HREQ is used to signal the host that data is available (read case, logic 0) or space is available in the host port data channel (write case, logic 1).

The read and write case are distinguished by the HMI based on the preceding message. Identify, Goto Translation (read), Goto Packet (read) and Goto Counters cause HREQ to represent read status. Goto Translation (write) and Goto Packet (write) switch HREQ to write mode. All other commands have no effect on HREQ operation.

In general, the host can read from the CS1810xx/CS4961xx when is low and can write data to CS1810xx/CS4961xx when is high.

7.2 Host Port Timing - Motorola® Mode

(C_L=20 pF)

Parameter Symbol Min Max Unit
Address setup before and low t	mas	5	-	ns
Address hold time after and low t	mah	5	-	ns
Read
Delay between then low or then low	t_mcdr	0	-	ns
Data valid after and low with HR high t	mdd	-	19	ns
and low for read	t_mrpw	24	-	ns
Data hold time after or high after read	t_mdhr	8	-	ns
Data high-Z after or high after read	t_mdis	-	18	ns
or high to and low for next read	t_mrd	30	-	ns
or high to and low for next write	t_mrdtw	30	-	ns
HR/ rising to falling	t_mrwirqh	-	12	ns
Write
Delay between then low or then low	t_mcdw	0	-	ns
Data setup before or high	t_mdsu	8	-	ns
and low for write	t_mwpw	24	-	ns
HR setup before and low	t_mrwsu	24	-	ns
HR hold time after or high	t_mrwhld	8	-	ns
Data hold after or high	t_mdhw	8	-	ns
or high to and low with HR high for next read	t_mwtrd	30	-	ns
or high to and low for next write	t_mwd	30	-	ns
HR rising to falling	t_mrwbsyl	-	12	ns

NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed to prevent overflowing the input data buffer.

HADDR[3:0] HDATA[7:0] HEN HRW HDS HREQ LSP MSP t_mas t_mah t_mdd t_mdhr t_mdr t_mdis t_mrwsu t_mcdr t_mrpw t_mrd t_mrwtw t_mrwrqh

Figure 14. Host Port Read Cycle Timing - Motorola Mode

HADDR[3:0] HDATA[7:0] LSP MSP t_mas t_mah t_mdsu t_mdhw HEN t_mcdw t_mwpw t_mrwhld HRW t_mrwsu t_mwd t_mwtrd HDS HREQ t_mrwire1

Figure 15. Host Port Write Cycle Timing - Motorola Mode

7.3 Host Port Timing - Intel® Mode

(C_L = 20pF)

Parameter Symbol Min Max Unit
Address setup before and low or and low	t_ias	5	-	ns
Address hold time after and low or and high	t_iah	5	-	ns
Read
Delay between then low or then low	t_icdr	0	-	ns
Data valid after and low t	_idd	-	1
and low for read t	_irpw	24	-	ns
Data hold time after or high	t_idhr	8	-	ns
Data high-Z after or high	t_idis	-	1
or high to and low for next read	t_ird	30	-	ns
or high to and low for next write	t_irdtw	30	-	ns
rising to rising	t_irdirqhl	-	1
Write
Delay between then low or then low	t_icdw	0	-	ns
Data setup before or high	t_idsu	8	-	ns
and low for write	t_iwpw	24	-	ns
Data hold after or high t	_idhw	8	-	ns
or high to and low for next read	t_iwtrd	30	-	ns
or high to and low for next write	t_iwd	30	-	ns
rising to falling	t_iwrbsyl	-	1

NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed to prevent overflowing the input data buffer.

HADDR[3:0] HDATA[7:0] t_iah LSP t_idhr MSP HCS t_ies t_idd t_idls HWR t_lrpw t_lrd t_lrdtw HRD t_rdirqh HREQ

Figure 16. Parallal Control Port - Intel Mode Read Cycle

HADDR[3:0] HDATA[7:0] HCS HRD HWR HREQ t_ias t_iah LSP MSP t_idhw t_icdw t_idsu t_iwpw t_iwd t_iwtrd t_iwrbsyl

Figure 17. Parallel Control Port - Intel Mode Write Cycle

7.4 Protocol and Messages

The message conduit is used to issue commands to the CS1810xx/CS4961xx and retrieve HMI status. The data conduit is used to transfer data dependent on the HMI state as determined by commands issued by the host via the message conduit.

7.4.1 Messages

Messages are used to efficiently invoke action in the CS1810xx/CS4961xx. To send a message, the host optionally writes to the A, B, and C registers. Writing to the D register transmits the message to the CS1810xx/CS4961xx. A listing of all HMI messages is shown in Table 4. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34.

Message	DRQ Handshake Mode	A B C D
Translate Address	n/c	Address (MS)	Address	Address (LS)	0xB3
Acknowledge Interrupt	n/c	n/c	n/c	n/c	0xB4
Identify	read	n/c	n/c	7	0xB5
Goto Packet Transmit Buffer	write	n/c	n/c	6	0xB5
Goto Translation	write	n/c	n/c	5	0xB5
Acknowledge Packet Receipt	n/c	n/c	n/c	4	0xB5
Transmit Packet	n/c	n/c	n/c	3	0xB5
Goto Counters	read	n/c	n/c	2	0xB5
Goto Packet Receive Buffer	read	n/c	n/c	1	0xB5
Goto Translation	read	n/c	n/c	0	0xB5

Table 4. HMI messages

7.4.1.1. Translate Address

Translate Address does not actually update the address pointers but initiates the processing required to eventually move them. The host can accomplish other tasks, including HMI Reads and Writes while the address translation is being processed. A logical description of Translate Address is given below. A contextual use of the Translate Address operation is shown in the reference implementations. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34.

void TranslateAddress(
    long address )
{
    int msgack = MSG_D;
    MSG_A = (address & 0xff0000) >> 16;
    MSG_B = (address & 0xff00) >> 8;
    MSG_C = address & 0xff;
    MSG_D = CVR_TRANSLATE_ADDRESS;
    while (!((msgack ^ MSG_D) & (1 << MSG_TOGGLE_BO));
} 

7.4.1.2. Interrupt Acknowledge

Causes HACK to be de-asserted.

void InterruptAck( void )
{
    int msgack = MSG_D;
    MSG_D = CVR_INTERRUPT_ACK;
    while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
} 

7.4.1.3. Goto Packet

Moves HMI pointers to bridgeRxPktBuffer (write = 0) or bridgeTxPktBuffer (write = 1).

void GotoPacket(
    bool write )
{
    int msgack = MSG_D;
    MSG_C = write ? MOP_GOTO_PACKET_TRANSMIT : MOP_GOTO_PACKET_RECEIVE;
    MSG_D = CVR_MULTIPLEX_OP;
    while (!((msgack ^MSG_D) & (1 << MSG_TOGGLE_BO)));
} 

7.4.1.4. Goto Translation

Moves HMI data pointers to the results of the most recently completed translate address operation. The write parameter dictates the operation of the HREQ signal and only needs to be supplied for applications using hardware data handshaking via this signal.

void GotoTranslation(
    bool write = 0 )
{
    int msgack = MSG_D;
    MSG_C = write ? MOP_GOTO_TRANSLATION_WRITE : MOP_GOTO_TRANSLATION_READ;
    MSG_D = CVR_MULTIPLEX_OP;
    while (!((msgack ^MSG_D) & (1 << MSG_TOGGLE_BO)));
} 

7.4.1.5. Packet Received

Sets bridgeRxPkt = bridgeRxReady thus acknowledging receipt of the packet in bridgeRxPktBuffer.

void PacketReceive( void )
{
    int msgack = MSG_D;
    MSG_C = MOP_PACKET_RECEIVE;
    MSG_D = CVR_MULTIPLEX_OP;
    while (!((msgack ^MSG_D) & (1 << MSG_TOGGLE_BO));
} 

7.4.1.6. Packet Transmit

Sets bridgeTxPkt = bridgeTxPktDone+1 thus initiating transmission of the contents of bridgeTxPktBuffer. Presumably bridgeTxPktBuffer has been previously written with valid packet data.

void PacketTransmit( void )
{
    int msgack = MSG_D;
    MSG_C = MOP_PACKET_TRANSMIT;
    MSG_D = CVR_MULTIPLEX_OP;
    while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
} 

7.4.1.7. Goto Counters

Moves HMI data pointers to interrupt status variables (beginning at hackStatus).

void GotoCounters( void )
{
    int msgack = MSG_D;
    MSG_C = MOP_GOTO_COUNTERS;
    MSG_D = CVR_MULTIPLEX_OP;
    while (!((msgack ^MSG_D) & (1 << MSG_TOGGLE_BO));
} 

7.4.2 Status

HMI status can always be retrieved by reading the message conduit. Status is updated in a pipelined manner whenever the Message D register is read. Reading the message conduit gives the current status as of the last time the conduit was read. Bitfields in the HMI Status Register are outlined in Table 5 below. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34.

Status Bit(s)
Reserved [31:24]
Region Length [23:8]
Reserved [7:5]
Writable Region 4
Translation Complete 3
Packet Transmission Complete 2
Received Packet Available 1
Message Togglebit	0

Table 5. HMI status bits

7.4.3 Data

Before accessing data, address setup must be performed. Address setup consists of issuing a Translate Address request, waiting for the request to complete, then issuing a Goto Translation.

Pipelining requires that a “garbage read” be performed following an address change. The second word read contains the data for the address requested. No similar pipelining issue exists with respect to write operations.

7.4.3.1. Region length

Distance from the original pointer position (as per Translate Address) to the end of the instantiated region. A value of 0 indicates an invalid pointer.

7.4.3.2. Writable Region

When set, this bit indicates the address pointer is positioned within a writable region. MI variables may be modified in a writable region by writing data to the data conduit.

7.4.3.3. Translation Complete

When set, this bit indicates that the address translator is available (translation results are available and a new translation request may be submitted). This bit is cleared when a Translate Address message is issued and is set when the translation completes.

7.4.3.4. Packet Transmission Complete

This bit is cleared when transmission is initiated by issuance of the Transmit Packet message. The bit is set when the packet has been transmitted and the transmit buffer is ready to accept a new packet.

7.4.3.5. Received Packet Available

This bit is set when a packet is received into the packet bridge. It is cleared when the packet data is read and receipt is acknowledged by issuance of an Acknowledge Packet Receipt message. Note that Received Packet Available only goes low when there are no longer any pending received packets for the packet bridge. The packet bridge has the capacity to queue multiple packets in the receive direction.

7.4.3.6. Message Togglebit

This bit toggles on completion of processing of each message. A safe means for the host to acknowledge processing of messages is as follows:

void WaitToggle( void )
{
    int msgack = MSG_D; /* clean pipeline */
    msgack = MSG_D; /* record current state of togglebit */
    MSG_D = YOUR_COMMAND_HERE; /* issue command */
    /* wait for togglebit to flip */
    while (!((msgack ^MSG_D) & (1 << MSG_TOGGLE_BO));
} 

8.0 HMI Reference Code

The following C code provides examples in using HMI messages, HMI status, and the HMI memory map.

8.1 HMI Definitions

/*
** hmi.h
** CobraNet Host Management Interface example code
** Definitions
**
** Header
** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc.
**================*/
#define MSG_A 0
#define MSG_B 1
#define MSG_C 2
#define MSG_D 3
#define DATA_A 4
#define DATA_B 5
#define DATA_C 6
#define DATA_D 7
#define CONTROL 8
#define STATUS 9

#define CVR_SET_ADDRESS 0xb2    /* Not availbale on CS1810xx/CS4961xx/CM-2. */
    /*CM-1 and Reference Design only. */
#define CVR_TRANSLATE_ADDRESS 0xb3
#define CVR_INTERRUPT_ACK 0xb4
#define CVR_MULTIPLEX_OP 0xb5

#define MOP_GOTO_TRANSLATION_READ 0
#define MOP_GOTO_TRANSLATION_WRITE 5
#define MOP_GOTO_PACKET_RECEIVE 1
#define MOP_GOTO_PACKET_TRANSMIT 6
#define MOP_GOTO_COUNTERS 2
#define MOP_PACKET_TRANSMIT 3
#define MOP_PACKET_RECEIPT 4
#define MOP_IDENTIFIERY 7

#define MSG_TOGGLE_BO 0
#define MSG_RXPACKET_BO 1
#define MSG_TXPACKET_BO 2
#define MSG_TRANSLATION_BO 3
#define MSG_WRITABLE_BO 4
#define MSG_LENGTH_BO 8 

8.2 HMI Access Code

/*
** hmi.c
** CobraNet Host Management Interface example code
** Simple edition
**
** Header
** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc.
**----*/
#include "hmi.h"

/* variables model HMI state */
long PeekLimit;
long PeekPointer = -1;
long PokeLimit;
long PokePointer = -1;

/* access host port hardware */
#define HMI_BASE 0

unsigned char ReadRegister(
    int hmiregister )
{
    return *(unsigned char volatile *const) ( hmiregister + HMI_BASE );
}

void WriteRegister(
    int hmiregister,
    unsigned char value )
{
    *(unsigned char volatile *const) ( hmiregister + HMI_BASE ) = value;
}

void SendMessage(
    unsigned char message )
{
    int msgack = ReadRegister( MSG_D );
    /* issue (last byte of) message */
    WriteRegister( MSG_D, message );
    /* wait for acceptance of message */
    while( !( ( msgack ^ ReadRegister( MSG_D ) ) & ( 1 << MSG_TOGGLE_BO ) ) );
}

void SetAddress(
    long address )
{
    /* translate address */
    WriteRegister( MSG_A, ( address & 0xff0000 ) >> 16 );
    WriteRegister( MSG_B, ( address & 0xff00 ) >> 8 );
    WriteRegister( MSG_C, address & 0xff );
    SendMessage( CVR_TRANSLATE_ADDRESS );
    /* wait for completion of translate address */ 

while( !( ReadRegister(MSG_D) & ( 1 << MSG_TRANSLATION_BO ) ) );
    /* goto translation */
    WriteRegister(MSG_C, MOP_GOTO_TRANSLATION_READ );
    SendMessage(CVR_MULTIPLEX_OP );
    /* "garbage" read clears data pipeline */
    ReadRegister(DATA_D);
    /* maintain local pointers */
    PeekPointer = PokePointer = address;
    PeekLimit = PokeLimit = PeekPointer +
    ReadRegister(MSG_C) + ( ReadRegister(MSG_B) << 8 );
    /* read-only region addressed */
    if( !( ReadRegister(MSG_A) & ( 1 << MSG_WRITABLE_BO ) ) {
    PokeLimit = PokePointer;
    }
}

unsigned long Peek(
    long address )
{
    if( address != PeekPointer ) {
    SetAddress(address );
    }
    if( PeekPointer >= PeekLimit ) {
    throw "Peek addressing error!";
    }
    unsigned long value = ReadRegister(DATA_A) << 24;
    value += ReadRegister(DATA_B) << 16;
    value += ReadRegister(DATA_C) << 8;
    value += ReadRegister(DATA_D);
    PeekPointer++; /* maintain local pointer */
    return value;
}

void Poke(
    long address,
    unsigned long value )
{
    if( address != PokePointer ) {
    SetAddress(address );
    }
    if( PokePointer >= PokeLimit ) {
    throw "Poke addressing error or read-only!";
    }
    WriteRegister(DATA_A, (unsigned char) (( value >> 24 ) & 0xff ) );
    WriteRegister(DATA_B, (unsigned char) (( value >> 16 ) & 0xff ) );
    WriteRegister(DATA_C, (unsigned char) (( value >> 8 ) & 0xff ) );
    WriteRegister(DATA_D, (unsigned char) (value & 0xff ) );
    /* maintain local pointers */
    PokePointer++;
    PeekPointer = -1; /* force SetAddress()next Peek() to freshen data */
} 

8.3 CM-1, CM-2 Auto-detection

The following function is useful for systems that support both the CM-1 and CM-2 or where a CobraNet interface is an optional add-in.

Detect() returns 0 if no CobraNet interface module is detected, 1 for CM-1 and 2 for CM-2.

int Detect( void ) {
    /* check for presence of CM-1 */
    MSG_B = 0x55; /* write to CM-1 CVR register */
    DATA_A = 0xaa; /* write to unused CM-1 register to flip data bus */
    if (MSG_B == 0x55) { /* read back CVR */
    /* redo same detection with different data */
    MSG_B = 0x3c;
    DATA_A = 0xc3;
    if (MSG_B == 0x3c) {
    return 1; /* CM-1 detected */
    }
    }
    /* check for presence of CM-2 */
    /* issue identify command */
    MSG_C = MOP_IDENTIFIER;
    MSG_D = CVR_MULTIPLEX_OP;
    int msgack = MSG_D; /* clean pipeline */
    msgack = MSG_D;
    /* wait for togglebit to flip in response to command */
    int tm0 = gettimeofday();
    while (!((MSG_D^ toggle) & (1 << MSG_TOGGLE_BO)) {
    int tm1 = gettimeofday();
    if ((tm1 - tm0) > time_out) {
    return 0; /* command timed out, no CobraNet interface present */
    }
    }
    int garbage = MSG_D; /* clean pipeline */
    /* verify identify results */
    if (DATA_A == 'C') if (DATA_B == 'S')
    if (DATA_C == (18101 >> 8)) if (DATA_D == (18101&0xff) {
    return 2; /* CM-2 detected */
    }
    return 0; /* no interface or non-supported interface */
} 

9.0 Mechanical Drawings and Schematics

The section contains detailed drawings of the CM-2 board and CS1810xx/CS4961xx device package design. The mechanical drawings are arranged as follows:

• "CM-2 Module Assembly Drawing, Top" on page 38
• "General PCB Dimensions" on page 40
• "Example Configuration, Side View" on page 41
  • "Faceplate Dimensions" on page 42
• "Connector Detail" on page 43
• "CM-2 RevF Schematic Page 1 of 7" on page 44
• "CM-2 RevF Schematic Page 2 of 7" on page 45
• "CM-2 RevF Schematic Page 3 of 7" on page 46
• "CM-2 RevF Schematic Page 4 of 7" on page 47
• "CM-2 RevF Schematic Page 5 of 7" on page 48
• "CM-2 RevF Schematic Page 6 of 7" on page 49
• "CM-2 RevF Schematic Page 7 of 7" on page 50
• "144-Pin LQFP Package Drawing" on page 51

9.1 CM-2 Mechanical Drawings

Faceplate (not part of the PCB) 3540 (mil) Cobranet Module CM-2 Rev. E Cirrus Logic, Inc. 2500 55th Street Suite 210 Boulder, CO 80301 Cobranet Module CM-2 Rev. F 27-Oct-2004 (C) 2003, Cirrus Logic, Inc. Meph@recabyLayer 2 Stack Order: -- 6 LAYER DESIGN -- 6 MIL TRACES / AIR GAP -- SOLDER MASK OVER BARE COPPER (0.5 OZ) BLUE, BOTH SIDES -- SILKSCREEN, BOTH SIDES, WHITE -- FR4, FINISHED BOARD THICKNESS 0.062 -- NOMINAL DIELECTRIC CONSTANT OF 4.5 -- Note: 8 pairs of 47mil non-plated holes do overlap Cirrus Logic, Inc. Confidential

Figure 18. CM-2 Module Assembly Drawing, Top
NOT TO SCALE

Cobranet Module CM-2 Rev. E 3540 (w1) → Lecbiplis (ou bact of this BCB) 3500 (w1) Cobranet / Dali / Dc - [cat/hag]s] Note: 8 bacts of 45W1 you-bisig poser po oveljib --- Importance Electrical Constant Of 4.2 --- Load, Limitzed Boao TO ICKIN22 0.0PS --- 20DEA Weak Order Base Cobbler (0.2 OS) Brne, B0TH SIZE2 --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, --- 21K2CEEN, B0TH SIZE2, MHLE --- 21K2CEEN, --- 21K2CEEN, B0TH SIZE2, MHLE ----- 5S-0Cr-5004 --- 5S-0Cr-5004 --- 5S-0Cr-5004 --- 5S-0Cr-5004 --- 5S-0Cr-5004 --- 5S-0Cr-5004 --- 5S-0Cr-5004 --- 5S-0Cr-5004 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- 5S-0Cr-5O4 --- Co 80301 CoLung Rodic Inc. CoLung Molei CM-S CoLung Rodic Inc. CoLung Molei CM-S CoLung Rodic Inc. CoLung Molei CM-S CoLung Rodic Inc. CoLung Molei CM-S CoLung Rodic Inc. CoLung Molei CM-S CoLung Rodic Inc. CoLung Molei CM-S CoLung Rodic Inc. CoLung Molei CM-S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S CoLungs/Chips/Chips S

Cikuna Rodic, Inc. Coutigustin
Figure 19. CM-2 Module Assembly Drawing, Bottom

NOT TO SCALE

2x Mounting holes for front faceplate. 4x 0.16 Hole, 0.3 pads 2x Mounting holes for PCB standoffs Component Side = J3 Bottom Side = J4 Viewed from component side up. 3.500 3.500 0.175 A20 B20 A1 B1 A20 B20 0.175 A1 B1 0.3 2.86 NOT TO SCALE General PCB dimensions

Figure 20. General PCB Dimensions

0.340 This distance accounts for the thickness of the faceplate

NOT TO SCALE
Figure 21. Example Configuration, Side View

Note: Mechanical dimensions for the CM-2 and CM-1 Rev F are identical. There are differences with earlier versions of the CM-1, however. For reference, earlier versions of the CM-1 dimensions are shown in RED.

3.500 0.175 0.125 dia, 2x 0.500 0.431 0.421 1.343 1.333 0.550 0.680 0.700 0.800 0.810 1.000 max, 0.9 typ. 1.000 1.000 4-40 PEM's, x2 0.862 0.300 0.300 2x, Hole Diameter 0.160 0.175 0.340 0.490

Faceplate material is 20 guage, 0.037" thick Chrome plating on faceplate

Faceplate Dimensions

NOT TO SCALE

Figure 22. Faceplate Dimensions

Connector Detail 0.208 0.039 J1 0.157 1.576 1.925 3.343 8x 0.047 Alignment holes J3 Component Side Up

Figure 23. Connector Detail

NOT TO SCALE

9.2 CM-2 Schematics

graph LR
    subgraph_core_sch["core"]
        HRESET1["HRESET1"] --> HRESET2["HRESET2"]
        HLEN["HLEN"] --> HLEN2["HLEN"]
        HRW["HRW"] --> HRW2["HRW"]
        IDS["IIDS"] --> IDS2["IIDS"]
        HADDR["0..3"] --> HADDR["0..3"]
        IDATA["0..7"] --> IDATA["0..7"]
        HREQ["HREQ"] --> HREQ2["HREQ2"]
        IACK["IACK"] --> IACK2["IACK2"]
        WATCHDOG["WATCHDOG"] --> WATCHDOG["WATCHDOG"]
        MUTL["MUTL"] --> MUTL2["MUTL2"]
        UART TX_OE --> UART_TX_OE["UART TX_OE"]
        UART_TXD --> UART_TXD["UART_TXD"]
        UART_RXD --> UART_RXD["UART_RXD"]
        MCLK_OUT --> MCLK_OUT["MIK_OUT"]
        MCLK_IN --> MCLK_IN["MIK_IN"]
        REFCLK_IN --> REFCLK_IN["REFCLK_IN"]
        FSI["FSI"] --> FSI2["FSI"]
        SSI_CLK["SSI_CLK"] --> SSI_DIN["SSI_DIN[0..3"]]
        SSI_DOUT["SSI_DOUT[0..3"]] --> SSI_DOUT["SSI_DOUT[0..3"]]
        RSVD["RSVD[1..5"]] --> RSVD1["RSVD[1..5"]]
        AUX_POWLR[" AUX_POWLR[0..3 "] ] --> AUX_POWER[" AUX_POWER[0..3 "] ]
    end

    subgraph core_sch
        HRESET1 --> HRESET2
        HLEN --> HLEN2
        HRW --> HRW2
        IDS --> IDS2
        HADDR["0..3"] --> HADDR["0..3"]
        IDATA["0..7"] --> IDATA["0..7"]
        HREQ --> HREQ2
        IACK --> IACK2
        WATCHDOG --> WATCHDOG["WATCHDOG"]
        MUTL --> MUTL2
        UART_TX_OE --> UART_TX_OE
        UART_TXD --> UART_TXD
        UART_RXD --> UART_RXD
        MCLK_OUT --> MCLK_OUT
        MCLK_IN --> MCLK_IN
        REFCLK_IN --> REFCLK_IN
        FSI2 --> FSI2
        SSI_CLK --> SSI_CLK
        SSI_DIN["0..3"] --> SSI_DIN["0..3"]
        SSI_DOUT["0..3"] --> SSI_DOUT["0..3"]
        RSVD1["RSVD[1..5"]] --> RSVD1
        AUX_POWER1[" AUX_POWER[0..3 "] ] --> AUX_POWER2[" AUX_POWLR[0..3 "] ]
    end

    GIANO["GPIO1"] --> R1GPI00["R1GPI00"]
    R1GPI00 --> R2["R2"]
    R2 --> GND["GND"]
    style core_sch fill:#f9f,stroke:#333,stroke-width:2px
    note right of GIANO: GPIO["GPIO1"] is not used elsewhere. These pulldowns are used for test points and to keep these signals at valid levels.

This linear regulator is used to assure that the +1.8v rail quickly passes the 0.5v threshold at powerup, thus minimizing power sequencing issues and making sure that the DSP does not draw excessive power as the power rails ramp up. This linear regulator is set with Vout-1.22v, so it is effectively shut off once the switching regulator comes up. Further testing and characterization of the DSP is required to determine if this linear regulator is in fact required.

U9 IN OUT BYP GND ADJ LTC1761 4 3 5 C45 0.01 uF U1 LTC3406-1.8 VIN SW RUN GND Vout/TB 3 5 L1 2.2 uH C1 10 uF, XSR, 6.3 Volts VCC -3.3 C2 C3 10 uF, XSR, 6.3 Volts VCC -1.8

This is a simple switching regulator. It produces 1.8V at >500 mA at about 90% efficiency. A simple low drop out linear regulator would be a cheaper alternative at the expense of power. A linear regulator would dissipate about 0.75 watts max, This switching regulator dissipates about 0.10 watts max.

Figure 24. CM-2 RevF Schematic Page 1 of 7

graph TD
    A["Microcontroller"] -->|Pin 1| B["LED Driver"]
    A -->|Pin 2| C["Cascade"]
    A -->|Pin 3| D["LED Tether"]
    A -->|Pin 4| E["Display"]
    A -->|Pin 5| F["Control Signals"]
    A -->|Pin 6| G["Display Inputs"]
    A -->|Pin 7| H["Display Outputs"]
    A -->|Pin 8| I["Display Inputs"]
    A -->|Pin 9| J["Display Outputs"]
    A -->|Pin 10| K["Display Inputs"]
    A -->|Pin 11| L["Display Outputs"]
    A -->|Pin 12| M["Display Inputs"]
    A -->|Pin 13| N["Display Outputs"]
    A -->|Pin 14| O["Display Inputs"]
    A -->|Pin 15| P["Display Outputs"]
    A -->|Pin 16| Q["Display Inputs"]
    A -->|Pin 17| R["Display Outputs"]
    A -->|Pin 18| S["Display Inputs"]
    A -->|Pin 19| T["Display Outputs"]
    A -->|Pin 20| U["Display Inputs"]
    A -->|Pin 21| V["Display Outputs"]
    A -->|Pin 22| W["Display Inputs"]
    A -->|Pin 23| X["Display Outputs"]
    A -->|Pin 24| Y["Display Inputs"]
    A -->|Pin 25| Z["Display Outputs"]
    A -->|Pin 26| AA["Display Inputs"]
    A -->|Pin 27| AB["Display Outputs"]
    A -->|Pin 28| AC["Display Inputs"]
    A -->|Pin 29| AD["Display Outputs"]
    A -->|Pin 30| AE["Display Inputs"]
    A -->|Pin 31| AF["Display Outputs"]
    A -->|Pin 32| AG["Display Inputs"]
    A -->|Pin 33| AH["Display Outputs"]
    A -->|Pin 34| AI["Display Inputs"]
    A -->|Pin 35| AJ["Display Outputs"]
    A -->|Pin 36| AK["Display Inputs"]
    A -->|Pin 37| AL["Display Outputs"]
    A -->|Pin 38| AM["Display Inputs"]
    A -->|Pin 39| AN["Display Outputs"]
    A -->|Pin 40| AO["Display Inputs"]
    A -->|Pin 41| AP["Display Outputs"]
    A -->|Pin 42| AQ["Display Inputs"]
    A -->|Pin 43| AR["Display Outputs"]
    A -->|Pin 44| AS["Display Inputs"]
    A -->|Pin 45| AT["Display Outputs"]
    A -->|Pin 46| AU["Display Inputs"]
    A -->|Pin 47| AV["Display Outputs"]
    A -->|Pin 48| AW["Display Inputs"]
    A -->|Pin 49| AX["Display Outputs"]
    A -->|Pin 50| AY["Display Inputs"]
    A -->|Pin 51| AZ["Display Outputs"]
    A -->|Pin 52| BA["Display Inputs"]
    A -->|Pin 53| BB["Display Outputs"]
    A -->|Pin 54| BC["Display Inputs"]
    A -->|Pin 55| BD["Display Outputs"]
    A -->|Pin 56| BE["Display Inputs"]
    A -->|Pin 57| BF["Display Outputs"]
    A -->|Pin 58| BG["Display Inputs"]
    A -->|Pin 59| BH["Display Outputs"]
    A -->|Pin 60| BI["Display Inputs"]
    A -->|Pin 61| BJ["Display Outputs"]
    A -->|Pin 62| BK["Display Inputs"]
    A -->|Pin 63| BL["Display Outputs"]
    A -->|Pin 64| BM["Display Inputs"]
    A -->|Pin 65| BN["Display Outputs"]
    A -->|Pin 66| BO["Display Inputs"]
    A -->|Pin 67| BP["Display Outputs"]
    A -->|Pin 68| BQ["Display Inputs"]
    A -->|Pin 69| BR["Display Outputs"]
    A -->|Pin 70| BS["Display Inputs"]
    A -->|Pin 71| BT["Display Outputs"]
    A -->|Pin 72| BU["Display Inputs"]
    A -->|Pin 73| BV["Display Outputs"]
    A -->|Pin 74| BW["Display Inputs"]
    A -->|Pin 75| BX["Display Outputs"]
    A -->|Pin 76| BY["Display Inputs"]
    A -->|Pin 77| BZ["Display Outputs"]
    A -->|Pin 78| CA["Display Inputs"]
    A -->|Pin 79| CB["Display Outputs"]
    A -->|Pin 80| CC["Display Inputs"]
    A -->|Pin 81| CD["Display Outputs"]
    A -->|Pin 82| CE["Display Inputs"]
    A -->|Pin 83/CE | DD
    A -->|Pin 84/CE | DE
    A -->|Pin 85/CE | DE
    A -->|Pin 86/CE | DE
    A -->|Pin 87/CE | DE
    A -->|Pin 88/CE | DE
    A -->|Pin 89/CE | DE
    A -->|Pin 90/CE | DE
    A -->|Pin 91/CE | DE
    A -->|Pin 92/CE | DE
    A -->|Pin 93/CE | DE
    A -->|Pin 94/CE | DE
    A -->|Pin 95/CE | DE
    A -->|Pin 96/CE | DE
    A -->|Pin 97/CE | DE
    A -->|Pin 98/CE | DE
    A -->|Pin 99/CE | DE
    B["Microcontroller"] --> C["Cascade"]
    C["Cascade"] --> D["LCD Driver"]
    C["Cascade"] --> E["LCD Powertrain"]
    C["Cascade"] --> F["LCD Powerline"]<br>[CLK_25, MAX_PWR_PA, AUX_POWER_PA, LED_CLR_PA, LED_BLF_PA, LED_CLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA] --> E
    E["Cascade"] --> F
    F["Cascade"] --> G["LCD Driver"]
    F["Cascade"] --> H["LCD Powertrain"]
    F["Cascade"] --> I["LCD Powerline"]<br>[CLK_25, MAX_PWR_PA, AUX_POWER_PA, LED_CLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA] --> E
    E["Cascade"] --> H
    E["Cascade"] --> I
    E["Cascade"] --> J["LCD Driver"]
    E["Cascade"] --> K["LCD Powertrain"]
    E["Cascade"] --> L["LCD Powerline"]<br>[CLK_25, MAX_PWR_PA, AUX_POWER_PA, LED_CLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA, LED_DLR_PA] --> E
    E["Cascade"] --> K
    E["Cascade"] --> L
    E["Cascade"] --> J

</details>

Figure 25. CM-2 RevF Schematic Page 2 of 7

![](images/1212faa59bb4634b8ba16bd0928e2d3afb0cdebb56b34d1cb4364fd2695c7719.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph TD
    A["ADDR[0..19"]] --> B["ADDR[0..19"]]
    B --> C["ADDR19"]
    C --> D["ADDR18"]
    D --> E["ADDR17"]
    E --> F["ADDR16"]
    F --> G["ADDR15"]
    G --> H["ADDR14"]
    H --> I["ADDR13"]
    I --> J["ADDR12"]
    J --> K["ADDR11"]
    K --> L["ADDR10"]
    L --> M["ADDR9"]
    M --> N["ADDR8"]
    N --> O["ADDR7"]
    O --> P["ADDR6"]
    P --> Q["ADDR5"]
    Q --> R["ADDR4"]
    R --> S["ADDR3"]
    S --> T["ADDR2"]
    T --> U["ADDR1"]
    U --> V["IRESET_BUF#"]
    V --> W["HRESET_BUF#"]
    W --> X["RESET#"]
    X --> Y["CE#"]
    Y --> Z["FLASH_CS#"]
    Z --> AA["FLASH_CS#"]
    AA --> AB["WE#"]
    AB --> AC["OE#"]
    AC --> AD["FLASH_TSOP"]
    D --> AE["VCC +3.3"]
    AE --> AF["U5"]
    AF --> AG["ADDR0"]
    AF --> AH["DATA[0..15"]]
    AH --> AI["DATA[0..15"]]
    AI --> AJ["ERR0"]
    AJ --> AK["VCC +3.3"]
    AK --> AL["ERR0"]
    AL --> AM["VCC +3.3"]
    AM --> AN["ERR0"]
    AN --> AO["VCC +3.3"]
    AO --> AP["VCC +3.3"]
    AP --> AQ["VCC +3.3"]
    AQ --> AR["VCC +3.3"]
    AR --> AS["VCC +3.3"]
    AS --> AT["VCC +3.3"]
    AT --> AU["VCC +3.3"]
    AU --> AV["VCC +3.3"]

Figure 26. CM-2 RevF Schematic Page 3 of 7

Circuit diagram of a microcontroller with labeled components, power supply, and control signals including ADC, memory, and I/O pins.

Figure 27. CM-2 RevF Schematic Page 4 of 7

VCC 4.22 VCC 100 TDC 700 100kA 60kV 50kA 50kV 30kA 100kA LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.5 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.6 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.7 LED 47810.8 LED 47810.8 LED 47810.8 LED 47810.8 LED 47810.8 LED 47810.8 LED 47810.8 LED 47810.8 LED 47810.8 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.9 LED 47810.10 LED 47810.10 LED 47810.10 LED 47810.10 LED 47810.10 LED 47810.10 LED 47810.10 LED 47810.10 LED 47810.10 LED 47810.10

Figure 28. CM-2 RevF Schematic Page 5 of 7

VCC_12.5 VCC_PFF2 11 14 201.62 19.47, 320, 62.75 Volts VCC_13 10 14 201.62 19.47, 320, 62.75 Volts VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC_PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 VCC-PFF2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Figure 29. CM-2 RevF Schematic Page 6 of 7

Figure 30. CM-2 RevF Schematic Page 7 of 7

9.3 CS1810xx/CS4961xx Package

E E1 D D1 e b ddd B SEATING PLANE B L1 A θ A1 L

Figure 31. 144-Pin LQFP Package Drawing

DIM	MILLIMETERS INCHES
	MIN NOM	MAX MIN NOM MAX
A --- --- 1.60	--- --- .063"
A1 0.05 --- 0.15 .002" --- .006"
b	0.17	0.22	0.27	.007"	.009"	.011"
D	22.00 BSC			.866"
D1	20.00 BSC			.787"
E	22.00 BSC			.866"
E1	20.00 BSC			.787"
e	0.50 BSC			.020"
θ	0° ---	7°	0° ---	7°
L	0.45	0.60	0.75	.018"	.024"	.030"
L1	1.00 REF			.039" REF
TOLERANCES OF FORM AND POSITION
ddd	0.08			.003"

Notes:

1. Controlling dimension is millimeter.
2. Dimensioning and tolerancing per ASME Y14.5M-1994.
3. Controlling dimension is millimeter.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Controlling dimension is millimeter.
6. Dimensioning and tolerancing per ASME Y14.5M-1994.
7. Controlling dimension is millimeter.
8. Dimensioning and tolerancing per ASME Y14.5M-1994.
9. Controlling dimension is millimeter.
10. Dimensioning and tolerancing per ASME Y14.5M-1994.
11. Controlling dimension is millimeter.

12. Dimensioning and tolerancing per ASME Y14.5M-1994.

13. Controlling dimension is millimeter.

14. Dimensioning and tolerancing per ASME Y14.5M-1994.

15. Controlling dimension is millimeter.

16. Dimensioning and tolerancing per ASME Y14.5M-1994.

17. Controlling dimension is millimeter.

18. Dimensioning and tolerancing per ASME Y14.5M-1994.

19. Controlling dimension is millimeter.

20. Dimensioning and tolerancing per ASME Y14.5M-1994.

21. Controlling dimension is millimeter.

22. Dimensioning and tolerancing per ASME Y14.5M-1994.

9.4 Temperature Specifications

• Thermal Coefficient (junction-to-ambient): _ja - 38° C / Watt
- Ambient Temperature Range: 0-70 deg C
• Junction Temperature Range: 0-125 deg C

10.0 Ordering Information

10.1 Device Part Numbers

CS181002-CQ/A1	2x2 Channels	0°C to +70°C	144-pin LQFP
CS181012-CQ/A1	8x8 Channels	0°C to +70°C	144-pin LQFP
CS181022-CQ/A1	16x16 Channels	0°C to +70°C	144-pin LQFP
CS181002-CQZ/A1	2x2 Channels	0°C to +70°C	144-pin LQFP	Lead Free
CS181012-CQZ/A1	8x8 Channels	0°C to +70°C	144-pin LQFP	Lead Free
CS181022-CQZ/A1	16x16 Channels	0°C to +70°C	144-pin LQFP	Lead Free
CS496102-CQZ/A1	2x2 Channels + DSP	0°C to +70°C	144-pin LQFP	Lead Free
CS496112-CQZ/A1	8x8 Channels + DSP	0°C to +70°C	144-pin LQFP	Lead Free
CS496122-CQZ/A1	16x16 Channels + DSP	0°C to +70°C	144-pin LQFP	Lead Free

10.2 Device Part Numbering Scheme

graph TD
    A["CS1810x2 — CQZ/A1"] --> B["Base Part Number"]
    A --> C["Channel Count Designator: 0 = 2x2, 1 = 8x8, 2 = 16x16"]
    A --> D["ROM Version (ROM ID)"]
    A --> E["Die Revision"]
    A --> F["Lead-free Designator: Z = Lead-free Device Packaging (not present if device contains lead)"]
    A --> G["Package Type: Q = LQFP (144-pin)"]
    A --> H["Temperature Grade Designator: C = Commercial (0°C to +70°C)"]

CS4961x2 — CQZ/A1 Base Part Number Channel Count Designator: 0 = 2x2 1 = 8x8 2 = 16x16 ROM Version (ROM ID) Die Revision Lead-free Designator: Z = Lead-free Device Packaging (not present if device contains lead) Package Type: Q = LQFP (144-pin) Temperature Grade Designator: C = Commercial (0°C to +70°C)

Note: Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.

Figure 32. Device Part Numbering Explanation

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com

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