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PIC32MZ1024ECM124 - Electronic component Microchip - Free user manual and instructions

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USER MANUAL PIC32MZ1024ECM124 Microchip

32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog

Operating Conditions

- 2.3V to 3.6V, -40°C to +85°C, DC to 200 MHz

Core: 200 MHz (up to 330 DMIPS) microAptiv™

• 16 KB I-Cache, 4 KB D-Cache
- MMU for optimum embedded OS execution
- microMIPS™ mode for up to 35% smaller code size
- DSP-enhanced core:

- Four 64-bit accumulators

- Single-cycle MAC, saturating and fractional math

• Code-efficient (C and Assembly) architecture

Clock Management

Internal oscillator
Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timers (WDT) and Deadman Timer (DMT)
Fast wake-up and start-up

Power Management

Low-power modes (Sleep and Idle)
Integrated Power-on Reset and Brown-out Reset

Memory Interfaces

• 50 MHz External Bus Interface (EBI)
• 50 MHz Serial Quad Interface (SQI)

Audio and Graphics Interfaces

• Graphics interfaces: EBI or PMP
• Audio data communication: I ^2 S, LJ, and RJ
• Audio control interfaces: SPI and I 2C
• Audio master clock: Fractional clock frequencies with USB synchronization

High-Speed (HS) Communication Interfaces (with Dedicated DMA)

• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface

Security Features

Crypto Engine with a RNG for data encryption/decryption and authentication (AES, 3DES, SHA, MD5, and HMAC)
Advanced memory protection:

- Peripheral and memory region access control

Direct Memory Access (DMA)

• Eight channels with automatic data size detection
- Programmable Cyclic Redundancy Check (CRC)

Advanced Analog Features

• 10-bit ADC resolution and up to 48 analog inputs
• Flexible and independent ADC trigger sources
- Two comparators with 32 programmable voltage references
• Temperature sensor with ±2°C accuracy

Communication Interfaces

Two CAN modules (with dedicated DMA channels): - 2.0B Active with DeviceNet™ addressing support
Six UART modules (25 Mbps):
Supports LIN 1.2 and IrDA ^® protocols
Six 4-wire SPI modules
SQI configurable as an additional SPI module (50 MHz)
• F i 2Cmodules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
Peripheral Pin Select (PPS) to enable function remap

Timers/Output Compare/Input Capture

Nine 16-bit or up to four 32-bit timers/counters
• Nine Output Compare (OC) modules
• Nine Input Capture (IC) modules
PPS to enable function remap
• Real-Time Clock and Calendar (RTCC) module

Input/Output

5V-tolerant pins with up to 32 mA source/sink
Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins

Qualification and Class B Support

• Class B Safety Library, IEC 60730
- Back-up internal oscillator

Debugger Development Support

• In-circuit and in-application programming
• 4 - w i r®EnInMancePJTAG interface
• Unlimited software and 12 complex breakpoints
- IEEE 1149.2-compatible (JTAG) boundary scan
• Non-intrusive hardware-based instruction trace

Software and Tools Support

• C/C++ compiler with native DSP/fractional support
• M P L® Harmony Integrated Software Framework
• TCP/IP, USB, Graphics, and mTouch™ middleware
- MFi, Android™, and Bluetooth ^ audio frameworks
- RTOS Kernels: Express Logic ThreadX, FreeRTOS™, OPENRTOS®, Micriμm® μC/OS™, and SEGGER embOS®

Packages

Type QFN TQFP VTLA LQFP
Pin Count	64	64	100		144	124	144
I/O Pins (up to)	53	53	78		120	98	120
Contact/Lead Pitch	0.50 mm	0.50 mm	0.40 mm	0.50 mm	0.40 mm	0.50 mm	0.50 mm
Dimensions	9x9x0.9 mm	10x10x1 mm	12x12x1 mm	14x14x1 mm	16x16x1 mm	9x9x0.9 mm	20x20x1.40 mm

TABLE 1: PIC32MZ EC FAMILY FEATURES

Device

Program Memory (KB)

Data Memory (KB)

Pins

Packages

Boot Flash Memory (KB)

Remappable Peripherals

Crypto

RNG

DMA Channels (Programmable/Dedicated)

ADC (Channels)

Analog Comparators

USB 2.0 HS OTG

I^2C

PMP

EBI

SQI

RTCC

Ethernet

I/O Pins

JTAG

Trace

Remappable Pins

Timers/Capture ^(1) Compare ^(1)

UART

SPIU ^2 S

External Interrupts ^(2)

CAN 2.0B

PIC32MZ1024ECG064

1024

512 64

TQFP, QFN

160 34

9/9/9

6 4 5

/ / 24

1 1 1 1 1

2 5 8 2 5 8

PIC32MZ1024ECH064

PIC32MZ1024ECM064

PIC32MZ2048ECG064

2048

PIC32MZ2048ECH064

PIC32MZ2048ECM064

PIC32MZ1024ECG100

1024

512

100

TQFP

160

9/9/9

/ / 40

1 1 1 1

2 5 8 2 5 8

PIC32MZ1024ECH100

PIC32MZ1024ECM100

PIC32MZ2048ECG100

2048

PIC32MZ2048ECH100

PIC32MZ2048ECM100

PIC32MZ1024ECG124

1024

512

124

VTLA

160

9/9/9

/ / 48

1 1 1 1

2 5 8 2 5 8

PIC32MZ1024ECH124

PIC32MZ1024ECM124

PIC32MZ2048ECG124

2048

PIC32MZ2048ECH124

PIC32MZ2048ECM124

PIC32MZ1024ECG144

1024

512

144

LQFP, TQFP

160 53

9/9/9

6 6 5

/ / 48

1 1 1 1

2 5 8 2 5 8

120

PIC32MZ1024ECH144

PIC32MZ1024ECM144

PIC32MZ2048ECG144

2048

PIC32MZ2048ECH144

PIC32MZ2048ECM144

Note 1: Eight out of nine timers are remappable.
2: Four out of five external interrupts are remappable.

Device Pin Tables

TABLE 2: PIN NAMES FOR 64-PIN DEVICES

64-PIN QFN(4) AND TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)064PIC32MZ1024EC(G/H/M)064PIC32MZ1024EC(E/F/K)064PIC32MZ2048EC(G/H/M)064
Pin # Full Pin Name Pin # Full Pin Name
1 AN 17/ETXEN/RPE5/PMD5/RE5	33	VBUS
2 AN 16/ETXD0/PMD6/RE6 34 V		USB3V3
3 AN 15/ETXD1/PMD7/RE7 35 V		SS
4 AN 14/C1IND/RPG6/SCK2/PMA5/RG6 36 D-
5 AN 13/C1INC/RPG7/SDA4/PMA4/RG7 37 D+
6 AN 12/C2IND/RPG8/SCL4/PMA3/RG8 38 RPF3/USBID/RF3
7 Vss	39	VDD
8 VDD	40	Vss
9 M C L R		41 RPF4/SDA5/PMA9/RF4
10 AN 11/C2INC/RPG9/PMA2/RG9	42 RP	F5/SCL5/PMA8/RF5
11 AN 45/C1INA/RPB5/RB5	43 AE	RXD0/ETXD2/RPD9/SDA1/PMCS2/PMA15/RD9
12 AN 4/C1INB/RB4	44 E	OL/RPD10/SCL1/SCK4/RD10
13 AN 3/C2INA/RPB3/RB3	45 AE	RXCLK/AEREFCLK/ECRS/RPD11/PMCS1/PMA14/RD11
14 AN 2/C2INB/RPB2/RB2	46 AE	RXD1/ETXD3/RPD0/RTCC/INT0/RD0
15 PGEC1/V REF-/CVREF-/AN1/RPB1/RB1	47 SO	SCI/RPC13/RC13
16 PGED1/V REF+/CVREF+/AN0/RPB0/PMA6/RB0	48 SO	SCO/RPC14/T1CK/RC14
17 PGEC2/AN46/RPB6/RB6	49 E	MDIO/AEMDIO/RPD1/SCK1/RD1
18 PGED2/AN47/RPB7/RB7	50 ET	XERR/AETXEN/RPD2/SDA3/RD2
19 AV DD	51	AERXERR/ETXCLK/RPD3/SCL3/RD3
20 AVss	52 SO	ICS0/RPD4/PMWR/RD4
21 AN 48/RPB8/PMA10/RB8	53	SQICS1/RPD5/PMRD/RD5
22 AN 49/RPB9/PMA7/RB9	54 V	DD
23 TMS/CV REFOUT/AN5/RPB10/PMA13/RB10	55	Vss
24 TDO/AN6/PMA12/RB11	56 ERXD3/AETXD1/RPF0/RF0
25 Vss	57	TRCLK/SQICLK/ERXD2/AETXD0/RPF1/RF1
26 VDD	58 TR	D0/SQID0/ERXD1/PMD0/RE0
27 TCK/AN7/PMA11/RB12	59 V	SS
28 TDI/AN8/RB13	60 V	DD
29 AN 9/RPB14/SCK3/PMA1/RB14	61 TRD1	SQID1/ERXD0/PMD1/RE1
30 AN 10/EMDC/AEMDC/RPB15/OCFB/PMA0/RB15	62 TR	D2/SQID2/ERXDV/ECRSDV/AECRSDV/PMD2/RE2
31 OSC1/CLKI/RC12	63 TR	D3/SQID3/ERXCLK/EREFCLK/RPE3/PMD3/RE3
32 OSC2/CLKO/RC15	64 AN 18	ERXERR/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to Vss externally.

TABLE 3: PIN NAMES FOR 100-PIN DEVICES

100-PIN TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)100PIC32MZ1024EC(G/H/M)100PIC32MZ1024EC(E/F/K)100PIC32MZ2048EC(G/H/M)100
Pin #	Full Pin Name Pin # Full Pin Name	F13
1 AN23/AERXERR/RG15 36 V				SS
2 EBIA5/AN34/PMA5/RA5 37 V				DD
3 EBID5/AN17/RPE5/PMD5/RE5 38 TCK/EBIA19/AN29/RA1
4 EBID6/AN16/PMD6/RE6 39 TDI/EBIA18/AN30/RPF13/SCK5/R
5 EBID7/AN15/PMD7/RE7 40 TDO/EBIA17/AN31/RPF12/RF12
6 EBIA6/AN22/RPC1/PMA6/RC1 41 EBIA11/AN7/ERXD0/AECRS/PMA11/RB12
7 EBIA12/AN21/RPC2/PMA12/RC2			42 AN8/ERXD1/AECOL/RB13
8 EBWE/AN20/RPC3/PMWR/RC3			43 EBIA1/AN9/ERXD2/AETXD3/RPB14/SCK3/PMA1/RB14
9 EBIOE/AN19/RPC4/PMRD/RC4			44 EBIA0/AN10/ERXD3/AETXD2/RPB15/OCFB/PMA0/RB15
10 AN14/C1IND/ECOL/RPG6/SCK2/RG6			45 V	SS
11 EBIA4/AN13/C1INC/ECRS/RPG7/SDA4/PMA4/RG7			46 V	DD
12 EBIA3/AN12/C2IND/ERXDV/ECRSDV/AERXDV/AECRSDV/RPG8/SCL4/PMA3/RG8			47 AN32/AETXD0/RPD14/RD14
13 Vss			48 AN33/AETXD1/RPD15/SCK6/RD15
14 VDD			49 OSC1/CLKI/RC12
15 MCLR			50 OSC2/CLKO/RC15
16 EBIA2/AN11/C2INC/ERXCLK/EREFCLK/AERXCLK/AEREFCLK/RPG9/PMA2/RG9			51	Vbus
17 TMS/EBIA16/AN24/RA0 52 V				USB3V3
18 AN25/AERXD0/RPE8/RE8			53 V	SS
19 AN26/AERXD1/RPE9/RE9			54 D-
20 AN45/C1INA/RPB5/RB5			55 D+
21 AN4/C1INB/RB4			56 RPF3/USBID/RF3
22 AN3/C2INA/RPB3/RB3			57 EBIRDY3/RPF2/SDA3/RF2
23 AN2/C2INB/RPB2/RB2			58 EBIRDY2/RPF8/SCL3/RF8
24 PGEC1/AN1/RPB1/RB1			59 EBICS0/SCL2/RA2
25 PGED1/AN0/RPB0/RB0			60 EBIRDY1/SDA2/RA3
26 PGEC2/AN46/RPB6/RB6			61 EBIA14/PMCS1/PMA14/RA4
27 PGED2/AN47/RPB7/RB7			62 V	DD
28 VREF-/CVREF-/AN27/AERXD2/RA9			63 V	SS
29 VREF+/CVREF+/AN28/AERXD3/RA10			64 EBIA9/RPF4/SDA5/PMA9/RF4
30 AV DD			65 EBIA8/RPF5/SCL5/PMA8/RF5
31 AV SS			66 AETXCLK/RPA14/SCL1/RA14
32 EBIA10/AN48/RPB8/PMA10/RB8			67 AETXEN/RPA15/SDA1/RA15
33 EBIA7/AN49/RPB9/PMA7/RB9			68 EBIA15/RPD9/PMCS2/PMA15/RD9
34 EBIA13/CV REFOUT/AN5/RPB10/PMA13/RB10			69 RPD10/SCK4/RD10
35 AN6/ERXERR/AETXERR/RB11			70 EMDC/AEMDC/RPD11/RD11

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.

TABLE 3: PIN NAMES FOR 100-PIN DEVICES (CONTINUED)

100-PIN TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)100PIC32MZ1024EC(G/H/M)100PIC32MZ1024EC(E/F/K)100PIC32MZ2048EC(G/H/M)100
Pin #	Full Pin Name	Pin #	Full Pin Name
71 EMDIO/AEMDIO/RPD0/RTCC/INT0/RD0 86 EBID10/ETXD0/RPF1		/PMD10/RF1
72 SOSCI/RPC13/RC13		87 EBID9/ETXERR/RPG1/PMD9/RG1
73 SOSCO/RPC14/T1CK/RC14		88 EBID8/RPG0/PMD8/RG0
74 VDD		89 TRCLK/SQICLK/RA6
75 Vss		90 TRD3/SQID3/RA7
76 RPD1/SCK1/RD1 91 EBID0/PMD0/RE0
77 EBID14/ETXEN/RPD2/PMD14/RD2 92 V			SS
78 EBID15/ETXCLK/RPD3/PMD15/RD3 93 V			DD
79 EBID12/ETXD2/RPD12/PMD12/RD12 94 EBID1/PMD1/RE1
80 EBID13/ETXD3/PMD13/RD13 95 TRD2/SQID2/RG14
81 SQICS0/RPD4/RD4 96 TRD1/SQID1/RG12
82 SQICS1/RPD5/RD5 97 TRD0/SQID0/RG13
83 VDD		98 EBID2/PMD2/RE2
84 Vss		99 EBID3/RPE3/PMD3/RE3
85 EBID11/ETXD1/RPF0/PMD11/RF0 100 EBID4/AN18/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.

TABLE 4: PIN NAMES FOR 124-PIN DEVICES

124-PIN VTLA (BOTTOM VIEW)PIC32MZ0512EC(E/F/K)124PIC32MZ1024EC(G/H/M)124PIC32MZ1024EC(E/F/K)124PIC32MZ2048EC(G/H/M)124		Pola
Package Pin #	Full Pin Name	Package Pin #	Full Pin Name
A1 No Connect		A35 V	BUS
A2 AN23/RG15 A36 V			USB3V3
A3 EBID5/AN17/RPE5/PMD5/RE5 A37 D-
A4 EBID7/AN15/PMD7/RE7 A38 RPF3/USBID/RF3
A5 AN35/ETXD0/RJ8		A39 EBIRDY2/RPF8/SCL3/RF8
A6 EBIA12/AN21/RPC2/PMA12/RC2		A40 ERXD3/RH9
A7 EBIOE /AN19/RPC4/PMRD/RC4 A41 EBICS0/SCL2/RA2
A8 EBIA4/AN13/C1INC/RPG7/SDA4/PMA4/RG7		A42 EBIA14/PMCS1/PMA14/RA4
A9 Vss		A43 V	SS
A10 MCLR A44 EBIA8/RPF5/SCL5/PMA8/RF5
A11 TMS/EBIA16/AN24/RA0		A45 RPA15/SDA1/RA15
A12 AN26/RPE9/RE9		A46 RPD10/SCK4/RD10
A13 AN4/C1INB/RB4		A47 ECRS/RH12
A14 AN3/C2INA/RPB3/RB3		A48 RPD0/RTCC/INT0/RD0
A15 V DD		A49 SOSCO/RPC14/T1CK/RC14
A16 AN2/C2INB/RPB2/RB2 A50 V			DD
A17 PGE C1/AN1/RPB1/RB1		A51 V	SS
A18 PGED1/AN0/RPB0/RB0		A52 RPD1/SCK1/RD1
A19 PGED2/AN47/RPB7/RB7		A53 EBID15/RPD3/PMD15/RD3
A20 VREF+/CV REF+/AN28/RA10		A54 EBID13/PMD13/RD13
A21 AV SS		A55 EMDO/RJ1
A22 AN39/ETXD3/RH1		A56 SQCSO/RPD4/RD4
A23 EBIA7/AN49/RPB9/PMA7/RB9		A57 ETXEN/RPD6/RD6
A24 AN6/RB11		A58 V	DD
A25 V DD		A59 EBID11/RPF0/PMD11/RF0
A26 TD/EBIA18/AN30/RPF13/SCK5/RF13		A60 EBID9/RPG1/PMD9/RG1
A27 EBIA11/AN7/PMA11/RB12		A61 TRCLK/SQICLK/RA6
A28 EBIA1/AN9/RPB14/SCK3/PMA1/RB14		A62 RJ4
A29 V SS		A63 V	SS
A30 AN40/ERXERR/RH4		A64 EBID1/PMD1/RE1
A31 AN42/ERXD2/RH6		A65 TRD1/SQID1/RG12
A32 AN33/RPD15/SCK6/RD15		A66 EBID2/SQID2/PMD2/RE2
A33 OSC2/CLKO/RC15		A67 EBID4/AN18/PMD4/RE4
A34 No Connect		A68 No Connect

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAX-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to Vss externally.

TABLE 4: PIN NAMES FOR 124-PIN DEVICES (CONTINUED)
124-PIN VTLA (BOTTOM VIEW)
PIC32MZ0512EC(E/F/K)124 PIC32MZ1024EC(G/H/M)124 PIC32MZ1024EC(E/F/K)124 PIC32MZ2048EC(G/H/M)124
Microchip PIC32MZ1024ECM124 - Device Pin Tables - 4

text_image

A17 B13 B29 A34 B1 B56 B41 A51 A1 A68 Parity Indicator

Package Pin #	Full Pin Name
B1 EBIA5/AN34/PMA5/RA5 B29 V
B2 EBID6/AN16/PMD6/RE6 B30 D+
B3 EBIA6/AN22/RPC1/PMA6/RC1
B4 AN36/ETXD1/RJ9
B5 EBIWE /AN20/RPC3/PMWR/RC3 B33 ECOL/RH10
B6 AN14/C1IND/RPG6/SCK2/RG6
B7 EBIA3/AN12/C2IND/RPG8/SCL4/PMA3/RG8
B8	VDD
B9 EBIA2/AN11/C2INC/RPG9/PMA2/RG9
B10 AN25/RPE8/RE8
B11 AN45/C1INA/RPB5/RB5
B12 AN37/ERXCLK/EREFCLK/RJ11
B13 V	SS
B14 PGE C2/AN46/RPB6/RB6
B15 V	REF-/CVREF-/AN27/RA9 B43 EBID12/RPD12/PMD12/RD1
B16 AV	DD
B17 AN38/ETXD2/RH0
B18 EBIA10/AN48/RPB8/PMA10/RB8
B19 EBIA13/CV REFOUT/AN5/RPB10/PMA13/RB10 B47 ETXCLK
B20 V	SS
B21 TCK/EBIA19/AN29/RA1 B49 EBID10/RPF1/PMD10/RF1
B22 TDO/EBIA17/AN31/RPF12/RF12
B23 AN8/RB13
B24 EBIA0/AN10/RPB15/OCFB/PMA0/RB15
B25 V	DD
B26 AN41/ERXD1/RH5 B54 TRD2/SQID2/RG14
B27 AN32/AETXD0/RPD14/RD14
B28 OSC1/CLKI/RC12

Package Pin #	Full Pin Name
	SS

B31 RPF2/SDA3/RF2
B32 ERXD0/RH8

B34 EBIRDY1/SDA2/RA3
B35 V	DD
B36 EBIA9/RPF4/SDA5/PMA9/RF4
B37 RPA14/SCL1/RA14
B38 EBIA15/RPD9/PMCS2/PMA15/RD9
B39 EMDC/RPD11/RD11
B40 ERXDV/ECRSDV/RH13
B41 SOSCI/RPC13/RC13
B42 EBID14/RPD2/PMD14/RD2

B44 ETXERR/RJ0
B45 EBIRDY3/RJ2
B46 SQCS1/RPD5/RD5
I/RD7
B48 V	SS

B50 EBID8/RPG0/PMD8/RG0
B51 TRD3/SQID3/RA7
B52 EBID0/PMD0/RE0
B53 V	DD

B55 TRD0/SQID0/RG13
B56 EBID3/RPE3/PMD3/RE3

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

TABLE 5: PIN NAMES FOR 144-PIN DEVICES

144-PIN LQFP AND TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)144PIC32MZ1024EC(G/H/M)144PIC32MZ1024EC(E/F/K)144PIC32MZ2048EC(G/H/M)144
Pin Number	Full Pin Name		Pin Number	Full Pin Name
1 AN23/RG15 37 PGEC2/AN46/RPB6/RB6
2 EBIA5/AN34/PMA5/RA5 38 PGED2/AN47/RPB7/RB7
3 EBID5/AN17/RPE5/PMD5/RE5 39 V			REF-/CVREF-/AN27/RA9
4 EBID6/AN16/PMD6/RE6 40 V			REF+/CVREF+/AN28/RA10
5 EBID7/AN15/PMD7/RE7 41 AV			DD
6 EBIA6/AN22/RPC1/PMA6/RC1 42 AV			SS
7 AN35/ETXD0/RJ8 43 AN38/ETXD2/RH0
8 AN36/ETXD1/RJ9 44 AN39/ETXD3/RH1
9 EBIES0/RJ12 45 EBIRP/RH2			—
10 EBIBS1/RJ10 46 RH3
11 EBIA12/AN21/RPC2/PMA12/RC2		47 EBIA10/AN48/RPB8/PMA10/RB8
12 EBIWE /AN20/RPC3/PMWR/RC3		48 EBIA7/AN49/RPB9/PMA7/RB9
13 EBIOE/AN19/RPC4/PMRD/RC4		49 CV	REFOUT/AN5/RPB10/RB10
14 AN14/C1IND/RPG6/SCK2/RG6		50 AN6/RB11
15 AN13/C1INC/RPG7/SDA4/RG7		51 EBIA1/PMA1/RK1
16 AN12/C2IND/RPG8/SCL4/RG8		52 EBIA3/PMA3/RK2
17 Vss		53 EBIA17/RK3
18 VDD		54	Vss
19 EBIA16/RK0		55 V	DD
20 MCLR		56 TCK/AN29/RA1
21 EBIA2/AN11/C2INC/RPG9/PMA2/RG9		57 TDI/AN30/RPF13/SCK5/RF13
22 TM$/AN24/RA0		58 TDO/AN31/RPF12/RF12
23 AN25/RPE8/RE8		59 AN7/RB12
24 AN26/RPE9/RE9		60 AN8/RB13
25 AN45/C1INA/RPB5/RB5		61 AN9/RPB14/SCK3/RB14
26 AN4/C1INB/RB4		62 AN10/RPB15/OCFB/RB15
27 AN37/ERXCLK/EREFCLK/RJ11		63 V	SS
28 EBIA13/PMA13/RJ13		64 V	DD
29 EBIA11/PMA11/RJ14		65 AN40/ERXERR/RH4
30 EBIA0/PMA0/RJ15		66 AN41/ERXD1/RH5
31 AN3/C2INA/RPB3/RB3		67 AN42/ERXD2/RH6
32 Vss		68 EBIA4/PMA4/RH7
33 VDD		69 AN32/RPD14/RD14
34 AN2/C2INB/RPB2/RB2		70 AN33/RPD15/SCK6/RD15
35 PGEC1/AN1/RPB1/RB1		71 OSC1/CLKI/RC12
36 PGED1/AN0/RPB0/RB0		72 OSC2/CLKO/RC15

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.

TABLE 5: PIN NAMES FOR 144-PIN DEVICES (CONTINUED)

144-PIN LQFP AND TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)144PIC32MZ1024EC(G/H/M)144PIC32MZ1024EC(E/F/K)144PIC32MZ2048EC(G/H/M)144
Pin Number	Full Pin Name	Pin Number Full Pin Name
73	VBUS	109 RPD1/SCK1/RD1
74	VUSB3V3	110 EBID14/RPD2/PMD14/RD2
75	Vss	111 EBID15/RPD3/PMD15/RD3
76 D-		112 EBID12/RPD12/PMD12/RD12
77 D+	13 EBID13/PMD13/RD13
78 RPF3/USBID/RF3		114 ETXERR/RJ0
79 SDA3/RPF2/RF2 115 EMDIO/RJ1
80 SCL3/RPF8/RF8 116 EBIRDY3/RJ2
81 ERXD0/RH8 117 EBIA22/RJ3
82 ERXD3/RH9 118 SQICS0/RPD4/RD4
83 ECOL/RH10 119 SQICS1/RPD5/RD5
84 EBIRDY2/RH11 120 ETXEN/RPD6/RD6
85 SCL2/RA2		121 ETXCLK/RPD7/RD7
86 EBIRDY1/SDA2/RA3		122 V DD
87 EBIA14/PMCS1/PMA14/RA4		123 V SS
88	VDD	124 EBID11/RPF0/PMD11/RF0
89	VSS	125 EBID10/RPF1/PMD10/RF1
90 EBIA9/RPF4/SDA5/PMA9/RF4		126 EBIA21/RK7
91 EBIA8/RPF5/SCL5/PMA8/RF5		127 EBID9/RPG1/PMD9/RG1
92 EBIA18/RK4		128 EBID8/RPG0/PMD8/RG0
93 EBIA19/RK5		129 TRCLK/SQICLK/RA6
94 EBIA20/RK6		130 TRD3/SQID3/RA7
95 RPA14/SCL1/RA14		131 EBICS0/RJ4
96 RPA15/SDA1/RA15		132 EBICS1/RJ5
97	EBIA15/RPD9/PMCS2/PMA15/RD9	133 EBICS2/RJ6
98 RPD10/SCK4/RD10		134 EBICS3/RJ7
99 EMDC/RPD11/RD11		135 EBID0/PMD0/RE0
100 ECRS/RH12		136 V SS
101 ERXDV/ECRSDV/RH13		137 V DD
102 RH14		138 EBID1/PMD1/RE1
103 EBIA23/RH15		139 TRD2/SQID2/RG14
104 RPDO/RTCC/INT0/RD0		140 TRD1/SQID1/RG12
105 SOSCI/RPC13/RC13		141 TRD0/SQID0/RG13
106 SOSCO/RPC14/T1CK/RC14		142 EBID2/PMD2/RE2
107 V DD		143 EBID3/RPE3/PMD3/RE3
108 V SS		144 EBID4/AN18/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.

2: Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 "I/O Ports" for more information.

3: Shaded pins are 5V tolerant.

NOTES:

1.0 Device Overview 15

2.0 Guidelines for Getting Started with 32-bit Microcontrollers 37

3.0 CPU 47

4.0 Memory Organization....59

5.0 Flash Program Memory....97

6.0 Resets....107

7.0 CPU Exceptions and Interrupt Controller 113

8.0 Oscillator Configuration....149

9.0 Prefetch Module 161

10.0 Direct Memory Access (DMA) Controller 165

11.0 Hi-Speed USB with On-The-Go (OTG) 189

12.0 I/O Ports 237

13.0 Timer1 273

14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9 277

15.0 Deadman Timer (DMT) 283

16.0 Watchdog Timer (WDT) 291

17.0 Input Capture....295

18.0 Output Compare....299

19.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I^2S) 305

20.0 Serial Quad Interface (SQI) 315

21.0 Inter-Integrated Circuit (I ^2 C) 339

22.0 Universal Asynchronous Receiver Transmitter (UART) 347

23.0 Parallel Master Port (PMP) 355

24.0 External Bus Interface (EBI) 365

25.0 Real-Time Clock and Calendar (RTCC) 373

26.0 Crypto Engine 383

27.0 Random Number Generator (RNG) 403

28.0 Pipelined Analog-to-Digital Converter (ADC) 409

29.0 Controller Area Network (CAN) 439

30.0 Ethernet Controller 477

31.0 Comparator 521

32.0 Comparator Voltage Reference (CV REF) 525

33.0 Power-Saving Features 529

34.0 Special Features 535

35.0 Instruction Set 559

36.0 Development Support....561

37.0 Electrical Characteristics....565

38.0 AC and DC Characteristics Graphs 613

39.0 Packaging Information....615

The Microchip Web Site 663

Customer Change Notification Service 663

Customer Support 663

Product Identification System 664

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Errata

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Customer Notification System

Referenced Sources

This device data sheet is based on the following individual sections of the "PIC32 Family Reference Manual". These documents should be considered as the general reference for the operation of a particular module or device feature.

Note: To access the following documents, refer to the Documentation > Reference Manuals section of the Microchip PIC32 website: http://www.microchip.com/pic32.

• Section 1. "Introduction" (DS60001127)
• Section 7. "Resets" (DS60001118)
• Section 8. "Interrupt Controller" (DS60001108)
• Section 9. "Watchdog, Deadman, and Power-up Timers" (DS60001114)
• Section 10. "Power-Saving Features" (DS60001130)
• Section 12. "I/O Ports" (DS60001120)
• Section 13. "Parallel Master Port (PMP)" (DS60001128)
• Section 14. "Timers" (DS60001105)
• Section 15. "Input Capture" (DS60001122)
• Section 16. "Output Compare" (DS60001111)
• Section 18. "12-bit Pipelined Analog-to-Digital Converter (ADC)" (DS60001194)
• Section 19. "Comparator" (DS60001110)
• Section 20. "Comparator Voltage Reference (CV REF)" (DS60001109)
• Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107)
• Section 23. "Serial Peripheral Interface (SPI)" (DS60001106)
- Section 24. "Inter-Integrated Circuit (I ^2 C)" (DS60001116)
• Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
• Section 31. "Direct Memory Access (DMA) Controller" (DS60001117)
• Section 32. "Configuration" (DS60001124)
• Section 33. "Programming and Diagnostics" (DS60001129)
• Section 34. "Controller Area Network (CAN)" (DS60001154)
• Section 35. "Ethernet Controller" (DS60001155)
• Section 41. "Prefetch Module for Devices with L1 CPU Cache" (DS60001183)
• Section 42. "Oscillators with Enhanced PLL" (DS60001250)
• Section 46. "Serial Quad Interface (SQL)" (DS60001244)
• Section 47. "External Bus Interface (EBI)" (DS60001245)
• Section 48. "Memory Organization and Permissions" (DS60001214)
• Section 49. "Crypto Engine (CE) and Random Number Generator (RNG)" (DS60001246)
- Section 50. "CPU for Devices with MIPS32® microAptiv™ and M-Class Cores" (DS60001192)
• Section 51. "Hi-Speed USB with On-The-Go (OTG)" (DS60001326)
• Section 52. "Flash Program Memory with Support for Live Update" (DS60001193)

NOTES:

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the documents provided in the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

This data sheet contains device-specific information for PIC32MZ Embedded Connectivity (EC) devices.

Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MZ EC family of devices.

Table 1-21 through Table 1-22 list the pinout I/O descriptions for the pins shown in the device pin tables (see Table 2 through Table 5).

FIGURE 1-1: PIC32MZ EC FAMILY BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - DEVICE OVERVIEW - 1

flowchart

graph TD
    subgraph System Bus
        A["Peripheral Bus 1"] --> B["Flash Controller"]
        C["Peripheral Bus 2"] --> D["Data Ram Bank 1"]
        E["Peripheral Bus 3"] --> F["Data Ram Bank 2"]
        G["Peripheral Bus 4"] --> H["Peripheral Bus 5"]
        I["Peripheral Bus 5"] --> J["Peripheral Bus 6"]
        K["Peripheral Bus 6"] --> L["Peripheral Bus 7"]
        M["Peripheral Bus 7"] --> N["Peripheral Bus 8"]
        O["Peripheral Bus 8"] --> P["Peripheral Bus 9"]
        Q["Peripheral Bus 9"] --> R["Peripheral Bus 10"]
        S["Peripheral Bus 10"] --> T["Peripheral Bus 11"]
        U["Peripheral Bus 11"] --> V["Peripheral Bus 12"]
        W["Peripheral Bus 12"] --> X["Peripheral Bus 13"]
        Y["Peripheral Bus 13"] --> Z["Peripheral Bus 14"]
        AA["Peripheral Bus 14"] --> AB["PFM Flash Wrapper and ECC"]
        AC["Peripheral Bus 14"] --> AD["140-bit Wide Dual Panel Flash Memory"]
        AE["Peripheral Bus 14"] --> AF["CVREF"]
        AG["Peripheral Bus 14"] --> AH["CPG"]
        AI["Peripheral Bus 14"] --> AJ["PPS"]
        AK["Peripheral Bus 14"] --> AL["ICD"]
        AM["Peripheral Bus 14"] --> AN["WDT"]
        AO["Peripheral Bus 14"] --> AP["DMT"]
        AQ["Peripheral Bus 14"] --> AR["RTCC"]
    end

    subgraph System Bus
        AS["EVIC"] --> AT["DMAC"]
        AU["MIPS32® microAptiv™ Core"] --> AV["I-Cache"]
        AW["D-Cache"] --> AX["System Bus I/F"]
        AY["EJTAG"] --> AZ["INT"]
        BA["MCLR"] --> BB["MCLR"]
    end

    subgraph Timing Generation
        BC["POLI"] --> BD["FRC/LPRC Oscillators"]
        BE["Voltage Regulator"] --> BF["POLL"]
        BG["PRESS"] --> BH["DIVIDERS"]
        BI["PDLL-USB"] --> BJ["Timing Generation"]
    end

    subgraph SYSCLK PBCLKx
        BK["Voltage Regulator"] --> BL["Policator Start-up Timer"]
        BM["Power-on Reset"] --> BN["Power-on Reset"]
        BO["Watchdog Timer"] --> BP["Brown-out Reset"]
    end

    subgraph Power-up Timer
        BQ["Power-up Timer"] --> BR["Oscillator Start-up Timer"]
        BS["Power-on Reset"] --> BT["Power-on Reset"]
        BU["Brown-out Reset"] --> BV["Brown-out Reset"]
    end

    subgraph System Bus
        BW["T12"] --> BX["T11"]
        BY["T10"] --> BZ["T9"]
        CA["T11"] --> BZ
        CB["T10"] --> BZ
        CC["T11"] --> BZ
        DD["T10"] --> BZ
        DV["T9"] --> BZ
    end

    subgraph Timing Generation
        DW["T6"] --> BX
        BX --> BX
    end

    subgraph SYSCLK PBCLKx
        BX <--> DC["VDD, Vss"]
        BX <--> DB["MCLR"]

    subgraph Timing Generation
        DC <--> DC
    end

    subgraph System Bus
        DB <--> DC
    end

    subgraph SYSCLK PBCLKx
        DC <--> DC
    end

    subgraph System Bus
        DC <--> DC
    end

    subgraph System Bus
        DC <--> DC
    end

    subgraph SYSCLK PBCLKx
        DC <--> DC
    end

    subgraph System Bus
        DC <--> DC
    end

    subgraph SYSCLK PBCLKx
        DC <--> DC
    end

    subgraph System Bus
        DC <--> DC
    end

    subgraph SYSCLK PBCLKx
        DC <--> DC
    end

    subgraph System Bus
        DC <--> DC
    end

    subgraph SYSCLK PBCLKx

Note: Not all features are available on all devices. Refer to TABLE 1: "PIC32MZ EC Family Features" for the list of features by device.

TABLE 1-1: ADC1 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AN0 16 25 A	18 36 I Analog	Analog	Input Channels
AN1 15 24 A	17 35 I Analog
AN2 14 23 A	16 34 I Analog
AN3 13 22 A	14 31 I Analog
AN4 12 21 A	13 26 I Analog
AN5 23 34 B	19 49 I Analog
AN6 24 35 A	24 50 I Analog
AN7 27 41 A	27 59 I Analog
AN8 28 42 B	23 60 I Analog
AN9 29 43 A	28 61 I Analog
AN10 30 44 B	24 62 I Analog
AN11	10 16	B9 21 I Analog
AN12	6	12	B7 16 I Analog
AN13	5	11	A8 15 I Analog
AN14	4	10	B6 14 I Analog
AN15	3	5	A4	5	I	Analog
AN16	2	4	B2	4	I	Analog
AN17	1	3	A3	3	I	Analog
AN18 64	100 A67 144		I Analog
AN19	—	9	A7 13 I Analog
AN20	—	8	B5 12 I Analog
AN21	—	7	A6	11	I	Analog
AN22	—	6	B3	6	I	Analog
AN23	—	1	A2	1	I	Analog
AN24	—	17 A11	22 I Analog
AN25	—	18 B10	23 I Analog
AN26	—	19 A12	24 I Analog
AN27	—	28 B15	39 I Analog
AN28	—	29 A20	40 I Analog
AN29	—	38 B21	56 I Analog
AN30	—	39 A26	57 I Analog
AN31	—	40 B22	58 I Analog
AN32	—	47 B27	69 I Analog
AN33	—	48 A32	70 I Analog
AN34	—	2	B1	2	I	Analog
AN35	—	—	A5	7	I	Analog

Legend: CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select

TABLE 1-1: ADC1 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AN36 — —	B4 8 I Analog						Analog Input Channels
AN37 — —	B12 27 I Analog
AN38 — —	B17 43 I Analog
AN39 — —	A22 44 I Analog
AN40 — —	A30 65 I Analog
AN41 — —	B26 66 I Analog
AN42 — —	A31 67 I Analog
AN45 11 20	B11 25 I Analog
AN46	17 26	B14	37 I Analog
AN47	18 27	A19	38 I Analog
AN48	21 32	B18	47 I Analog
AN49	22 33	A23	48 I Analog

TABLE 1-2: OSCILLATOR PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
CLKI 31 49 B28 71 I ST	CMOS External clock			source input.	Always associated with OSC1 pin function.
CLKO	32	50	A33	72	O	—	Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
OSC1 31 49 B28 71 I ST	CMOS Oscillator crystal input.				ST buffer when configured in RC mode; CMOS otherwise.
OSC2	32	50	A33	72	O	—	Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI	47	72	B41	105	I	ST/CMOS	32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO	48	73	A49	106	O	—	32.768 low-power oscillator crystal output.
REFCLKI1	PPS	PPS	PPS	PPS	I	—	Reference Clock Generator Inputs 1-4
REFCLKI3	PPS	PPS	PPS	PPS	I	—
REFCLKI4	PPS	PPS	PPS	PPS	I	—
REFCLKO1	PPS	PPS	PPS	PPS	O	—	Reference Clock Generator Outputs 1-4
REFCLKO3	PPS	PPS	PPS	PPS	O	—
REFCLKO4	PPS	PPS	PPS	PPS	O	—

Legend: CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Analog = Analog input
O = Output
P = Power
I = Input
PPS = Peripheral Pin Select

TABLE 1-3: IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Input Capture
IC1	PPS	PPS	PPS	PPS	I	ST	Input Capture Inputs 1-9
IC2	PPS	PPS	PPS	PPS	I	ST
IC3	PPS	PPS	PPS	PPS	I	ST
IC4	PPS	PPS	PPS	PPS	I	ST
IC5	PPS	PPS	PPS	PPS	I	ST
IC6	PPS	PPS	PPS	PPS	I	ST
IC7	PPS	PPS	PPS	PPS	I	ST
IC8	PPS	PPS	PPS	PPS	I	ST
IC9	PPS	PPS	PPS	PPS	I	ST

TABLE 1-4: OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Output Compare
OC1 PPS PPS PPS PPS S O — Output Compare Outputs 1-9
OC2 PPS PPS PPS PPS S O —
OC3 PPS PPS PPS PPS S O —
OC4 PPS PPS PPS PPS S O —
OC5 PPS PPS PPS PPS S O —
OC6 PPS PPS PPS PPS S O —
OC7 PPS PPS PPS PPS S O —
OC8 PPS PPS PPS PPS S O —
OC9 PPS PPS PPS PPS S O —
OCFA PPS PPS PPS PPS I			ST Output Compare Fault A Input
OCFB	30	44	B24	62	I	ST	Output Compare Fault B Input

TABLE 1-5: EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
External Interrupts
INT0	46	71	A48	104	I	ST	External Interrupt 0
INT1	PPS	PPS	PPS	PPS	I	ST	External Interrupt 1
INT2	PPS	PPS	PPS	PPS	I	ST	External Interrupt 2
INT3	PPS	PPS	PPS	PPS	I	ST	External Interrupt 3
INT4	PPS	PPS	PPS	PPS	I	ST	External Interrupt 4

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PORTA
RA0 — 17 A	11 22 I/O ST	PORTA is a bidirectional I/O port
RA1 — 38 B	21 56 I/O ST
RA2 — 59 A	41 85 I/O ST
RA3 — 60 B	34 86 I/O ST
RA4 — 61 A	42 87 I/O ST
RA5 —	2	B1	2 I/O ST
RA6 — 89 A	61 129	I/O ST
RA7 — 90 B	51 130	I/O ST
RA9 — 28 B	15 39 I/O ST
RA10	— 29 A	20 40 I/O ST
RA14	— 66 B	37 95 I/O ST
RA15	— 67 A	45 96 I/O ST
PORTB
RB0	16	25 A18	36 I/O ST	PORTB is a bidirectional I/O port
RB1	15	24 A17	35 I/O ST
RB2	14	23 A16	34 I/O ST
RB3	13	22 A14	31 I/O ST
RB4	12	21 A13	26 I/O ST
RB5 11 20 B	11 25	I/O ST
RB6	17	26 B14	37 I/O ST
RB7	18	27 A19	38 I/O ST
RB8	21	32 B18	47 I/O ST
RB9	22	33 A23	48 I/O ST
RB10	23	34 B19	49 I/O ST
RB11	24	35 A24	50 I/O ST
RB12	27	41 A27	59 I/O ST
RB13	28	42 B23	60 I/O ST
RB14	29	43 A28	61 I/O ST
RB15	30	44 B24	62 I/O ST
PORTC
RC1	—	6	B3	6	I/O	ST	PORTC is a bidirectional I/O port
RC2	—	7	A6	11	I/O	ST
RC3	—	8	B5 12	I/O ST
RC4	—	9	A7 13	I/O ST
RC12	31	49 B28	71 I/O ST
RC13	47	72	B41	105	I/O	ST
RC14	48	73	A49	106	I/O	ST
RC15	32	50 A33	72 I/O ST

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PORTD
RD0 46 71 A	48 104 I/O	ST PORTD is a bidirectional I/O port
RD1 49 76 A	52 109 I/O	ST
RD2 50 77 B	42 110 I/O	ST
RD3 51 78 A	53 111 I/O	ST
RD4 52 81 A	56 118 I/O	ST
RD5 53 82 B	46 119 I/O	ST
RD6 —	—	A57 120 I/O ST
RD7 —	—	B47 121 I/O ST
RD9 43 68	B38	97	I/O ST
RD10	44 69 A	46 98 I/O ST
RD11	45	70	B39	99	I/O	ST
RD12	—	79 B43	112 I/O ST
RD13	—	80 A54	113 I/O ST
RD14	—	47	B27	69	I/O	ST
RD15	—	48	A32	70	I/O	ST
PORTE
RE0 58 91 B	52 135 I/O	ST PORTE is a bidirectional I/O port
RE1 61 94 A	64 138 I/O	ST
RE2 62 98 A	66 142 I/O	ST
RE3 63 99 B	56 143 I/O	ST
RE4 64	100	A67 144 I/O ST
RE5	1	3	A3	3	I/O	ST
RE6	2	4	B2	4	I/O	ST
RE7	3	5	A4	5	I/O	ST
RE8	—	18	B10	23	I/O	ST
RE9	—	19	A12	24	I/O	ST
PORTF
RF0	56 85 A	59 124 I/O	ST PORTF is a bidirectional I/O port
RF1	57 86	B49	125 I/O ST
RF2	—	57	B31	79	I/O	ST
RF3	38	56	A38	78	I/O	ST
RF4	41	64	B36	90	I/O	ST
RF5	42	65	A44	91	I/O	ST
RF8	—	58	A39	80	I/O	ST
RF12	—	40	B22	58	I/O	ST
RF13	—	39	A26	57	I/O	ST

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PORTG
RG0 — 88 B	50 128 I/O	ST PORTG is a bidirectional I/O port
RG1 — 87 A	60 127 I/O	ST
RG6 4 10 B	14 I/O ST
RG7 5 11	A8 15	I/O ST
RG8 6 12 B	16 I/O ST
RG9	10	16 B9	21 I/O ST
RG12	— 96	A65 140 I/O	ST
RG13	— 97	B55 141 I/O	ST
RG14	— 95	B54 139 I/O	ST
RG15	— 1	A2 1	I/O ST
PORTH
RH0	—	—	B17	43	I/O	ST	PORTH is a bidirectional I/O port
RH1	—	—	A22	44	I/O	ST
RH2	—	—	—	45	I/O	ST
RH3	—	—	—	46	I/O	ST
RH4	—	—	A30	65	I/O	ST
RH5	—	—	B26	66	I/O	ST
RH6	—	—	A31	67	I/O	ST
RH7	—	—	—	68	I/O	ST
RH8	—	—	B32	81	I/O	ST
RH9	—	—	A40	82	I/O	ST
RH10	—	—	B33	83	I/O	ST
RH11	—	—	—	84	I/O	ST
RH12	—	—	A47 100	I/O ST
RH13	—	—	B40 101	I/O ST
RH14	—	—	—	102	I/O	ST
RH15	—	—	—	103	I/O	ST
PORTJ
RJ0	—	—	B44	114	I/O	ST	PORTJ is a bidirectional I/O port
RJ1	—	—	A55	115	I/O	ST
RJ2	—	—	B45	116	I/O	ST
RJ3	—	—	—	117	I/O	ST
RJ4	—	—	A62	131	I/O	ST
RJ5	—	—	—	132	I/O	ST
RJ6	—	—	—	133	I/O	ST
RJ7	—	—	—	134	I/O	ST
RJ8	—	—	A5 7 I/O ST
RJ9	—	—	B4 8 I/O ST
RJ10	—	—	—	10	I/O	ST
RJ11	—	—	B12	27	I/O	ST
RJ12	—	—	—	9	I/O	ST
RJ13	—	—	—	28	I/O	ST
RJ14	—	—	—	29	I/O	ST
RJ15	—	—	—	30	I/O	ST
Legend: CMOS = CMOS-compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = InputTTL = Transistor-transistor Logic input buffer PPS = Peripheral Pin SelectPORTK
RK0 — — —	19 I/O ST	PORTK is a bidirectional I/O port
RK1 — — —	51 I/O ST
RK2 — — —	52 I/O ST
RK3 — — —	53 I/O ST
RK4 — — —	92 I/O ST
RK5 — — —	93 I/O ST
RK6 — — —	94 I/O ST
RK7 — — —	126 I/O ST

TABLE 1-7: TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Timer1 through Timer9
T1CK 48 73	A49 106 I $T Timer1 External Clock Input
T2CK	PPS	PPS	PPS	PPS	I	ST	Timer2 External Clock Input
T3CK	PPS	PPS	PPS	PPS	I	ST	Timer3 External Clock Input
T4CK	PPS	PPS	PPS	PPS	I	ST	Timer4 External Clock Input
T5CK	PPS	PPS	PPS	PPS	I	ST	Timer5 External Clock Input
T6CK	PPS	PPS	PPS	PPS	I	ST	Timer6 External Clock Input
T7CK	PPS	PPS	PPS	PPS	I	ST	Timer7 External Clock Input
T8CK	PPS	PPS	PPS	PPS	I	ST	Timer8 External Clock Input
T9CK	PPS	PPS	PPS	PPS	I	ST	Timer9 External Clock Input
Real-Time Clock and Calendar
RTCC	46	71	A48	104	O	—	Real-Time Clock Alarm/Seconds Output

TABLE 1-8: UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Universal Asynchronous Receiver Transmitter 1
U1RX PPS PPS PPS PPS PPS I ST UA	RT1 Rece	ve
U1TX PPS PPS PPS PPS PPS O	— U	ART1 Tran	smit
U1CTS	PPS PPS PPS PPS I ST UART1 Clear to Send
U1RTS	PPS PPS PPS PPS O	— U	ART1 Ready to Send
Universal Asynchronous Receiver Transmitter 2
U2RX PPS PPS PPS PPS I ST UA	RT2 Rece	ve
U2TX PPS PPS PPS PPS O	— U	ART2 Tran	smit
U2CTS	PPS PPS PPS PPS I ST UART2 Clear To Send
U2RTS	PPS	PPS	PPS	PPS	O	—	UART2 Ready To Send
Universal Asynchronous Receiver Transmitter 3
U3RX PPS PPS PPS PPS I ST UART3 Rece	ve
U3TX PPS PPS PPS PPS O	— U	ART3 Tran	smit
U3CTS	PPS PPS PPS PPS I ST UART3 Clear to Send
U3RTS	PPS PPS PPS PPS O	— U	ART3 Ready to Send
Universal Asynchronous Receiver Transmitter 4
U4RX PPS PPS PPS PPS I ST UART4 Rece	ve
U4TX PPS PPS PPS PPS O	— U	ART4 Tran	smit
U4CTS	PPS PPS PPS PPS I ST UART4 Clear to Send
U4RTS	PPS PPS PPS PPS O	— U	ART4 Ready to Send
Universal Asynchronous Receiver Transmitter 5
U5RX PPS PPS PPS PPS I ST UART5 Rece	ve
U5TX PPS PPS PPS PPS O	— U	ART5 Tran	smit
U5CTS	PPS PPS PPS PPS I ST UART5 Clear to Send
U5RTS	PPS PPS PPS PPS O	— U	ART5 Ready to Send
Universal Asynchronous Receiver Transmitter 6
U6RX PPS PPS PPS PPS I ST UART6 Rece	ve
U6TX PPS PPS PPS PPS O	— U	ART6 Tran	smit
U6CTS	PPS PPS PPS PPS I ST UART6 Clear to Send
U6RTS	PPS PPS PPS PPS O	— U	ART6 Ready to Send

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-9: SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Serial Peripheral Interface 1
SCK1 49 76	A52 109 I/O	ST SPI1 Synchronous	is Serial	Clock Input/Output
SDI1	PPS	PPS	PPS	PPS	I	ST	SPI1 Data In
SDO1	PPS	PPS	PPS	PPS	O	—	SPI1 Data Out
SS1	PPS	PPS	PPS	PPS	I/O	ST	SPI1 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 2
SCK2	4	10	B6	14	I/O	ST	SPI2 Synchronous Serial Clock Input/output
SDI2	PPS	PPS	PPS	PPS	I	ST	SPI2 Data In
SDO2	PPS	PPS	PPS	PPS	O	—	SPI2 Data Out
SS2	PPS	PPS	PPS	PPS	I/O	ST	SPI2 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 3
SCK3	29	43	A28	61	I/O	ST	SPI3 Synchronous Serial Clock Input/Output
SDI3	PPS	PPS	PPS	PPS	I	ST	SPI3 Data In
SDO3	PPS	PPS	PPS	PPS	O	—	SPI3 Data Out
SS3	PPS	PPS	PPS	PPS	I/O	ST	SPI3 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 4
SCK4	44	69	A46	98	I/O	ST	SPI4 Synchronous Serial Clock Input/Output
SDI4	PPS	PPS	PPS	PPS	I	ST	SPI4 Data In
SDO4	PPS	PPS	PPS	PPS	O	—	SPI4 Data Out
SS4	PPS	PPS	PPS	PPS	I/O	ST	SPI4 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 5
SCK5	—	39	A26	57	I/O	ST	SPI5 Synchronous Serial Clock Input/Output
SDI5	—	PPS	PPS	PPS	I	ST	SPI5 Data In
SDO5	—	PPS	PPS	PPS	O	—	SPI5 Data Out
SS5	—	PPS	PPS	PPS	I/O	ST	SPI5 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 6
SCK6	—	48	A32	70	I/O	ST	SPI6 Synchronous Serial Clock Input/Output
SDI6	—	PPS	PPS	PPS	I	ST	SPI6 Data In
SDO6	—	PPS	PPS	PPS	O	—	SPI6 Data Out
SS6	—	PPS	PPS	PPS	I/O	ST	SPI6 Slave Synchronization Or Frame Pulse I/O

TABLE 1-10: I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP
Inter-Integrated Circuit 1
SCL1 44 66	B37 95 I/O	ST I2C1 Synchronous		Serial Clock Input/Output
SDA1 43 67	A45 96 I/O	ST I2C1 Synchronous		Serial Data Input/Output
Inter-Integrated Circuit 2
SCL2	—	59 A41	85 I/O ST	I2C2 Synchronous	Serial Clock Input/Output
SDA2	—	60 B34	86 I/O ST	I2C2 Synchronous	Serial Data Input/Output
Inter-Integrated Circuit 3
SCL3 51 58	A39 80 I/O	ST I2C3 Synchronous		Serial Clock Input/Output
SDA3 50 57	B31 79 I/O	ST I2C3 Synchronous		Serial Data Input/Output
Inter-Integrated Circuit 4
SCL4	6	12	B7	16	I/O	ST	I2C4 Synchronous Serial Clock Input/Output
SDA4	5	11	A8	15	I/O	ST	I2C4 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 5
SCL5 42 65	A44 91 I/O	ST I2C5 Synchronous		Serial Clock Input/Output
SDA5 41 64	B36 90 I/O	ST I2C5 Synchronous		Serial Data Input/Output

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-11: COMPARATOR 1, COMPARATOR 2 AND CREF PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Comparator Voltage Reference
CVREF+	16	29	A20	40	I	Analog	Comparator Voltage Reference (High) Input
CVREF-	15	28	B15	39	I	Analog	Comparator Voltage Reference (Low) Input
CVREFOUT	23	34	B19	49	O	Analog	Comparator Voltage Reference Output
Comparator 1
C1INA	11	20	B11	25	I	Analog	Comparator 1 Positive Input
C1INB	12	21	A13	26	I	Analog	Comparator 1 Selectable Negative Input
C1INC	5	11	A8	15	I	Analog
C1IND	4	10	B6	14	I	Analog
C1OUT	PPS	PPS	PPS	PPS	O	—	Comparator 1 Output
Comparator 2
C2INA	13	22	A14	31	I	Analog	Comparator 2 Positive Input
C2INB	14	23	A16	34	I	Analog	Comparator 2 Selectable Negative Input
C2INC	10	16	B9	21	I	Analog
C2IND	6	12	B7	16	I	Analog
C2OUT	PPS	PPS	PPS	PPS	O	—	Comparator 2 Output

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-12: PMP PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PMA0 30 44	B24 30 I/O	TTL/ST	Parallel Master	Port Address bit	0 Input (Buffered Slave modes) and Output (Master modes)
PMA1 29 43	A28 51 I/O	TTL/ST	Parallel Master	Port Address bit	1 Input (Buffered Slave modes) and Output (Master modes)
PMA2	10	16	B9	21	O	—	Parallel Master Port Address (Demultiplexed Master modes)
PMA3	6	12 B7	52	O —
PMA4	5	11 A8	68	O —
PMA5	4	2	B1	2	O	—
PMA6	16	6	B3	6	O	—
PMA7	22	33	A23	48	O	—
PMA8	42	65	A44	91	O	—
PMA9	41	64	B36	90	O	—
PMA10	21	32	B18	47	O	—
PMA11	27	41	A27	29	O	—
PMA12	24	7	A6	11	O	—
PMA13	23	34	B19	28	O	—
PMA14	45	61	A42	87	O	—
PMA15	43	68	B38	97	O	—
PMCS1	45	61	A42	87	O	—	Parallel Master Port Chip Select 1 Strobe
PMCS2	43	68	B38	97	O	—	Parallel Master Port Chip Select 2 Strobe
PMD0	58	91	B52	135	I/O	TTL/ST	Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes)
PMD1	61 94	A64	138	I/O TTL/ST
PMD2	62 98	A66	142	I/O TTL/ST
PMD3	63 99	B56	143	I/O TTL/ST
PMD4	64	100	A67	144	I/O	TTL/ST
PMD5	1	3	A3	3	I/O	TTL/ST
PMD6	2	4	B2	4	I/O	TTL/ST
PMD7	3	5	A4	5	I/O	TTL/ST
PMD8	—	88	B50	128	I/O	TTL/ST
PMD9	—	87	A60	127	I/O	TTL/ST
PMD10	—	86	B49	125	I/O	TTL/ST
PMD11	—	85	A59	124	I/O	TTL/ST
PMD12	—	79	B43	112	I/O	TTL/ST
PMD13	—	80	A54	113	I/O	TTL/ST
PMD14	—	77	B42	110	I/O	TTL/ST
PMD15	—	78	A53	111	I/O	TTL/ST
PMALL	30	44	B24	30	O	—	Parallel Master Port Address Latch Enable Low Byte (Multiplexed Master modes)
PMALH	29	43	A28	51	O	—	Parallel Master Port Address Latch Enable High Byte (Multiplexed Master modes)
PMRD	53	9	A7	13	O	—	Parallel Master Port Read Strobe
PMWR	52	8	B5	12	O	—	Parallel Master Port Write Strobe

TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
EBIA0 — 44	B24 30 O	External	Bus Interface Address		Bus
EBIA1 — 43	A28	51 O	—
EBIA2 — 16	B9	21 O	—
EBIA3 — 12	B7	52 O	—
EBIA4 —	11 A8	68 O	—
EBIA5 —	2 B1	2 O	—
EBIA6 —	6 B3	6 O	—
EBIA7 — 33	A23	48 O	—
EBIA8 — 65	A44	91 O	—
EBIA9 — 64	B36	90 O	—
EBIA10	— 32	B18	47 C	—
EBIA11	— 41	A27	29 O	—
EBIA12	—	7	A6	11	O	—
EBIA13	— 34	B19	28 C	—
EBIA14	— 61	A42	87 C	—
EBIA15	— 68	B38	97 C	—
EBIA16	— 17	A11	19 O	—
EBIA17	— 40	B22	53 C	—
EBIA18	— 39	A26	92 C	—
EBIA19	— 38	B21	93 C	—
EBIA20	—	—	—	94	O	—
EBIA21	—	—	—	126	O	—
EBIA22	—	—	—	117	O	—
EBIA23	—	—	—	103	O	—
EBID0	—	91	B52	135	I/O	ST	External Bus Interface Data I/O Bus
EBID1	—	94	A64	138	I/O	ST
EBID2	—	98	A66	142	I/O	ST
EBID3	—	99	B56	143	I/O	ST
EBID4	—	100	A67	144	I/O	ST
EBID5	—	3	A3	3	I/O	ST
EBID6	—	4	B2	4	I/O	ST
EBID7	—	5	A4	5	I/O	ST
EBID8	—	88	B50	128	I/O	ST
EBID9	—	87	A60	127	I/O	ST
EBID10	—	86	B49	125	I/O	ST
EBID11	— 85	A59	124 I/O ST
EBID12	—	79	B43	112	I/O	ST
EBID13	—	80	A54	113	I/O	ST
EBID14	—	77	B42	110	I/O	ST
EBID15	—	78	A53	111	I/O	ST
EBIBS0	—	—	—	9	O	—	External Bus Interface Byte Select
EBIBS1	—	—	—	10	O	—	External Bus Interface Byte Select
EBICS0	— 59	A41	131 O	— External Bus Interface Chip			Select
EBICS1	—	—	—	132	O	—
EBICS2	—	—	—	133	O	—
EBICS3	—	—	—	134	O	—

TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
EBIOE	— 9 A7	13 O — External Bus Interface	Interface	Output Enable
EBIRDY1 —	60 B34 86	I ST External Bus Interface Ready Input
EBIRDY2 —	58 A39	84 I	ST
EBIRDY3 —	57 B45	116 I ST
EBIRP	— —	— 45 O — External Bus Interface	Flash Reset	Pin
EBIWE	— 8 B5	12 O — External Bus Interface	Write Enable

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-14: USB PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
VBUS	33 51	A35 73 I An	alog USB bus power		monitor
VUSB3V3	34 52	A36 74 P —	USB internal transceiver		supply. If the USB module is not used, this pin must be connected to Vss. When connected, the shared pin functions on USBID will not be available.
D+	37 55	B30 77	I/O	Analog USB D+
D-	36 54	A37 76	I/O	Analog USB D-
USBID	38	56	A38	78	I	ST	USB OTG ID detect

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-15: CAN1 AND CAN2 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
C1TX	PPS	PPS	PPS	PPS	O	—	CAN1 Bus Transmit Pin
C1RX	PPS	PPS	PPS	PPS	I	ST	CAN1 Bus Receive Pin
C2TX	PPS	PPS	PPS	PPS	O	—	CAN2 Bus Transmit Pin
C2RX	PPS	PPS	PPS	PPS	I	ST	CAN2 Bus Receive Pin

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-16: ETHERNET MII I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
ERXD0 61 41	B32 81 I	ST Ethernet	Receive Data 0
ERXD1 58 42	B26 66 I	ST Ethernet	Receive Data 1
ERXD2 57 43	A31 67 I	ST Ethernet	Receive Data 2
ERXD3 56 44	A40 82 I	ST Ethernet	Receive Data 3
ERXERR 64	35 A30 65	I ST Ethernet	Receive Error Input
ERXDV 62 12	B40 101	I ST	Ethernet Receive Data Valid
ERXCLK	63 16	B12 27 I ST	Ethernet Receive Clock
ETXD0	2	86	A5	7	O	—	Ethernet Transmit Data 0
ETXD1	3	85	B4	8	O	—	Ethernet Transmit Data 1
ETXD2	43	79	B17	43	O	—	Ethernet Transmit Data 2
ETXD3	46	80	A22	44	O	—	Ethernet Transmit Data 3
ETXERR	50	87	B44	114	O	—	Ethernet Transmit Error
ETXEN	1	77	A57	120	O	—	Ethernet Transmit Enable
ETXCLK	51	78	B47	121	I	ST	Ethernet Transmit Clock
ECOL	44 10	B33 83 I ST	Ethernet Collision Detect
ECRS	45	11	A47	100	I	ST	Ethernet Carrier Sense
EMDC	30	70	B39	99	O	—	Ethernet Management Data Clock
EMDIO	49	71	A55	115	I/O	—	Ethernet Management Data

TABLE 1-17: ETHERNET RMII PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Ethernet MII Interface
ERXD0	61	41	B32	81	I	ST	Ethernet Receive Data 0
ERXD1	58	42	B26	66	I	ST	Ethernet Receive Data 1
ERXERR	64	35	A30	65	I	ST	Ethernet Receive Error Input
ETXD0	2	86	A5	7	O	—	Ethernet Transmit Data 0
ETXD1	3	85	B4	8	O	—	Ethernet Transmit Data 1
ETXEN	1	77	A57	120	O	—	Ethernet Transmit Enable
EMDC	30	70	B39	99	O	—	Ethernet Management Data Clock
EMDIO	49	71	A55	115	I/O	—	Ethernet Management Data
EREFCLK	63	16	B12	27	I	ST	Ethernet Reference Clock
ECRSDV	62	12	B40	101	I	ST	Ethernet Carrier Sense Data Valid

TABLE 1-18: ALTERNATE ETHERNET MII PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AERXD0 —	18 — — I ST	Alternate	Ethernet	Receive Data 0
AERXD1 —	19 — — I ST	Alternate	Ethernet	Receive Data 1
AERXD2 —	28 — — I ST	Alternate	Ethernet	Receive Data 2
AERXD3 —	29 — — I ST	Alternate	Ethernet	Receive Data 3
AERXERR —	1 — — I ST	Alternate	Ethernet	Receive Error Input
AERXDV	— 12 — — I ST	Alternate Ethernet	Receive Data Valid
AERXCLK	— 16 — — I ST	Alternate Ethernet	Receive Clock
AETXD0	—	47	—	—	O	—	Alternate Ethernet Transmit Data 0
AETXD1	—	48	—	—	O	—	Alternate Ethernet Transmit Data 1
AETXD2	—	44	—	—	O	—	Alternate Ethernet Transmit Data 2
AETXD3	—	43	—	—	O	—	Alternate Ethernet Transmit Data 3
AETXERR	—	35	—	—	O	—	Alternate Ethernet Transmit Error
AECOL	— 42 — — I ST	Alternate Ethernet	Collision Detect
AECRS — 41 — — I ST	Alternate Ethernet Carrier Sense
AETXCLK	— 66 — — I ST	Alternate Ethernet	Transmit Clock
AEMDC	—	70	—	—	O	—	Alternate Ethernet Management Data Clock
AEMDIO	—	71	—	—	I/O	—	Alternate Ethernet Management Data
AETXEN	—	67	—	—	O	—	Alternate Ethernet Transmit Enable

TABLE 1-19: ALTERNATE ETHERNET RMII PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AERXD0	43	18	—	—	I	ST	Alternate Ethernet Receive Data 0
AERXD1	46	19	—	—	I	ST	Alternate Ethernet Receive Data 1
AERXERR	51	1	—	—	I	ST	Alternate Ethernet Receive Error Input
AETXD0	57	47	—	—	O	—	Alternate Ethernet Transmit Data 0
AETXD1	56	48	—	—	O	—	Alternate Ethernet Transmit Data 1
AEMDC	30	70	—	—	O	—	Alternate Ethernet Management Data Clock
AEMDIO	49	71	—	—	I/O	—	Alternate Ethernet Management Data
AETXEN	50	67	—	—	O	—	Alternate Ethernet Transmit Enable
AEREFCLK	45	16	—	—	I	ST	Alternate Ethernet Reference Clock
AECRSDV	62	12	—	—	I	ST	Alternate Ethernet Carrier Sense Data Valid

TABLE 1-20: SQI1 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
SQICLK 57 89 A61 129	O — Serial	Quad Interface Clock
SQICS0	52 81 A56 118	O — Serial Quad			Interface	Chip Select 0
SQICS1	53 82 B46 119	O — Serial Quad			Interface	Chip Select 1
SQID0	58	97	B55	141	I/O	ST	Serial Quad Interface Data 0
SQID1	61	96	A65	140	I/O	ST	Serial Quad Interface Data 1
SQID2	62	95	B54	139	I/O	ST	Serial Quad Interface Data 2
SQID3	63	90	B51	130	I/O	ST	Serial Quad Interface Data 3

Legend:

CMOS = CMOS-compatible input or outputST = Schmitt Trigger input with CMOS levelsTTL = Transistor-transistor Logic input buffer

Analog = Analog inputO = OutputPPS = Peripheral Pin Select

P = PowerI = Input

TABLE 1-21: POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Power and Ground
AVDD	19	30	B16	41	P	P	Positive supply for analog modules. This pin must be connected at all times.
AVss	20	31	A21	42	P	P	Ground reference for analog modules. This pin must be connected at all times
VDD	8, 26, 39, 54, 60	14, 37, 46, 62, 74, 83, 93	B8, A15, A25, B25, B35, A50, A58, B53	18, 33, 55, 64, 88, 107, 122, 137	P	—	Positive supply for peripheral logic and I/O pins. This pin must be connected at all times.
Vss	7, 25, 35, 40, 55, 59	13, 36, 45, 53, 63, 75, 84, 92	A9, B13, B20, B29, A29, A43, A51, B48, A63	17, 32, 54, 63, 75, 89, 108, 123, 136	P	—	Ground reference for logic, I/O pins, and USB. This pin must be connected at all times.
Voltage Reference
VREF+	16	29	A20	40	I	Analog	Analog Voltage Reference (High) Input
VREF-	15	28	B15	39	I	Analog	Analog Voltage Reference (Low) Input

Legend:	CMOS = CMOS-compatible input or output	Analog = Analog input	P = Power
	ST = Schmitt Trigger input with CMOS levels	O = Output	I = Input
	TTL = Transistor-transistor Logic input buffer	PPS = Peripheral Pin Select

TABLE 1-22: JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
JTAG
TCK 27 38 B	21 56 I ST	JTAG Test	Clock Input	Pin
TDI	28 39	A26 57 I ST	JTAG Test	Data Input	Pin
TDO	24	40	B22	58	O	—	JTAG Test Data Output Pin
TMS	23 17	A11	22 I ST JTAG	Test Mode	Select Pin
Trace
TRCLK	57	89	A61	129	O	—	Trace Clock
TRD0	58	97	B55	141	O	—	Trace Data bits 0-3
TRD1	61	96	A65	140	O	—
TRD2	62	95	B54	139	O	—
TRD3	63	90	B51	130	O	—
Programming/Debugging
PGED1	16	25	A18	36	I/O	ST	Data I/O pin for Programming/Debugging Communication Channel 1
PGEC1	15 24	A17 35 I ST	Clock input	pin for Programming/Debugging	I/O	ST	Data I/O pin for Programming/Debugging Communication Channel 2
PGED2	18	27	A19	38	I/O	ST	Data I/O pin for Programming/Debugging Communication Channel 2
PGEC2	17 26	B14 37 I ST	Clock input	pin for Programming/Debugging	I/P	ST	Master Clear (Reset) input. This pin is an active-low Reset to the device.
MCLR	9	15	A10	20	I/P	ST	Master Clear (Reset) input. This pin is an active-low Reset to the device.

NOTES:

2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS

2.1 Basic Connection Requirements

Note: The PIC32MZ EC family of devices require a unique VDD ramp-up time. Please refer to parameter DC17 in Table 37-4 of 37.0 "Electrical Characteristics" before finalizing regulator design.

Getting started with the PIC32MZ EC family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected:

A I DD and Vss pins (see 2.2 "Decoupling Capacitors")
A I DD and AVSS pins, even if the ADC module is not used (see 2.2 "Decoupling Capacitors")
MCLR pin (see 2.3 "Master Clear (MCLR) Pin")
PGECx/PGEDx pins, used for In-Circuit Serial Programming (ICSP™) and debugging purposes (see 2.4 "ICSP Pins")
OSC1 and OSC2 pins, when external oscillator source is used (see 2.7 "External Oscillator Pins")

The following pin(s) may be required as well:

VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented.

Note: The AV DD and AVss pins must be connected, regardless of ADC use and the ADC voltage reference source.

2.2 Decoupling Capacitors

The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1.

Consider the following criteria when using decoupling capacitors:

Value and type of capacitor: A value of 0.1 F (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used.

- Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

- Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F . Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F .

- Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

Note: The PIC32MZ EC family of devices require a unique VDD ramp-up time. Please refer to parameter DC17 in Table 37-4 of 37.0 "Electrical Characteristics" before finalizing regulator design.

FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
Microchip PIC32MZ1024ECM124 - Decoupling Capacitors - 1

text_image

VDD R1 MCLR VSS VDD VDD VSS 0.1 μF Ceramic VSS VDD PIC32 VUSB3v(1) VSS VDD VSS 0.1 μF Ceramic 0.1 μF Ceramic VDD VSS AVDD AVSS VDD VSS 0.1 μF Ceramic Connect(2) 0.1 μF Ceramic 0.1 μF Ceramic L1(2)

Note 1: If the USB module is not used, this pin must not be connected to VDD.
2: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1 and the inductor capacity greater than 10 mA.

Where:

$$ f = \frac {F _ {C N V}}{2} \quad (\text { i.e., ADC conversion rate } / 2) $$

$$ f = \frac {1}{(2 \pi \sqrt {L C})} $$

$$ L = \left(\frac {1}{(2 \pi f \sqrt {C})}\right) ^ {2} $$

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible.

2.3 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device functions:

Device Reset
• Device programming and debugging

Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.

For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations.

Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS ^(1,2,3)
Microchip PIC32MZ1024ECM124 - Master Clear (MCLR) Pin - 1

text_image

VDD R 10k 0.1 μF(2) C R1(1) 1 kΩ MCLR PIC32 5 4 2 VDD 3 Vss 6 NC PGECx(3) PGEDx(3)

Note 1: 470 ≤ R1 ≤ 1 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VH and VII specifications are met without interfering with the Debug/Programmer tools.
2: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR.
3: No pull-ups or bypass capacitors are allowed on active debug/program PGECx/PGEDx pins.

2.4 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements.

Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™.

For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available from the Microchip web site.

"Using MPLAB ^ ICD 3" (poster) (DS50001765)
"MPLAB ^ ICD 3 Design Advisory" (DS50001764)
"MPLAB ^ REAL ICE ^TM In-Circuit Debugger User's Guide" (DS50001616)
"Using MPLAB ^ REAL ICE ^TM Emulator" (poster) (DS50001749)

2.5 JTAG

The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VL) requirements.

2.6 Trace

The trace pins can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. When used for trace, the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 Ohm series resistor between the trace pins and the trace connector.

2.7 External Oscillator Pins

Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details).

The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3.

FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT
Microchip PIC32MZ1024ECM124 - External Oscillator Pins - 1

text_image

Oscillator Secondary Guard Trace Guard Ring Main Oscillator

2.7.1 CRYSTAL OSCILLATOR DESIGN CONSIDERATION

The following example assumptions are used to calculate the Primary Oscillator loading capacitor values:

• CIN = PIC32_OSC2_Pin Capacitance = \~4-5 pF
• COUT = PIC32_OSC1_Pin Capacitance = \~4-5 pF
- C1 and C2 = XTAL manufacturing recommended loading capacitance
- Estimated PCB stray capacitance, (i.e., 12 mm length) = 2.5 pF

Crystals with a speed of 4 MHz to 12 MHz that meet the following requirements will meet the PIC32MZ EC oscillation requirements when configured, as depicted in Figure 8-1.

Manufacturer Drive Level (min) ≤ 10 μW (hard requirements, 1 μW preferred).
Manufacturer ESR ≤ 50Ω (hard requirement, lower is better).

2.7.1.1 Calculating XTAL Capacitive Loading:

PIC32 C IN = COUT = \~4 pF (PIC32 OSCI and OSCO package pin capacitance).
C1 MFG = C2MFG = Manufacturer Recommended Load Capacitance.
CLOAD = {{[CIN + C1MFG] [C2MFG + COUT] / [CIN + C1MFG + C2MFG + COUT]} + estimated PCB stray capacitance (2.5 pF). (Simplified) CLOAD = (((CIN + C1 MFG) / 2) + 2.5 pF).

Actual C1, C2 Load value to use:

• C 2 ±OAD
• C 1 =LO(ADC-2 pF)

Note: These recommendations are atypical, and are only applicable to the PIC32MZ EC family.

2.7.1.2 Validated Crystals

Temperature Range: (-45°C to +110°C)
V_DD=2.4V to 3.6V, RP=1M , RK=10k
• ABLS-12.000 MHz-L4Q-T (12 MHz surface mount)

Note: These recommendations are atypical, and only applicable to the PIC32MZ EC family.

2.7.1.3 Additional Microchip References

• A N 5 8 8 "P1 Microcontroller Oscillator Design Guide"
- A N 8 2 6 "Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices"
• A N 8 4 9 "Basic P1O5mator Design"

2.8 Unused I/Os

Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state.

Alternatively, inputs can be reserved by connecting the pin to Vss through a 1k to 10k resistor and configuring the pin as an input.

2.9 Designing for High-Speed Peripherals

The PIC32MZ EC family devices have peripherals that operate at frequencies much higher than typical for an embedded environment. Table 2-1 lists the peripherals that produce high-speed signals on their external pins:

TABLE 2-1: PERIPHERALS THAT PRODUCE HS SIGNALS ON EXTERNAL PINS

Peripheral	High-Speed Signal Pins	Maximum Speed on Signal Pin
EBI	EBIAx, EBIDx	50 MHz
SQI1	SQICLK, , SQIDx	50 MHz
HS USB	D+, D-	480 MHz

Due to these high-speed signals, it is important to take into consideration several factors when designing a product that uses these peripherals, as well as the PCB on which these components will be placed. Adhering to these recommendations will help achieve the following goals:

Minimize the effects of electromagnetic interference to the proper operation of the product
Ensure signals arrive at their intended destination at the same time
Minimize crosstalk
Maintain signal integrity
Reduce system noise
Minimize ground bounce and power sag

2.9.1 SYSTEM DESIGN

2.9.1.1 Impedance Matching

When selecting parts to place on high-speed buses, particularly the SQI bus, if the impedance of the peripheral device does not match the impedance of the pins on the PIC32MZ EC device to which it is connected, signal reflections could result, thereby degrading the quality of the signal.

If it is not possible to select a product that matches impedance, place a series resistor at the load to create the matching impedance. See Figure 2-4 for an example.

FIGURE 2-4: SERIES RESISTOR
Microchip PIC32MZ1024ECM124 - Impedance Matching - 1

text_image

PIC32MZ 50Ω SQI Flash Device

2.9.1.2 PCB Layout Recommendations

The following list contains recommendations that will help ensure the PCB layout will promote the goals previously listed.

- Component Placement

Place bypass capacitors as close to their component power and ground pins as possible, and place them on the same side of the PCB
Devices on the same bus that have larger setup times should be placed closer to the PIC32MZ EC device

- Power and Ground

Multi-layer PCBs will allow separate power and ground planes
Each ground pin should be connected to the ground plane individually
Place bypass capacitor vias as close to the pad as possible (preferably inside the pad)
If power and ground planes are not used, maximize width for power and ground traces
Use low-ESR, surface-mount bypass capacitors

- Clocks and Oscillators

Place crystals as close as possible to the PIC32MZ EC device OSC/SOSC pins
Do not route high-speed signals near the clock or oscillator
Avoid via usage and branches in clock lines (SQICLK)
Place termination resistors at the end of clock lines

- Traces

Higher-priority signals should have the shortest traces
Match trace lengths for parallel buses (EBIAx, EBIDx, SQIDx)
Avoid long run lengths on parallel traces to reduce coupling
Make the clock traces as straight as possible
Use rounded turns rather than right-angle turns
Have traces on different layers intersect on right angles to minimize crosstalk
Maximize the distance between traces, preferably no less than three times the trace width
Power traces should be as short and as wide as possible
High-speed traces should be placed close to the ground plane

2.10 Considerations When Interfacing to Remotely Powered Circuits

2.10.1 NON-5V TOLERANT INPUT PINS

A quick review of the absolute maximum rating section in 37.0 "Electrical Characteristics" will indicate that the voltage on any non-5v tolerant pin may not exceed AVDD/VDD + 0.3V. Figure 2-5 shows an example of a remote circuit using an independent power source, which is powered while connected to a PIC32 non-5V tolerant circuit that is not powered.

FIGURE 2-5: PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE
Microchip PIC32MZ1024ECM124 - NON-5V TOLERANT INPUT PINS - 1

flowchart

graph TD
    A["Remote 0.3V ≤ VIH ≤ 3.6V"] --> B["AN2/RB0"]
    C["Remote GND"] --> B
    B --> D["AnSEL"]
    D --> E["I/O IN"]
    D --> F["I/O OUT"]
    D --> G["TRIS"]
    H["VDD"] --> I["On/Off"]
    I --> J["CPU LOGIC"]
    J --> K["VSS"]
    L["PIC32 POWER SUPPLY"] --> M["On/Off"]
    N["Note: When V DD power is OFF."] --> O["Current Flow"]
    O --> P["AND Gate"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style H fill:#ccf,stroke:#333
    style L fill:#cfc,stroke:#333

Without proper signal isolation, on non-5V tolerant pins, the remote signal can power the PIC32 device through the high side ESD protection diodes. Besides violating the absolute maximum rating specification when VDD of the PIC32 device is restored and ramping up or ramping down, it can also negatively affect the internal Power-on Reset (POR) and Brown-out Reset (BOR) circuits, which can lead to improper initialization of internal PIC32 logic circuits. In these cases, it is recommended to implement digital or analog signal isolation as depicted in Figure 2-6, as appropriate. This is indicative of all industry microcontrollers and not just Microchip products.

TABLE 2-2: EXAMPLES OF DIGITAL/ ANALOG ISOLATORS WITH OPTIONAL LEVEL TRANSLATION

Example Digital/Analog Signal Isolation Circuits	Inductive Coupling	Capacitive Coupling	Opto Coupling	Analog/Digital Switch
ADuM7241 / 40 ARZ (1 Mbps) X	— —	—
ADuM7241 / 40 CRZ (25 Mbps)	X —	— —
ISO721 — X — —
LTV-829S (2 Channel)	— —	X —
LTV-849S (4 Channel)	— —	X —
FSA266 / NC7WB66	— —	—	X

FIGURE 2-6: DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS
Microchip PIC32MZ1024ECM124 - NON-5V TOLERANT INPUT PINS - 2

flowchart

Circuit diagrams of PIC32 and VDD-based analog-to-digital isolation systems, showing connections between external, remote, and digital isolators.

2.10.2 5V TOLERANT INPUT PINS

The internal high side diode on 5V tolerant pins are bussed to an internal floating node, rather than being connected to VDD, as shown in Figure 2-7. Voltages on these pins, if VDD < 2.3V, should not exceed roughly 3.2V relative to Vss of the PIC32 device. Voltage of 3.6V or higher will violate the absolute maximum specification, and will stress the oxide layer separating the high side floating node, which impacts device reliability. If a remotely powered "digital-only" signal can be guaranteed to always be ≤ 3.2V relative to Vss on the PIC32 device side, a 5V tolerant pin could be used without the need for a digital isolator. This is assuming there is not a ground loop issue, logic ground of the two circuits not at the same absolute level, and a remote logic low input is not less than Vss - 0.3V.

FIGURE 2-7: PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
Microchip PIC32MZ1024ECM124 - 5V TOLERANT INPUT PINS - 1

flowchart

graph TD
    A["Remote GND"] --> B["Remote VIH = 2.5V"]
    B --> C["RG10"]
    C --> D["Floating Bus Oxide BV = 3.6V if VDD < 2.3V"]
    D --> E["OXIDE"]
    E --> F["ANSEL"]
    F --> G["I/O IN"]
    F --> H["I/O OUT"]
    F --> I["TRIS"]
    G --> J["CPU LOGIC"]
    H --> J
    I --> J
    J --> K["VSS"]
    L["On/Off"] --> M["PIC32 POWER SUPPLY"]
    N["VDD"] --> O["On/Off"]
    P["VSS"] --> Q["AnSEL"]
    R["VSS"] --> S["TRIS"]

2.10.2.1 EMI Suppression Considerations

The use of LDO regulators is preferred to reduce overall system noise and provide a cleaner power source. However, when utilizing switching Buck/Boost regulators as the local power source for PIC32MZ EF devices, as well as in electrically noisy environments, users should evaluate the use of T-Filters (i.e., L-C-L) on the power pins, as shown in Figure 2-8. In addition to a more stable power source, use of this type of T-Filter can greatly reduce susceptibility to EMI sources and events.

FIGURE 2-8:
Microchip PIC32MZ1024ECM124 - EMI Suppression Considerations - 1

text_image

Ferrite Chip SMD DCR = 0.15Ω (max) 600 ma ISAT 300Ω @ 100 MHz PN#: 1-1624117-3 VDD Ferrite Chips 0.01 μF 0.1 μF VDD VSS VSS VDD PIC32MZ VSS VDD 0.1 μF 0.1 μF VSS VDD 0.1 μF 0.1 μF VSS VDD 0.1 μF 0.1 μF AVDD AVSS VSS VDD 0.1 μF 0.1 μF 0.1 μF Ferrite Chips VDD 0.01 μF

2.11 Typical Application Connection Examples

Examples of typical application connections are shown in Figure 2-9 and Figure 2-10.

FIGURE 2-9: AUDIO PLAYBACK APPLICATION
Microchip PIC32MZ1024ECM124 - Typical Application Connection Examples - 1

flowchart

graph LR
    A["USB Host"] <--> B["USB"]
    B --> C["PMP"]
    C --> D["Display"]
    B --> E["PMD<7:0>"]
    E --> D
    B --> F["PMWR"]
    F --> D
    B --> G["I²S"]
    G --> H["Audio Codec"]
    H --> I["Stereo Headphones"]
    H --> J["Speaker"]
    B --> K["REFCLKO"]
    K --> L["MMC SD"]
    B --> M["SPI"]
    M --> N["SDI"]
    N --> O["3/"]
    O --> H

FIGURE 2-10: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH PROJECTED CAPACITIVE TOUCH
Microchip PIC32MZ1024ECM124 - Typical Application Connection Examples - 2

flowchart

graph TD
    A["Microchip mTouch™ Library"] --> B["Microchip GFX Library"]
    B --> C["DMA"]
    B --> D["EBI"]
    D --> E["LED Display"]
    E --> F["Projected Capacitive Touch Overlay"]
    F --> G["SRAM"]
    G --> H["External Frame Buffer"]
    I["ADC"] --> B
    J["Render"] --> D
    K["ANx"] --> E
    L["PIC32"] --> A
    L --> B

3.0 CPU

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 50. "CPU for Devices with MIPS32® microAptiv™ and M-Class Cores" (DS60001192), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

MIPS32 ^® microAptiv ^™ Microprocessor Core resources are available at: www.imgtec.com.

The MIPS32 ^® microAptiv ^™ Microprocessor Core is the heart of the PIC32MZ EC family device processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations.

3.1 Features

PIC32MZ EC family processor core key features:

5-stage pipeline
• 32-bit address and data paths
MIPS32 ^® Enhanced Architecture (Release 2):
Multiply-accumulate and multiply-subtract instructions
Targeted multiply instruction
Zero/One detect instructions
WAIT instruction
Conditional move instructions (MOVN, MOVZ)
Vectored interrupts
Programmable exception vector base
Atomic interrupt enable/disable
GPR shadow registers to minimize latency for interrupt handlers
Bit field manipulation instructions
Virtual memory support

- microMIPS™ compatible instruction set:

- Improves code size density over MIPS32, while maintaining MIPS32 performance.

- Supports all MIPS32 instructions (except branch- likely instructions)

- Fifteen additional 32-bit instructions and 39 16-bit instructions corresponding to commonly-used MIPS32 instructions

- Stack pointer implicit in instruction

- MIPS32 assembly and ABI compatible

MMU with Translation Lookaside Buffer (TLB) mechanism:
16 dual-entry fully associative Joint TLB
4-entry fully associative Instruction TLB
4-entry fully associative Data TLB
4 KB pages

- Separate L1 data and instruction caches:

- 16 KB 4-way Instruction Cache (I-Cache)

- 4 KB 4-way Data Cache (D-Cache)

• Autonomous Multiply/Divide Unit (MDU):

- Maximum issue rate of one 32x32 multiply per clock

- Early-in iterative divide. Minimum 12 and maximum 38 clock latency (dividend (rs) sign extension-dependent)

- Power Control:

Minimum frequency: 0 MHz
Low-Power mode (triggered by WAIT instruction)
Extensive use of local gated clocks

- EJTAG Debug and Instruction Trace:

Support for single stepping
Virtual instruction and data address/value breakpoints
Hardware breakpoint supports both address match and address range triggering.
Eight instruction and four data complex breakpoints

- iFlowtrace ^® version 2.0 support:

Real-time instruction program counter
Special events trace capability
Two performance counters with 34 user-selectable countable events
Disabled if the processor enters Debug mode

- Four Watch registers:

Instruction, Data Read, Data Write options
Address match masking options

- DSP ASE Extension:

- Native fractional format data type operations

- Register Single Instruction Multiple Data (SIMD) operations (add, subtract, multiply, shift)

- GPR-based shift

- Bit manipulation

- Compare-Pick

- DSP Control Access

- Indexed-Load

- Branch

- Multiplication of complex operands

- Variable bit insertion and extraction

- Virtual circular buffers

- Arithmetic saturation and overflow handling

- Zero-cycle overhead saturation and rounding operations

A block diagram of the PIC32MZ EC family processor core is shown in Figure 3-1.

FIGURE 3-1: PIC32MZ EC FAMILY MICROPROCESSOR CORE
BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - Features - 1

flowchart

graph TD
    A["PBCLK7"] --> B["Decode (MIPS32®/microMIPSTM)"]
    B --> C["Execution Unit"]
    C --> D["ALU/Shift Atomic/LdSt DSP ASE"]
    D --> E["System Coprocessor"]
    E --> F["Debug/Profiling Break Points iFlowtrace® Fast Debug Channel Performance Counters Sampling Secure Debug"]
    F --> G["EJTAG"]
    G --> H["2-wire Debug"]
    H --> I["Power Management"]
    I --> J["D-Cache Controller"]
    J --> K["MMU (TLB)"]
    K --> L["I-Cache Controller"]
    L --> M["BIU"]
    M --> N["System Bus"]
    C --> O["GPR (8 sets)"]
    C --> P["Enhanced MDU (with DSP ASE)"]
    C --> Q["System Interface"]
    C --> R["Interrupt Interface"]
    R --> S["System Coprocessor"]
    S --> T["Debug/Profiling Break Points iFlowtrace® Fast Debug Channel Performance Counters Sampling Secure Debug"]
    T --> U["D-Cache Controller"]
    U --> V["I-Cache Controller"]
    V --> W["BIU"]
    W --> X["System Bus"]

3.2 Architecture Overview

The MIPS32 microAptiv Microprocessor core in PIC32MZ EC family devices contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core:

Execution unit
• General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
• System control coprocessor (CP0)
• Memory Management Unit (MMU)
Instruction/Data cache controllers
• Power Management
Instructions and data caches
microMIPS support
• Enhanced JTAG (EJTAG) controller

3.2.1 EXECUTION UNIT

The processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. Seven additional register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.

The execution unit includes:

• 32-bit adder used for calculating the data address
- Address unit for calculating the next instruction address
- Logic for branch determination and branch target address calculation
- Load aligner
- Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results

Leading Zero/One detect unit for implementing the CLZ and CLO instructions
Arithmetic Logic Unit (ALU) for performing arithmetic and bitwise logical operations
Shifter and store aligner
DSP ALU and logic block for performing DSP instructions, such as arithmetic/shift/compare operations

3.2.2 MULTIPLY/DIVIDE UNIT (MDU)

The processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions.

The high-performance MDU consists of a 32x32 booth recoded multiplier, four pairs of result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown ('32' of 32x32) represents the rs operand. The second number ('32' of 32x32) represents the rt operand.

The MDU supports execution of one multiply or multiply-accumulate operation every clock cycle.

Divide operations are implemented with a simple 1-bit-per-clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation has completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the processor core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks.

TABLE 3-1: MIPS32 microAptiv MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode	Operand Size (mul rt) (div rs)	Latency	Repeat Rate
MULT/MULTU, MADD/MADDU,MSUB/MSUBU (HI/LO destination)	16 bits	5	1
MULT/MULTU, MADD/MADDU,MSUB/MSUBU (HI/LO destination)	32 bits	5	1
MUL (GPR destination)	16 bits	5	1
MUL (GPR destination)	32 bits	5	1
DIV/DIVU	8 bits	12/14	12/14
	16 bits	20/22	20/22
	24 bits	28/30	28/30
	32 bits	36/38	36/38

The MIPS architecture defines that the result of a multiply or divide operation be placed in one of four pairs of HI and LO registers. Using the Move-From-HI (MFHI) and Move-From-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file.

In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased.

Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms.

The MDU also implements various shift instructions operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all of the data types required for this purpose and includes three extra HI/LO registers as defined by the ASE.

Table 3-2 lists the latencies and repeat rates for the DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of pipeline clocks.

TABLE 3-2: DSP-RELATED LATENCIES AND REPEAT RATES

Op code Latency		Repeat Rate
Multiply and dot-product without saturation after accumulation	5	1
Multiply and dot-product with saturation after accumulation	5	1
Multiply without accumulation	5	1

3.2.3 SYSTEM CONTROL COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation and cache protocols, the exception control system, the processor's diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as cache size and set associativity, and the presence of options like microMIPS, is also available by accessing the CP0 registers, listed in Table 3-3.

TABLE 3-3: COPROCESSOR 0 REGISTERS

Register Number	Register Name	Function
0 Index	Index into the TLB array (microAptiv MPU only).
1 Random	Randomly generated index into the TLB array (microAptiv MPU only).
2 Entry	Lo0 Low-order portion of the TLB entry for even-numbered virtual pages (microAptiv MPU only).
3 Entry	Lo1 Low-order portion of the TLB entry for odd-numbered virtual pages (microAptiv MPU only).
4	C o n UserLocal	Pointer to the page table entry in memory (microAptiv MPU only).User information that can be written by privileged software and read via the RDHWR instruction.
5 Page	Mask/ PageGrain	PageMask controls the variable page sizes in TLB entries. PageGrain enables support of 1 KB pages in the TLB (microAptiv MPU only).
6 Wired	Controls the number of fixed (i.e., wired) TLB entries (microAptiv MPU only).
7	HWREna	Enables access via the RDHWR instruction to selected hardware registers in Non-privileged mode.
8 Bad	VAddr Reports the address for the most recent address-related exception.
9 Count	Processor cycle count.
10 Entry	Hi High-order portion of the TLB entry (microAptiv MPU only).
11	Compare Core timer interrupt control.
12 Status	Processor status and control.
	IntCtl	Interrupt control of vector spacing.
	SRSCtl	Shadow register set control.
	SRSMap Shadow register mapping control.
	View_IPL	Allows the Priority Level to be read/written without extracting or inserting that bit from/to the Status register.
	SRSMAP2	Contains two 4-bit fields that provide the mapping from a vector number to the shadow set number to use when servicing such an interrupt.
13 Cause	Describes the cause of the last exception.
	NestedExc	Contains the error and exception level status bit values that existed prior to the current exception.
	View_RIPL	Enables read access to the RIPL bit that is available in the Cause register.
14	EPC	Program counter at last exception.
14	NestedEPC	Contains the exception program counter that existed prior to the current exception.
15	PRID	Processor identification and revision
	Ebase	Exception base address of exception vectors.
	CDMMBase	Common device memory map base.
16	Config	Configuration register.
	Config1	Configuration register 1.
	Config2	Configuration register 2.
	Config3	Configuration register 3.
	Config4	Configuration register 4.
	Config5	Configuration register 5.
	Config7	Configuration register 7.
17 LLa	Addr Load link address (microAptiv MPU only).
18 WatchLo	Low-order watchpoint address (microAptiv MPU only).
19 WatchHi	High-order watchpoint address (microAptiv MPU only).
20-22	Reserved	Reserved in the PIC32 core.
23	Debug EJTAG debug register.
	TraceControl EJTAG trace control.
	TraceControl2 EJTAG trace control 2.
	UserTraceData1 EJTAG user trace data 1 register.
	TraceBPC EJTAG trace breakpoint register.
	Debug2 Debug control/exception status 1.
24	DEPC Program counter at last debug exception.
24	UserTraceData2 EJTAG user trace data 2 register.
25	PerfCtl0 Performance counter 0 control.
	PerfCnt0	Performance counter 0.
	PerfCtl1	Performance counter 1 control.
	PerfCnt1	Performance counter 1.
26	ErrCtl	Software test enable of way-select and data RAM arrays for I-Cache and D-Cache (microAptiv MPU only).
27	Reserved	Reserved in the PIC32 core.
28	TagLo/DataLo	Low-order portion of cache tag interface (microAptiv MPU only).
29	Reserved	Reserved in the PIC32 core.
30	ErrorEPC	Program counter at last error exception.
31	DeSave Debug exception save.

3.3 Power Management

The processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during Idle periods.

3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT

The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 33.0 "Power-Saving Features".

The majority of the power consumed by the processor core is in the clock tree and clocking registers. The PIC32MZ family makes extensive use of local gated-clocks to reduce this dynamic power consumption.

3.4 L1 Instruction and Data Caches

3.4.1 INSTRUCTION CACHE (I-CACHE)

The I-Cache is an on-core memory block of 16 Kbytes. Because the I-Cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access rather than having to wait for the physical address translation. The tag holds 22 bits of physical address, a valid bit, and a lock bit. The LRU replacement bits are stored in a separate array.

The I-Cache block also contains and manages the instruction line fill buffer. Besides accumulating data to be written to the cache, instruction fetches that reference data in the line fill buffer are serviced either by a bypass of that data, or data coming from the external interface. The I-Cache control logic controls the bypass function.

The processor core supports I-Cache locking. Cache locking allows critical code or data segments to be locked into the cache on a per-line basis, enabling the system programmer to maximize the efficiency of the system cache.

The cache locking function is always available on all I-Cache entries. Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction.

3.4.2 DATA CACHE (D-CACHE)

The D-Cache is an on-core memory block of 4 Kbytes. This virtually indexed, physically tagged cache is protected. Because the D-Cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access. The tag holds 22 bits of physical address, a valid bit, and a lock bit. There is an additional array holding dirty bits and LRU replacement algorithm bits for each set of the cache.

In addition to I-Cache locking, the processor core also supports a D-Cache locking mechanism identical to the I-Cache. Critical data segments are locked into the cache on a per-line basis. The locked contents can be updated on a store hit, but cannot be selected for replacement on a cache miss.

The D-Cache locking function is always available on all D-Cache entries. Entries can then be marked as locked or unlocked on a per-entry basis using the CACHE instruction.

3.4.3 ATTRIBUTES

The processor core I-Cache and D-Cache attributes are listed in the Configuration registers (see Register 3-1 through Register 3-4).

3.5 EJTAG Debug Support

The processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine.

The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification specify which registers are selected and how they are used.

3.6 MIPS DSP ASE Extension

The MIPS DSP Application-Specific Extension Revision 2 is an extension to the MIPS32 architecture. This extension comprises new integer instructions and states that include new HI/LO accumulator register pairs and a DSP control register. This extension is crucial in a wide range of DSP, multimedia, and DSP-like algorithms covering Audio and Video processing applications. The extension supports native fractional format data type operations, register Single Instruction Multiple Data (SIMD) operations, such as add, subtract, multiply, and shift. In addition, the extension includes the following features that are essential in making DSP algorithms computationally efficient:

• Support for multiplication of complex operands
- Variable bit insertion and extraction
- Implementation and use of virtual circular buffers
- Arithmetic saturation and overflow handling support
- Zero cycle overhead saturation and rounding operations

3.7 microAptiv™ Core Configuration

Register 3-1 through Register 3-4 show the default configuration of the microAptiv core, which is included on PIC32MZ EC family devices.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	r-1 U-0 U-0	U-0 U-0 U-0 U-0	R-0
31:24	—	—	—	—	—	—	—	ISP
23:16	R-0	R-0 R-1 R-0	U-0 R-1 R-0	R-0
23:16	DSP	UDI	SB	MDU	—	MM<1:0>		BM
15:8	R-0	R-0 R-0 R-0	R-0 R-1	R-0	R-0
15:8	BE	AT<1:0>		AR<2:0>			MT<2:1>
7:0	R-1	U-0	U-0	U-0	U-0	R/W-0	R/W-1	R/W-0
7:0	MT<0>	—	—	—	—	K0<2:0>

Legend:	r = Reserved bit
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 Reserved: This bit is hardwired to '1' to indicate the presence of the Config1 register.

bit 30-25 Unimplemented: Read as '0'

bit 24 ISP: Instruction Scratch Pad RAM bit 0 = Instruction Scratch Pad RAM is not implemented

bit 23 DSP: Data Scratch Pad RAM bit 0 = Data Scratch Pad RAM is not implemented

bit 22 UDI: User-defined bit 0 = CorExtend User-Defined Instructions are not implemented

bit 21 SB: SimpleBE bit 1 = Only Simple Byte Enables are allowed on the internal bus interface

bit 20 MDU: Multiply/Divide Unit bit 0 = Fast, high-performance MDU

bit 19 Unimplemented: Read as '0'

bit 18-17 MM<1:0>: Merge Mode bits 10 = Merging is allowed

bit 16 BM: Burst Mode bit 0 = Burst order is sequential

bit 15 BE: Endian Mode bit 0 = Little-endian

bit 14-13 AT<1:0>: Architecture Type bits 00 = MIPS32

bit 12-10 AR<2:0>: Architecture Revision Level bits 001 = MIPS32 Release 2

bit 9-7 MT<2:0>: MMU Type bits 001 = microAptiv MPU Microprocessor core uses a TLB-based MMU

bit 6-3 Unimplemented: Read as '0'

bit 2-0 K0<2:0>: Kseg0 Coherency Algorithm bits 011 = Cacheable, non-coherent, write-back, write allocate 010 = Uncached 001 = Cacheable, non-coherent, write-through, write allocate 000 = Cacheable, non-coherent, write-through, no write allocate All other values are not used and are mapped to other values. Values 100, 101, and 110 are mapped to 010. Value 111 is mapped to 010.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	r-1 R-0 R-0	R-1 R-1 R-1 R-1	R-0
31:24	— MMU	Size<5:0> IS<2>
23:16	R-1 R-0 R-0	R-1 R-1 R-0 R-1	R-1
23:16	IS<1:0> IL<2:0> IA<2:0>
15:8	R-0 R-0 R-0	R-0 R-1 R-1 R-0	R-1
15:8	DS<2:0> DL<2:0> DA<2:1>
7:0	R-1 U-0 U-0	R-1 R-1 R-0 R-1	R-0
7:0	DA<0>	—	—	PC	WR	CA	EP	FP

Legend:	r = Reserved bit
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 Reserved: This bit is hardwired to a '1' to indicate the presence of the Config2 register.

bit 30-25 MMU Size<5:0>: Contains the number of TLB entries minus 1

001111 = 16 TLB entries

bit 24-22 IS<2:0>: Instruction Cache Sets bits

010 = Contains 256 instruction cache sets per way

bit 21-19 IL<2:0>: Instruction-Cache Line bits

011 = Contains instruction cache line size of 16 bytes

bit 18-16 IA<2:0: Instruction-Cache Associativity bits

011 = Contains 4-way instruction cache associativity

bit 15-13 DS<2:0>: Data-Cache Sets bits

000 = Contains 64 data cache sets per way

bit 12-10 DL<2:0>: Data-Cache Line bits

011 = Contains data cache line size of 16 bytes

bit 9-7 DA<2:0>: Data-Cache Associativity bits

011 = Contains the 4-way set associativity for the data cache

bit 6-5 Unimplemented: Read as '0'

bit 4 PC: Performance Counter bit

1 = The processor core contains Performance Counters

bit 3 WR: Watch Register Presence bit

1 = No Watch registers are present

bit 2 CA: Code Compression Implemented bit

0 = No MIPS16e® present

bit 1 EP: EJTAG Present bit

1 = Core implements EJTAG

bit 0 FP: Floating Point Unit bit

0 = Floating Point Unit is not implemented

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	r-1 U-0 U-0	U-0 U-0	U-0 U-0	U-0
31:24	— — —	— — — —	— — — —	—
23:16	U-0 R-0 R-1	R-0 R-0	R-0 R-1	R/W-y
23:16	—	IPLW<1:0>		MMAR<2:0>			MCU	ISAONEXC^(1)
15:8	R-y	R-y R-1	R-1 R-1	R-1 U-0 R-1
15:8	ISA<1:0>(^1)		ULRI	RXI	DSP2P	DSPP	—	ITL
7:0	U-0 R-1 R-1	R-0 R-1	U-0 U-0	R-0
7:0	—	VEIC	VINT	SP	CDMM	—	—	TL

Legend:	r = Reserved bit	y = Value set from Configuration bits on POR
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: This bit is hardwired as '1' to indicate the presence of the Config4 register

bit 30-23 Unimplemented: Read as '0'

bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits 01 = IPL and RIPL bits are 8-bits in width

bit 20-18 MMAR<2:0>: microMIPS Architecture Revision Level bits 000 = Release 1

bit 17 MCU: MIPS MCU ASE Implemented bit 1 = MCU ASE is implemented

bit 16 ISAONEXC: ISA on Exception bit ^(1) 1 = microMIPS is used on entrance to an exception vector 0 = MIPS32 ISA is used on entrance to an exception vector

bit 15-14 ISA<1:0>: Instruction Set Availability bits ^(1) 11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of reset

10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of reset

bit 13 ULRI: UserLocal Register Implemented bit 1 = UserLocal Coprocessor 0 register is implemented

bit 12 RXI: RIE and XIE Implemented in PageGrain bit 1 = RIE and XIE bits are implemented

bit 11 DSP2P: MIPS DSP ASE Revision 2 Presence bit 1 = DSP Revision 2 is present

bit 10 DSPP: MIPS DSP ASE Presence bit 1 = DSP is present

bit 9 Unimplemented: Read as '0'

bit 8 ITL: Indicates that iFlowtrace hardware is present 1 = The iFlowtrace is implemented in the core

bit 7 Unimplemented: Read as '0'

bit 6 VEIC: External Vector Interrupt Controller bit 1 = Support for an external interrupt controller is implemented.

bit 5 VINT: Vector Interrupt bit 1 = Vector interrupts are implemented

bit 4 SP: Small Page bit 0 = 4 KB page size

bit 3 CDMM: Common Device Memory Map bit 1 = CDMM is implemented

bit 2-1 Unimplemented: Read as '0'

bit 0 TL: Trace Logic bit 0 = Trace logic is not implemented

Note 1: These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0<6>).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — — — —
7:0	U-0 U-0 U-0	U-0 U-0 U-0 U-0	R-1
7:0	— — —	— — — —	N	F

Legend:	r = Reserved
R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-1 Unimplemented: Read as '0'

bit 0 NF: Nested Fault bit

1 = Nested Fault feature is implemented

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-1	U-0	U-0	U-0	U-0	U-0	U-0	U-0
31:24	WII — —	— — — — —
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
23:16	— — —	— — — — —
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	— — —	— — — — —
7:0	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
7:0	— — —	— — — — —

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31 WII: Wait IE Ignore bit

1 = Indicates that this processor will allow an interrupt to unblock a WAIT instruction

bit 30-0 Unimplemented: Read as '0'

NOTES:

4.0 MEMORY ORGANIZATION

Note:

This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. This document is not intended to be a comprehensive reference source. For detailed information, refer to Section 48. "Memory Organization and Permissions" (DS60001214), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

PIC32MZ EC microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, Special Function Registers (SFRs) and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, PIC32MZ EC devices allow execution from data memory.

Key features include:

• 32-bit native data width
- Separate User (KUSEG) and Kernel (KSEG0/KSEG1/KSEG2/KSEG3) mode address space
- Separate boot Flash memory for protected code
- Robust bus exception handling to intercept runaway code
- Cacheable (KSEG0/KSEG2) and non-cacheable (KSEG1/KSEG3) address regions
- Read-Write permission access to predefined memory regions

4.1 Memory Layout

PIC32MZ EC microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU.

The main memory maps for the PIC32MZ EC devices are illustrated in Figure 4-1 through Figure 4-4. Figure 4-5 provides memory map information for boot Flash and boot alias. Table 4-1 provides memory map information for SFRs.

FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY (1,2)
Microchip PIC32MZ1024ECM124 - Memory Layout - 1

bar_stacked

| Virtual Memory Map | KSEG1KSEG0 | Physical Memory Map | | ------------------- | ---------- | ------------------- | | 0xFFFFFFF | Reserved | 0xFFFFFFF | | 0xF4000000 | Reserved | 0x3FFFFFFF | | 0xF3FFFFFF | External Memory via SQI | 0x33FFFFFFF | | 0xF0000000 | Reserved | External Memory via SQI | | 0xE4000000 | Reserved | 0x30000000 | | 0xE3FFFFFF | External Memory via EBI | Reserved | | 0xE0000000 | Reserved | 0x24000000 | | 0xD4000000 | Reserved | 0x23FFFFFFF | | 0xD3FFFFFF | External Memory via SQI | Reserved | | 0xD0000000 | Reserved | External Memory via EBI | | 0xC4000000 | Reserved Reserve | Boot Flash (see Figure 4-5) | | 0xC3FFFFFF | External Memory via EBI | Reserved | | 0xC0000000 | Reserved | SFRs (see Table 4-1) | | 0xBFFFFFF | Reserved | Reserved0xBF8FFFFF | | 0xBFC74000 | Reserved | Program Flash | | 0xBFC73FFF | Boot Flash (see Figure 4-5) | Reserved | | 0xBFC00000 | Reserved | Reserved | | 0xBF900000 | SFRs (see Table 4-1) | Reserved | | 0xBF800000 | Reserved | RAM(3) | | 0xBD808000 | Reserved | Reserved | | 0xBD7FFFF | Program Flash | Reserved | | 0xBD000000 | Reserved | Reserved | | 0xA0221111 | Reserved | Reserved | | 0xA1111111 | RAM(3) | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA1111111 | Reserved | Reserved | | 0xA9FC742222 | Reserved | Reserved | | 0x9FC732222 | Boot Flash (see Figure 4-5) | Reserved | | 0x9FC732222 | Reserved | Reserved | | 0x9FC732222 | Program Flash | Reserved | | 0x9D882222 | Reserved | Reserved | | 0x9D882222 | Program Flash | Reserved | | 0x9D882222 | Reserved | Reserved | | 0x9D772222 | Reserved | Reserved | | 0x9D772222 | Program Flash | Reserved | | 0x9D772222 | Reserved | Reserved | | 0x9D762222 | Reserved | Reserved | | 0x9D762222 | Program Flash | Reserved | | 0x9D762222 | Reserved | Reserved | | 0x9D752222 | Reserved | Reserved | | 0x9D752222 | Program Flash | Reserved | | 0x9D752222 | Reserved | Reserved | | 0x9D742222 | Reserved | Reserved | | 0x9D742222 | Program Flash | Reserved | | 0x9D742222 | Reserved | Reserved | | 0x9D732222 | Reserved | Reserved | | 0x9D732222 | Program Flash | Reserved | | 0x9D732222 | Reserved | Reserved | | 0x9D722222 | Program Flash | Reserved | | 0x9D722222 | Reserved | Reserved | | 0x9D712222 | Reserved | Reserved | | 0x9D712222 | Program Flash | Reserved | | 0x9D712222 | Reserved | Reserved | | 0x9D7633333 | Reserved | Reserved | | 0x9D7633333 | Program Flash | Reserved | | 0x9D7633333 | Reserved | Reserved | | 0x9D7533333 | Reserved | Reserved | | 0x9D7533333 | Program Flash | Reserved | | 0x9D7533333 | Reserved | Reserved | | 0x9D7434444 | Reserved | Reserved | | 0x9D7434444 | Program Flash | Reserved | | 0x9D7434444 | Reserved | Reserved | | 0x9D7344444 | Program Flash | Reserved | | 0x9D7344444 | Reserved | Reserved | | 0x9D7344444 | Program Flash (see Figure 4-5) - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4 - Modified) - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 4-5) - Reserved - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) - Program Flash (see Table 5 - Modified) = SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF, SRDF6FF Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve Reserved Reserve

Note 1: Memory areas are not shown to scale.
2: The Cache, MMU, and TLB are initialized by compiler start-up code.
3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
4: The MMU must be enabled and the TLB must be set up to access this segment.

FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND 256 KB OF RAM ^(1,2)
Microchip PIC32MZ1024ECM124 - Memory Layout - 2
Note 1: Memory areas are not shown to scale.
2: The Cache, MMU, and TLB are initialized by compiler start-up code.
3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
4: The MMU must be enabled and the TLB must be set up to access this segment.

FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND 512 KB OF RAM ^(1,2)
Microchip PIC32MZ1024ECM124 - Memory Layout - 3

bar_stacked

| Virtual Memory Map | KSEG1KSEG0 | Physical Memory Map | | ------------------ | ---------- | ------------------- | | 0xFFFFFFF | Reserved | 0xFFFFFFF | | 0xF4000000 | Reserved | 0x33FFFFFF | | 0xF3FFFFFF | External Memory via SQI | 0x33FFFFFF | | 0xF0000000 0x34000000 | Reserved | External Memory via SQI | | 0xE4000000 | Reserved | 0x30000000 | | 0xE3FFFFFF | External Memory via EBI | Reserved | | 0xE0000000 | Reserved | 0x24000000 | | 0xD4000000 | Reserved | 0x23FFFFFF | | 0xD3FFFFFF | External Memory via SQI | Reserved | | 0xD0000000 0x20000006 | Reserved | External Memory via EBI | | 0xC4000000 0x1FC74000 | Reserved | Boot Flash (see Figure 4-5) | | 0xC3FFFFFF | Reserved | 0x1FC73FFF | | 0xC0000000 | Reserved | 0x1FC00000 | | 0xBFFFFFF | Reserved | Reserved | | 0xBFC74000 | Reserved | SFRs (see Table 4-1) | | 0xBFC73FFF | Boot Flash (see Figure 4-5) | Reserved | | 0xBFC00000 | Reserved | Reserved(See Table 4-1) | | 0xBF900000 | Reserved | Reserved(See Table 4-1) | | 0xBF800000 | SFRs (see Table 4-1) | Program Flash | | 0xBD1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1 D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1D1CFF | | 0xBDF8888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888888B | 2xBD74747777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777777| | 2x9FC6666666666666666666666666666666666666666666666666666666666666666666666666666666666666666666666666666 | | 2x9FC333333333333333333333333333333333333333333333333333333333333333333333333333333333333Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Restricted Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash: Program Flash:

FIGURE 4-4: MEMORY MAP FOR DEVICES WITH 2048 KB OF PROGRAM MEMORY (1,2)
Microchip PIC32MZ1024ECM124 - Memory Layout - 4
Note 1: Memory areas are not shown to scale.
2: The Cache, MMU, and TLB are initialized by compiler start-up code.
3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
4: The MMU must be enabled and the TLB must be set up to access this segment.

FIGURE 4-5: BOOT AND ALIAS MEMORY MAP

Physical Memory Map(1)	0x1FC74000
Sequence/Configuration Space(3)	0x1FC700000x1FC6FF00
Boot Flash 2	0x1FC60000
Reserved 0x1FC54028
Serial Number(5)	0x1FC54020
ADC Calibration Space (3)	0x1FC54000
Sequence/Configuration Space(4)	0x1FC500000x1FC4FF00
Boot Flash 1	0x1FC40000
Reserved	0x1FC34000
Unused Configuration Space(6)	0x1FC300000x1FC2FF00
Upper Boot Alias	0x1FC20000
Reserved	0x1FC14000
Configuration Space(2,3)	0x1FC100000x1FC0FF00
Lower Boot Alias	0x1FC00000

Note 1: Memory areas are not shown to scale.
2: Memory locations 0x1FC0FF40 through 0x1FC0FFFC are used to initialize Configuration registers (see Section 34.0 "Special Features").
3: Memory locations 0x1FC54000 through 0x1FC54010 are used to initialize the ADC Calibration registers (see Section 34.0 "Special Features").
4: Refer to Section 4.1.1 "Boot Flash Sequence and Configuration Spaces" for more information.
5: Memory locations 0x1FC54020 and 0x1FC54024 contain a unique device serial number (see Section 34.0 "Special Features").
6: This configuration space cannot be used for executing code in the upper boot alias.

TABLE 4-1: SFR MEMORY MAP

Peripheral	Virtual Address
Peripheral	Base	Offset Start
System Bus(1)	0xBF8F0000	0x0000
RNG	0xBF8E0000	0x6000
Crypto 0x5000
USB 0x3000
SQI1 0x2000
EBI 0x1000
Prefetch 0x0000
Ethernet	0xBF880000	0x2000
CAN1 and CAN2 0x0000	0xBF880000
PORTA-PORTK	0xBF860000	0x0000
Comparator 1, 2	0xBF840000	0xC000
ADC1		0xB000
OC1-OC9		0x4000
IC1-IC9		0x2000
Timer1-Timer9		0x0000
PMP	0xBF820000	0xE000
UART1-UART6		0x2000
SPI1-SPI6		0x1000
I2C1-I2C5		0x0000
DMA	0xBF810000	0x1000
Interrupt Controller	0xBF810000	0x0000
PPS	0xBF800000	0x1400
Oscillator		0x1200
CVREF		0x0E00
RTCC		0x0C00
Deadman Timer		0x0A00
Watchdog Timer		0x0800
Flash Controller		0x0600
Configuration		0x0000

Note 1: Refer to 4.2 "System Bus Arbitration" for important legal information.

4.1.1 BOOT FLASH SEQUENCE AND CONFIGURATION SPACES

Sequence space is used to identify which boot Flash is aliased by aliased regions. If the value programmed into the TSEQ<15:0> bits of the BF1SEQ0 word is equal to or greater than the value programmed into the TSEQ<15:0> bits of the BF2SEQ0 word, Boot Flash 1 is aliased by the lower boot alias region, and Boot Flash 2 is aliased by the upper boot alias region. If TSEQ<15:0> bits of BF2SEQ0 is greater than TSEQ<15:0> bits of BF1SEQ0, the opposite is true (see Table 4-2 and Table 4-3 for BFxSEQ0 word memory locations).

The CSEQ<15:0> bits must contain the complement value of the TSEQ<15:0> bits; otherwise, the value of TSEQ<15:0> is considered invalid, and an alternate sequence is used. See Section 4.1.2 "Alternate Sequence and Configuration Words" for more information.

Once boot Flash memories are aliased, configuration space located in the lower boot alias region is used as the basis for the Configuration words, DEVSIGN0, DEVCP0, and DEVCFGx (and the associated alternate configuration registers). This means that the boot Flash region to be aliased by lower boot alias region memory must contain configuration values in the appropriate memory locations.

Note: Do not use word program operation (NVMOP<3:0>=0001) when programming data into the sequence and configuration spaces.

4.1.2 ALTERNATE SEQUENCE AND CONFIGURATION WORDS

Every word in the configuration space and sequence space has an associated alternate word (designated by the letter A as the first letter in the name of the word). During device start-up, primary words are read and if uncorrectable ECC errors are found, the BCFGERR (RCON<27>) flag is set and alternate words are used. If uncorrectable ECC errors are found in primary and alternate words, the BCFGFAIL (RCON<26>) flag is set and the default configuration is used.

TABLE 4-2: BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY

Legend: x = unknown value on Reset; — = Reserved, read as '1'. Reset values are shown in hexadecimal.

TABLE 4-3: BOOT FLASH 2 SEQUENCE AND CONFIGURATION WORDS SUMMARY

Virtual Address(BFC6,#)

Bit Range

Bits

All Resets

31/15 30

14 29/13

28/12 27/11

26/10 25/9

24/8 23/7

22/6 21/5

20/4 19/3

18/2 17/1

16/0

FF40

ABF2DEVCFG3 31:0

Note: See Table 34-2 for the bit descriptions.

xxxxx

FF44

ABF2DEVCFG2 31:0 xxxx

FF48

ABF2DEVCFG1 31:0 xxxx

FF4C

ABF2DEVCFG0 31:0 xxxx

FF50

ABF2DEVCP3 31:0 xxxx

FF54

ABF2DEVCP2 31:0 xxxx

FF58

ABF2DEVCP1 31:0 xxxx

FF5C

ABF2DEVCP0 31:0 xxxx

FF60

ABF2DEVSIGN3 31:0 xxxx

FF64

ABF2DEVSIGN2 31:0 xxxx

FF68

ABF2DEVSIGN1 31:0 xxxx

FF6C

ABF2DEVSIGN0 31:0 xxxx

FF70

ABF2SEQ3

31:16

——

xxxxx

15:0

——

xxxxx

FF74

ABF2SEQ2

31:16

——

xxxxx

15:0

——

xxxxx

FF78

ABF2SEQ1

31:16

——

xxxxx

15:0

——

xxxxx

FF7C

ABF2SEQ0

31:16

CSEQ<15:0>

xxxxx

15:0

TSEQ<15:0>

xxxxx

FFC0

BF2DEVCFG3

31:0

Note: See Table 34-1 for the bit descriptions.

xxxxx

FFC4

BF2DEVCFG2

31:0 xxxx

FFC8

BF2DEVCFG1

31:0 xxxx

FFCC

BF2DEVCFG0

31:0 xxxx

FFD0

BF2DEVCP3 31:0 xxxx

FFD4

BF2DEVCP2 31:0 xxxx

FFD8

BF2DEVCP1 31:0 xxxx

FFDC

BF2DEVCP0 31:0 xxxx

FFE0

BF2DEVSIGN3

31:0 xxxx

FFE4

BF2DEVSIGN2

31:0 xxxx

FFE8

BF2DEVSIGN1

31:0 xxxx

FFEC

BF2DEVSIGN0

31:0 xxxx

FFF0

BF2SEQ3

31:16

——

xxxxx

15:0

——

xxxxx

FFF4

BF2SEQ2

31:16

——

xxxxx

15:0

——

xxxxx

FFF8

BF2SEQ1

31:16

——

xxxxx

15:0

——

xxxxx

FFFC

BF2SEQ0

31:16

CSEQ<15:0>

xxxxx

15:0

TSEQ<15:0>

xxxxx

Legend: x = unknown value on Reset; — = Reserved, read as '1'. Reset values are shown in hexadecimal.

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 CSEQ<15:0>: Boot Flash Complement Sequence Number bits

bit 15-0 TSEQ<15:0>: Boot Flash True Sequence Number bits

Note: The BFxSEQ1 through BFxSEQ3 and ABFxSEQ1 through ABFxSEQ3 registers are used for Quad Word programming operation when programming the BFxSEQ0/ABFxSEQ0 registers, and do not contain any valid information.

4.2 System Bus Arbitration

Note: The System Bus interconnect implements one or more instantiations of the SonicsSX® interconnect from Sonics, Inc. This document contains materials that are (c) 2003-2015 Sonics, Inc., and that constitute proprietary information of Sonics, Inc. SonicsSX is a registered trademark of Sonics, Inc. All such materials and trademarks are used under license from Sonics, Inc.

As shown in the PIC32MZ EC Family Block Diagram (see Figure 1-1), there are multiple initiator modules (I1 through I14) in the system that can access various target modules (T1 through T13). Table 4-4 illustrates which initiator can access which target. The System Bus supports simultaneous access to targets by initiators, so long as the initiators are accessing different targets. The System Bus will perform arbitration, if multiple initiators attempt to access the same target.

TABLE 4-4: INITIATORS TO TARGETS ACCESS ASSOCIATION

Target #

I n i

Name CPU DMA Read DMA Write USB

Ethernet Read

Ethernet Write

CAN1

CAN2

SQI1

Flash Controller

Crypto

Flash Memory:Program FlashBoot FlashPrefetch Module

RAM Bank 1 Memory

RAM Bank 2 Memory

External Memory via EBI and EBI Module

Peripheral Set 1:System Control, Flash Control, DMT, RTCC, CVR, PPS Input, PPS Output, Interrupts, DMA, WDT

Peripheral Set 2:SPI1-SPI6I2C1-I2C5UART1-UART6PMP

Peripheral Set 3:Timer1-Timer9IC1-IC9OC1-OC9ADC1Comparator 1Comparator 2

Peripheral Set 4:PORTA-PORTK

Peripheral Set 5:CAN1CAN2Ethernet Controller

Peripheral Set 6:USB

External Memory via SQI1 and SQI1 Module

Peripheral Set 7:Crypto Engine

Peripheral Set 8:RNG Module

The System Bus arbitration scheme implements a non-programmable, Least Recently Serviced (LRS) priority, which provides Quality Of Service (QOS) for most initiators. However, some initiators can use Fixed High Priority (HIGH) arbitration to guarantee their access to data.

The arbitration scheme for the available initiators is shown in Table 4-5.

TABLE 4-5: INITIATOR ID AND QOS

Name	ID	QOS
CPU	1	LRS^(1)
CPU	2	HIGH^(1,2)
DMA Read	3	LRS^(1)
DMA Read	4	HIGH^(1,2)
DMA Write	5	LRS^(1)
DMA Write	6	HIGH^(1,2)
USB	7	LRS
Ethernet Read	8	LRS
Ethernet Write	9	LRS
CAN1	10	LRS
CAN2	11	LRS
SQI1	12	LRS
Flash Controller	13	HIGH^(2)
Crypto	14	LRS

Note 1: When accessing SRAM, the DMAPRI bit (CFGCON<25>) and the CPUPRI bit (CFGCON<24>) provide arbitration control for the DMA and CPU (when servicing an interrupt (i.e., EXL = 1)), respectively, by selecting the use of LRS or HIGH When using HIGH, the DMA and CPU get arbitration preference over all initiators using LRS.

2: Using HIGH arbitration can have serious negative effects on other initiators. Therefore, it is recommended to not enable this type of arbitration for an initiator that uses significant system bandwidth. HIGH arbitration is intended to be used for low bandwidth applications that require low latency, such as LCC graphics applications.

4.3 Permission Access and System Bus Registers

The System Bus on PIC32MZ EC family of microcontrollers provides access control capabilities for the transaction initiators on the System Bus.

The System Bus divides the entire memory space into fourteen target regions and permits access to each target by initiators via permission groups. Four Permission Groups (0 through 3) can be assigned to each initiator. Each permission group is independent of the others and can have exclusive or shared access to a region.

Using the CFGPG register (see Register 34-10 in Section 34.0 "Special Features"), Boot firmware can assign a permission group to each initiator, which can make requests on the System Bus.

The available targets and their regions, as well as the associated control registers to assign protection, are described and listed in Table 4-6.

To change these registers, they must be unlocked in hardware. The register lock is controlled by the PGLOCK Configuration bit (CFGCON<11>). Setting PGLOCK prevents writes to the control registers; clearing PGLOCK allows writes.

To set or clear the PGLOCK bit, an unlock sequence must be executed. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

TABLE 4-6: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS

Target Number

Target Description^(5)

SBTxREGy Register SBTxRDy Register SBTxWRy Register

Name

Region Base (BASE<21:0>) (see Note 2)

Physical Start Address

Region Size (SIZE<4:0>) (see Note 3)

Region Size

Priority (PRI)

Priority Level

Name

Read Permission (GROUP3, GROUP2, GROUP1, GROUP0)

Name

Write Permission (GROUP3, GROUP2, GROUP1, GROUP0)

System Bus

SBT0REG0 R

0x1F8F0000 R 64 KB

— 0

SBT0RD0 R/W

(1)

SBT0WR0

R/W(1)

SBT0REG1 R

0x1F8F8000 R 32 KB

— 3

SBT0RD1 R/W

(1)

SBT0WR1

R/W(1)

Flash Memory(6):Program FlashBoot FlashPrefetch Module

SBT1REG0 R

0x1D000000

(4)

R(4)

— 0

SBT1RD0 R/W

(1)

SBT1WR0

0, 0, 0, 0

SBT1REG2

0x1F8E0000

4 KB

SBT1RD2

R/W(1)

SBT1WR2

R/W(1)

SBT1REG3

R/W

SBT1RD3

R/W(1)

SBT1WR3

0, 0, 0, 0

SBT1REG4

R/W

SBT1RD4

R/W(1)

SBT1WR4

0, 0, 0, 0

SBT1REG5

R/W

SBT1RD5

R/W(1)

SBT1WR5

0, 0, 0, 0

SBT1REG6

R/W

SBT1RD6

R/W(1)

SBT1WR6

0, 0, 0, 0

SBT1REG7

R/W

SBT1RD7

R/W(1)

SBT1WR7

0, 0, 0, 0

SBT1REG8

R/W

SBT1RD8

R/W(1)

SBT1WR8

0, 0, 0, 0

RAM Bank 1 Memory

SBT2REG0 R

0x00000000

(4)

R(4)

— 0

SBT2RD0 R/W

(1)

SBT2WR0

R/W(1)

SBT2REG1

R/W

—

SBT2RD1

R/W(1)

SBT2WR1

R/W(1)

SBT2REG2

R/W

SBT2RD2

R/W(1)

SBT2WR2

R/W(1)

RAM Bank 2 Memory

SBT3REG0

R(4)

— 0

SBT3RD0 R/W

(1)

SBT3WR0

R/W(1)

SBT3REG1

R/W

—

SBT3RD1

R/W(1)

SBT3WR1

R/W(1)

SBT3REG2

R/W

SBT3RD2

R/W(1)

SBT3WR2

R/W(1)

External Memory via EBI and EBI Module^(6)

SBT4REG0

0x20000000

64 MB

—

SBT4RD0

R/W(1)

SBT4WR0

R/W(1)

SBT4REG2

0x1F8E1000

4 KB

SBT4RD2

R/W(1)

SBT4WR2

R/W(1)

Peripheral Set 1:System ControlFlash ControlDMT/WDTRTCCCVRPPS InputPPS OutputInterruptsDMA

SBT5REG0

R 0x1F800000 R 128 KB

— 0

SBT5RD0 R/W

(1)

SBT5WR0

R/W(1)

SBT5REG1

R/W

—

SBT5RD1

R/W(1)

SBT5WR1

R/W(1)

SBT5REG2

R/W

SBT5RD2

R/W(1)

SBT5WR2

R/W(1)

Legend: R = Read; R/W = Read/Write; 'x' in a register name = 0-13; 'y' in a register name = 0-8.
Note 1: Reset values for these bits are '0', '1', '1', '1', respectively.
2: The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
3: The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2 ^(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
4: Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
5: See Table 4-1 for information on specific target memory size and start addresses.
6: The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.

TABLE 4-6: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)

Target Number

Target Description^(5)

SBTxREGy Register

SBTxRDy Register

SBTxWRy Register

Name

Region Base (BASE<21:0>) (see Note 2)

Physical Start Address

Region Size (SIZE<4:0>) (see Note 3)

Region Size

Priority (PRI)

Priority Level

Name

Read Permission (GROUP3, GROUP2, GROUP1, GROUP0)

Name

Write Permission (GROUP3, GROUP2, GROUP1, GROUP0)

Peripheral Set 2:SP11-SPI6I2C1-I2C5UART1-UART6PMP

SBT6REG0 R

0x1F820000 R 64 KB

— 0 SBT6RD0 R/W

(1)

SBT6WR0 R/W

(1)

SBT6REG1 R/W

R/W R/W R/W — 3 SBT6RD1 R/W

(1)

SBT6WR1 R/W

(1)

Peripheral Set 3:Timer1-Timer9IC1-IC9OC1-OC9ADC1Comparator 1Comparator 2

SBT7REG0 R

0x1F840000 R 64 KB

— 0 SBT7RD0 R/W

(1)

SBT7WR0 R/W

(1)

SBT7REG1 R/W

R/W R/W R/W — 3 SBT7RD1 R/W

(1)

SBT7WR1 R/W

(1)

Peripheral Set 4:PORTA-PORTK

SBT8REG0 R

0x1F860000 R 64 KB

— 0 SBT8RD0 R/W

(1)

SBT8WR0 R/W

(1)

SBT8REG1 R/W

R/W R/W R/W — 3 SBT8RD1 R/W

(1)

SBT8WR1 R/W

(1)

Peripheral Set 5:CAN1CAN2Ethernet Controller

SBT9REG0 R

0x1F880000 R 64 KB

— 0 SBT9RD0 R/W

(1)

SBT9WR0 R/W

(1)

SBT9REG1 R/W

R/W R/W R/W — 3 SBT9RD1 R/W

(1)

SBT9WR1 R/W

(1)

Peripheral Set 6:USB

SBT10REG0

R 0x1F8E 3000 R

4 KB

— 0 SBT10RD0

R/W

(1)

SBT10WR0

R/W^(1)

External Memory via SQI1 and SQI1 Module

SBT11REG0

R 0x30000 0000 R

64 MB

— 0 SBT11RD0

R/W

(1)

SBT11WR0

R/W^(1)

SBT11REG1

0x1F8E2000

4 KB

—

SBT11RD1

R/W^(1)

SBT11WR1

R/W^(1)

Peripheral Set 7:Crypto Engine

SBT12REG0

R 0x1F8E 5000 R

4 KB

— 0 SBT12RD0

R/W

(1)

SBT12WR0

R/W^(1)

Peripheral Set 8:RNG Module

SBT13REG0

R 0x1F8E 6000 R

4 KB

— 0 SBT13RD0

R/W

(1)

SBT13WR0

R/W^(1)

Legend: R = Read; R/W = Read/Write; 'x' in a register name = 0-13; 'y' in a register name = 0-8.
Note 1: Reset values for these bits are '0', '1', '1', '2', respectively.
2: The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
3: The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
4: Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
5: See Table 4-1 for information on specific target memory size and start addresses.
6: The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.

TABLE 4-7: SYSTEM BUS REGISTER MAP

Virtual Address(BF8F_#)	Register Name	Bit Range	Bits																	All Resets
Virtual Address(BF8F_#)	Register Name	Bit Range	31/15	30/14 29	13 28/12 27	11 26/10 25	9 24/8 23	7 22/6 21/5	20/4 19/3	18/2 17/1 16	0									All Resets
0510	SBFLAG	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0510	SBFLAG	15:0	—	—	T13PGV	T12PGV	T11PGV	T10PGV	T9PGV	T8PGV	T7PGV	T6PGV	T5PGV	T4PGV	T3PGV	T2PGV	T1PGV	T0PGV	0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.

TABLE 4-8: SYSTEM BUS TARGET 0 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-9: SYSTEM BUS TARGET 1 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'c'. Reset values are shown in hexadecimal.
Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-9: SYSTEM BUS TARGET 1 REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-10: SYSTEM BUS TARGET 2 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-11: SYSTEM BUS TARGET 3 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'u'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-12: SYSTEM BUS TARGET 4 REGISTER MAP

TABLE 4-13: SYSTEM BUS TARGET 5 REGISTER MAP

TABLE 4-14: SYSTEM BUS TARGET 6 REGISTER MAP

TABLE 4-15: SYSTEM BUS TARGET 7 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-16: SYSTEM BUS TARGET 8 REGISTER MAP

TABLE 4-17: SYSTEM BUS TARGET 9 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-18: SYSTEM BUS TARGET 10 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'c'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-19: SYSTEM BUS TARGET 11 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-20: SYSTEM BUS TARGET 12 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-21: SYSTEM BUS TARGET 13 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — — —	—
15:8	U-0 U-0 R-0	R-0 R-0	R-0 R-0
15:8	—	—	T13PGV	T12PGV	T11PGV	T10PGV	T9PGV	T8PGV
7:0	R-0 R-0 R-0	R-0 R-0	R-0 R-0
7:0	T7PGV	T6PGV	T5PGV	T4PGV	T3PGV	T2PGV	T1PGV	T0PGV

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared

bit 31-14 Unimplemented: Read as '0'

bit 13-0 TxPGV: Target 'x' Permission Group Violation Status bits ('x' = 0-13)

Refer to Table 4-6 for the list of available targets and their descriptions.

1 = Target is reporting a Permission Group (PG) violation

0 = Target is not reporting a PG violation

Note: All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM registers).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0, C U-0	U-0 U-0 R/W-0, C	R/W-0, C R/W-0, C R/W-0, C
31:24	MULTI —	— —		C	O			D
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	—	— — —	—
15:8	R-0 R-0 R-0	R-0 R-0 R-0	R-0 R-0
15:8	INITID<7:0>
7:0	R-0 R-0 R-0	R-0 U-0 R-0 R-0	R-0
7:0	REGION<3:0>				—	CMD<2:0>

Legend:	C = Clearable bit
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared

bit 31 MULTI: Multiple Permission Violations Status bit

This bit is cleared by writing a '1'.

1 = Multiple errors have been detected

0 = No multiple errors have been detected

bit 30-28 Unimplemented: Read as '0'

bit 27-24 CODE<3:0>: Error Code bits

Indicates the type of error that was detected. These bits are cleared by writing a '1'.

1111 = Reserved

1101 = Reserved

•

0011 = Permission violation

0010 = Reserved

0001 = Reserved

0000 = No error

bit 23-16 Unimplemented: Read as '0'

bit 15-8 INITID<7:0>: Initiator ID of Requester bits

11111111 = Reserved

•

00001111 = Reserved

00001110 = Crypto Engine

00001101 = Flash Controller

00001100 = SQI1

00001011 = CAN2

00001010 = CAN1

00001001 = Ethernet Write

00001000 = Ethernet Read

00000111 = USB

00000110 = DMA Write (DMAPRI (CFGCON<25>) = 1)

00000101 = DMA Write (DMAPRI (CFGCON<25>) = 0)

00000100 = DMA Read (DMAPRI (CFGCON<25>) = 1)

00000011 = DMA Read (DMAPRI (CFGCON<25>) = 0)

00000010 = CPU (CPUPRI (CFGCON<24>) = 1)

00000001 = CPU (CPUPRI (CFGCON<25>) = 0)

00000000 = Reserved

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

REGISTER 4-3: SBTxELOG1: SYSTEM BUS TARGET 'x' ERROR LOG REGISTER 1
('x' = 0-13) (CONTINUED)
bit 7-4 REGION<3:0>: Requested Region Number bits 1111 - 0000 = Target's region that reported a permission group violation bit 3 Unimplemented: Read as '0' bit 2-0 CMD<2:0>: Transaction Command of the Requester bits 111 = Reserved 110 = Reserved 101 = Write (a non-posted write) 100 = Reserved 011 = Read (a locked read caused by a Read-Modify-Write transaction) 010 = Read 001 = Write 000 = Idle

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	———	——— —— ——
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0	U-0
23:16	———	——— —— ——
15:8	U-0 U-0 U-0	U-0 U-0	U-0 U-0	U-0
15:8	———	——— —— ——
7:0	U-0 U-0 U-0	U-0 U-0	U-0 R-0	R-0
7:0	———	——— —— GROUP<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared

bit 31-3 Unimplemented: Read as '0'

bit 1-0 GROUP<1:0>: Requested Permissions Group bits

11 = Group 3 10 = Group 2 01 = Group 1 00 = Group 0

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	R/W-0
31:24	— — —	— — — —	ERRP
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — — —
15:8	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
15:8	— — —	— — — —
7:0	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
7:0	— — —	— — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared

bit 31-25 Unimplemented: Read as '0'

bit 24 ERRP: Error Control bit

1 = Report protection group violation errors
0 = Do not report protection group violation errors

bit 23-0 Unimplemented: Read as '0'

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	—— —	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	—— —	—— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	—— —	—— — — — —
7:0	U-0 U-0 U-0	U-0 U-0 U-0	U-0 R-0
7:0	—— —	—— — — — —	CLEAR

Legend:

R = Readable bit W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared

bit 31-1 Unimplemented: Read as '0'

bit 0 CLEAR: Clear Single Error on Read bit

A single error as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	—— —	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
23:16	—— —	—— — — — —
15:8	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
15:8	—— —	—— — — — —
7:0	U-0 U-0 U-0	U-0 U-0	U-0 U-0 R-0
7:0	—— —	—— — — — — CLEAR

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared

bit 31-1 Unimplemented: Read as '0'

bit 0 CLEAR: Clear Multiple Errors on Read bit

Multiple errors as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

('x' = 0-13; 'y' = 0-8)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W0 R/W-0	R/W0 R/W-0 R/W0	R/W0 R/W-0 R/W0	R/W-0
31:24	BASE<21:14>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0
23:16	BASE<13:6>
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R-0	U-0
15:8	BASE<5:0>						PRI	—
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	U-0	U-0	U-0
7:0	SIZE<4:0>					—	—	—

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared

bit 31-10 BASE<21:0>: Region Base Address bits

bit 9 PRI: Region Priority Level bit

1 = Level 2

0 = Level 1

bit 8 Unimplemented: Read as '0'

bit 7-3 SIZE<4:0>: Region Size bits

Permissions for a region are only active is the SIZE is non-zero.

11111 = Region size = 2(SIZE - 1) x 1024 (bytes)

•

00001 = Region size = 2(SIZE - 1) x 1024 (bytes)

00000 = Region is not present

bit 2-0 Unimplemented: Read as '0'

Note 1: Refer to Table 4-6 for the list of available targets and their descriptions.

2: For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	———	——— —— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	———	——— —— ——
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	———	——— —— ——
7:0	U-0 U-0 U-0	U-0 R/W-0 R/W-1	R/W-1 R/W-1
7:0	—	—	—	—	GROUP3	GROUP2	GROUP1	GROUP0

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared

bit 31-4 Unimplemented: Read as '0'

bit 3 Group3: Group3 Read Permissions bits

1 = Privilege Group 3 has read permission
0 = Privilege Group 3 does not have read permission

bit 2 Group2: Group2 Read Permissions bits

1 = Privilege Group 2 has read permission
0 = Privilege Group 2 does not have read permission

bit 1 Group1: Group1 Read Permissions bits

1 = Privilege Group 1 has read permission
0 = Privilege Group 1 does not have read permission

bit 0 Group0: Group0 Read Permissions bits

1 = Privilege Group 0 has read permission
0 = Privilege Group 0 does not have read permission

Note 1: Refer to Table 4-6 for the list of available targets and their descriptions.

2: For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	———	——— —— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	———	——— —— ——
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	———	——— —— ——
7:0	U-0 U-0 U-0	U-0 R/W-0 R/W-1	R/W-1 R/W-1
7:0	—	—	—	—	GROUP3	GROUP2	GROUP1	GROUP0

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared

bit 31-4 Unimplemented: Read as '0'

bit 3 Group3: Group 3 Write Permissions bits

1 = Privilege Group 3 has write permission
0 = Privilege Group 3 does not have write permission

bit 2 Group2: Group 2 Write Permissions bits

1 = Privilege Group 2 has write permission
0 = Privilege Group 2 does not have write permission

bit 1 Group1: Group 1 Write Permissions bits

1 = Privilege Group 1 has write permission
0 = Privilege Group 1 does not have write permission

bit 0 Group0: Group 0 Write Permissions bits

1 = Privilege Group 0 has write permission
0 = Privilege Group 0 does not have write permission

Note 1: Refer to Table 4-6 for the list of available targets and their descriptions.

2: For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for more information.

5.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 52. “Flash Program Memory with Support for Live Update” (DS60001193), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

PIC32MZ EC devices contain an internal Flash program memory for executing user code, which includes the following features:

Two Flash banks for live update support
Dual boot support
Write protection for program and boot Flash
ECC support

There are three methods by which the user can program this memory:

- Run-Time Self-Programming (RTSP)

- EJTAG Programming

- In-Circuit Serial Programming™ (ICSP™)

RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 52. "Flash Program Memory with Support for Live Update" (DS60001193) in the "PIC32 Family Reference Manual".

EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer.

ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP.

The EJTAG and ICSP methods are described in the "PIC32 Flash Programming Specification" (DS60001145), which is available for download from the Microchip website.

Note: In PIC32MZ EC devices, the Flash page size is 16 KB (4096 IW) and the row size is 2 KB (512 IW).

5.1 Flash Control Registers

TABLE 5-1: FLASH CONTROLLER REGISTER MAP

Virtual Address(BF00_f)	Register Name	Bit Range	Bits																All Resets
Virtual Address(BF00_f)	Register Name	Bit Range	31/15 30	4 29/13 28	12 27/11 26	10 25/9 24	8 23/7 22/6	21/5 20/4	19/3 18/2 17	1/1 16/0									All Resets
0600	NVMCON(1)	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0600	NVMCON(1)	15:0	WR	WREN	WRERR	LVDERR	—	—	—	—	SWAP	—	—	—	NVMOP<31:0>				0000
0610	NVMKEY	31:16	NVMKEY<31:0>																0000
0610	NVMKEY	15:0	NVMKEY<31:0>																0000
0620	NVMADDR(1)	31:16	NVMADDR<31:0>																0000
0620	NVMADDR(1)	15:0	NVMADDR<31:0>																0000
0630	NVMDATA0	31:16	NVMDATA0<31:0>																0000
0630	NVMDATA0	15:0	NVMDATA0<31:0>																0000
0640	NVMDATA1	31:16	NVMDATA1<31:0>																0000
0640	NVMDATA1	15:0	NVMDATA1<31:0>																0000
0650	NVMDATA2	31:16	NVMDATA2<31:0>																0000
0650	NVMDATA2	15:0	NVMDATA2<31:0>																0000
0660	NVMDATA3	31:16	NVMDATA3<31:0>																0000
0660	NVMDATA3	15:0	NVMDATA3<31:0>																0000
0670	NVMSRC ADDR	31:16	NVMSRCADDR<31:0>																0000
0670	NVMSRC ADDR	15:0	NVMSRCADDR<31:0>																0000
0680	NVMPWP(1)	31:16	PWPULOCK	—	—	—	—	—	—	—	PWP<23:16>								0000
0680	NVMPWP(1)	15:0	PWP<15:0>																0000
0690	NVMBWP(1)	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0690	NVMBWP(1)	15:0	LBWPULOCK	—	—	LBWP4	LBWP3	LBWP2	LBWP1	LBWP0	UBWPULOCK	—	—	UBWP4	UBWP3	UBWP2	UBWP1	UBWP0	9TDF

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —	—
15:8	R/W-0, HC	R/W-0	R-0, HS, HC	R-0, HS, HC	U-0	U-0	U-0	U-0
15:8	WR(1)	WREN(1)	WRERR(1)	LVDERR(1)	— — —	—
7:0	R/W-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	SWAP	—	—	—	NVMOP<3:0>

Legend:	HS = Hardware Set	HC = Hardware Cleared
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 WR: Write Control bit ^(1)

This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been performed.

1 = Initiate a Flash operation

0 = Flash operation is complete or inactive

bit 14 WREN: Write Enable bit ^(1)

1 = Enable writes to the WR bit and disables writes to the NVMOP<3:0> bits

0 = Disable writes to WR bit and enables writes to the NVMOP<3:0> bits

bit 13 WRERR: Write Error bit ^(1)

This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.

1 = Program or erase sequence did not complete successfully

0 = Program or erase sequence completed normally

bit 12 LVDERR: Low-Voltage Detect Error bit ^(1)

This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.

1 = Low-voltage detected (possible data corruption, if WRERR is set)

0 = Voltage level is acceptable for programming

bit 11-8 Unimplemented: Read as '0'

bit 7 SWAP: Program Flash Bank Swap Control bit

This bit can be modified only when the WREN bit is '0' and the unlock sequence has been performed.

1 = Program Flash Bank 2 is mapped to the lower mapped region and program Flash Bank 1 is mapped to the upper mapped region

0 = Program Flash Bank 1 is mapped to the lower mapped region and program Flash Bank 2 is mapped to the upper mapped region

bit 6-4 Unimplemented: Read as '0'

Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

2: This operation results in a "no operation" (NOP) when the Dynamic Flash ECC Configuration bits = 00 (FECCCON<1:0> (DVCFG0<9:8>)), which enables ECC at all times. For all other FECCCON<1:0> bit settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors if dynamic Flash ECC is enabled (FECCCON<1:0> = 01). Refer to Section 52. "Flash Program Memory with Support for Live Update" (DS60001193) for information regarding ECC and Flash programming.

REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)

bit 3-0 NVMOP<3:0>: NVM Operation bits

These bits are only writable when WREN = 0.

1111 = Reserved

•

1000 = Reserved

0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected, PWP<23:0> = 0x000000)

0110 = Upper program Flash memory erase operation: erases only the upper mapped region of program Flash (all pages in that region must be unprotected)

0101 = Lower program Flash memory erase operation: erases only the lower mapped region of program Flash (all pages in that region must be unprotected)

0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected

0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected

0010 = Quad Word (128-bit) program operation: programs the 128-bit Flash word selected by NVMADDR, if it is not write-protected

0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected ^(2)

0000 = No operation

Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
31:24	NVMKEY<31:24>
23:16	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
23:16	NVMKEY<23:16>
15:8	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
15:8	NVMKEY<15:8>
7:0	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
7:0	NVMKEY<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMKEY<31:0>: Unlock Register bits

These bits are write-only, and read as '0' on any read

Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	NVMADDR<31:24>(1)
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	NVMADDR<23:16>(1)
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	NVMADDR<15:8>(1)
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	NVMADDR<7:0>(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMADDR<31:0>: Flash Address bits (1)

NVMOP<3:0>Selection	Flash Address Bits (NVMADDR<31:0>)
Page Erase	Address identifies the page to erase (NVMADDR<13:0> are ignored).
Row Program	Address identifies the row to program (NVMADDR<11:0> are ignored).
Word Program	Address identifies the word to program (NVMADDR<1:0> are ignored).
Quad Word Program	Address identifies the quad word (128-bit) to program (NVMADDR<3:0> bits are ignored).

Note 1: For all other NVMOP<3:0> bit settings, the Flash address is ignored. See the NVMCON register (Register 5-1) for additional information on these bits.

Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	NVMDATA<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	NVMDATA<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	NVMDATA<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	NVMDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMDATA<31:0>: Flash Data bits

Word Program: Writes NVMDATA0 to the target Flash address defined in NVMADDR

Quad Word Program: Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR. NVMDATA0 contains the Least Significant Instruction Word.

Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	NVMSRCADDR<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	NVMSRCADDR<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	NVMSRCADDR<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	NVMSRCADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits (NVMCON<3:0>) are set to perform row programming.

Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-1 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	PWPULOCK —	— — — —	—	—
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	PWP<23:16>
15:8	R/W-0	R/W-0	R-0 R-0 R-0	0 R-0 R-0 R-0
15:8	PWP<15:8>
7:0	R-0	R-0 R-0 R-0	0 R-0 R-0 R-0	0
7:0	PWP<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31 PWPULOCK: Program Flash Memory Page Write-protect Unlock bit

1 = Register is not locked and can be modified

0 = Register is locked and cannot be modified

This bit is only clearable and cannot be set except by any reset.

bit 30-24 Unimplemented: Read as '0'

bit 23-0 PWP<23:0>: Flash Program Write-protect (Page) Address bits

Physical memory below address 0x1Dxxxxxx is write protected, where 'xxxxxx' is specified by PWP<23:0>. When PWP<23:0> has a value of '0', write protection is disabled for the entire program Flash. If the specified address falls within the page, the entire page and all pages below the current page will be protected.

Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —
15:8	R/W-1	U-0	U-0	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
15:8	LBWPULOCK	—	—	LBWP4(1)	LBWP3(1)	LBWP2(1)	LBWP1(1)	LBWP0(1)
7:0	R/W-1	r-1	U-0	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
7:0	UBWPULOCK	—	—	UBWP4(1)	UBWP3(1)	UBWP2(1)	UBWP1(1)	UBWP0(1)

Legend:		r = Reserved
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 LBWPULOCK: Lower Boot Alias Write-protect Unlock bit

1 = LBWPx bits are not locked and can be modified

0 = LBWPx bits are locked and cannot be modified

This bit is only clearable and cannot be set except by any reset.

bit 14-13 Unimplemented: Read as '0'

bit 12 LBWP4: Lower Boot Alias Page 4 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled

bit 11 LBWP3: Lower Boot Alias Page 3 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled

bit 10 LBWP2: Lower Boot Alias Page 2 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled

bit 9 LBWP1: Lower Boot Alias Page 1 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF enabled
0 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF disabled

bit 8 LBWP0: Lower Boot Alias Page 0 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF enabled
0 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF disabled

bit 7 UBWPULOCK: Upper Boot Alias Write-protect Unlock bit

1 = UBWPx bits are not locked and can be modified
0 = UBWPx bits are locked and cannot be modified

This bit is only user-clearable and cannot be set except by any reset.

bit 6 Reserved: This bit is reserved for use by development tools
bit 5 Unimplemented: Read as '0'

Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock bit (LBWPULOCK or UBWPULOCK) is set.

Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.

REGISTER 5-7: NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER

bit 4 UBWP4: Upper Boot Alias Page 4 Write-protect bit (1)

1 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF enabled
0 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF disabled

bit 3 UBWP3: Upper Boot Alias Page 3 Write-protect bit (1)

1 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF enabled
0 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF disabled

bit 2 UBWP2: Upper Boot Alias Page 2 Write-protect bit (1)

1 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF enabled
0 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF disabled

bit 1 UBWP1: Upper Boot Alias Page 1 Write-protect bit (1)

1 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF enabled
0 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF disabled

bit 0 UBWP0: Upper Boot Alias Page 0 Write-protect bit (1)

1 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF enabled
0 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF disabled

Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock bit (LBWPULOCK or UBWPULOCK) is set.

Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.

NOTES:

6.0 RESETS

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS60001118), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The device Reset sources are as follows:

• Power-on Reset (POR)
- Master Clear Reset pin (MCLR)
- Software Reset (SWR)
- Watchdog Timer Reset (WDTR)
- Brown-out Reset (BOR)
- Configuration Mismatch Reset (CMR)
- Deadman Timer Reset (DMTR)

A simplified block diagram of the Reset module is illustrated in Figure 6-1.

FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - RESETS - 1

flowchart

graph TD
    A["MCLR"] --> B["Amplifier"]
    B --> C["Glitch Filter"]
    C --> D["MCLR"]
    E["Sleep or Idle"] --> F["WDT Time-out"]
    E --> G["DMT Time-out"]
    F --> H["NMI Time-out"]
    G --> H
    H --> I["AND"]
    I --> J["DMTR/WDTR"]
    K["Voltage Regulator Enabled"] --> L["Power-up Timer"]
    L --> M["AND"]
    M --> N["POR"]
    O["VDD"] --> P["VDD Rise Detect"]
    P --> Q["Brown-out Reset"]
    Q --> R["BOR"]
    S["Configuration Mismatch Reset"] --> T["CMR"]
    U["Software Reset"] --> V["SWR"]
    W["SYSRST"] --> N

6.1 Reset Control Registers

TABLE 6-1: RESETS REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'D'. Reset values are shown in hexadecimal.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 RW-0, HS	R/W-0, HS U-0	U-0
31:24	—	—	—	—	BCFGERR	BCFGFAIL	—	—
23:16	U-0 U-0 U-0	U-0	U-0	U-0	U-0 U-0
23:16	— — —	— —	—	—	—
15:8	U-0 U-0 U-0	U-0 U-0	U-0	R/W-0, H$				U-0
15:8	—	—	—	—	—	—	CMR	—
7:0	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-1, HS	R/W-1, HS
7:0	EXTR	SWR	DMTO	WDTO	SLEEP	IDLE	BOR(1)	POR(1)

Legend:	HS = Hardware Set HC = Hardware Cleared
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-28 Unimplemented: Read as '0'

bit 27 BCFGERR: Primary Configuration Registers Error Flag bit

1 = An error occurred during a read of the primary configuration registers
0 = No error occurred during a read of the primary configuration registers

bit 26 BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit

1 = An error occurred during a read of the primary and alternate configuration registers
0 = No error occurred during a read of the primary and alternate configuration registers

bit 25-10 Unimplemented: Read as '0'

bit 9 CMR: Configuration Mismatch Reset Flag bit

1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred

bit 8 Unimplemented: Read as '0'

bit 7 EXTR: External Reset (MCLR) Pin Flag bit

1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset Flag bit

1 = Software Reset was executed
0 = Software Reset was not executed

bit 5 DMTO: Deadman Timer Time-out Flag bit

1 = A DMT time-out has occurred
0 = A DMT time-out has not occurred

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred

bit 3 SLEEP: Wake From Sleep Flag bit

1 = Device was in Sleep mode
0 = Device was not in Sleep mode

bit 2 IDLE: Wake From Idle Flag bit

1 = Device was in Idle mode
0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit ^(1)

1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit ^(1)

1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred

Note 1: User software must clear this bit to view the next detection.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — —	—	—
7:0	U-0 U-0 U-0	U-0 U-0 U-0 U-0	0					W-0, HC
7:0	—	—	—	—	—	—	—	SWRST(1,2)

Legend:	HC = Hardware Cleared
R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-1 Unimplemented: Read as '0'

bit 0 SWRST: Software Reset Trigger bit ^(1,2)

1 = Enable software Reset event
0 = No effect

Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

2: Once this bit is set, any read of the RSWRST register will cause a reset to occur.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	R/W-0 R/W-0
31:24	— — —	— — —	D	M	T	O W	D	T
23:16	R/W-0	U-0 U-0 U-0	U-0 U-0				R/W-0 R/W-0
23:16	SWNMI	—	—	—	—	—	CF	WDTS
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0	U-0
15:8	— — —	— — —	—	—
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	NMICNT<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-26 Unimplemented: Read as '0'

bit 25 DMTO: Deadman Timer Time-out Flag bit

1 = DMT time-out has occurred and caused a NMI

0 = DMT time-out has not occurred

Setting this bit will cause a DMT NMI event, and NMICNT will begin counting.

bit 24 WDTO: Watchdog Timer Time-Out Flag bit

1 = WDT time-out has occurred and caused a NMI

0 = WDT time-out has not occurred

Setting this bit will cause a WDT NMI event, and MNICNT will begin counting.

bit 23 SWNMI: Software NMI Trigger.

1 = An NMI will be generated

0 = An NMI will not be generated

bit 22-18 Unimplemented: Read as '0'

bit 17 CF: Clock Fail Detect bit

1 = FSCM has detected clock failure and caused an NMI

0 = FSCM has not detected clock failure

Setting this bit will cause a CF NMI event, but will not cause a clock switch to the BFRC.

bit 16 WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit

1 = WDT time-out has occurred during Sleep mode and caused a wake-up from sleep

0 = WDT time-out has not occurred during Sleep mode

Setting this bit will cause a WDT NMI.

bit 15-8 Unimplemented: Read as '0'

bit 7-0 NMICNT<7:0>: NMI Reset Counter Value bits

These bits specify the reload value used by the NMI reset counter.

11111111-00000001 = Number of SYSCLK cycles before a device Reset occurs ^(1)

00000000 = No delay between NMI assertion and device Reset event

Note 1: When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset. This NMI reset counter is only applicable to these two specific NMI events.

Note: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — —	—	—
7:0	U-0 U-0 U-0	U-0 U-0 U-0 U-0	0					R/W-0
7:0	—	—	—	—	—	—	—	VREGS

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-1 Unimplemented: Read as '0'

bit 0 VREGS: Voltage Regulator Stand-by Enable bit

1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep

7.0 CPU EXCEPTIONS AND INTERRUPT CONTROLLER

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupt Controller" (DS60001108) and Section 50. "CPU for Devices with MIPS32® microAptiv™ and M-Class Cores" (DS60001192), which are available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

PIC32MZ EC devices generate interrupt requests in response to interrupt events from peripheral modules. The Interrupt Controller module exists outside of the CPU and prioritizes the interrupt events before presenting them to the CPU.

The CPU handles interrupt events as part of the exception handling mechanism, which is described in Section 7.1 "CPU Exceptions".

The Interrupt Controller module includes the following features:

Up to 190 interrupt sources and vectors with dedicated programmable offsets, eliminating the need for redirection
Single and multi-vector mode operations
Five external interrupts with edge polarity control
Interrupt proximity timer
Seven user-selectable priority levels for each vector
Four user-selectable subpriority levels within each priority
Seven shadow register sets that can be used for any priority level, eliminating software context switch and reducing interrupt latency
Software can generate any interrupt

Figure 7-1 shows the block diagram for the Interrupt Controller and CPU exceptions.
FIGURE 7-1: CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - CPU EXCEPTIONS AND INTERRUPT CONTROLLER - 1

flowchart

graph LR
    A["Interrupt Requests"] --> B["Interrupt Controller"]
    C["SYSCLK"] --> B
    B --> D["Vector Number and Offset"]
    B --> E["Priority Level"]
    B --> F["Shadow Set Number"]
    D --> G["CPU Core (Exception Handling)"]
    E --> G
    F --> G

7.1 CPU Exceptions

CPU coprocessor 0 contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data, external events or program errors. Table 7-1 lists the exception types in order of priority.

TABLE 7-1: MIPS32 ^ microAptiv™ MICROPROCESSOR CORE EXCEPTION TYPES

Exception Type(In Order of Priority)	Description Branches to		StatusBits Set	Debug BitsSet	EXCCODE	XC32 Function Name
Highest Priority
Reset	Assertion MCLR or a Power-on Reset (POR).	0xBFC0_0000	BEV, ERL	—	—	_on_reset
Soft Reset	Assertion of a software Reset.	0xBFC0_0000	BEV, SR, ERL	—	—	_on_reset
DSS	EJTAG debug single step.	0xBFC0_0480	—	DSS	—	—
DINT	EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register.	0xBFC0_0480	—	DINT	—	—
NMI	Assertion of NMI signal.	0xBFC0_0000	BEV, NMI, ERL	—	—	_nmi_handler
Machine Check	TLB write that conflicts with an existing entry.	EBASE+0x180	MCHECK, EXL	—	0x18 _general_exception_handler
Interrupt	Assertion of unmasked hardware or software interrupt signal.	See Table 7-2.	IPL<2:0>	—	0x00	See Table 7-2.
Deferred Watch	Deferred watch (unmasked by K\|DM=>!(K\|DM) transition).	EBASE+0x180	WP, EXL	—	0x17	_general_exception_handler
DIB	EJTAG debug hardware instruction break matched.	0xBFC0_0480	—	DIB	—	—
WATCH	A reference to an address that is in one of the Watch registers (fetch).	EBASE+0x180	EXL	—	0x17	_general_exception_handler
AdEL	Fetch address alignment error. Fetch reference to protected address.	EBASE+0x180	EXL	—	0x04	_general_exception_handler
TLBL	Fetch TLB miss or fetch TLB hit to page with V = 0.	EBASE if Status.EXL = 0	—	—	0x02	—
TLBL	Fetch TLB miss or fetch TLB hit to page with V = 0.	EBASE+0x180 if Status.EXL == 1	—	—	0x02	_general_exception_handler
TLBL Execute Inhibit	An instruction fetch matched a valid TLB entry that had the XI bit set.	EBASE+0x180	EXL	—	0x14	_general_exception_handler
IBE	Instruction fetch bus error.	EBASE+0x180	EXL	—	0x06	_general_exception_handler
Exception Type(In Order of Priority)	Description	Branches to	StatusBits Set	Debug BitsSet	EXCCODE	XC32 Function Name
Instruction Validity Exceptions	An instruction could not be completed because it was not allowed to access the required resources (Coprocessor Unusable) or was illegal (Reserved Instruction). If both exceptions occur on the same instruction, the Coprocessor Unusable Exception takes priority over the Reserved Instruction Exception.	EBASE+0x180 EXL	— 0x0A or		0x0B	_general_exception_handler
Execute Exception	An instruction-based exception occurred: Integer overflow, trap, system call, breakpoint, floating point, or DSP ASE state disabled exception.	EBASE+0x180	EXL	—	0x08-0x0C	_general_exception_handler
Tr	Execution of a trap (when trap condition is true).	EBASE+0x180	EXL	—	0x0D	_general_exception_handler
DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).		0xBFC0_0480 —	DDBL or DDBS	—	—	—
WATCH	A reference to an address that is in one of the Watch registers (data).	EBASE+0x180	EXL	—	0x17	_general_exception_handler
AdEL	Load address alignment error. User mode load reference to kernel address.	EBASE+0x180	EXL	—	0x04	_general_exception_handler
AdES	Store address alignment error. User mode store to kernel address.	EBASE+0x180	EXL	—	0x05	_general_exception_handler
TLBL	Load TLB miss or load TLB hit to page with V = 0.	EBASE+0x180	EXL	—	0x02	_general_exception_handler
TLBS	Store TLB miss or store TLB hit to page with V = 0.	EBASE+0x180	EXL	—	0x03	_general_exception_handler
DBE	Load or store bus error.	EBASE+0x180	EXL	—	0x07	_general_exception_handler
DDBL	EJTAG data hardware breakpoint matched in load data compare.	0xBFC0_0480	—	DDBL	—	—
CBrk	EJTAG complex breakpoint.	0xBFC0_0480	—	DIBIMPR,DDBLIMPR,and/orDDBSIMPR	—	—
Lowest Priority

7.2 Interrupts

The PIC32MZ EC family uses variable offsets for vector spacing. This allows the interrupt vector spacing to be configured according to application needs. A unique interrupt vector offset can be set for each vector using its associated OFFx register.

For details on the Variable Offset feature, refer to 8.5.2 "Variable Offset" in Section 8. "Interrupt Controller" (DS60001108) of the "PIC32 Family Reference Manual".

Table 7-2 provides the Interrupt IRQ, vector and bit location information.

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag Enable Priority Sub-priority				Persistent Interrupt
Highest Natural Order Priority
Core Timer Interrupt	_CORE_TIMER_VECTOR	0	OFF000<17:1>	IFS0<0>	IEC0<0>	IPC0<4:2>	IPC0<1:0>	No
Core Software Interrupt 0	_CORE_SOFTWARE_0_VECTOR	1	OFF001<17:1>	IFS0<1>	IEC0<1>	IPC0<12:10>	IPC0<9:8>	No
Core Software Interrupt 1	_CORE_SOFTWARE_1_VECTOR	2	OFF002<17:1>	IFS0<2>	IEC0<2>	IPC0<20:18>	IPC0<17:16>	No
External Interrupt	_EXTERNAL_0_VECTOR	3	OFF003<17:1>	IFS0<3>	IEC0<3>	IPC0<28:26>	IPC0<25:24>	No
Timer1	_TIMER_1_VECTOR	4	OFF004<17:1>	IFS0<4>	IEC0<4>	IPC1<4:2>	IPC1<1:0>	No
Input Capture 1 Error	_INPUT_CAPTURE_1_ERROR_VECTOR	5	OFF005<17:1>	IFS0<5>	IEC0<5>	IPC1<12:10>	IPC1<9:8>	Yes
Input Capture 1	_INPUT_CAPTURE_1_VECTOR	6	OFF006<17:1>	IFS0<6>	IEC0<6>	IPC1<20:18>	IPC1<17:16>	Yes
Output Compare 1	_OUTPUT_COMPARE_1_VECTOR	7	OFF007<17:1>	IFS0<7>	IEC0<7>	IPC1<28:26>	IPC1<25:24>	No
External Interrupt 1	_EXTERNAL_1_VECTOR	8	OFF008<17:1>	IFS0<8>	IEC0<8>	IPC2<4:2>	IPC2<1:0>	No
Timer2	_TIMER_2_VECTOR	9	OFF009<17:1>	IFS0<9>	IEC0<9>	IPC2<12:10>	IPC2<9:8>	No
Input Capture 2 Error	_INPUT_CAPTURE_2_ERROR_VECTOR	10	OFF010<17:1>	IFS0<10>	IEC0<10>	IPC2<20:18>	IPC2<17:16>	Yes
Input Capture 2	_INPUT_CAPTURE_2_VECTOR	11	OFF011<17:1>	IFS0<11>	IEC0<11>	IPC2<28:26>	IPC2<25:24>	Yes
Output Compare 2	_OUTPUT_COMPARE_2_VECTOR	12	OFF012<17:1>	IFS0<12>	IEC0<12>	IPC3<4:2>	IPC3<1:0>	No
External Interrupt 2	_EXTERNAL_2_VECTOR	13	OFF013<17:1>	IFS0<13>	IEC0<13>	IPC3<12:10>	IPC3<9:8>	No
Timer3	_TIMER_3_VECTOR	14	OFF014<17:1>	IFS0<14>	IEC0<14>	IPC3<20:18>	IPC3<17:16>	No
Input Capture 3 Error	_INPUT_CAPTURE_3_ERROR_VECTOR	15	OFF015<17:1>	IFS0<15>	IEC0<15>	IPC3<28:26>	IPC3<25:24>	Yes
Input Capture 3	INPUT_CAPTURE_3_VECTOR	16	OFF016<17:1>	IFS0<16>	IEC0<16>	IPC4<4:2>	IPC4<1:0>	Yes
Output Compare 3	_OUTPUT_COMPARE_3_VECTOR	17	OFF017<17:1>	IFS0<17>	IEC0<17>	IPC4<12:10>	IPC4<9:8>	No
External Interrupt 3	_EXTERNAL_3_VECTOR	18	OFF018<17:1>	IFS0<18>	IEC0<18>	IPC4<20:18>	IPC4<17:16>	No
Timer4	_TIMER_4_VECTOR	19	OFF019<17:1>	IFS0<19>	IEC0<19>	IPC4<28:26>	IPC4<25:24>	No
Input Capture 4 Error	_INPUT_CAPTURE_4_ERROR_VECTOR	20	OFF020<17:1>	IFS0<20>	IEC0<20>	IPC5<4:2>	IPC5<1:0>	Yes

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MZ EC Family Features" for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
4: This interrupt source is not available on 124-pin devices.

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
Input Capture 4	_INPUT_CAPTURE_4_VECTOR	21	OFF021<17:1>	IFS0<21>	IEC0<21>	IPC5<12:10>	IPC5<9:8>	Yes
Output Compare 4	_OUTPUT_COMPARE_4_VECTOR	22	OFF022<17:1>	IFS0<22>	IEC0<22>	IPC5<20:18>	IPC5<17:16>	No
External Interrupt 4	_EXTERNAL_4_VECTOR	23	OFF023<17:1>	IFS0<23>	IEC0<23>	IPC5<28:26>	IPC5<25:24>	No
Timer5	_TIMER_5_VECTOR	24	OFF024<17:1>	IFS0<24>	IEC0<24>	IPC6<4:2>	IPC6<1:0>	No
Input Capture 5 Error	_INPUT_CAPTURE_5_ERROR_VECTOR	25	OFF025<17:1>	IFS0<25>	IEC0<25>	IPC6<12:10>	IPC6<9:8>	Yes
Input Capture 5	_INPUT_CAPTURE_5_VECTOR	26	OFF026<17:1>	IFS0<26>	IEC0<26>	IPC6<20:18>	IPC6<17:16>	Yes
Output Compare 5	_OUTPUT_COMPARE_5_VECTOR	27	OFF027<17:1>	IFS0<27>	IEC0<27>	IPC6<28:26>	IPC6<25:24>	No
Timer6	_TIMER_6_VECTOR	28	OFF028<17:1>	IFS0<28>	IEC0<28>	IPC7<4:2>	IPC7<1:0>	No
Input Capture 6 Error	_INPUT_CAPTURE_6_ERROR_VECTOR	29	OFF029<17:1>	IFS0<29>	IEC0<29>	IPC7<12:10>	IPC7<9:8>	Yes
Input Capture 6	_INPUT_CAPTURE_6_VECTOR	30	OFF030<17:1>	IFS0<30>	IEC0<30>	IPC7<20:18>	IPC7<17:16>	Yes
Output Compare 6	_OUTPUT_COMPARE_6_VECTOR	31	OFF031<17:1>	IFS0<31>	IEC0<31>	IPC7<28:26>	IPC7<25:24>	No
Timer7	_TIMER_7_VECTOR	32	OFF032<17:1>	IFS1<0>	IEC1<0>	IPC8<4:2>	IPC8<1:0>	No
Input Capture 7 Error	_INPUT_CAPTURE_7_ERROR_VECTOR	33	OFF033<17:1>	IFS1<1>	IEC1<1>	IPC8<12:10>	IPC8<9:8>	Yes
Input Capture 7	INPUT_CAPTURE_7_VECTOR	34	OFF034<17:1>	IFS1<2>	IEC1<2>	IPC8<20:18>	IPC8<17:16>	Yes
Output Compare 7	_OUTPUT_COMPARE_7_VECTOR	35	OFF035<17:1>	IFS1<3>	IEC1<3>	IPC8<28:26>	IPC8<25:24>	No
Timer8	_TIMER_8_VECTOR	36	OFF036<17:1>	IFS1<4>	IEC1<4>	IPC9<4:2>	IPC9<1:0>	No
Input Capture 8 Error	_INPUT_CAPTURE_8_ERROR_VECTOR	37	OFF037<17:1>	IFS1<5>	IEC1<5>	IPC9<12:10>	IPC9<9:8>	Yes
Input Capture 8	_INPUT_CAPTURE_8_VECTOR	38	OFF038<17:1>	IFS1<6>	IEC1<6>	IPC9<20:18>	IPC9<17:16>	Yes
Output Compare 8	_OUTPUT_COMPARE_8_VECTOR	39	OFF039<17:1>	IFS1<7>	IEC1<7>	IPC9<28:26>	IPC9<25:24>	No
Timer9	_TIMER_9_VECTOR	40	OFF040<17:1>	IFS1<8>	IEC1<8>	IPC10<4:2>	IPC10<1:0>	No
Input Capture 9 Error	_INPUT_CAPTURE_9_ERROR_VECTOR	41	OFF041<17:1>	IFS1<9>	IEC1<9>	IPC10<12:10>	IPC10<9:8>	Yes
Input Capture 9	_INPUT_CAPTURE_9_VECTOR	42	OFF042<17:1>	IFS1<10>	IEC1<10>	IPC10<20:18>	IPC10<17:16>	Yes
Output Compare 9	_OUTPUT_COMPARE_9_VECTOR	43	OFF043<17:1>	IFS1<11>	IEC1<11>	IPC10<28:26>	IPC10<25:24>	No
ADC1 Global Interrupt	_ADC1_VECTOR	44	OFF044<17:1>	IFS1<12>	IEC1<12>	IPC11<4:2>	IPC11<1:0>	Yes
Reserved	—	45	—	—	—	—	—	—
ADC1 Digital Comparator 1	_ADC1_DC1_VECTOR	46	OFF046<17:1>	IFS1<14>	IEC1<14>	IPC11<20:18>	IPC11<17:16>	Yes
ADC1 Digital Comparator 2	_ADC1_DC2_VECTOR	47	OFF047<17:1>	IFS1<15>	IEC1<15>	IPC11<28:26>	IPC11<25:24>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
ADC1 Digital Comparator 3	_ADC1_DC3_VECTOR	48	OFF048<17:1>	IFS1<16>	IEC1<16>	IPC12<4:2>	IPC12<1:0>	Yes
ADC1 Digital Comparator 4	_ADC1_DC4_VECTOR	49	OFF049<17:1>	IFS1<17>	IEC1<17>	IPC12<12:10>	IPC12<9:8>	Yes
ADC1 Digital Comparator 5	_ADC1_DC5_VECTOR	50	OFF050<17:1>	IFS1<18>	IEC1<18>	IPC12<20:18>	IPC12<17:16>	Yes
ADC1 Digital Comparator 6	_ADC1_DC6_VECTOR	51	OFF051<17:1>	IFS1<19>	IEC1<19>	IPC12<28:26>	IPC12<25:24>	Yes
ADC1 Digital Filter 1	_ADC1_DF1_VECTOR	52	OFF052<17:1>	IFS1<20>	IEC1<20>	IPC13<4:2>	IPC13<1:0>	Yes
ADC1 Digital Filter 2	_ADC1_DF2_VECTOR	53	OFF053<17:1>	IFS1<21>	IEC1<21>	IPC13<12:10>	IPC13<9:8>	Yes
ADC1 Digital Filter 3	_ADC1_DF3_VECTOR	54	OFF054<17:1>	IFS1<22>	IEC1<22>	IPC13<20:18>	IPC13<17:16>	Yes
ADC1 Digital Filter 4	_ADC1_DF4_VECTOR	55	OFF055<17:1>	IFS1<23>	IEC1<23>	IPC13<28:26>	IPC13<25:24>	Yes
ADC1 Digital Filter 5	_ADC1_DF5_VECTOR	56	OFF056<17:1>	IFS1<24>	IEC1<24>	IPC14<4:2>	IPC14<1:0>	Yes
ADC1 Digital Filter 6	_ADC1_DF6_VECTOR	57	OFF057<17:1>	IFS1<25>	IEC1<25>	IPC14<12:10>	IPC14<9:8>	Yes
Reserved	—	58	—	—	—	—	—	—
ADC1 Data 0	_ADC1_DATA0_VECTOR	59	OFF059<17:1>	IFS1<27>	IEC1<27>	IPC14<28:26>	IPC14<25:24>	Yes
ADC1 Data 1	_ADC1_DATA1_VECTOR	60	OFF060<17:1>	IFS1<28>	IEC1<28>	IPC15<4:2>	IPC15<1:0>	Yes
ADC1 Data 2	_ADC1_DATA2_VECTOR	61	OFF061<17:1>	IFS1<29>	IEC1<29>	IPC15<12:10>	IPC15<9:8>	Yes
ADC1 Data 3	_ADC1_DATA3_VECTOR	62	OFF062<17:1>	IFS1<30>	IEC1<30>	IPC15<20:18>	IPC15<17:16>	Yes
ADC1 Data 4	_ADC1_DATA4_VECTOR	63	OFF063<17:1>	IFS1<31>	IEC1<31>	IPC15<28:26>	IPC15<25:24>	Yes
ADC1 Data 5	_ADC1_DATA5_VECTOR	64	OFF064<17:1>	IFS2<0>	IEC2<0>	IPC16<4:2>	IPC16<1:0>	Yes
ADC1 Data 6	_ADC1_DATA6_VECTOR	65	OFF065<17:1>	IFS2<1>	IEC2<1>	IPC16<12:10>	IPC16<9:8>	Yes
ADC1 Data 7	_ADC1_DATA7_VECTOR	66	OFF066<17:1>	IFS2<2>	IEC2<2>	IPC16<20:18>	IPC16<17:16>	Yes
ADC1 Data 8	_ADC1_DATA8_VECTOR	67	OFF067<17:1>	IFS2<3>	IEC2<3>	IPC16<28:26>	IPC16<25:24>	Yes
ADC1 Data 9	_ADC1_DATA9_VECTOR	68	OFF068<17:1>	IFS2<4>	IEC2<4>	IPC17<4:2>	IPC17<1:0>	Yes
ADC1 Data 10	_ADC1_DATA10_VECTOR	69	OFF069<17:1>	IFS2<5>	IEC2<5>	IPC17<12:10>	IPC17<9:8>	Yes
ADC1 Data 11	_ADC1_DATA11_VECTOR	70	OFF070<17:1>	IFS2<6>	IEC2<6>	IPC17<20:18>	IPC17<17:16>	Yes
ADC1 Data 12	_ADC1_DATA12_VECTOR	71	OFF071<17:1>	IFS2<7>	IEC2<7>	IPC17<28:26>	IPC17<25:24>	Yes
ADC1 Data 13	_ADC1_DATA13_VECTOR	72	OFF072<17:1>	IFS2<8>	IEC2<8>	IPC18<4:2>	IPC18<1:0>	Yes
ADC1 Data 14	_ADC1_DATA14_VECTOR	73	OFF073<17:1>	IFS2<9>	IEC2<9>	IPC18<12:10>	IPC18<9:8>	Yes
ADC1 Data 15	_ADC1_DATA15_VECTOR	74	OFF074<17:1>	IFS2<10>	IEC2<10>	IPC18<20:18>	IPC18<17:16>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
ADC1 Data 16	_ADC1_DATA16_VECTOR	75	OFF075<17:1>	IFS2<11>	IEC2<11>	IPC18<28:26>	IPC18<25:24>	Yes
ADC1 Data 17	_ADC1_DATA17_VECTOR	76	OFF076<17:1>	IFS2<12>	IEC2<12>	IPC19<4:2>	IPC19<1:0>	Yes
ADC1 Data 18	_ADC1_DATA18_VECTOR	77	OFF077<17:1>	IFS2<13>	IEC2<13>	IPC19<12:10>	IPC19<9:8>	Yes
ADC1 Data 19^(2)	_ADC1_DATA19_VECTOR	78	OFF078<17:1>	IFS2<14>	IEC2<14>	IPC19<20:18>	IPC19<17:16>	Yes
ADC1 Data 20^(2)	_ADC1_DATA20_VECTOR	79	OFF079<17:1>	IFS2<15>	IEC2<15>	IPC19<28:26>	IPC19<25:24>	Yes
ADC1 Data 21^(2)	_ADC1_DATA21_VECTOR	80	OFF080<17:1>	IFS2<16>	IEC2<16>	IPC20<4:2>	IPC20<1:0>	Yes
ADC1 Data 22^(2)	_ADC1_DATA22_VECTOR	81	OFF081<17:1>	IFS2<17>	IEC2<17>	IPC20<12:10>	IPC20<9:8>	Yes
ADC1 Data 23^(2)	_ADC1_DATA23_VECTOR	82	OFF082<17:1>	IFS2<18>	IEC2<18>	IPC20<20:18>	IPC20<17:16>	Yes
ADC1 Data 24^(2)	_ADC1_DATA24_VECTOR	83	OFF083<17:1>	IFS2<19>	IEC2<19>	IPC20<28:26>	IPC20<25:24>	Yes
ADC1 Data 25^(2)	_ADC1_DATA25_VECTOR	84	OFF084<17:1>	IFS2<20>	IEC2<20>	IPC21<4:2>	IPC21<1:0>	Yes
ADC1 Data 26^(2)	_ADC1_DATA26_VECTOR	85	OFF085<17:1>	IFS2<21>	IEC2<21>	IPC21<12:10>	IPC21<9:8>	Yes
ADC1 Data 27^(2)	_ADC1_DATA27_VECTOR	86	OFF086<17:1>	IFS2<22>	IEC2<22>	IPC21<20:18>	IPC21<17:16>	Yes
ADC1 Data 28^(2)	_ADC1_DATA28_VECTOR	87	OFF087<17:1>	IFS2<23>	IEC2<23>	IPC21<28:26>	IPC21<25:24>	Yes
ADC1 Data 29^(2)	_ADC1_DATA29_VECTOR	88	OFF088<17:1>	IFS2<24>	IEC2<24>	IPC22<4:2>	IPC22<1:0>	Yes
ADC1 Data 30^(2)	_ADC1_DATA30_VECTOR	89	OFF089<17:1>	IFS2<25>	IEC2<25>	IPC22<12:10>	IPC22<9:8>	Yes
ADC1 Data 31^(2)	_ADC1_DATA31_VECTOR	90	OFF090<17:1>	IFS2<26>	IEC2<26>	IPC22<20:18>	IPC22<17:16>	Yes
ADC1 Data 32^(2)	_ADC1_DATA32_VECTOR	91	OFF091<17:1>	IFS2<27>	IEC2<27>	IPC22<28:26>	IPC22<25:24>	Yes
ADC1 Data 33^(2)	_ADC1_DATA33_VECTOR	92	OFF092<17:1>	IFS2<28>	IEC2<28>	IPC23<4:2>	IPC23<1:0>	Yes
ADC1 Data 34^(2)	_ADC1_DATA34_VECTOR	93	OFF093<17:1>	IFS2<29>	IEC2<29>	IPC23<12:10>	IPC23<9:8>	Yes
ADC1 Data 35^(2,3)	_ADC1_DATA35_VECTOR	94	OFF094<17:1>	IFS2<30>	IEC2<30>	IPC23<20:18>	IPC23<17:16>	Yes
ADC1 Data 36^(2,3)	_ADC1_DATA36_VECTOR	95	OFF095<17:1>	IFS2<31>	IEC2<31>	IPC23<28:26>	IPC23<25:24>	Yes
ADC1 Data 37^(2,3)	_ADC1_DATA37_VECTOR	96	OFF096<17:1>	IFS3<0>	IEC3<0>	IPC24<4:2>	IPC24<1:0>	Yes
ADC1 Data 38^(2,3)	_ADC1_DATA38_VECTOR	97	OFF097<17:1>	IFS3<1>	IEC3<1>	IPC24<12:10>	IPC24<9:8>	Yes
ADC1 Data 39^(2,3)	_ADC1_DATA39_VECTOR	98	OFF098<17:1>	IFS3<2>	IEC3<2>	IPC24<20:18>	IPC24<17:16>	Yes
ADC1 Data 40^(2,3)	_ADC1_DATA40_VECTOR	99	OFF099<17:1>	IFS3<3>	IEC3<3>	IPC24<28:26>	IPC24<25:24>	Yes
ADC1 Data 41^(2,3)	_ADC1_DATA41_VECTOR	100	OFF100<17:1>	IFS3<4>	IEC3<4>	IPC25<4:2>	IPC25<1:0>	Yes
ADC1 Data 42^(2,3)	_ADC1_DATA42_VECTOR	101	OFF101<17:1>	IFS3<5>	IEC3<5>	IPC25<12:10>	IPC25<9:8>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
ADC1 Data 43	_ADC1_DATA43_VECTOR	102	OFF102<17:1>	IFS3<6>	IEC3<6>	IPC25<20:18>	IPC25<17:16>	Yes
ADC1 Data 44	_ADC1_DATA44_VECTOR	103	OFF103<17:1>	IFS3<7>	IEC3<7>	IPC25<28:26>	IPC25<25:24>	Yes
Core Performance Counter Interrupt	_CORE_PERF_COUNT_VECTOR	104	OFF104<17:1>	IFS3<8>	IEC3<8>	IPC26<4:2>	IPC26<1:0>	No
Core Fast Debug Channel Interrupt	CORE_FAST_DEBUG_CHAN_VECTOR	105	OFF105<17:1>	IFS3<9>	IEC3<9>	IPC26<12:10>	IPC26<9:8>	Yes
System Bus Protection Violation	_SYSTEM_BUS_PROTECTION_VECTOR	106	OFF106<17:1>	IFS3<10>	IEC3<10>	IPC26<20:18>	IPC26<17:16>	Yes
Crypto Engine Event	_CRYPTO_VECTOR	107	OFF107<17:1>	IFS3<11>	IEC3<11>	IPC26<28:26>	IPC26<25:24>	Yes
Reserved	—	108	—	—	—	—	—	—
SPI1 Fault	_SPI1_FAULT_VECTOR	109	OFF109<17:1>	IFS3<13>	IEC3<13>	IPC27<12:10>	IPC27<9:8>	Yes
SPI1 Receive Done	_SPI1_RX_VECTOR	110	OFF110<17:1>	IFS3<14>	IEC3<14>	IPC27<20:18>	IPC27<17:16>	Yes
SPI1 Transfer Done	_SPI1_TX_VECTOR	111	OFF111<17:1>	IFS3<15>	IEC3<15>	IPC27<28:26>	IPC27<25:24>	Yes
UART1 Fault	_UART1_FAULT_VECTOR	112	OFF112<17:1>	IFS3<16>	IEC3<16>	IPC28<4:2>	IPC28<1:0>	Yes
UART1 Receive Done	_UART1_RX_VECTOR	113	OFF113<17:1>	IFS3<17>	IEC3<17>	IPC28<12:10>	IPC28<9:8>	Yes
UART1 Transfer Done	_UART1_TX_VECTOR	114	OFF114<17:1>	IFS3<18>	IEC3<18>	IPC28<20:18>	IPC28<17:16>	Yes
I2C1 Bus Collision Event	_I2C1_BUS_VECTOR	115	OFF115<17:1>	IFS3<19>	IEC3<19>	IPC28<28:26>	IPC28<25:24>	Yes
I2C1 Slave Event	_I2C1_SLAVE_VECTOR	116	OFF116<17:1>	IFS3<20>	IEC3<20>	IPC29<4:2>	IPC29<1:0>	Yes
I2C1 Master Event	_I2C1_MASTER_VECTOR	117	OFF117<17:1>	IFS3<21>	IEC3<21>	IPC29<12:10>	IPC29<9:8>	Yes
PORTA Input Change Interrupt(2)	_CHANGE_NOTICE_A_VECTOR	118	OFF118<17:1>	IFS3<22>	IEC3<22>	IPC29<20:18>	IPC29<17:16>	Yes
PORTB Input Change Interrupt	_CHANGE_NOTICE_B_VECTOR	119	OFF119<17:1>	IFS3<23>	IEC3<23>	IPC29<28:26>	IPC29<25:24>	Yes
PORTC Input Change Interrupt	CHANGE_NOTICE_C_VECTOR	120	OFF120<17:1>	IFS3<24>	IEC3<24>	IPC30<4:2>	IPC30<1:0>	Yes
PORTD Input Change Interrupt	CHANGE_NOTICE_D_VECTOR	121	OFF121<17:1>	IFS3<25>	IEC3<25>	IPC30<12:10>	IPC30<9:8>	Yes
PORTE Input Change Interrupt	_CHANGE_NOTICE_E_VECTOR	122	OFF122<17:1>	IFS3<26>	IEC3<26>	IPC30<20:18>	IPC30<17:16>	Yes
PORTF Input Change Interrupt	CHANGE_NOTICE_F_VECTOR	123	OFF123<17:1>	IFS3<27>	IEC3<27>	IPC30<28:26>	IPC30<25:24>	Yes
PORTG Input Change Interrupt	CHANGE_NOTICE_G_VECTOR	124	OFF124<17:1>	IFS3<28>	IEC3<28>	IPC31<4:2>	IPC31<1:0>	Yes
PORTH Input Change Interrupt(2,3)	CHANGE_NOTICE_H_VECTOR	125	OFF125<17:1>	IFS3<29>	IEC3<29>	IPC31<12:10>	IPC31<9:8>	Yes
PORTJ Input Change Interrupt(2,3)	_CHANGE_NOTICE_J_VECTOR	126	OFF126<17:1>	IFS3<30>	IEC3<30>	IPC31<20:18>	IPC31<17:16>	Yes
PORTK Input Change Interrupt(2,3,4)	_CHANGE_NOTICE_K_VECTOR	127	OFF127<17:1>	IFS3<31>	IEC3<31>	IPC31<28:26>	IPC31<25:24>	Yes
Parallel Master Port	PMP_VECTOR	128	OFF128<17:1>	IFS4<0>	IEC4<0>	IPC32<4:2>	IPC32<1:0>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
Parallel Master Port Error	_PMP_ERROR_VECTOR	129	OFF129<17:1>	IFS4<1>	IEC4<1>	IPC32<12:10>	IPC32<9:8>	Yes
Comparator 1 Interrupt	_COMPARATOR_1_VECTOR	130	OFF130<17:1>	IFS4<2>	IEC4<2>	IPC32<20:18>	IPC32<17:16>	No
Comparator 2 Interrupt	_COMPARATOR_2_VECTOR	131	OFF131<17:1>	IFS4<3>	IEC4<3>	IPC32<28:26>	IPC32<25:24>	No
USB General Event	_USB1_VECTOR	132	OFF132<17:1>	IFS4<4>	IEC4<4>	IPC33<4:2>	IPC33<1:0>	Yes
USB DMA Event	_USB1_DMA_VECTOR	133	OFF133<17:1>	IFS4<5>	IEC4<5>	IPC33<12:10>	IPC33<9:8>	Yes
DMA Channel 0	_DMA0_VECTOR	134	OFF134<17:1>	IFS4<6>	IEC4<6>	IPC33<20:18>	IPC33<17:16>	No
DMA Channel 1	_DMA1_VECTOR	135	OFF135<17:1>	IFS4<7>	IEC4<7>	IPC33<28:26>	IPC33<25:24>	No
DMA Channel 2	_DMA2_VECTOR	136	OFF136<17:1>	IFS4<8>	IEC4<8>	IPC34<4:2>	IPC34<1:0>	No
DMA Channel 3	_DMA3_VECTOR	137	OFF137<17:1>	IFS4<9>	IEC4<9>	IPC34<12:10>	IPC34<9:8>	No
DMA Channel 4	_DMA4_VECTOR	138	OFF138<17:1>	IFS4<10>	IEC4<10>	IPC34<20:18>	IPC34<17:16>	No
DMA Channel 5	_DMA5_VECTOR	139	OFF139<17:1>	IFS4<11>	IEC4<11>	IPC34<28:26>	IPC34<25:24>	No
DMA Channel 6	_DMA6_VECTOR	140	OFF140<17:1>	IFS4<12>	IEC4<12>	IPC35<4:2>	IPC35<1:0>	No
DMA Channel 7	_DMA7_VECTOR	141	OFF141<17:1>	IFS4<13>	IEC4<13>	IPC35<12:10>	IPC35<9:8>	No
SPI2 Fault	_SPI2_FAULT_VECTOR	142	OFF142<17:1>	IFS4<14>	IEC4<14>	IPC35<20:18>	IPC35<17:16>	Yes
SPI2 Receive Done	_SPI2_RX_VECTOR	143	OFF143<17:1>	IFS4<15>	IEC4<15>	IPC35<28:26>	IPC35<25:24>	Yes
SPI2 Transfer Done	_SPI2_TX_VECTOR	144	OFF144<17:1>	IFS4<16>	IEC4<16>	IPC36<4:2>	IPC36<1:0>	Yes
UART2 Fault	_UART2_FAULT_VECTOR	145	OFF145<17:1>	IFS4<17>	IEC4<17>	IPC36<12:10>	IPC36<9:8>	Yes
UART2 Receive Done	_UART2_RX_VECTOR	146	OFF146<17:1>	IFS4<18>	IEC4<18>	IPC36<20:18>	IPC36<17:16>	Yes
UART2 Transfer Done	_UART2_TX_VECTOR	147	OFF147<17:1>	IFS4<19>	IEC4<19>	IPC36<28:26>	IPC36<25:24>	Yes
I2C2 Bus Collision Event^(2)	_I2C2_BUS_VECTOR	148	OFF148<17:1>	IFS4<20>	IEC4<20>	IPC37<4:2>	IPC37<1:0>	Yes
I2C2 Slave Event^(2)	_I2C2_SLAVE_VECTOR	149	OFF149<17:1>	IFS4<21>	IEC4<21>	IPC37<12:10>	IPC37<9:8>	Yes
I2C2 Master Event^(2)	_I2C2_MASTER_VECTOR	150	OFF150<17:1>	IFS4<22>	IEC4<22>	IPC37<20:18>	IPC37<17:16>	Yes
Control Area Network 1	_CAN1_VECTOR	151	OFF151<17:1>	IFS4<23>	IEC4<23>	IPC37<28:26>	IPC37<25:24>	Yes
Control Area Network 2	_CAN2_VECTOR	152	OFF152<17:1>	IFS4<24>	IEC4<24>	IPC38<4:2>	IPC38<1:0>	Yes
Ethernet Interrupt	_ETHERNET_VECTOR	153	OFF153<17:1>	IFS4<25>	IEC4<25>	IPC38<12:10>	IPC38<9:8>	Yes
SPI3 Fault	_SPI3_FAULT_VECTOR	154	OFF154<17:1>	IFS4<26>	IEC4<26>	IPC38<20:18>	IPC38<17:16>	Yes
SPI3 Receive Done	_SPI3_RX_VECTOR	155	OFF155<17:1>	IFS4<27>	IEC4<27>	IPC38<28:26>	IPC38<25:24>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
SPI3 Transfer Done	_SPI3_TX_VECTOR	156	OFF156<17:1>	IFS4<28>	IEC4<28>	IPC39<4:2>	IPC39<1:0>	Yes
UART3 Fault	_UART3_FAULT_VECTOR	157	OFF157<17:1>	IFS4<29>	IEC4<29>	IPC39<12:10>	IPC39<9:8>	Yes
UART3 Receive Done	_UART3_RX_VECTOR	158	OFF158<17:1>	IFS4<30>	IEC4<30>	IPC39<20:18>	IPC39<17:16>	Yes
UART3 Transfer Done	_UART3_TX_VECTOR	159	OFF159<17:1>	IFS4<31>	IEC4<31>	IPC39<28:26>	IPC39<25:24>	Yes
I2C3 Bus Collision Event	_I2C3_BUS_VECTOR	160	OFF160<17:1>	IFS5<0>	IEC5<0>	IPC40<4:2>	IPC40<1:0>	Yes
I2C3 Slave Event	_I2C3_SLAVE_VECTOR	161	OFF161<17:1>	IFS5<1>	IEC5<1>	IPC40<12:10>	IPC40<9:8>	Yes
I2C3 Master Event	_I2C3_MASTER_VECTOR	162	OFF162<17:1>	IFS5<2>	IEC5<2>	IPC40<20:18>	IPC40<17:16>	Yes
SPI4 Fault	_SPI4_FAULT_VECTOR	163	OFF163<17:1>	IFS5<3>	IEC5<3>	IPC40<28:26>	IPC40<25:24>	Yes
SPI4 Receive Done	_SPI4_RX_VECTOR	164	OFF164<17:1>	IFS5<4>	IEC5<4>	IPC41<4:2>	IPC41<1:0>	Yes
SPI4 Transfer Done	_SPI4_TX_VECTOR	165	OFF165<17:1>	IFS5<5>	IEC5<5>	IPC41<12:10>	IPC41<9:8>	Yes
Real Time Clock	_RTCC_VECTOR	166	OFF166<17:1>	IFS5<6>	IEC5<6>	IPC41<20:18>	IPC41<17:16>	No
Flash Control Event	_FLASH_CONTROL_VECTOR	167	OFF167<17:1>	IFS5<7>	IEC5<7>	IPC41<28:26>	IPC41<25:24>	No
Prefetch Module SEC Event	_PREFETCH_VECTOR	168	OFF168<17:1>	IFS5<8>	IEC5<8>	IPC42<4:2>	IPC42<1:0>	Yes
SQI1 Event	_SQI1_VECTOR	169	OFF169<17:1>	IFS5<9>	IEC5<9>	IPC42<12:10>	IPC42<9:8>	Yes
UART4 Fault	_UART4_FAULT_VECTOR	170	OFF170<17:1>	IFS5<10>	IEC5<10>	IPC42<20:18>	IPC42<17:16>	Yes
UART4 Receive Done	_UART4_RX_VECTOR	171	OFF171<17:1>	IFS5<11>	IEC5<11>	IPC42<28:26>	IPC42<25:24>	Yes
UART4 Transfer Done	_UART4_TX_VECTOR	172	OFF172<17:1>	IFS5<12>	IEC5<12>	IPC43<4:2>	IPC43<1:0>	Yes
I2C4 Bus Collision Event	_I2C4_BUS_VECTOR	173	OFF173<17:1>	IFS5<13>	IEC5<13>	IPC43<12:10>	IPC43<9:8>	Yes
I2C4 Slave Event	_I2C4_SLAVE_VECTOR	174	OFF174<17:1>	IFS5<14>	IEC5<14>	IPC43<20:18>	IPC43<17:16>	Yes
I2C4 Master Event	_I2C4_MASTER_VECTOR	175	OFF175<17:1>	IFS5<15>	IEC5<15>	IPC43<28:26>	IPC43<25:24>	Yes
SPI5 Fault(2)	_SPI5_FAULT_VECTOR	176	OFF176<17:1>	IFS5<16>	IEC5<16>	IPC44<4:2>	IPC44<1:0>	Yes
SPI5 Receive Done(2)	_SPI5_RX_VECTOR	177	OFF177<17:1>	IFS5<17>	IEC5<17>	IPC44<12:10>	IPC44<9:8>	Yes
SPI5 Transfer Done(2)	_SPI5_TX_VECTOR	178	OFF178<17:1>	IFS5<18>	IEC5<18>	IPC44<20:18>	IPC44<17:16>	Yes
UART5 Fault	_UART5_FAULT_VECTOR	179	OFF179<17:1>	IFS5<19>	IEC5<19>	IPC44<28:26>	IPC44<25:24>	Yes
UART5 Receive Done	_UART5_RX_VECTOR	180	OFF180<17:1>	IFS5<20>	IEC5<20>	IPC45<4:2>	IPC45<1:0>	Yes
UART5 Transfer Done	_UART5_TX_VECTOR	181	OFF181<17:1>	IFS5<21>	IEC5<21>	IPC45<12:10>	IPC45<9:8>	Yes
I2C5 Bus Collision Event	_I2C5_BUS_VECTOR	182	OFF182<17:1>	IFS5<22>	IEC5<22>	IPC45<20:18>	IPC45<17:16>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
I2C5 Slave Event	I2C5_SLAVE_VECTOR	183	OFF183<17:1>	IFS5<23>	IEC5<23>	IPC45<28:26>	IPC45<25:24>	Yes
I2C5 Master Event	I2C5_MASTER_VECTOR	184	OFF184<17:1>	IFS5<24>	IEC5<24>	IPC46<4:2>	IPC46<1:0>	Yes
SPI6 Fault(2)	_SPI6_FAULT_VECTOR	185	OFF185<17:1>	IFS5<25>	IEC5<25>	IPC46<12:10>	IPC46<9:8>	Yes
SPI6 Receive Done(2)	_SPI6_RX_VECTOR	186	OFF186<17:1>	IFS5<26>	IEC5<26>	IPC46<20:18>	IPC46<17:16>	Yes
SPI6 Transfer Done(2)	_SPI6_TX_VECTOR	187	OFF187<17:1>	IFS5<27>	IEC5<27>	IPC46<28:26>	IPC46<25:24>	Yes
UART6 Fault	_UART6_FAULT_VECTOR	188	OFF188<17:1>	IFS5<28>	IEC5<28>	IPC47<4:2>	IPC47<1:0>	Yes
UART6 Receive Done	_UART6_RX_VECTOR	189	OFF189<17:1>	IFS5<29>	IEC5<29>	IPC47<12:10>	IPC47<9:8>	Yes
UART6 Transfer Done	_UART6_TX_VECTOR	190	OFF190<17:1>	IFS5<30>	IEC5<30>	IPC47<20:18>	IPC47<17:16>	Yes
Lowest Natural Order Priority

7.3 Interrupt Control Registers

TABLE 7-3: INTERRUPT REGISTER MAP

Virtual Address(BF61_2)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

0000

INTCON

31:16

—

0000

15:0

—

MVEC

—

TPC<2:0>

—

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

0000

0010

PRISS

31:16

PRI7SS<3:0>

PRI6SS<3:0>

PRI5SS<3:0>

PRI4SS<3:0>

0000

15:0

PRI3SS<3:0>

PRI2SS<3:0>

PRI1SS<3:0>

—

SS0

0000

0020

INTSTAT

31:16

—

0000

15:0

—

SRIPL<2:0>

SIRQ<7:0>

0000

0030

IPTMR

31:16

IPTMR<31:0>

0000

15:0

0000

0040

IFS0

31:16

OC6IF

IC6IF

IC6EIF

T6IF

OC5IF

IC5IF

IC5EIF

T5IF

INT4IF

OC4IF

IC4IF

IC4EIF

T4IF

INT3IF

OC3IF

IC3IF

0000

15:0

IC3EIF

T3IF

INT2IF

OC2IF

IC2IF

IC2EIF

T2IF

INT1IF

OC1IF

IC1IF

IC1EIF

T1IF

INT0IF

CS1IF

CS0IF

CTIF

0000

0050

IFS1

31:16

AD1D4IF

AD1D3IF

AD1D2IF

AD1D1IF

AD1D0IF

—

AD1DF6IF

AD1DF5IF

AD1DF4IF

AD1DF3IF

AD1DF2IF

AD1DF1IF

AD1DC6IF

AD1DC5IF

AD1DC4IF

AD1DC3IF

0000

15:0

AD1DC2IF

AD1DC1IF

—

AD1IF

OC9IF

IC9IF

IC9EIF

T9IF

OC8IF

IC8IF

IC8EIF

T8IF

OC7IF

IC7IF

IC7EIF

T7IF

0000

0060

IFS2(5)

31:16

AD1D36IF

AD1D35IF

AD1D34IF

AD1D33IF

AD1D32IF

AD1D31IF

AD1D30IF

AD1D29IF

AD1D28IF

AD1D27IF

AD1D26IF

AD1D25IF

AD1D24IF

AD1D23IF

AD1D22IF

AD1D21IF

0000

15:0

AD1D20IF

AD1D19IF

AD1D18IF

AD1D17IF

AD1D16IF

AD1D15IF

AD1D14IF

AD1D13IF

AD1D12IF

AD1D11IF

AD1D10IF

AD1D9IF

AD1D8IF

AD1D7IF

AD1D6IF

AD1D5IF

0000

0070

IFS3(6)

31:16

CNKIF

CNJIF

CNHIF

CNGIF

CNFIF

CNEIF

CNDIF

CNCIF

CNBIF

CNAIF

I2C1MIF

I2C1SIF

I2C1BIF

U1TXIF

U1RXIF

U1EIF

0000

15:0

SPI1TXIF

SPI1RXIF

SPI1EIF

—

CRPTIF

SBIF

CFDCIF

CPCIF

AD1D44IF

AD1D43IF

AD1D42IF

AD1D41IF

AD1D40IF

AD1D39IF

AD1D38IF

AD1D37IF

0000

0080

IFS4

31:16

U3TXIF

U3RXIF

U3EIF

SPI3TXIF

SPI3RXIF

SPI3EIF

ETHIF

CAN2IF(3)

CAN1IF(3)

I2C2MIF(2)

I2C2SIF(2)

I2C2BIF(2)

U2TXIF

U2RXIF

U2EIF

SPI2TXIF

0000

15:0

SPI2RXIF

SPI2EIF

DMA7IF

DMA6IF

DMA5IF

DMA4IF

DMA3IF

DMA2IF

DMA1IF

DMA0IF

USBDMAIF

USBIF

CMP2IF

CMP1IF

PMPEIF

PMPIF

0000

0090

IFS5

31:16

—

U6TXIF

U6RXIF

U6EIF

SPI6TX(2)

SPI6RXIF(2)

SPI5IF(2)

I2C5MIF

I2C5SIF

I2C5BIF

U5TXIF

U5RXIF

U5EIF

SPI5TXIF(2)

SPI5RXIF(2)

SPI5EIF(2)

0000

15:0

I2C4MIF

I2C4SIF

I2C4BIF

U4TXIF

U4RXIF

U4EIF

SQI1IF

PREIF

FCEIF

RTCCIF

SPI4TXIF

SPI4RXIF

SPI4EIF

I2C3MIF

I2C3SIF

I2C3BIF

0000

00C0

IEC0

31:16

OC6IE

IC6EIE

T6IE

OC5IE

IC5IE

IC5EIE

T5IE

INT4IE

OC4IE

IC4IE

IC4EIE

T4IE

INT3IE

OC3IE

IC3IE

0000

15:0

IC3EIE

T3IE

INT2IE

OC2IE

IC2IE

IC2EIE

T2IE

INT1IE

OC1IE

IC1IE

IC1EIE

T1IE

INT0IE

CS1IE

CS0IE

CTIE

0000

00D0

IEC1

31:16

AD1D4IE

AD1D3IE

AD1D2IE

AD1D1IE

AD1D0IE

—

AD1DF6IE

AD1DF5IE

AD1DF4IE

AD1DF3IE

AD1DF2IE

AD1DF1IE

AD1DC6IE

AD1DC5IE

AD1DC4IE

AD1DC3IE

0000

15:0

AD1DC2IE

AD1DC1IE

—

AD1IE

OC9IE

IC9IE

IC9EIE

T9IE

OC8IE

IC8IE

IC8EIE

T8IE

OC7IE

IC7IE

IC7EIE

T7IE

0000

00E0

IEC2(5)

31:16

AD1D36IE

AD1D35IE

AD1D34IE

AD1D33IE

AD1D32IE

AD1D31IE

AD1D30IE

AD1D29IE

AD1D28IE

AD1D27IE

AD1D26IE

AD1D25IE

AD1D24IE

AD1D23IE

AD1D22IE

AD1D21IE

0000

15:0

AD1D20IE

AD1D19IE

AD1D18IE

AD1D17IE

AD1D16IE

AD1D15IE

AD1D14IE

AD1D13IE

AD1D12IE

AD1D11IE

AD1D10IE

AD1D9IE

AD1D8IE

AD1D7IE

AD1D6IE

AD1D5IE

0000

00F0

IEC3(6)

31:16

CNKIE

CNJIE

CNHIE

CNGIE

CNFIE

CNEIE

CNDIE

CNCIE

CNBIE

CNAIE

I2C1MIE

I2C1SIE

I2C1BIE

U1TXIE

U1RXIE

U1EIE

0000

15:0

SPI1TXIE

SPI1RXIE

SPI1EIE

—

CRPTIE

SBIE

CFDCIE

CPCIE

AD1D44IE

AD1D43IE

AD1D42IE

AD1D41IE

AD1D40IE

AD1D39IE

AD1D38IE

AD1D37IE

0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Virtual Address(BF31_2)	Register Name(1)	Bit Range	Bits																All Resets
			31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0
0100	IEC4	31:16	U3TXIE	U3RXIE	U3EIE	SPI3TXIE	SPI3RXIE	SPI3EIE	ETHIE	CAN2IE(3)	CAN1IE(3)	I2C2MIE(2)	I2C2SIE(2)	I2C2BIE(2)	U2TXIE	U2RXIE	U2EIE	SPI2TXIE	0000
		15:0	SPI2RXIE	SPI2EIE	DMA7IE	DMA6IE	DMA5IE	DMA4IE	DMA3IE	DMA2IE	DMA1IE	DMA0IE	USBDMAIE	USBIE	CMP2IE	CMP1IE	PMPEIE	PMPIE	0000
0110	IEC5	31:16	—	U6TXIE	U6RXIE	U6EIE	SPI6TXIE(2)	SPI6RXIE(2)	SPI6IE(2)	I2C5MIE	I2C5SIE	I2C5BIE	U5TXIE	U5RXIE	U5EIE	SPI6TXIE(2)	SPI5RXIE(2)	SPI5EIE(2)	0000
		15:0	I2C4MIE	I2C4SIE	I2C4BIE	U4TXIE	U4RXIE	U4EIE	SQLIE	PREIE	FCEIE	RTCCIE	SPI4TXIE	SPI4RXIE	SPI4EIE	I2C3MIE	I2C3SIE	I2C3BIE	0000
0140	IPC0	31:16	—	—	—	INT0IP<2.0>			INT0IS<1.0>		—	—	—	CS1IP<2.0>			CS1IS<1.0>		0000
		15:0	—	—	—	CS0IP<2.0>			CS0IS<1.0>		—	—	—	CTIP<2.0>			CTIS<1.0>		0000
0150	IPC1	31:16	—	—	—	OC1IP<2.0>			OC1IS<1.0>		—	—	—	IC1IP<2.0>			IC1IS<1.0>		0000
		15:0	—	—	—	IC1EIP<2.0>			IC1IS<1.0>		—	—	—	T1IP<2.0>			T1IS<1.0>		0000
0160	IPC2	31:16	—	—	—	IC2IP<2.0>			IC2IS<1.0>		—	—	—	IC2EIP<2.0>			IC2EIS<1.0>		0000
		15:0	—	—	—	T2IP<2.0>			T2IS<1.0>		—	—	—	INT1IP<2.0>			INT1IS<1.0>		0000
0170	IPC3	31:16	—	—	—	IC3EIP<2.0>			IC3EIS<1.0>		—	—	—	T3IP<2.0>			T3IS<1.0>		0000
		15:0	—	—	—	INT2IP<2.0>			INT2IS<1.0>		—	—	—	OC2IP<2.0>			OC2IS<1.0>		0000
0180	IPC4	31:16	—	—	—	T4IP<2.0>			T4IS<1.0>		—	—	—	INT3IP<2.0>			INT3IS<1.0>		0000
		15:0	—	—	—	OC3IP<2.0>			OC3IS<1.0>		—	—	—	IC3IP<2.0>			IC3IS<1.0>		0000
0190	IPC5	31:16	—	—	—	INT4IP<2.0>			INT4IS<1.0>		—	—	—	OC4IP<2.0>			OC4IS<1.0>		0000
		15:0	—	—	—	IC4IP<2.0>			IC4IS<1.0>		—	—	—	IC4EIP<2.0>			IC4EIS<1.0>		0000
01A0	IPC6	31:16	—	—	—	OC5IP<2.0>			OC5IS<1.0>		—	—	—	IC5IP<2.0>			IC5IS<1.0>		0000
		15:0	—	—	—	IC5EIP<2.0>			IC5EIS<1.0>		—	—	—	T5IP<2.0>			T5IS<1.0>		0000
01B0	IPC7	31:16	—	—	—	OC6IP<2.0>			OC6IS<1.0>		—	—	—	IC6IP<2.0>			IC6IS<1.0>		0000
		15:0	—	—	—	IC6EIP<2.0>			IC6EIS<1.0>		—	—	—	T6IP<2.0>			T6IS<1.0>		0000
01C0	IPC8	31:16	—	—	—	OC7IP<2.0>			OC7IS<1.0>		—	—	—	IC7IP<2.0>			IC7IS<1.0>		0000
		15:0	—	—	—	IC7EIP<2.0>			IC7EIS<1.0>		—	—	—	T7IP<2.0>			T7IS<1.0>		0000
01D0	IPC9	31:16	—	—	—	OC8IP<2.0>			OC8IS<1.0>		—	—	—	IC8IP<2.0>			IC8IS<1.0>		0000
		15:0	—	—	—	IC8EIP<2.0>			IC8EIS<1.0>		—	—	—	T8IP<2.0>			T8IS<1.0>		0000
01E0	IPC10	31:16	—	—	—	OC9IP<2.0>			OC9IS<1.0>		—	—	—	IC9IP<2.0>			IC9IS<1.0>		0000
		15:0	—	—	—	IC9EIP<2.0>			IC9EIS<1.0>		—	—	—	T9IP<2.0>			T9IS<1.0>		0000
01F0	IPC11	31:16	—	—	—	AD1DC2IP<2.0>			AD1DC2IS<1.0>		—	—	—	AD1DC1IP<2.0>			AD1DC1IS<1.0>		0000
		15:0	—	—	—	—	—	—	—	—	—	—	—	AD1IP<2.0>			AD1IS<1.0>		0000
0200	IPC12	31:16	—	—	—	AD1DC6IP<2.0>			AD1DC6IS<1.0>		—	—	—	AD1DC5IP<2.0>			AD1DC5IS<1.0>		0000
		15:0	—	—	—	AD1DC4IP<2.0>			AD1DC4IS<1.0>		—	—	—	AD1DC3IP<2.0>			AD1DC3IS<1.0>		0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Virtual Address(BF61_2)	Register Name(1)	Bit Range	Bits																All Resets
			31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0
0210	IPC13	31:16	—	—	—	AD1DF4IP<2.0>			AD1DF4IS<1.0>		—	—	—	AD1DF3IP<2.0>			AD1DF3IS<1.0>		0000
		15:0	—	—	—	AD1DF2IP<2.0>			AD1DF2IS<1.0>		—	—	—	AD1DF1IP<2.0>			AD1DF1IS<1.0>		0000
0220	IPC14	31:16	—	—	—	AD1D0IP<2.0>			AD1D0IS<1.0>		—	—	—	—	—	—	—	—	0000
		15:0	—	—	—	AD1DF8IP<2.0>			AD1DF8IS<1.0>		—	—	—	AD1DF5IP<2.0>			AD1DF5IS<1.0>		0000
0230	IPC15	31:16	—	—	—	AD1D4IP<2.0>			AD1D4IS<1.0>		—	—	—	AD1D3IP<2.0>			AD1D3IS<1.0>		0000
		15:0	—	—	—	AD1D2IP<2.0>			AD1D2IS<1.0>		—	—	—	AD1D1IP<2.0>			AD1D1IS<1.0>		0000
0240	IPC16	31:16	—	—	—	AD1D8IP<2.0>			AD1D8IS<1.0>		—	—	—	AD1D7IP<2.0>			AD1D7IS<1.0>		0000
		15:0	—	—	—	AD1D6IP<2.0>			AD1D6IS<1.0>		—	—	—	AD1D5IP<2.0>			AD1D5IS<1.0>		0000
0250	IPC17	31:16	—	—	—	AD1D12IP<2.0>			AD1D12IS<1.0>		—	—	—	AD1D11IP<2.0>			AD1D11IS<1.0>		0000
		15:0	—	—	—	AD1D10IP<2.0>			AD1D10IS<1.0>		—	—	—	AD1D9IP<2.0>			AD1D9IS<1.0>		0000
0260	IPC18	31:16	—	—	—	AD1D16IP<2.0>			AD1D16IS<1.0>		—	—	—	AD1D15IP<2.0>			AD1D15IS<1.0>		0000
		15:0	—	—	—	AD1D14IP<2.0>			AD1D14IS<1.0>		—	—	—	AD1D13IP<2.0>			AD1D13IS<1.0>		0000
0270	IPC19	31:16	—	—	AD1D20IP<2.0>			(2)	AD1D20IS<1.0>(2)		—	—	AD1D19IP<2.0>			(2)	AD1D19IS<1.0>(2)		0000
		15:0	—	—	—	AD1D18IP<2.0>			AD1D18IS<1.0>		—	—	—	AD1D17IP<2.0>			AD1D17IS<1.0>		0000
0280	IPC20	31:16	—	—	AD1D24IP<2.0>			(2)	AD1D24IS<1.0>(2)		—	—	AD1D23IP<2.0>			(2)	AD1D23IS<1.0>(2)		0000
		15:0	—	—	AD1D22IP<2.0>			(2)	AD1D22IS<1.0>(2)		—	—	AD1D21IP<2.0>			(2)	AD1D21IS<1.0>(2)		0000
0290	IPC21	31:16	—	—	AD1D28IP<2.0>			(2)	AD1D28IS<1.0>(2)		—	—	AD1D27IP<2.0>			(2)	AD1D27IS<1.0>(2)		0000
		15:0	—	—	AD1D25IP<2.0>			(2)	AD1D26IS<1.0>(2)		—	—	AD1D25IP<2.0>			(2)	AD1D25IS<1.0>(2)		0000
02A0	IPC22	31:16	—	—	AD1D32IP<2.0>			(2)	AD1D32IS<1.0>(2)		—	—	AD1D31IP<2.0>			(2)	AD1D31IS<1.0>(2)		0000
		15:0	—	—	AD1D30IP<2.0>			(2)	AD1D30IS<1.0>(2)		—	—	AD1D29IP<2.0>			(2)	AD1D29IS<1.0>(2)		0000
02B0	IPC23	31:16	—	—	AD1D36IP<2.0>			(2,4)	AD1D36IS<1.0>(2,4)		—	—	AD1D35IP<2.0>			(2,4)	AD1D35IS<1.0>(2,4)		0000
		15:0	—	—	AD1D34IP<2.0>			(2)	AD1D34IS<1.0>(2)		—	—	AD1D33IP<2.0>			(2)	AD1D33IS<1.0>(2)		0000
02C0	IPC24	31:16	—	—	AD1D40IP<2.0>			(2,4)	AD1D40IS<1.0>(2,4)		—	—	AD1D39IP<2.0>			(2,4)	AD1D39IS<1.0>(2,4)		0000
		15:0	—	—	AD1D38IP<2.0>			(2,4)	AD1D38IS<1.0>(2,4)		—	—	AD1D37IP<2.0>			(2,4)	AD1D37IS<1.0>(2,4)		0000
02D0	IPC25	31:16	—	—	—	AD1D44IP<2.0>			AD1D44IS<1.0>		—	—	—	AD1D43IP<2.0>			AD1D43IS<1.0>		0000
		15:0	—	—	AD1D42IP<2.0>			(2,4)	AD1D42IS<1.0>(2,4)		—	—	AD1D41IP<2.0>			(2,4)	AD1D41IS<1.0>(2,4)		0000
02E0	IPC26	31:16	—	—	CRPTIP<2.0>			(7)	CRPTIS<1.0>(7)		—	—	—	SBIP<2.0>			SBIS<1.0>		0000
		15:0	—	—	—	CFDCIP<2.0>			CFDCIS<1.0>		—	—	—	CPCIP<2.0>			CPCIS<1.0>		0000
02F0	IPC27	31:16	—	—	—	SPIITXIP<2.0>			SPIITXIS<1.0>		—	—	—	SPI1RXIP<2.0>			SPI1RXIS<1.0>		0000
		15:0	—	—	—	SPIIIEIP<2.0>			SPIIIEIS<1.0>		—	—	—	—	—	—	—	—	0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: AI registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4* This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31. 30. 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Coprin module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100 pin devices.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 54-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.
6. This bit of register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices: bit 31 is not available on 124-pin devices: bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR. SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
2: This bit or register is not available on devices without a CAN module.
4: This bit as registers is not available on 100-pin devices.
4. This ON OF Regulator is not available on TVV-Off Devices. 5. Date: 01 and 02 are not available on 04 pts and 100 pts devices, but 09 through 14 are not available on 04 pts devices.
5: Bits 31 and 32 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
B: This bit or register is not available on 124-pin devices

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — —	—	—
15:8	U-0	U-0	U-0	R/W-0	U-0	R/W-0	R/W-0	R/W-0
15:8	—	—	—	MVEC	—	TPC<2:0>
7:0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	INT4EP	INT3EP	INT2EP	INT1EP	INT0EP

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-13 Unimplemented: Read as '0'

bit 12 MVEC: Multi Vector Configuration bit

1 = Interrupt controller configured for multi vectored mode
0 = Interrupt controller configured for single vectored mode

bit 11 Unimplemented: Read as '0'

bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits

111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer

bit 7-5 Unimplemented: Read as '0'

bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit

bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit

bit 0 INTOEP: External Interrupt 0 Edge Polarity Control bit

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-28 PRI7SS<3:0>: Interrupt with Priority Level 7 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0)

0111 = Interrupt with a priority level of 7 uses Shadow Set 7

0110 = Interrupt with a priority level of 7 uses Shadow Set 6

。

•

0001 = Interrupt with a priority level of 7 uses Shadow Set 1

0000 = Interrupt with a priority level of 7 uses Shadow Set 0

bit 27-24 PRI6SS<3:0>: Interrupt with Priority Level 6 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0)

0111 = Interrupt with a priority level of 6 uses Shadow Set 7

0110 = Interrupt with a priority level of 6 uses Shadow Set 6

广力云智慧零售收银系统

•

0001 = Interrupt with a priority level of 6 uses Shadow Set 1

0000 = Interrupt with a priority level of 6 uses Shadow Set 0

bit 23-20 PRI5SS<3:0>: Interrupt with Priority Level 5 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0)

0111 = Interrupt with a priority level of 5 uses Shadow Set 7

0110 = Interrupt with a priority level of 5 uses Shadow Set 6

0001 = Interrupt with a priority level of 5 uses Shadow Set 1

0000 = Interrupt with a priority level of 5 uses Shadow Set 0

bit 19-16 PRI4SS<3:0>: Interrupt with Priority Level 4 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0)

0111 = Interrupt with a priority level of 4 uses Shadow Set 7

0110 = Interrupt with a priority level of 4 uses Shadow Set 6

0001 = Interrupt with a priority level of 4 uses Shadow Set 1

0000 = Interrupt with a priority level of 4 uses Shadow Set 0

Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
bit 15-12 PRI3SS<3:0>: Interrupt with Priority Level 3 Shadow Set bits ^(1) 1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0)

0111 = Interrupt with a priority level of 3 uses Shadow Set 7

0110 = Interrupt with a priority level of 3 uses Shadow Set 6

0001 = Interrupt with a priority level of 3 uses Shadow Set 1

0000 = Interrupt with a priority level of 3 uses Shadow Set 0

bit 11-8 PRI2SS<3:0>: Interrupt with Priority Level 2 Shadow Set bits ^(1) 1xxx = Reserved (by default, an interrupt with a priority level of 2 uses Shadow Set 0)

0111 = Interrupt with a priority level of 2 uses Shadow Set 7

0110 = Interrupt with a priority level of 2 uses Shadow Set 6

0001 = Interrupt with a priority level of 2 uses Shadow Set 1

0000 = Interrupt with a priority level of 2 uses Shadow Set 0

bit 7-4 PRI1SS<3:0>: Interrupt with Priority Level 1 Shadow Set bits ^(1) 1xxx = Reserved (by default, an interrupt with a priority level of 1 uses Shadow Set 0)

0111 = Interrupt with a priority level of 1 uses Shadow Set 7

0110 = Interrupt with a priority level of 1 uses Shadow Set 6

0001 = Interrupt with a priority level of 1 uses Shadow Set 1

0000 = Interrupt with a priority level of 1 uses Shadow Set 0

bit 3-1 Unimplemented: Read as '0'

bit 0 SS0: Single Vector Shadow Register Set bit

1 = Single vector is presented with a shadow set

0 = Single vector is not presented with a shadow set

Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— —	—	—	—
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0	—	—
23:16	— — —	— —	—	—	—
15:8	U-0 U-0 U-0	U-0 U-0	R-0 R-0	—	—
15:8	—	—	—	—	—	SRIPL<2:0>
7:0	R-0 R-0 R-0	R-0 R-0	R-0 R-0	—	—
7:0	SIRQ<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-11 Unimplemented: Read as '0'

bit 10-8 SRIPL<2:0>: Requested Priority Level bits for Single Vector Mode bits

111-000 = The priority level of the latest interrupt presented to the CPU

bit 7-6 Unimplemented: Read as '0'

bit 7-0 SIRQ<7:0>: Last Interrupt Request Serviced Status bits

11111111-00000000 = The last interrupt request number serviced by the CPU

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	IPTMR<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	IPTMR<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	IPTMR<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	IPTMR<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits

Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by an interrupt event.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
31:24	IFS31 IFS	IFS29 IFS	28 IFS27 IFS	26 IFS25 IFS	24
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
23:16	IFS23 IFS	IFS21 IFS	20 IFS19 IFS	18 IFS17 IFS	16
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	IFS15	IFS14	IFS13	IFS12	IFS11	IFS10	IFS9	IFS8
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	IFS7	IFS6	IFS5	IFS4	IFS3	IFS2	IFS1	IFS0

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-0 IFS31-IFS0: Interrupt Flag Status bits

1 = Interrupt request has occurred
0 = No interrupt request has occurred

Note: This register represents a generic definition of the IFSx register. Refer to Table 7-2 for the exact bit definitions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	IEC31	IEC30	IEC29	IEC28	IEC27	IEC26	IEC25	IEC24
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	IEC23	IEC22	IEC21	IEC20	IEC19	IEC18	IEC17	IEC16
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	IEC15	IEC14	IEC13	IEC12	IEC11	IEC10	IEC9	IEC8
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	IEC7	IEC6	IEC5	IEC4	IEC3	IEC2	IEC1	IEC0

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-0 IEC31-IEC0: Interrupt Enable bits

1 = Interrupt is enabled
0 = Interrupt is disabled

Note: This register represents a generic definition of the IECx register. Refer to Table 7-2 for the exact bit definitions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
31:24	— — —	IP3<2:0>		IS3<1:0>
23:16	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
23:16	— — —	IP2<2:0>		IS2<1:0>
15:8	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
15:8	— — —	IP1<2:0>		IS1<1:0>
7:0	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
7:0	— — —	IP0<2:0>		ISO<1:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28-26 IP3<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 25-24 IS3<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 23-21 Unimplemented: Read as '0'

bit 20-18 IP2<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 17-16 IS2<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 15-13 Unimplemented: Read as '0'

Note: This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit definitions.

bit 12-10 IP1<2:0>: Interrupt Priority bits
    111 = Interrupt priority is 7
    :
    010 = Interrupt priority is 2
    001 = Interrupt priority is 1
    000 = Interrupt is disabled
bit 9-8 IS1<1:0>: Interrupt Subpriority bits
    11 = Interrupt subpriority is 3
    10 = Interrupt subpriority is 2
    01 = Interrupt subpriority is 1
    00 = Interrupt subpriority is 0
bit 7-5 Unimplemented: Read as '0'
bit 4-2 IP0<2:0>: Interrupt Priority bits
    111 = Interrupt priority is 7
    :
    010 = Interrupt priority is 2
    001 = Interrupt priority is 1
    000 = Interrupt is disabled
bit 1-0 ISO<1:0>: Interrupt Subpriority bits
    11 = Interrupt subpriority is 3
    10 = Interrupt subpriority is 2
    01 = Interrupt subpriority is 1
    00 = Interrupt subpriority is 0

Note: This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit definitions.

Legend:
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 17-1 VOFF<17:1>: Interrupt Vector 'x' Address Offset bits

bit 0 Unimplemented: Read as '0'

8.0 OSCILLATOR CONFIGURATION

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The PIC32MZ EC oscillator system has the following modules and features:

A total of five external and internal oscillator options as clock sources
On-Chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources
On-Chip user-selectable divisor postscaler on select oscillator sources
Software-controllable switching between various clock sources
A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown with dedicated Back-up FRC (BFRC)
• Dedicated On-Chip PLL for USB peripheral
Flexible reference clock output
Multiple clock branches for peripherals for better performance flexibility

A block diagram of the oscillator system is provided in Figure 8-1. Table 8-1 shows the clock distribution.

FIGURE 8-1: PIC32MZ EC FAMILY OSCILLATOR DIAGRAM
Microchip PIC32MZ1024ECM124 - OSCILLATOR CONFIGURATION - 1

flowchart

graph TD
    A["USB PLL"] --> B["UPPLLSELUPLLEN"]
    B --> C["System PLL"]
    C --> D["PLLCLK"]
    D --> E["÷N"]
    E --> F["FIN(6)"]
    F --> G["PLL x M"]
    G --> H["PLL RANGE<2:0>(M)"]
    H --> I["÷N"]
    I --> J["FPLL(6)"]
    J --> K["REFCLKIx"]
    K --> L["POSC"]
    K --> M["FRC"]
    K --> N["LPRC"]
    K --> O["Sosc"]
    K --> P["PBCCLK1"]
    K --> Q["SYSCLK"]
    K --> R["BFRC"]
    L --> S["Reference Clock(5)"]
    M --> T["REFOxCON"]
    M --> U["REFOxTRIM"]
    T --> V["ROTRIM<8:0>(M)"]
    U --> W["OE"]
    V --> X["÷2×(N M/512)"]
    W --> Y["REFCLKOx"]
    X --> Z["RODIV<14:0>(N)"]
    Y --> AA["REFCLKOx"]
    Z --> AB["To SPI, ADC, SQI"]
    AA --> AC["'x' = 1-4'"]
    D --> AD["To USB PLL"]
    AD --> AE["VDD"]
    AE --> AF["XTAL"]
    AF --> AG["1 MΩ"]
    AG --> AH["OSC1"]
    AH --> AI["10 KΩ"]
    AI --> AJ["RF(2)"]
    AJ --> AK["Enable"]
    AK --> AL["OSC2(4)"]
    AL --> AM["Primary Oscillator (Posc)"]
    AM --> AN["To SYSCLK Mux"]
    AN --> AO["SPLL"]
    AO --> AP["SPLL"]
    AP --> AQ["Posc (HS, EC)"]
    AQ --> AR["Peripheral Bus Clock(5)"]
    AR --> AS["Postscaler"]
    AS --> AT["Peripherals, CPU"]
    AT --> AU["PBCCLKx"]
    AU --> AV["'x' = 1-5, 7, 8'"]
    AQ --> AW["To ADC and Flash"]
    AW --> AX["FRC Oscillator 8 MHz typical"]
    AX --> AY["TUN<5:0>"]
    AY --> AZ["Backup FRC Oscillator 8 MHz typical"]
    AZ --> BA["BFRC"]
    BA --> BB["LPRC Oscillator"]
    BB --> BC["32.768 kHz"]
    BC --> BD["SOSC"]
    BD --> BE["SOSCI"]
    BE --> BF["SOSCEN"]
    BF --> BG["SOSC"]
    BG --> BH["SOSC"]
    BH --> BI["SOSCL"]
    BI --> BJ["SOSCO"]
    BJ --> BK["SOSCI"]
    BK --> BL["SOSCO"]
    BL --> BM["SOSCI"]
    BM --> BN["SOSCO"]
    BN --> BO["SOSCI"]
    BO --> BP["SOSCO"]
    BP --> BQ["SOSCI"]

Notes: 1. A series resistor, RS, may be required for AT strip cut crystals, or to eliminate clipping. Alternately, to increase oscillator circuit gain, add a parallel resistor, RP.
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
3. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for help in determining the best oscillator components.
4. PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
5. Shaded regions indicate multiple instantiations of a peripheral or feature.
6. Refer to Table 37-19 in Section 37.0 "Electrical Characteristics" for frequency limitations.

TABLE 8-1: SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION

Peripheral

Clock Source

FRC

LPRC

SOSC

SYSCLK

USBCLK

PBCLK1^(1)

PBCLK2

PBCLK3

PBCLK4

PBCLK5

PBCLK7

PBCLK8

REFCLK01

REFCLK02

REFCLK03

CPU X

WDT X X

(2)

Deadman Timer X

(2)

Flash X

(2)

X^(2)

ADC

X X

(3)

Comparator

Crypto

RNG

USB

X^(3)

CAN

Ethernet

X^(3)

PMP

I2C

UART

RTCC

X^(2)

EBI

SQI

X^(3)

SPI

Timers

X^(4)

Output Compare

Input Capture

Ports

DMA

Interrupts

Prefetch

OSC2 Pin

X^(5)

Note 1: PBCLK1 is used by system modules and cannot be turned off.
2: SYSCLK/PBCLK1 is used to fetch data from/to the Flash Controller, while the FRC clock is used for programming.
3: Special Function Register (SFR) access only.
4: Timer1 only.
5: PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.

8.1 Fail-Safe Clock Monitor (FSCM)

The PIC32MZ EC oscillator system includes a Fail-safe Clock Monitor (FSCM). The FSCM monitors the SYSCLK for continuous operation. If it detects that the SYSCLK has failed, it switches the SYSCLK over to the BFRC oscillator and triggers a NMI. The BFRC is an untuned 8 MHz oscillator that will drive the SYSCLK during FSCM event. When the NMI is executed, soft -ware can attempt to restart the main oscillator or shut down the system.

In Sleep mode both the SYSCLK and the FSCM halt, which prevents FSCM detection.

8.2 Oscillator Control Registers

TABLE 8-2: OSCILLATOR CONFIGURATION REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 R/W-0	R/W-0 R/W-0
31:24	— — —	— — FRCD	IV<2:0>
23:16	R/W-0 R-0	U-0 U-0 U-0	U-0	U-0	U-0
23:16	DRMEN	SOSCRDY	—	—	—	—	—	—
15:8	U-0 R-0 R-0	R-0 U-0 R/W-y	R/W-y	R/W-y
15:8	—	COSC<2:0>			—	NOSC<2:0>
7:0	R/W-0	R-0	R-0	R/W-0	R/W-0, HS	U-0	R/W-y	R/W-y
7:0	CLKLOCK	ULOCK	SLOCK	SLPEN	CF	—	SOSCEN	OSWEN^(1)

Legend:	y = Value set from Configuration bits on POR	HS = Hardware Set
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared	x = Bit is unknown

bit 31-27 Unimplemented: Read as '0'

bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits

111 = FRC divided by 256

110 = FRC divided by 64

101 = FRC divided by 32

100 = FRC divided by 16

011 = FRC divided by 8

010 = FRC divided by 4

001 = FRC divided by 2

000 = FRC divided by 1 (default setting)

bit 23 DRMEN: Dream Mode Enable bit

1 = Dream mode is enabled

0 = Dream mode is disabled

bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit

1 = Indicates that the Secondary Oscillator is running and is stable

0 = Secondary Oscillator is still warming up or is turned off

bit 21-15 Unimplemented: Read as '0'

bit 14-12 COSC<2:0>: Current Oscillator Selection bits

111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

110 = Back-up Fast RC (BFRC) Oscillator

101 = Internal Low-Power RC (LPRC) Oscillator

100 = Secondary Oscillator (SOSC)

011 = Reserved

010 = Primary Oscillator (Posc) (HS or EC)

001 = System PLL (SPLL)

000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

bit 11 Unimplemented: Read as '0'

Note 1: The reset value for this bit depends on the setting of the IESO (DEVCFG1<7>) bit. When IESO = 1, the reset value is '1'. When IESO = 0, the reset value is '0'.

Note: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV) 110 = Reserved 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (S osc) 011 = Reserved 010 = Primary Oscillator (P osc) (HS or EC) 001 = System PLL (SPLL) 000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV) On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (DEVCFG1<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified
bit 6 ULOCK: USB PLL Lock Status bit 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled bit 5 SLOCK: System PLL Lock Status bit 1 = System PLL module is in lock or module start-up timer is satisfied 0 = System PLL module is out of lock, start-up timer is running or system PLL is disabled bit 4 SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 Unimplemented: Read as '0' bit 1 SOSCEN: Secondary Oscillator (S osc) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit (1) 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete
Note 1: The reset value for this bit depends on the setting of the IESO (DEVCFG1<7>) bit. When IESO = 1, the reset value is '1'. When IESO = 0, the reset value is '0'.

Note: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	—— —	—— — — — —
23:16	U-0 R-0 U-0	U-0 U-0	U-0 U-0 U-0
23:16	—— —	—— — — — —
15:8	U-0 R-0 U-0	U-0 U-0	U-0 U-0 U-0
15:8	—— —	—— — — — —
7:0	U-0 U-0 R-0	W-0 R/W-0	R/W-0 R/W-0 R/W-0
7:0	—— TUN<5:0>		(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as '0'
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits ^(1) 100000 = Center frequency -12.5%

100001 =

•

111111 =

000000 = Center frequency; Oscillator runs at minimal frequency (8 MHz)

000001 =

•

011110 =

011111 = Center frequency +12.5%

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized, nor tested.

Note: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 R/W-y	R/W-y R/W-y
31:24	— — —	— — PLLODIV<2:0>
23:16	U-0 R/W-y	R/W-y R/W-y R/W-y	R/W-y R/W-y R/W-y	R/W-y
23:16	— PLLMULT<6:0>
15:8	U-0 U-0 U-0	U-0 U-0 R/W-y	R/W-y R/W-y
15:8	— PLLIDIV<2:0>
7:0	R/W-y U-0	U-0 U-0 R/W-y	R/W-y R/W-y
7:0	PLLICLK —	— — — PLLRANGE<2:0>

Legend: y = Value set from Configuration bits on POR
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-27 Unimplemented: Read as '0'

bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits

111 = Reserved

110 = Reserved

101 = PLL Divide by 32

100 = PLL Divide by 16

011 = PLL Divide by 8

010 = PLL Divide by 4

001 = PLL Divide by 2

000 = Reserved

The default setting is specified by the FPLLODIV<2:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

bit 23 Unimplemented: Read as '0'

bit 22-16 PLLMULT<6:0>: System PLL Multiplier bits

1111111 = Multiply by 128

1111110 = Multiply by 127

1111101 = Multiply by 126

1111100 = Multiply by 125

•

0000000 = Multiply by 1

The default setting is specified by the FPLLMULT<6:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

bit 15-11 Unimplemented: Read as '0'

Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.

2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0>=001).

REGISTER 8-3: SPLLCON: SYSTEM PLL CONTROL REGISTER

bit 10-8 PLLIDIV<2:0>: System PLL Input Clock Divider bits

111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1

The default setting is specified by the FPLLIDIV<2:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information. If the PLLICLK bit is set for FRC, this setting is ignored by the PLL and the divider is set for Divide-by-1.

bit 7 PLLICLK: System PLL Input Clock Source bit

1 = FRC is selected as the input to the System PLL
0 = Posc is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

bit 6-3 Unimplemented: Read as '0'

bit 2-0 PLLRANGE<2:0>: System PLL Frequency Range Selection bits

111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass

The default setting is specified by the FPLL RNG<2:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.

2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0>=001).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	— RODIV<14:8>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	RODIV<7:0>
15:8	R/W-0 U-0	R/W-0 R/W-0 R/W-0	U-0 R/W-0, HC	R-0, HS, HC
15:8	ON(1)	—	SIDL	OE	RSLP^(2)	—	DIVSWEN	ACTIVE(1)
7:0	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	—	ROSEL<3:0>(3)

Legend:	HC = Hardware Clearable	HS = Hardware Settable
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31 Unimplemented: Read as '0'

bit 30-16 RODIV<14:0> Reference Clock Divider bits

The value selects the reference clock divider bits (see Figure 8-1 for details). A value of '0' selects no divider.

bit 15 ON: Output Enable bit ^(1)

1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Peripheral Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode

bit 12 OE: Reference Clock Output Enable bit

1 = Reference clock is driven out on REFCLKOx pin
0 = Reference clock is not driven out on REFCLKOx pin

bit 11 RSLP: Reference Oscillator Module Run in Sleep bit ^(2)

1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep

bit 10 Unimplemented: Read as '0'

bit 9 DIVSWEN: Divider Switch Enable bit

1 = Divider switch is in progress
0 = Divider switch is complete

bit 8 ACTIVE: Reference Clock Request Status bit ^(1)

1 = Reference clock request is active
0 = Reference clock request is not active

bit 7-4 Unimplemented: Read as '0'

bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits ^(3)

1111 = Reserved

•

1001 = BFRC

1000 = REFCLKIx

0111 = System PLL output

0110 = Reserved

0101 = SOSC

0100 = LPRC

0011 = FRC
0010 = Posc
0001 = PBCLK1
0000 = SYSCLK

Note 1: Do not write to this register when the ON bit is not equal to the ACTIVE bit.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
3: The ROSEL<3:0> bits should not be written while the ACTIVE bit is '1', as undefined behavior may result.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	ROTRIM<8:1>
23:16	R/W-0 R-0 U-0	U-0 U-0 U-0 U-0	U-0 U-0
23:16	ROTRIM<0>	— — — — —	— —
15:8	U-0 R-0 U-0	U-0 U-0 U-0	U-0 U-0
15:8	— — —	— — — — —
7:0	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
7:0	— — —	— — — — —

Legend:	y = Value set from Configuration bits on POR
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits

111111111 = 511/512 divisor added to RODIV value

111111110 = 510/512 divisor added to RODIV value

•

100000000 = 256/512 divisor added to RODIV value

•

000000010 = 2/512 divisor added to RODIV value

000000001 = 1/512 divisor added to RODIV value

000000000 = 0 divisor added to RODIV value

bit 22-0 Unimplemented: Read as '0'

Note 1: While the ON bit (REFOxCON<15>) is '1', writes to this register do not take effect until the DIVSWEN bit is also set to '1'.
2: Do not write to this register when the ON bit (REFOxCON<15>) is not equal to the ACTIVE bit (REFOxCON<8>).
3: Specified values in this register do not take effect if RODIV<14:0> (REFOxCON<30:16>) = 0.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —
15:8	R/W-1 U-0 U-0	U-0 R-1 U-0	U-0 U-0
15:8	ON(1)	— — —	PBDIVRDY		— — —
7:0	U-0	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x
7:0	—	PBDIV<6:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Peripheral Bus 'x' Output Clock Enable bit ^(1)

1 = Output clock is enabled
0 = Output clock is disabled

bit 14-12 Unimplemented: Read as '0'

bit 11 PBDIVRDY: Peripheral Bus 'x' Clock Divisor Ready bit

1 = Clock divisor logic is not switching divisors and the PBxDIV<6:0> bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV<6:0> bits cannot be written

bit 10-7 Unimplemented: Read as '0'

bit 6-0 PBDIV<6:0>: Peripheral Bus 'x' Clock Divisor Control bits

1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127

•
•
•

0000011 = PBCLKx is SYSCLK divided by 4

0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x ≠ 7)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x = 7)

Note 1: The clock for peripheral bus 1 cannot be turned off. Therefore, the ON bit in the PB1DIV register cannot be written as a '0'.

Note: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

9.0 PREFETCH MODULE

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 41. "Prefetch Module for Devices with L1 CPU Cache" (DS60001183), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Prefetch module is a performance enhancing module that is included in PIC32MZ EC family devices. When running at high-clock rates, Wait states must be inserted into Program Flash Memory (PFM) read transactions to meet the access time of the PFM. Wait states can be hidden to the core by prefetching and storing instructions in a temporary holding area that the CPU can access quickly. Although the data path to the CPU is 32 bits wide, the data path to the PFM is 128 bits wide. This wide data path provides the same bandwidth to the CPU as a 32-bit path running at four times the frequency.

The Prefetch module holds a subset of PFM in temporary holding spaces known as lines. Each line contains a tag and data field. Normally, the lines hold a copy of what is currently in memory to make instructions or data available to the CPU without Flash Wait states.

9.1 Features

4x16 byte fully-associative lines
• One line for CPU instructions
• One line for CPU data
Two lines for peripheral data
• 16-byte parallel memory fetch
Configurable predictive prefetch
Error detection and correction

A simplified block diagram of the Prefetch module is shown in Figure 9-1.

FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - Features - 1

flowchart

graph TD
    CPU["CPU"] --> BusControl["Bus Control"]
    BusControl --> PrefetchBuffer["Prefetch Buffer"]
    BusControl --> LineControl["Line Control"]
    BusControl --> ProgramFlashMemory["Program Flash Memory (PFM)"]
    BusControl --> SYSCLK["SYSCLK"]
    BusControl --> Tag["Tag"]
    BusControl --> Data["Data"]
    BusControl --> CPU2["CPU"]
    ProgramFlashMemory --> Data
    Data --> CPU2

9.2 Prefetch Control Registers

TABLE 9-1: PREFETCH REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	U-0 U-0	U-0 U-0 U-0 R/W	U-0					U-0
31:24	— — —	— — PFMSECEN	—	—
23:16	U-0 U-0	U-0 U-0 U-0	U-0	U-0	U-0
23:16	— — —	— —	—	—	—
15:8	U-0 U-0	U-0 U-0 U-0	U-0	U-0	U-0
15:8	— — —	— —	—	—	—
7:0	U-0	U-0	R/W-0	R/W-0	U-0	R/W-1	R/W-1	R/W-1
7:0	—	—	PREFEN<1:0>		—	PFMWS<2:0>(1)

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-27 Unimplemented: Read as '0'

bit 26 PFMSECEN: Flash SEC Interrupt Enable bit

1 = Generate an interrupt when the PFMSEC bit (PRESTAT<26>) is set

0 = Do not generate an interrupt when the PFMSEC bit is set

bit 25-6 Unimplemented: Read as '0'

bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits

11 = Enable predictive prefetch for any address

10 = Enable predictive prefetch for CPU instructions and CPU data

01 = Enable predictive prefetch for CPU instructions only

00 = Disable predictive prefetch

bit 3 Unimplemented: Read as '0'

bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSCLK Wait States bits ^(1)

111 = Seven Wait states

•

010 = Two Wait states

001 = One Wait state

000 = Zero Wait states

Note 1: For the Wait states to SYSCLK relationship, refer to Table 37-13 in Section37.0 “Electrical Characteristics”.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0	U-0 U-0			R/W-0, HS	R/W-0, HS	U-0	U-0
31:24	— — —	— PFMDED	PFMSEC —	—
23:16	U-0 U-0	U-0 U-0	U-0 U-0	U-0 U-0
23:16	— — —	— — — —	—
15:8	U-0 U-0	U-0 U-0	U-0 U-0	U-0 U-0
15:8	— — —	— — — —	—
7:0	R/W-0 R/W	R/W-0	R/W-0	R/W-0 R/W-0	R/W-0 R/W-0
7:0	PFMSECCNT<7:0>

Legend: HS = Hardware Set

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR

'1' = Bit is set

'0' = Bit is cleared

x = Bit is unknown

bit 31-28 Unimplemented: Read as '0'

bit 27 PFMDED: Flash Double-bit Error Detected (DED) Status bit

This bit is set in hardware and can only be cleared (i.e., set to '0') in software.

1 = A DED error has occurred

0 = A DED error has not occurred

bit 26 PFMSEC: Flash Single-bit Error Corrected (SEC) Status bit

1 = A SEC error occurred when PFMSECCNT<7:0> was equal to '0'

0 = A SEC error has not occurred

bit 25-8 Unimplemented: Read as '0'

bit 7-0 PFMSECCNT<7:0>: Flash SEC Count bits

11111111 - 00000000 = SEC count

This field decrements by one each time an SEC error occurs. It will hold at zero on the two-hundred and fifty-sixth error. When an SEC error occurs, when PFMSECCNT = 0, the PFMSEC status bit is set. If PFMSECEN is also set, an interrupt is generated.

Note: These bits count all SEC errors and are not limited to SEC errors on unique addresses.

10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS60001117), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Direct Memory Access (DMA) Controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the device such as SPI, UART, PMP, etc., or memory itself.

Note: To avoid cache coherency problems on devices with L1 cache, DMA buffers must only be allocated or accessed from the KSEG1 segment.

Following are some of the key features of the DMA Controller module:

• Eight identical channels, each featuring:

Auto-increment source and destination address registers
Source and destination pointers
Memory to memory and memory to peripheral transfers

• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and destination
• Fixed priority channel arbitration
- Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining

- Flexible DMA requests:

A DMA request can be selected from any of the peripheral interrupt sources
Each channel can select any (appropriate) observable interrupt as its DMA request source
A DMA transfer abort can be selected from any of the peripheral interrupt sources
Up to 2-byte Pattern (data) match transfer termination

- Multiple DMA channel status interrupts:

- DMA channel block transfer complete

- Source empty or half empty

- Destination full or half full

- DMA transfer aborted due to an external event

- Invalid DMA address generated

• DMA debug support features:

Most recent error address accessed by a DMA channel
Most recent DMA channel to transfer data

• CRC Generation module:

CRC module can be assigned to any of the available channels
CRC module is highly configurable

FIGURE 10-1: DMA BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - DIRECT MEMORY ACCESS (DMA) CONTROLLER - 1

flowchart

graph TD
    A["INT Controller"] --> B["System IRQ"]
    B --> C["Address Decoder"]
    C --> D["Channel 0 Control"]
    C --> E["Channel 1 Control"]
    C --> F["Channel n Control"]
    D --> G["SEM"]
    E --> G
    F --> G
    G --> H["Channel Priority Arbitration"]
    H --> I["Bus Interface"]
    I --> J["System Bus + Bus Arbitration"]
    J --> K["DMA"]
    K --> L["SYSCLK"]
    L --> M["Peripheral Bus"]
    M --> N["Global Control (DMACON)"]
    N --> C
    style A fill:#ccc,stroke:#333
    style K fill:#fff,stroke:#333

10.1 DMA Control Registers

TABLE 10-1: DMA GLOBAL REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-2: DMA CRC REGISTER MAP

Virtual Address(BF81_#)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

1030

DCRCCON

31:16

—

BYTEO<1:0>

WBO

—

BITO

—

0000

15:0

—

PLEN<4:0>

CRCEN

CRCAPP

CRCTYP

—

CRCCH<2:0>

0000

1040

DCRCDATA

31:16

DCRCDATA<31:0>

0000

15:0

0000

1050

DCRCXOR

31:16

DCRCXOR<31:0>

0000

15:0

0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registlers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)

Virtual Address(BF81 #)	Register Name(1)	Bit Range	Bits																All Resets
Virtual Address(BF81 #)	Register Name(1)	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
1390	DCH4SSA	31:16	CHSSA<31:0>																0000
1390	DCH4SSA	15:0
13A0	DCH4DSA	31:16	CHDSA<31:0>																0000
13A0	DCH4DSA	15:0
13B0	DCH4SSIZ	31:16	——	——	——	——	——	——	——
13B0	DCH4SSIZ	15:0	CHSSIZ<15:0> 0000
13C0	DCH4DSIZ	31:16	——	——	——	——	——	——	——
13C0	DCH4DSIZ	15:0	CHDSIZ<15:0> 0000
13D0	DCH4SPTR	31:16	——	——	——	——	——	——	——
13D0	DCH4SPTR	15:0	CHSPTR<15:0> 0000
13E0	DCH4DPTR	31:16	——	——	——	——	——	——	——
13E0	DCH4DPTR	15:0	CHDPTR<15:0> 0000
13F0	DCH4CSIZ	31:16	——	——	——	——	——	——	——
13F0	DCH4CSIZ	15:0	CHCSIZ<15:0> 0000
1400	DCH4CPTR	31:16	——	——	——	——	——	——	——
1400	DCH4CPTR	15:0	CHCPTR<15:0> 0000
1410	DCH4DAT	31:16	——	——	——	——	——	——	——
1410	DCH4DAT	15:0	CHPDAT<15:0> 0000
1420	DCH5CON	31:16	CHPIGN<7:0>								——	——	——	0000
1420	DCH5CON	15:0	CHBUSY	—	CHPIGNEN	—	CHPATLEN	—	—	CHCHNS	CHEN	CHAED	CHCHN	CHAEN	—	CHEDET	CHPRI<1:0>		0000
1430	DCH5ECON	31:16	—	—	—	—	—	—	—	—	CHAIRQ<7:0>								0025
1430	DCH5ECON	15:0	CHSIRQ<7:0>								CFORCE	CABORT	PATEN	SIRQEN	AIRQEN	—	—	—	FF00
1440	DCH5INT	31:16	—	—	—	—	—	—	—	—	CHSDIE	CHSHIE	CHDDIE	CHDHIE	CHBCIE	CHCCIE	CHTAIE	CHERIE	0000
1440	DCH5INT	15:0	—	—	—	—	—	—	—	—	CHSDIF	CHSHIF	CHDDIF	CHDHIF	CHBCIF	CHCCIF	CHTAIF	CHERIF	0000
1450	DCH5SSA	31:16	CHSSA<31:0>																0000
1450	DCH5SSA	15:0
1460	DCH5DSA	31:16	CHDSA<31:0>																0000
1460	DCH5DSA	15:0
1470	DCH5SSIZ	31:16	——	——	——	——	——	——	——
1470	DCH5SSIZ	15:0	CHSSIZ<15:0>																0000
1480	DCH5DSIZ	31:16	——	——	——	——	——	——	——
1480	DCH5DSIZ	15:0	CHDSIZ<15:0> 0000
1490	DCH5SPTR	31:16	——	——	——	——	——	——	——
1490	DCH5SPTR	15:0	CHSPTR<15:0> 0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —	—
15:8	R/W-0 U-0	U-0	R/W-0	R/W-0	U-0 U-0 U-0
15:8	ON	—	—	SUSPEND	DMABUSY	—	—	—
7:0	U-0 U-0 U-0	U-0 U-0 U-0	U-0
7:0	— — —	— — — —	—

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: DMA On bit

1 = DMA module is enabled
0 = DMA module is disabled

bit 14-13 Unimplemented: Read as '0'

bit 12 SUSPEND: DMA Suspend bit

1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally

bit 11 DMABUSY: DMA Module Busy bit

1 = DMA module is active and is transferring data
0 = DMA module is disabled and not actively transferring data

bit 10-0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	RDWR —	— — — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	—	— — —	— — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	—	— — —	— — — —
7:0	U-0 U-0 U-0	U-0 U-0 R-0 R-0	R-0
7:0	—	— — —	—	DMACH<2:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 RDWR: Read/Write Status bit

1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write

bit 30-3 Unimplemented: Read as '0'

bit 2-0 DMACH<2:0>: DMA Channel bits

These bits contain the value of the most recent active DMA channel when an error was detected.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
31:24	DMAADDR<31:24>
23:16	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
23:16	DMAADDR<23:16>
15:8	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
15:8	DMAADDR<15:8>
7:0	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
7:0	DMAADDR<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DMAADDR<31:0>: DMA Module Address bits

These bits contain the address of the most recent DMA access when an error was detected.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 R/W-0 R/W-0 R/W-0		U-0 U-0 R/W-0
31:24	— — BYTO<1:0> WBO				(1)	—	—	BITO
23:16	U-0 U-0	U-0	U-0	U-0 U-0	U-0 U-0
23:16	—	—	—	—	—	—	—	—
15:8	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	— —	—		PLEN<4:0> (1)
7:0	R/W-0	R/W-0	R/W-0	U-0	U-0	R/W-0	R/W-0	R/W-0
7:0	CRCEN	CRCAPP(1)	CRCTYP	—	—	CRCCH<2:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as '0'

bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits

11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order per half-word)
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per half-word)
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)

bit 27 WBO: CRC Write Byte Order Selection bit ^(1)

1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered

bit 26-25 Unimplemented: Read as '0'

bit 24 BITO: CRC Bit Order Selection bit

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)

bit 23-13 Unimplemented: Read as '0'

bit 12-8 PLEN<4:0>: Polynomial Length bits ^(1)

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

These bits are unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Denotes the length of the polynomial - 1.

bit 7 CRCEN: CRC Enable bit

1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)

bit 6 CRCAPP: CRC Append Mode bit (1)

1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination

bit 5 CRCTYP: CRC Type Selection bit

1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC

bit 4-3 Unimplemented: Read as '0'

bit 2-0 CRCCH<2:0>: CRC Channel Select bits

111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	DCRCDATA<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	DCRCDATA<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	DCRCDATA<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	DCRCDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 DCRCDATA<31:0>: CRC Data Register bits

Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return '0' on any read.

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always '0'. Data written to this register is converted and read back in 1's complement form (i.e., current IP header checksum value).

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Bits greater than PLEN will return '0' on any read.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	DCRCXOR<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	DCRCXOR<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	DCRCXOR<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	DCRCXOR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

This register is unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = Enable the XOR input to the Shift register

0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0
31:24	CHPIGN<7:0>
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0
23:16	—	—	—	—	—	—	—	—
15:8	R/W-0	U-0	R/W-0	U-0	R/W-0	U-0	U-0	R/W-0
15:8	CHBUSY	—	CHIPGNEN	—	CHPATLEN	—	—	CHCHNS(1)
7:0	R/W-0 R/W-0	R/W-0 R/W-0	U-0 R-0	R/W-0	R/W-0
7:0	CHEN(2)	CHAED	CHCHN	CHAEN	—	CHEDET	CHPRI<1:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 CHPIGN<7:0>: Channel Register Data bits

Pattern Terminate mode:

Any byte matching these bits during a pattern match may be ignored during the pattern match determination when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match logic will treat it as a "don't care" when the pattern matching logic is enabled and the CHPIGEN bit is set.

bit 23-16 Unimplemented: Read as '0'

bit 15 CHBUSY: Channel Busy bit

1 = Channel is active or has been enabled

0 = Channel is inactive or has been disabled

bit 14 Unimplemented: Read as '0'

bit 13 CHPIGNEN: Enable Pattern Ignore Byte bit

1 = Treat any byte that matches the CHPIGN<7:0> bits as a "don't care" when pattern matching is enabled 0 = Disable this feature

bit 12 Unimplemented: Read as '0'

bit 11 CHPATLEN: Pattern Length bit

1 = 2 byte length

0 = 1 byte length

bit 10-9 Unimplemented: Read as '0'

bit 8 CHCHNS: Chain Channel Selection bit ^(1)

1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)

0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)

bit 7 CHEN: Channel Enable bit ^(2)

1 = Channel is enabled

0 = Channel is disabled

bit 6 CHAED: Channel Allow Events If Disabled bit

1 = Channel start/abort events will be registered, even if the channel is disabled

0 = Channel start/abort events will be ignored if the channel is disabled

bit 5 CHCHN: Channel Chain Enable bit

1 = Allow channel to be chained

0 = Do not allow channel to be chained

Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).

2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended.

REGISTER 10-7: DCHxCON: DMA CHANNEL x CONTROL REGISTER (CONTINUED)

bit 4 CHAEN: Channel Automatic Enable bit

1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete

bit 3 Unimplemented: Read as '0'

bit 2 CHEDET: Channel Event Detected bit

1 = An event has been detected
0 = No events have been detected

bit 1-0 CHPRI<1:0>: Channel Priority bits

11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0

Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	—— ——— ———
23:16	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
23:16	CHAIRQ<7:0>(1)
15:8	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
15:8	CHSIRQ<7:0>(1)
7:0	S-0 S-0	R/W-0 R	W-0	R/W-0	U-0 U-0 U-0
7:0	CFORCE	CABORT	PATEN	SIRQEN	AIRQEN	—	—	—

Legend:	S = Settable bit
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-24 Unimplemented: Read as '0'

bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits ^(1)

11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag

•

00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag

00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag

bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits ^(1)

11111111 = Interrupt 255 will initiate a DMA transfer

•

00000001 = Interrupt 1 will initiate a DMA transfer

00000000 = Interrupt 0 will initiate a DMA transfer

bit 7 CFORCE: DMA Forced Transfer bit

1 = A DMA transfer is forced to begin when this bit is written to a '1'

0 = This bit always reads '0'

bit 6 CABORT: DMA Abort Transfer bit

1 = A DMA transfer is aborted when this bit is written to a '1'

0 = This bit always reads '0'

bit 5 PATEN: Channel Pattern Match Abort Enable bit

1 = Abort transfer and clear CHEN on pattern match

0 = Pattern match is disabled

bit 4 SIRQEN: Channel Start IRQ Enable bit

1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs

0 = Interrupt number CHSIRQ is ignored and does not start a transfer

bit 3 AIRQEN: Channel Abort IRQ Enable bit

1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs

0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer

bit 2-0 Unimplemented: Read as '0'

Note 1: See Table 7-2: "Interrupt IRQ, Vector and Bit Location" for the list of available interrupt IRQ sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	CHSDIE	CHSHIE	CHDDIE	CHDHIE	CHBCIE	CHCCIE	CHTAIE	CHERIE
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	———	——— ——
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CHSDIF	CHSHIF	CHDDIF	CHDHIF	CHBCIF	CHCCIF	CHTAIF	CHERIF

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as '0'

bit 23 CHSDIE: Channel Source Done Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 16 CHERIE: Channel Address Error Interrupt Enable bit

1 = Interrupt is enabled

0 = Interrupt is disabled

bit 15-8 Unimplemented: Read as '0'

bit 7 CHSDIF: Channel Source Done Interrupt Flag bit

1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)

0 = No interrupt is pending

bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit

1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)

0 = No interrupt is pending

REGISTER 10-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED)

bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit

1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending

bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit

1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending

bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit

1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs
0 = No interrupt is pending

bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit

1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending

bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit

1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending

bit 0 CHERIF: Channel Address Error Interrupt Flag bit

1 = A channel address error has been detected Either the source or the destination address is invalid.
0 = No interrupt is pending

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	W-0 R/W-0 R/W-0	R/W-0
31:24	CHSSA<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	W-0 R/W-0 R/W-0	R/W-0
23:16	CHSSA<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	W-0 R/W-0 R/W-0	R/W-0
15:8	CHSSA<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	W-0 R/W-0 R/W-0	R/W-0
7:0	CHSSA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 CHSSA<31:0> Channel Source Start Address bits

Channel source start address.

Note: This must be the physical address of the source.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	CHDSA<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	CHDSA<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	CHDSA<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CHDSA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits

Channel destination start address.

Note: This must be the physical address of the destination.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	—— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ———
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	—— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——— ——
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	CHSSIZ<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CHSSIZ<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 CHSSIZ<15:0>: Channel Source Size bits

1111111111111111 = 65,535 byte source size

•

0000000000000010 = 2 byte source size

0000000000000001 = 1 byte source size

0000000000000000 = 65,536 byte source size

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	—— ——	—— —— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	—— ——	—— —— ——
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	CHDSIZ<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CHDSIZ<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits

1111111111111111 = 65,535 byte destination size

•

0000000000000010 = 2 byte destination size

0000000000000001 = 1 byte destination size

0000000000000000 = 65,536 byte destination size

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
15:8	CHSPTR<15:8>
7:0	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
7:0	CHSPTR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits

11111111111111111 = Points to byte 65,535 of the source

•

0000000000000001 = Points to byte 1 of the source

00000000000000000 = Points to byte 0 of the source

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
31:24	— — — —	—	— — — —
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
23:16	— — — —	—	— — — —
15:8	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
15:8	CHDPTR<15:8>
7:0	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
7:0	CHDPTR<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits

11111111111111111 = Points to byte 65,535 of the destination

•

000000000000001 = Points to byte 1 of the destination

0000000000000000 = Points to byte 0 of the destination

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	———	———	———
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	———	———	———
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	CHCSIZ<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CHCSIZ<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits

11111111111111111 = 65,535 bytes transferred on an event

•

000000000000010 = 2 bytes transferred on an event

0000000000000001= 1 byte transferred on an event

0000000000000000 = 65,536 bytes transferred on an event

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	—— —	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	—— —	—— — — — —
15:8	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
15:8	CHCPTR<15:8>
7:0	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
7:0	CHCPTR<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 CHCPTR<15:0>: Channel Cell Progress Pointer bits

1111111111111111 = 65,535 bytes have been transferred since the last event

•

000000000000001 = 1 byte has been transferred since the last event

0000000000000000 = 0 bytes have been transferred since the last event

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	CHPDAT<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CHPDAT<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 CHPDAT<15:0>: Channel Data Register bits

Pattern Terminate mode:

Data to be matched must be stored in this register to allow terminate on match.

All other modes:

Unused.

NOTES:

11.0 HI-SPEED USB WITH ON-THE-GO (OTG)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 51. "Hi-Speed USB with On-The-Go (OTG)" (DS60001232), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 embedded host, device, or OTG implementation with a minimum of external components.

The module supports Hi-Speed, Full-Speed, or Low-Speed in any of the operating modes. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller.

The USB module consists of the RAM controller, packet encode/decode, UTM synchronization, endpoint control, a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 11-1.

Note: To avoid cache coherency problems on devices with L1 cache, USB buffers must only be allocated or accessed from the KSEG1 segment.

The USB module includes the following features:

USB Hi-Speed, Full-Speed, and Low-Speed support for host and device
USB OTG support with one or more Hi-Speed, Full-Speed, or Low-Speed device
Integrated signaling resistors
Integrated analog comparators for V BUS monitoring
Integrated USB transceiver
Transaction handshaking performed by hardware
Integrated 8-channel DMA to access system RAM and Flash
Seven transmit endpoints and seven receive endpoints, in addition to Endpoint 0
Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) support
Suspend and resume signaling support
• Dynamic FIFO sizing
Integrated RAM for the FIFOs, eliminating the need for system RAM for the FIFOs
Link power management support

Note 1: The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations.

2: If the USB module is used, the Primary Oscillator (POSC) is limited to either 12 MHz or 24 MHz.

FIGURE 11-1: PIC32MZ EC FAMILY USB INTERFACE DIAGRAM
Microchip PIC32MZ1024ECM124 - HI-SPEED USB WITH ON-THE-GO (OTG) - 1

flowchart

graph TD
    A["USB PLL"] -->|UPLLEN| B["Endpoint Control"]
    A -->|UPLL FSEL| B
    B --> C["Combine Endpoints"]
    C --> D["EP0 Control Host"]
    C --> E["EPO Control Function"]
    C --> F["EP1 - EP7 Control"]
    D --> G["Transmit"]
    D --> H["Receive"]
    E --> I["Host Transaction Scheduler"]
    F --> I
    I --> J["Interrupt Control"]
    J --> K["EP Reg Decoder"]
    J --> L["Common Regs"]
    J --> M["Cycle Control"]
    M --> N["FIFO Decoder"]
    O["USB 2.0 HS PHY"] --> P["UTM Synchronization"]
    P --> Q["Data Sync"]
    P --> R["HS Negotiation"]
    P --> S["HNP/SRP"]
    P --> T["Timers"]
    U["Link Power Management"] --> V["Packet Encode/Decode"]
    V --> W["Packet Encode"]
    V --> X["Packet Decode"]
    V --> Y["CRC Gen/Check"]
    W --> Z["RX Buff"]
    W --> AA["RX Buff"]
    W --> AB["TX Buff"]
    W --> AC["TX Buff"]
    W --> AD["Cycle Control"]
    AD --> AE["RAM"]
    AF["DMA Requests"] --> J
    AG["Interrupts"] --> J
    AH["System Bus Slave mode"] --> AI

11.1 USB OTG Control Registers

TABLE 11-1: USB REGISTER MAP

Virtual Address

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

USBCSR0

31:16

—

EP7TXIF

EP6TXIF

EP5TXIF

EP4TXIF

EP3TXIF

EP2TXIF

EP1TXIF

EP0IF

3000

15:0

ISOUPD^(1)

SOFT CONN(1)

HSEN

HSMODE

RESET

RESUME

SUSP MODE

SUSPEN

—

FUNC<6:0> (1)

2000

_(2)

3004

USBCSR1

31:16

—

EP7TXIE

EP6TXIE

EP5TXIE

EP4TXIE

EP3TXIE

EP2TXIE

EP1TXIE

EP0IE

3005

15:0

—

EP7RXIF

EP5RXIF

EP4RXIF

EP3RXIF

EP2RXIF

EP1RXIF

—

3000

3008

USBCSR2

31:16

VBUSIE

SESSRQIE

DISCONIE

CONNIE

SOFIE

RESETIE

RESUMEIE

SUSPIE

VBUSIF

SESSREQIF

DISCONIF

CONNIF

SOFIF

RESETIF

RESUMEIF

SUSPIF

3000

15:0

—

EP7RXIE

EP6RXIE

EP5RXIE

EP4RXIE

EP3RXIE

EP2RXIE

EP1RXIE

—

3000

300C

USBCSR3

31:16

FORCEHST

FIFOACC

FORCEFS

FORCEHS

PACKET

TESTK

TESTJ

NAK

—

ENDPOINT<3:0>

3000

15:0

—

RFRMNUM<10:0>

3000

3010

USB IE0CSR0 (3)

31:16

—

_(1)

FLSHFIFO

SVC SETEND(1)

SVCRPR(1)

SEND STALL(1)

SETUP END(1)

DATAEND(1)

SENT STALL(1)

TXPKT RDY

RXPKT RDY

3000

DISPING(2)

DTWREN(2)

DATA TGGL(2)

NAK TMOUT(2)

STATPKT(2)

REQPKT(2)

ERROR(2)

SETUP PKT(2)

RXSTALL(2)

3000

15:0

—

3000

3018

USB IE0CSR2 (3)

31:16

—

NAKLIM<4:0> (2)

SPEED<1.0> (2)

—

3000

15:0

—

3000

301C

USB IE0CSR3 (3)

31:16

MPRXEN

MPTXEN

BIGEND

HBRXEN

HBTXEN

DYNFIOS

SOFTCONE

UTMIDWID

—

2x00

15:0

—

3000

3010

USB IENCSR0(4)

31:16

AUTOSET

ISO(1)

MODE

DMA REQEN

FRC DATTG

DMA REQMD

_(1)

INCOMP TX(1)

CLRDT

SENT STALL(1)

SEND STALL(1)

FLUSH

UNDER RUN(1)

FIFONE

TXPKT RDY

3000

—

DTWREN(2)

DATA TGGL(2)

NAK TMOUT(2)

RXSTALL(2)

SETUPPKT(2)

ERROR(2)

3000

15:0

MULT<4:0>

TXMAXP<10:0>

3000

3014

USB IENCSR1(4)

31:16

AUTOCLR

ISO(1)

DMA REQEN

DISNYET(1)

DMA REQMD

_(1)

INCOM PRX

CLRDT

SENTSTALL(1)

SENDSTALL(1)

FLUSH

DATAERR(1)

OVERRUN(1)

FIFOFULL

RXPKT RDY

3000

AUTOIRQ(2)

PIDERIF(2)

DATA TWEN(2)

DATA TGGL(2)

RXSTALL(2)

REQPKT(2)

DERR-NAKT(1)

ERROR(2)

3000

15:0

MULT<4:0>

RXMAXP<10:0>

3000

3018

USB IENCSR2(4)

31:16

TXINTERV<7:0> (2)

SPEED<1.0> (2)

PROTOCOL<1:0>

TEP<3:0>

3000

15:0

—

3000

301C

USB IENCSR9(3)

31:16

RXFIFOSZ<3:0>

TXFIFOSZ<3:0>

—

3000

15:0

RXINTERV<7:0>

SPEED<1:0>

PROTOCOL<1:0>

TEP<3:0>

3000

3020

USB FIFO0

31:16

DATA<31:16>

3000

15:0

DATA<15:0>

3000

3024

USB FIFO1

31:16

DATA<31:16>

3000

15:0

DATA<15:0>

3000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note
1: Device mode
2: Host mode
3: Definition for Endpoint 0 (ENDPOINT<3:0>/USBCSB<19:16>) = 0)
4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).

TABLE 11-1: USB REGISTER MAP (CONTINUED)

Virtual Address	Register Name	Bit Range	Bits																All Resets
Virtual Address	Register Name	Bit Range	31/15	30/14	29/13	26/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
3028	USB FIFO2	31:16	DATA<31:16> 0000
3028	USB FIFO2	15:0	DATA<15:0> 0000
302C	USB FIFO3	31:16	DATA<31:16> 0000
302C	USB FIFO3	15:0	DATA<15:0> 0000
3030	USB FIFO4	31:16	DATA<31:16> 0000
3030	USB FIFO4	15:0	DATA<15:0> 0000
3034	USB FIFO5	31:16	DATA<31:16> 0000
3034	USB FIFO5	15:0	DATA<15:0> 0000
3038	USB FIFO6	31:16	DATA<31:16> 0000
3038	USB FIFO6	15:0	DATA<15:0> 0000
303C	USB FIFO7	31:16	DATA<31:16> 0000
303C	USB FIFO7	15:0	DATA<15:0> 0000
3060	USBOTG	31:16	—	—	—	RXDPB	RXFIFOSZ<3:0>				—	—	—	TXDPB	TXFIFOSZ<3:0>				2000
3060	USBOTG	15:0	—	—	—	—	—	—	TXEDMA	RXEDMA	BDEV	FSDEV	LSDEV	VBUS<1:0>	HOSTMODE	HOSTREQ	SESSION	2000
3064	USB FFOA	31:16	—	—	—	RXFIFOAD<12:0>													2000
3064	USB FFOA	15:0	—	—	—	TXFIFOAD<12:0>													2000
306C	USB HWVER	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	2000
306C	USB HWVER	15:0	RC	VERMAJOR<4:0>					VERMINOR<9:0>										2000
3078	USB INFO	31:16	VPLEN<7:0>								WTCON<3:0>				WTID<3:0>				2000
3078	USB INFO	15:0	DMACHANS<3:0>				RAMBITS<3:0>				RXENDPTS<3:0>				TXENDPTS<3:0>				8:37
307C	USB EOFRST	31:16	—	—	—	—	—	—	NRSTX	NRST	LSEOF<7:0>								2000
307C	USB EOFRST	15:0	FSEOF<7:0>								HSEOF<7:0>								1730
3080	USB EOTXA	31:16	—	TXHUBPRT<5:0>							MULTTRAN	TXHUBADD<6:0>							2000
3080	USB EOTXA	15:0	—	—	—	—	—	—	—	—	—	TXFADDR<6:0>							2000
3084	USB EORXA	31:16	—	RXHUBPRT<6:0>							MULTTRAN	RXHUBADD<6:0>							2000
3084	USB EORXA	15:0	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	2000
3088	USB EITXA	31:16	—	TXHUBPRT<5:0>							MULTTRAN	TXHUBADD<6:0>							2000
		15:0	—	—	—	—	—	—	—	—	—	TXFADDR<6:0>							2000
		31:16	—	RXHUBPRT<6:0>							MULTTRAN	RXHUBADD<6:0>							2000
308C	USB EIRXA	15:0	—	—	—	—	—	—	—	—	—	RXFADDR<6:0>							2000
		31:16	—	TXHUBPRT<6:0>							MULTTRAN	TXHUBADD<6:0>							2000
		15:0	—	—	—	—	—	—	—	—	—	TXFADDR<6:0>							2000
3090	USB E2TXA	31:16	—	RXHUBPRT<6:0>							MULTTRAN	RXHUBADD<6:0>							2000
3090	USB E2TXA	15:0	—	—	—	—	—	—	—	—	—	RXFADDR<6:0>							2000
3094	USB E2RXA	31:16	—	TXHUBPRT<6:0>							MULTTRAN	TXHUBADD<6:0>							2000
3094	USB E2RXA	15:0	—	—	—	—	—	—	—	—	—	TXFADDR<6:0>							2000
2098	USB E3TXA	31:16	—	TXHUBPRT<6:0>							MULTTRAN	TXHUBADD<6:0>							2000
2098	USB E3TXA	15:0	—	—	—	—	—	—	—	—	—	TXFADDR<6:0>							2000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Resel values are shown in hexadecimal.

Note 1: Device mode

2: Host mode.

3: Definition for Endpoint 0 (ENDPOINT<3:0> {USBCSR<19:16>} = 0).

4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).

TABLE 11-1: USB REGISTER MAP (CONTINUED)

Virtual Address	Register Name	Bit Range	Bits																All Resets
Virtual Address	Register Name	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
309C	USB E3RXA	31:16	—	RXHUBPRT<6.0>							MULTTRAN	RXHUBADD<6.0>							2000
309C	USB E3RXA	15:0	—	—	—	—	—	—	—	—	—	—	RXFADDR<6.0>						2000
30A0	US BE4TXA	31:16	—	TXHUBPRT<6.0>							MULTTRAN	TXHUBADD<6.0>							2000
30A0	US BE4TXA	15:0	—	—	—	—	—	—	—	—	—	—	TXFADDR<6.0>						2000
30A4	USB E4RXA	31:16	—	RXHUBPRT<6.0>							MULTTRAN	RXHUBADD<6.0>							2000
30A4	USB E4RXA	15:0	—	—	—	—	—	—	—	—	—	—	RXFADDR<6.0>						2000.
30AB	USB E5TXA	31:16	—	TXHUBPRT<6.0>							MULTTRAN	TXHUBADD<6.0>							2000
30AB	USB E5TXA	15:0	—	—	—	—	—	—	—	—	—	—	TXFADDR<6.0>						2000.
30AC	USB E5RXA	31:16	—	RXHUBPRT<6.0>							MULTTRAN	RXHUBADD<6.0>							2000
30AC	USB E5RXA	15:0	—	—	—	—	—	—	—	—	—	—	RXFADDR<6.0>						2000 .
30B0	USB E6TXA	31:16	—	TXHUBPRT<6.0>							MULTTRAN	TXHUBADD<6.0>							2000
30B0	USB E6TXA	15:0	—	—	—	—	—	—	—	—	—	—	TXFADDR<6.0>						2000 .
30B4	USB E6RXA	31:16	—	RXHUBPRT<6.0>							MULTTRAN	RXHUBADD<6.0>							2000
30B4	USB E6RXA	15:0	—	—	—	—	—	—	—	—	—	—	RXFADDR<6.0>						2000 2
30B8	USB E7TXA	31:16	—	TXHUBPRT<6.0>							MULTTRAN	TXHUBADD<6.0>							2000
30B8	USB E7TXA	15:0	—	—	—	—	—	—	—	—	—	—	TXFADDR<6.0>						2000 2
30BC	USB E7RXA	31:16	—	RXHUBPRT<6.0>							MULTTRAN	RXHUBADD<6.0>							2000
30BC	USB E7RXA	15:0	—	—	—	—	—	—	—	—	—	—	RXFADDR<6.0>						2000 -
3100	USB E0CSR0	31:16	Indexed by the same bits in USBIE0CSR0																2000
3100	USB E0CSR0	15:0	Indexed by the same bits in USBIE0CSR0																2000 -
3106	USB E0CSR2	31:16	Indexed by the same bits in USBIE0CSR2																2000
3106	USB E0CSR2	15:0	Indexed by the same bits in USBIE0CSR2																2000 -
310C	USB E0CSR3	31:16	Indexed by the same bits in USBIE0CSR3																2000
310C	USB E0CSR3	15:0	Indexed by the same bits in USBIE0CSR3																2000 -
3110	USB E1CSR0	31:16	Indexed by the same bits in USBIE1CSR0																2000
3110	USB E1CSR0	15:0	Indexed by the same bits in USBIE1CSR0																2000 -
3114	USB E1CSR1	31:16	Indexed by the same bits in USBIE1CSR1																2000
3114	USB E1CSR1	15:0	Indexed by the same bits in USBIE1CSR1																2000 -
3118	USB E1CSR2	31:16	Indexed by the same bits in USBIE1CSR2																2000
3118	USB E1CSR2	15:0	Indexed by the same bits in USBIE1CSR2																2000 -
311C	USB E1CSR3	31:16	Indexed by the same bits in USBIE1CSR3																2000
311C	USB E1CSR3	15:0	Indexed by the same bits in USBIE1CSR3																2000 -
3129	USB E2CSR0	31:16	Indexed by the same bits in USBIE2CSR0																2000
3129	USB E2CSR0	15:0	Indexed by the same bits in USBIE2CSR0																2000 -
3124	USB E2CSR1	31:16	Indexed by the same bits in USBIE2CSR1																2000
3124	USB E2CSR1	15:0	Indexed by the same bits in USBIE2CSR1																2000 -

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note
1:
2: Host mode
3: Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSB<19:16>) = 0)
4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7)

TABLE 11-1: USB REGISTER MAP (CONTINUED)

Virtual Address

Bit Range

Bits

All Resets

31/15

30/14

29/13

26/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

3128

USB E2CSR2

31:16

Indexed by the same bits in USBIE2CSR2

C000

15:0

C00

312C

USB E2CSR3

31:16

Indexed by the same bits in USBIE2CSR3

C000

15:0

C00

3130

USB E3CSR0

31:16

Indexed by the same bits in USBIE3CSR0

C000

15:0

C00

3134

USB E3CSR1

31:16

Indexed by the same bits in USBIE3CSR1

C000

15:0

C00

3138

USB E3CSR2

31:16

Indexed by the same bits in USBIE3CSR2

C000

15:0

C00

313C

USB E3CSR3

31:16

Indexed by the same bits in USBIE3CSR3

C000

15:0

C00

3140

USB E4CSR0

31:16

Indexed by the same bits in USBIE4CSR0

C000

15:0

C00

3144

USB E4CSR1

31:16

Indexed by the same bits in USBIE4CSR1

C000

15:0

C00

3148

USB E4CSR2

31:16

Indexed by the same bits in USBIE4CSR2

C000

15:0

C00

314C

USB E4CSR3

31:16

Indexed by the same bits in USBIE4CSR3

C000

15:0

C00

3150

USB E5CSR0

31:16

Indexed by the same bits in USBIE5CSR0

C000

15:0

C00

3154

USB E6CSR1

31:16

Indexed by the same bits in USBIE5CSR1

C000

15:0

C00

3158

USB E5CSR2

31:16

Indexed by the same bits in USBIE5CSR2

C000

15:0

C00

315C

USB E6CSR3

31:16

Indexed by the same bits in USBIE5CSR3

C000

15:0

C00

3160

USB E6CSR0

31:16

Indexed by the same bits in USBIE6CSR0

C000

15:0

C00

3164

USB E6CSR1

31:16

Indexed by the same bits in USBIE6CSR1

C000

15:0

C00

3168

USB E6CSR2

31:16

Indexed by the same bits in USBIE6CSR2

C000

15:0

C00

316C

USB E6CSR3

31:16

Indexed by the same bits in USBIE6CSR3

C000

15:0

C00

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Resel values are shown in hexadecimal.

1: Device mode

2: Host mode.

3: Definition for Endpoint 0 (ENDPOINT<3:0> {USBCSR<19:16>} = 0).

4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).

TABLE 11-1: USB REGISTER MAP (CONTINUED)

Virtual Address	Register Name	Bit Range	Bits																All Resets
Virtual Address	Register Name	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
3170	USB E7CSR0	31:16	Indexed by the same bits in USBIE7CSR0																C000
3170	USB E7CSR0	15:0	C00
3174	USB E7CSR1	31:16	Indexed by the same bits in USBIE7CSR1																C000
3174	USB E7CSR1	15:0	C00
3178	USB E7CSR2	31:16	Indexed by the same bits in USBIE7CSR2																C000
3178	USB E7CSR2	15:0	C00
317C	USB E7CSR3	31:16	Indexed by the same bits in USBIE7CSR3																C000
317C	USB E7CSR3	15:0	C00
3200	USB DMAINT	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	C000
3200	USB DMAINT	15:0	—	—	—	—	—	—	—	—	DMABIF	DMA7IF	DMA8IF	DMA9IF	DMA4IF	DMA3IF	DMA2IF	DMA1IF	C000
3204	USB DMA1C	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	C000
3204	USB DMA1C	15:0	—	—	—	—	—	DMABRSTM<1.0>		DMAERR	DMAEP<3.0>				DMAIE	DMAMODE	DMADIR	DMAEN	C000
3208	USB DMA1A	31:16	DMAADDR<31:16>																C000
3208	USB DMA1A	15:0	DMAADDR<15.0>																C000
320C	USB DMAIN	31:16	DMACOUNT<31:16>																C000
320C	USB DMAIN	15:0	DMACOUNT<15.0>																C000
3214	USB DMA2C	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	C000
3214	USB DMA2C	15:0	—	—	—	—	—	DMABRSTM<1.0>		DMAERR	DMAEP<3.0>				DMAIE	DMAMODE	DMADIR	DMAEN	C000
3218	USB DMA2A	31:16	DMAADDR<31:16>																C000
3218	USB DMA2A	15:0	DMAADDR<15.0>																C000
321C	USB DMA2N	31:16	DMACOUNT<31:16>																C000
321C	USB DMA2N	15:0	DMACOUNT<15.0>																C000
3224	USB DMA3C	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	C000
3224	USB DMA3C	15:0	—	—	—	—	—	DMABRSTM<1.0>		DMAERR	DMAEP<3.0>				DMAIE	DMAMODE	DMADIR	DNAEN	C000
3228	USB DMA3A	31:16	DMAADDR<31:16>																C000
3228	USB DMA3A	15:0	DMAADDR<15.0>																C000
322C	USB DMA3N	31:16	DMACOUNT<31:16>																C000
322C	USB DMA3N	15:0	DMACOUNT<15.0>																C000
3234	USB DMA4C	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	C000
3234	USB DMA4C	15:0	—	—	—	—	—	DMABRSTM<1.0>		DMAERR	DMAEP<3.0>				DMAIE	DMAMODE	DMADIR	DAENA	C000
3238	USB DMA4A	31:16	DMAADDR<31:16>																C000
3238	USB DMA4A	15:0	DMAADDR<15.0>																C000
323C	USB DMA4N	31:16	DMACOUNT<31:16>																C000
323C	USB DMA4N	15:0	DMACOUNT<15.0>																C000
3244	USB DMA5C	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	C000
3244	USB DMA5C	15:0	—	—	—	—	—	DMABRSTM<1.0>		DMAERR	DMAEP<3.0>				DMAIE	DMAMODE	DMADIR	DLAENA	C000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note
1:
2: Host mode
3: Definition for Endpoint 0 (ENDPOINT<3:0> / USB/CSB<19:16>) = 0)
4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).

TABLE 11-1: USB REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Resel values are shown in hexadecimal.

Note 1: Device mode

2: Host mode.

3: Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:15>) = 0).

4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7)

TABLE 11-1: USB REGISTER MAP (CONTINUED)

Virtual Address	Register Name	Bit Range	Bits																All Resets
Virtual Address	Register Name	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
3340	USB DP8FD	31:16	—	—	—	—	—	—	—	—	EP7TXD	EP6TXD	EP5TXD	EP4TXD	EP3TXD	EP2TXD	EP1TXD	—	0000
3340	USB DP8FD	15:0	—	—	—	—	—	—	—	—	EP7RXD	EP6RXD	EP5RXD	EP4RXD	EP3RXD	EP2RXD	EP1RXD	—	0000
3344	USB TMCON1	31:16	THHSRTN<15:0>																0506
3344	USB TMCON1	15:0	TUCH<15:0>																4074
3348	USB TMCON2	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
3348	USB TMCON2	15:0	—	—	—	—	—	—	—	—	—	—	—	—	THSBT<3:0>				0000
3360	USB LPMRI	31:16	—		LPM ERRIE	LPM RESIE	LPMACKIE	LPMNYIE	LPMSTIE	LPMTOIE	—	—	—	LPMNAK(1)—(2)	LPMEN<1.0>		LPMRES	LPMXMT	000000000
3360	USB LPMRI	15:0	ENDPOINT<3:0>				—	—	—	RMTWAK	HIRD<3:0>				LNKSTATE<3:0>				0000
3364	USB LMPR2	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
3364	USB LMPR2	15:0	LPMFADDR<6:0>								—	—	LPMERR(1)—(2)	LPMRES	LPMNC	LPMACK	LPMNY	LPMST	00000000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: Device mode
2: Host mode
3: Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSB<19:16>) = 0)
4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0 U-0 U-0 U-0		U-0
31:24	— — —	— — —	—	—
23:16	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS
23:16	EP7TXIF	EP6TXIF	EP5TXIF	EP4TXIF	EP3TXIF	EP2TXIF	EP1TXIF	EP0IF
15:8	R/W-0	R/W-0	R/W-1	R-0, HS	R-0	R/W-0	R-0, HC	R/W-0
	ISOUPD	SOFTCONN	HSEN	HSMODE	RESET	RESUME	SUSPMODE	SUSPEN
	—	—	HSEN	HSMODE	RESET	RESUME	SUSPMODE	SUSPEN
7:0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
	—	FUNC<6:0>
	—	— —	— —	—	—	—

Legend:	HS = Hardware Settable HC = Hardware Clearable
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-24 Unimplemented: Read as '0'

bit 23-17 EP7TXIF:EP1TXIF: Endpoint 'n' TX Interrupt Flag bit

1 = Endpoint has a transmit interrupt to be serviced
0 = No interrupt event

bit 16 EP0IF: Endpoint 0 Interrupt bit

1 = Endpoint 0 has an interrupt to be serviced
0 = No interrupt event

All EPxTX and EP0 bits are cleared when the byte is read. Therefore, these bits must be read independently from the remaining bits in this register to avoid accidental clearing.

bit 15 ISOUPD: ISO Update bit (Device mode only; unimplemented in Host mode)

1 = USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet
0 = No change in behavior

This bit only affects endpoints performing isochronous transfers when in Device mode. This bit is unimplemented in Host mode.

bit 14 SOFTCONN: Soft Connect/Disconnect Feature Selection bit

1 = The USB D+/D- lines are enabled and active
0 = The USB D+/D- lines are disabled and are tri-stated

This bit is only available in Device mode.

bit 13 HSEN: Hi-Speed Enable bit

1 = The USB module will negotiate for Hi-Speed mode when the device is reset by the hub
0 = Module only operates in Full-Speed mode

bit 12 HSMODE: Hi-Speed Mode Status bit

1 = Hi-Speed mode successfully negotiated during USB reset
0 = Module is not in Hi-Speed mode

In Device mode, this bit becomes valid when a USB reset completes. In Host mode, it becomes valid when the RESET bit is cleared.

bit 11 RESET: Module Reset Status bit

1 = Reset signaling is present on the bus
0 = Normal module operation

In Device mode, this bit is read-only. In Host mode, this bit is read/write.

REGISTER 11-1: USBCSR0: USB CONTROL STATUS REGISTER 0 (CONTINUED)

bit 10 RESUME: Resume from Suspend control bit

1 = Generate Resume signaling when the device is in Suspend mode
0 = Stop Resume signaling

In Device mode, the software should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, the software should clear this bit after 20 ms.

bit 9 SUSPMODE: Suspend Mode status bit

1 = The USB module is in Suspend mode
0 = The USB module is in Normal operations

This bit is read-only in Device mode. In Host mode, it can be set by software, and is cleared by hardware.

bit 8 SUSPEN: Suspend Mode Enable bit

1 = Suspend mode is enabled
0 = Suspend mode is not enabled

bit 7 Unimplemented: Read as '0'

bit 6-0 FUNC<6:0>: Device Function Address bits

These bits are only available in Device mode. This field is written with the address received through a SET_ADDRESS command, which will then be used for decoding the function address in subsequent token packets.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24	— — —	— — — — —
23:16	R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1			R/W-0
23:16	EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE
15:8	U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8	— — —	— — — — —
7:0	R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS U-0
7:0	EP7RXIF EP6RXIF EP5RXIF EP4RXIF EP3RXIF EP2RXIF EP1RXIF —

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as '0'

bit 23-17 EP7TXIE:EP1TXIE: Endpoint 'n' Transmit Interrupt Enable bits

1 = Endpoint Transmit interrupt events are enabled
0 = Endpoint Transmit interrupt events are not enabled

bit 16 EPOIE: Endpoint 0 Interrupt Enable bit

1 = Endpoint 0 interrupt events are enabled
0 = Endpoint 0 interrupt events are not enabled

bit 15-8 Unimplemented: Read as '0'

bit 7-1 EP7RXIF:EP1RXIF: Endpoint 'n' RX Interrupt bit

1 = Endpoint has a receive event to be serviced
0 = No interrupt event

bit 0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-1 R/W-1	R/W-0
31:24	VBUSERRIE	SESSRQIE D	ISCONIE CONNIE SOFIE		RESETIE RESUMEIE SUSPIE
23:16	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS	R-0, HS
23:16	VBUSERRIF	SESSRQIF	DISCONIF	CONNIF	SOFIF	RESETIF	RESUMEIF	SUSPIF
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	—	—	—	—	—	—	—	—
7:0	R/W-1 R/W-1	R/W-1 R/W-1 R	W-1 R/W-1 R/W-1	U-0
7:0	EP7RXIE	EP6RXIE	EP5RXIE	EP4RXIE	EP3RXIE	EP2RXIE	EP1RXIE	—

Legend:	HS = Hardware Settable
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 VBUSERRIE: VBUS Error Interrupt Enable bit

1 = VBUS error interrupt is enabled
0 = VBUS error interrupt is disabled

bit 30 SESSRQIE: Session Request Interrupt Enable bit

1 = Session request interrupt is enabled
0 = Session request interrupt is disabled

bit 29 DISCONIE: Device Disconnect Interrupt Enable bit

1 = Device disconnect interrupt is enabled
0 = Device disconnect interrupt is disabled

bit 28 CONNIE: Device Connection Interrupt Enable bit

1 = Device connection interrupt is enabled
0 = Device connection interrupt is disabled

bit 27 SOFIE: Start of Frame Interrupt Enable bit

1 = Start of Frame event interrupt is enabled
0 = Start of Frame event interrupt is disabled

bit 26 RESETIE: Reset/Babble Interrupt Enable bit

1 = Interrupt when reset (Device mode) or Babble (Host mode) is enabled
0 = Reset/Babble interrupt is disabled

bit 25 RESUMEIE: Resume Interrupt Enable bit

1 = Resume signaling interrupt is enabled
0 = Resume signaling interrupt is disabled

bit 24 SUSPIE: Suspend Interrupt Enable bit

1 = Suspend signaling interrupt is enabled
0 = Suspend signaling interrupt is disabled

bit 23 VBUSERRIF: V BUS Error Interrupt bit

1 = VBUS has dropped below the VBUS valid threshold during a session
0 = No interrupt

bit 22 SESSRQIF: Session Request Interrupt bit

1 = Session request signaling has been detected
0 = No session request detected

bit 21 DISCONIF: Device Disconnect Interrupt bit

1 = In Host mode, indicates when a device disconnect is detected. In Device mode, indicates when a session ends.
0 = No device disconnect detected

bit 20 CONNIF: Device Connection Interrupt bit

1 = In Host mode, indicates when a device connection is detected
0 = No device connection detected

REGISTER 11-3: USBCSR2: USB CONTROL STATUS REGISTER 2 (CONTINUED)

bit 19 SOFIF: Start of Frame Interrupt bit

1 = A new frame has started
0 = No start of frame detected

bit 18 RESETIF: Reset/Babble Interrupt bit

1 = In Host mode, indicates babble is detected. In Device mode, indicates reset signaling is detected on the bus.
0 = No reset/babble detected

bit 17 RESUMEIF: Resume Interrupt bit

1 = Resume signaling is detected on the bus while USB module is in Suspend mode
0 = No Resume signaling detected

bit 16 SUSPIF: Suspend Interrupt bit

1 = Suspend signaling is detected on the bus (Device mode)
0 = No suspend signaling detected

bit 15-8 Unimplemented: Read as '0'

bit 7-1 EP7RXIE:EP1RXIE: Endpoint 'n' Receive Interrupt Enable bit

1 = Receive interrupt is enabled for this endpoint
0 = Receive interrupt is not enabled

bit 0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24	FORCEHST FIFOACC FORCEFS FORCEHS PACKET TESTK TESTJ NAK
23:16	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	—	—	—	—	ENDPOINT<3:0>
15:8	U-0	U-0	U-0	U-0	U-0	R-0	R-0	R-0
15:8	—	—	—	—	—	RFRMUM<10:8>
7:0	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
7:0	RFRMNUM<7:0>

Legend:	HC = Hardware Cleared
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31 FORCEHST: Test Mode Force Host Select bit

1 = Forces USB module into Host mode, regardless of whether it is connected to any peripheral
0 = Normal operation

bit 30 FIFOACC: Test Mode Endpoint 0 FIFO Transfer Force bit

1 = Transfers the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO
0 = No transfer

bit 29 FORCEFS: Test mode Force Full-Speed Mode Select bit

This bit is only active if FORCEHST = 1.

1 = Forces USB module into Full-Speed mode. Undefined behavior if FORCEHS = 1.
0 = If FORCEHS = 0, places USB module into Low-Speed mode.

bit 28 FORCEHS: Test mode Force Hi-Speed Mode Select bit

This bit is only active if FORCEHST = 1.

1 = Forces USB module into Hi-Speed mode. Undefined behavior if FORCEFS = 1.
0 = If FORCEFS = 0, places USB module into Low-Speed mode.

bit 27 PACKET: Test Packet Test Mode Select bit

This bit is only active if module is in Hi-Speed mode.

1 = The USB module repetitively transmits on the bus a 53-byte test packet. Test packet must be loaded into the Endpoint 0 FIFO before the test mode is entered.
0 = Normal operation

bit 26 TESTK: Test_K Test Mode Select bit

1 = Enters Test_K test mode. The USB module transmits a continuous K on the bus.
0 = Normal operation

This bit is only active if the USB module is in Hi-Speed mode.

bit 25 TESTJ: Test_J Test Mode Select bit

1 = Enters Test_J test mode. The USB module transmits a continuous J on the bus.
0 = Normal operation

This bit is only active if the USB module is in Hi-Speed mode.

bit 24 NAK: Test SEO NAK Test Mode Select bit

1 = Enter Test_SE0_NAK test mode. The USB module remains in Hi-Speed mode but responds to any valid IN token with a NAK
0 = Normal operation
This mode is only active if module is in Hi-Speed mode.

bit 23-20 Unimplemented: Read as '0'

REGISTER 11-4: USBCSR3: USB CONTROL STATUS REGISTER 3 (CONTINUED)
bit 19-16 ENDPOINT<3:0>: Endpoint Registers Select bits 1111 = Reserved . . . 1000 = Reserved 0111 = Endpoint 7 . . 0000 = Endpoint 0 These bits select which endpoint registers are accessed through addresses 3010-301F. bit 15-11 Unimplemented: Read as '0' bit 10-0 RFRMNUM<10:0>: Last Received Frame Number bits

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 R/W-0 R/	W-0, HC R/W-0 R/	W-0, HC
	— — —	—			— — —			FLSHFIFO
	— — —	—			DISPING	DTWREN	DATATGGL	FLSHFIFO
23:16	R/W-0, HC	R/W-0, HC	R/W-0, HC	R/C-0, HS	R/W-0, HS	R-0, HS	R-0	R-0
	SVCSETEND	SVCRPR	SENDSTALL	SETUPEND	DATAEND	SENTSTALL	TXPKTRDY	RXPKTRDY
	NAKTMOUT	STATPKT	REQPKT	ERROR	SETUPPKT	RXSTALL	TXPKTRDY	RXPKTRDY
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	— — —	—	—	—	— —
7:0	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
7:0	— — —	—	—	—	— —

Legend:	HC = Hardware Cleared	HS = Hardware Set
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-28 Unimplemented: Read as '0'

bit 27 DISPING: Disable Ping tokens control bit (Host mode)

1 = USB Module will not issue PING tokens in data and status phases of a Hi-Speed Control transfer
0 = Ping tokens are issued

bit 26 DTWREN: Data Toggle Write Enable bit (Host mode)

1 = Enable the current state of the Endpoint 0 data toggle to be written. Automatically cleared.
0 = Disable data toggle write

bit 25 DATATGGL: Data Toggle bit (Host mode)

When read, this bit indicates the current state of the Endpoint 0 data toggle.

If DTWREN = 1, this bit is writable with the desired setting.

If DTWREN = 0, this bit is read-only.

bit 24 FLSHFIFO: Flush FIFO Control bit

1 = Flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared. Automatically cleared when the operation completes. Should only be used when TXPKTRDY/RXPKTRDY = 1.
0 = No Flush operation

bit 23 SVCSETEND: Clear SETUPEND Control bit (Device mode)

1 = Clear the SETUPEND bit in this register. This bit is automatically cleared.
0 = Do not clear

NAKTMOUT: NAK Time-out Control bit (Host mode)

1 = Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLIM<4:0> bits (USBICSR<28:24>)
0 = Allow the endpoint to continue

bit 22 SVCRPR: Serviced RXPKTRDY Clear Control bit (Device mode)

1 = Clear the RXPKTRDY bit in this register. This bit is automatically cleared.
0 = Do not clear

STATPKT: Status Stage Transaction Control bit (Host mode)

1 = When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction
0 = Do not perform a status stage transaction

REGISTER 11-5: USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 0) (CONTINUED)

bit 21 SENDSTALL: Send Stall Control bit (Device mode)

1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared.
0 = Do not send STALL handshake.

REQPKT: IN transaction Request Control bit (Host mode)

1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set.
0 = Do not request an IN transaction

bit 20 SETUP: Early Control Transaction End Status bit (Device mode)

1 = A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and the FIFO flushed at this time.
0 = Normal operation

This bit is cleared by writing a '1' to the SVCSETEND bit in this register.

ERROR: No Response Error Status bit (Host mode)

1 = Three attempts have been made to perform a transaction with no response from the peripheral. An interrupt is generated.
0 = Clear this flag. Software must write a '0' to this bit to clear it.

bit 19 DATAEND: End of Data Control bit (Device mode)

The software sets this bit when:

Setting TXPKTRDY for the last data packet
Clearing RXPKTRDY after unloading the last data packet
Setting TXPKTRDY for a zero length data packet

Hardware clears this bit.

SETUPPKT: Send a SETUP token Control bit (Host mode)

1 = When set at the same time as the TXPKTRDY bit is set, the module sends a SETUP token instead of an OUT token for the transaction
0 = Normal OUT token operation

Setting this bit also clears the Data Toggle.

bit 18 SENTSTALL: STALL sent status bit (Device mode)

1 = STALL handshake has been transmitted
0 = Software clear of bit

RXSTALL: STALL handshake received Status bit (Host mode)

1 = STALL handshake was received
0 = Software clear of bit

bit 17 TXPKTRDY: TX Packet Ready Control bit

1 = Data packet has been loaded into the FIFO. It is cleared automatically.
0 = No data packet is ready for transmit

bit 16 RXPKTRDY: RX Packet Ready Status bit

1 = Data packet has been received. Interrupt is generated (when enabled) when this bit is set.
0 = No data packet has been received

This bit is cleared by setting the SVCRPR bit.

bit 15-0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	0
31:24	— — —	NAKLIM<4:0>
23:16	R/W-0 R/W	0 U-0	U-0	U-0 U-0 U-0 U-0
23:16	SPEED<1:0>		—	—	— — —	—
15:8	U-0 U-0 U	0	U-0	U-0 U-0 U-0 U-0
15:8	— — —	—		— — — —
7:0	U-0 R-0 R	0	R-0	R-0 R-0 R-0 R-0
7:0	—	RXCNT<6:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28-24 NAKLIM<4:0>: Endpoint 0 NAK Limit bits

The number of frames/microframes (Hi-Speed transfers) after which Endpoint 0 should time-out on receiving a stream of NAK responses.

bit 23-22 SPEED<1:0>: Operating Speed Control bits

11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved

bit 21-7 Unimplemented: Read as '0'

bit 6-0 RXCNT<6:0>: Receive Count bits

The number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY is set.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-x R-x R-0	R-x R-x R-x R-1	R-0
31:24	MPRXEN	MPTXEN	BIGEND	HBRXEN	HBTXEN	DYNFIFOS	SOFTCONE	UTMIDWID
23:16	U-0	U-0 U-0 U-0	U-0 U-0		U-0 U-0
23:16	—	—	—	—	—	—	—	—
15:8	U-0	U-0 U-0	U-0 U-0		U-0 U-0
15:8	—	—	—	—	—	—	—	—
7:0	U-0	U-0 U-0	U-0 U-0		U-0 U-0
7:0	—	—	—	—	—	—	—	—

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 MPRXEN: Automatic Amalgamation Option bit

1 = Automatic amalgamation of bulk packets is done

0 = No automatic amalgamation

bit 30 MPTXEN: Automatic Splitting Option bit

1 = Automatic splitting of bulk packets is done

0 = No automatic splitting

bit 29 BIGEND: Byte Ordering Option bit

1 = Big Endian ordering

0 = Little Endian ordering

bit 28 HBRXEN: High-bandwidth RX ISO Option bit

1 = High-bandwidth RX ISO endpoint support is selected

0 = No High-bandwidth RX ISO support

bit 27 HBTXEN: High-bandwidth TX ISO Option bit

1 = High-bandwidth TX ISO endpoint support is selected

0 = No High-bandwidth TX ISO support

bit 26 DYNFIFOS: Dynamic FIFO Sizing Option bit

1 = Dynamic FIFO sizing is supported

0 = No Dynamic FIFO sizing

bit 25 SOFTCONE: Soft Connect/Disconnect Option bit

1 = Soft Connect/Disconnect is supported

0 = Soft Connect/Disconnect is not supported

bit 24 UTMIDWID: UTMI+ Data Width Option bit

Always '0', indicating 8-bit UTMI+ data width

bit 23-0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
	AUTOSET	ISO	MODE DM	MAREQEN FR	CDATTG DMA	AREQMD	—	—
	AUTOSET	—	MODE DM	MAREQEN FR	CDATTG DMA	AREQMD	DATAWEN	DATATGGL
23:16	R/W-0, HS	R/W-0, HC	R/W-0, HS	R/W-0	R/W-0	R/W-0, HS	R/W-0	R/W-0, HC
	INCOMPTX	CLRDT	SENTSTALL	SENDSTALL	FLUSH	UNDERRUN	FIFONE	TXPKTRDY
	NAKTMOUT	CLRDT	RXSTALL	SETUPPKT	FLUSH	ERROR	FIFONE	TXPKTRDY
15:8	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	MULT<4:0>					TXMAXP<10:8>
7:0	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	TXMAXP<7:0>

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 AUTOSET: Auto Set Control bit

1 = TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have to be set manually.

0 = TXPKTRDY must be set manually for all packet sizes

bit 30 ISO: Isochronous TX Endpoint Enable bit (Device mode)

1 = Enables the endpoint for Isochronous transfers

0 = Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers.

This bit only has an effect in Device mode. In Host mode, it always returns '0'.

bit 29 MODE: Endpoint Direction Control bit

1 = Endpoint is TX

0 = Endpoint is RX

This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions.

bit 28 DMAREQEN: Endpoint DMA Request Enable bit

1 = DMA requests are enabled for this endpoint

0 = DMA requests are disabled for this endpoint

bit 27 FRCDATTG: Force Endpoint Data Toggle Control bit

1 = Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received.

0 = No forced behavior

bit 26 DMAREQMD: Endpoint DMA Request Mode Control bit

1 = DMA Request Mode 1

0 = DMA Request Mode 0

This bit must not be cleared either before or in the same cycle as the above DMAREQEN bit is cleared.

bit 25 DATAWEN: Data Toggle Write Enable bit (Host mode)

1 = Enable the current state of the TX Endpoint data toggle (DATATGGL) to be written

0 = Disables writing the DATATGGL bit

bit 24 DATATGGL: Data Toggle Control bit (Host mode)

When read, this bit indicates the current state of the TX Endpoint data toggle. If DATAWEN = 1, this bit may be written with the required setting of the data toggle. If DATAWEN = 0, any value written to this bit is ignored.

REGISTER 11-8: USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) (CONTINUED)

bit 23 INCOMPTX: Incomplete TX Status bit (Device mode)

1 = For high-bandwidth Isochronous endpoint, a large packet has been split into two or three packets for transmission but insufficient IN tokens have been received to send all the parts
0 = Normal operation

In anything other than isochronous transfers, this bit will always return '0'.

NAKTMOUT: NAK Time-out status bit (Host mode)

1 = TX endpoint is halted following the receipt of NAK responses for longer than the NAKLIM setting
0 = Written by software to clear this bit

bit 22 CLRDT: Clear Data Toggle Control bit

1 = Resets the endpoint data toggle to '0'
0 = Do not clear the data toggle

bit 21 SENTSTALL: STALL handshake transmission status bit (Device mode)

1 = STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit is cleared.
0 = Written by software to clear this bit

RXSTALL: STALL receipt bit (Host mode)

1 = STALL handshake is received. Any DMA request in progress is stopped, the FIFO is completely flushed and the TXPKTRDY bit is cleared.
0 = Written by software to clear this bit

bit 20 SENDSTALL: STALL handshake transmission control bit (Device mode)

1 = Issue a STALL handshake to an IN token
0 = Terminate stall condition

This bit has no effect when the endpoint is being used for Isochronous transfers.

SETUPPKT: Definition bit (Host mode)

1 = When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token for the transaction. This also clears the Data Toggle.
0 = Normal OUT token for the transaction

bit 19 FLUSH: FIFO Flush control bit

1 = Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, TXPKTRDY is cleared and an interrupt is generated.
0 = Do not flush the FIFO

bit 18 UNDERRUN: Underrun status bit (Device mode)

1 = An IN token has been received when TXPKTRDY is not set.
0 = Written by software to clear this bit.

ERROR: Handshake failure status bit (Host mode)

1 = Three attempts have been made to send a packet and no handshake packet has been received
0 = Written by software to clear this bit.

bit 17 FIFONE: FIFO Not Empty status bit

1 = There is at least 1 packet in the TX FIFO
0 = TX FIFO is empty

bit 16 TXPKTRDY: TX Packet Ready Control bit

The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a double-buffered FIFO.

REGISTER 11-8: USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) (CONTINUED)

bit 15-11 MULT<4:0>: Multiplier Control bits

For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1 for the payload size.

For Bulk endpoints, MULT can be up to 32 and defines the number of "USB" packets of the specified payload into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required to be an exact multiple of the payload specified by TXMAXP.

For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe.

bit 10-0 TXMAXP<10:0>: Maximum TX Payload per transaction Control bits

This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Full-Speed and Hi-Speed operations.

TXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
	AUTOCLR	ISO	DMAREQEN DERR DATAT	DISNYET	DMAREQMD TGGL	—	—	INCOMPRX
	AUTOCLR	AUTORQ PI	DMAREQEN DERR DATAT	WEN DATA	DMAREQMD TGGL			INCOMPRX
23:16	R/W-0, HC	R/W-0, HS	R/W-0	R/W-0, HC	R-0, HS	R/W-0, HS	R-0, HSC	R/W-0, HS
	CLRDT	SENTSTALL	SENDSTALL	FLUSH	DATAERR	OVERRUN	FIFOFULL	RXPKTRDY
	CLRDT	RXSTALL	REQPKT	FLUSH	DERRNAKT	ERROR	FIFOFULL	RXPKTRDY
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	MULT<4:0>					RXMAXP<10:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	RXMAXP<7:0>

Legend:	HC = Hardware Clearable HS = Hardware Settable
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 AUTOCLR: RXPKTRDY Automatic Clear Control bit

1 = RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte chunks regardless of the RXMAXP.

0 = No automatic clearing of RXPKTRDY

This bit should not be set for high-bandwidth Isochronous endpoints.

bit 30 ISO: Isochronous Endpoint Control bit (Device mode)

1 = Enable the RX endpoint for Isochronous transfers

0 = Enable the RX endpoint for Bulk/Interrupt transfers

AUTORQ: Automatic Packet Request Control bit (Host mode)

1 = REQPKT will be automatically set when RXPKTRDY bit is cleared.

0 = No automatic packet request

This bit is automatically cleared when a short packet is received.

bit 29 DMAREQEN: DMA Request Enable Control bit

1 = Enable DMA requests for the RX endpoint.

0 = Disable DMA requests for the RX endpoint.

bit 28 DISNYET: Disable NYET Handshakes Control/PID Error Status bit (Device mode)

1 = In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX packets are ACKed including at the point at which the FIFO becomes full.

0 = Normal operation.

In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for all Interrupt endpoints.

PIDERR: PID Error Status bit (Host mode)

1 = In ISO transactions, this indicates a PID error in the received packet.

0 = No error

bit 27 DMAREQMD: DMA Request Mode Selection bit

1 = DMA Request Mode 1

0 = DMA Request Mode 0

REGISTER 11-9: USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) (CONTINUED)

bit 26 DATATWEN: Data Toggle Write Enable Control bit (Host mode)

1 = DATATGGL can be written

0 = DATATGGL is not writable

bit 25 DATATGGL: Data Toggle bit (Host mode)

When read, this bit indicates the current state of the endpoint data toggle.

If DATATWEN = 1, this bit may be written with the required setting of the data toggle.

If DATATWEN = 0, any value written to this bit is ignored.

bit 24 INCOMPRX: Incomplete Packet Status bit

1 = The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because parts of the data were not received

0 = Written by then software to clear this bit

In anything other than Isochronous transfer, this bit will always return '0'.

bit 23 CLRDT: Clear Data Toggle Control bit

1 = Reset the endpoint data toggle to '0'

0 = Leave endpoint data toggle alone

bit 22 SENTSTALL: STALL Handshake Status bit (Device mode)

1 = STALL handshake is transmitted

0 = Written by the software to clear this bit

RXSTALL: STALL Handshake Receive Status bit (Host mode)

1 = A STALL handshake has been received. An interrupt is generated.

0 = Written by the software to clear this bit

bit 21 SENDSTALL: STALL Handshake Control bit (Device mode)

1 = Issue a STALL handshake

0 = Terminate stall condition

REQPKT: IN Transaction Request Control bit (Host mode)

1 = Request an IN transaction.

0 = No request

This bit is cleared when RXPKTRDY is set.

bit 20 FLUSH: Flush FIFO Control bit

1 = Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is double-buffered, FLUSH may need to be set twice to completely clear the FIFO.

0 = Normal FIFO operation

This bit is automatically cleared.

bit 19 DATAERR: Data Packet Error Status bit (Device mode)

1 = The data packet has a CRC or bit-stuff error.

0 = No data error

This bit is cleared when RXPKTRDY is cleared. This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns '0'.

DERRNAKT: Data Error/NAK Time-out Status bit (Host mode)

1 = The data packet has a CRC or bit-stuff error. In Bulk mode, the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK limit.

0 = No data or NAK time-out error

REGISTER 11-9: USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) (CONTINUED)

bit 18 OVERRUN: Data Overrun Status bit (Device mode)

1 = An OUT packet cannot be loaded into the RX FIFO.
0 = Written by software to clear this bit

This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.

ERROR: No Data Packet Received Status bit (Host mode)

1 = Three attempts have been made to receive a packet and no data packet has been received. An interrupt is generated.
0 = Written by the software to clear this bit.

This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero.

bit 17 FIFOFULL: FIFO Full Status bit

1 = No more packets can be loaded into the RX FIFO
0 = The RX FIFO has at least one free space

bit 16 RXPKTRDY: Data Packet Reception Status bit

1 = A data packet has been received. An interrupt is generated.
0 = Written by software to clear this bit when the packet has been unloaded from the RX FIFO.

bit 15-11 MULT<4:0>: Multiplier Control bits

For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1 for the payload size.

For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe.

bit 10-0 RXMAXP<10:0>: Maximum RX Payload Per Transaction Control bits

RXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W	0 R/W-0
31:24	TXINTERV<7:0>
23:16	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W	0 R/W-0
23:16	SPEED<1:0> PRO		OCOL<1:0> TEP<3:0>
15:8	U-0 U-0 R	0 R-0	R-0	R-0 R-0	R-0
15:8	——		RXCNT<13:8>
7:0	R-0 R-0 R	0 R-0	R-0	R-0 R-0	R-0
7:0	RXCNT<7:0>

Legend:	HC = Hardware Clearable HS = Hardware Settable
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-24 TXINTERV<7:0>: Endpoint TX Polling Interval/NAK Limit bits (Host mode)

For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses.

The following table describes the valid values and interpretation for these bits:

Transfer Type	Speed	Valid Values (m)	Interpretation
Interrupt	Low/Full	0x01 to 0xFF	Polling interval is ‘m’ frames.
Interrupt	High 0x01 to	0x10 Polling interval is 2 ^(m-1) frames.	Polling interval is ‘m’ frames.
Isochronous	Full or High	0x01 to 0x10	Polling interval is 2^(m-1) frames/microframes.
Bulk	Full or High	0x02 to 0x10	NAK limit is 2^(m-1) frames/microframes. A value of ‘0’ or ‘1’ disables the NAK time-out function.

bit 23-22 SPEED<1:0>: TX Endpoint Operating Speed Control bits (Host mode)

11 = Low-Speed

10 = Full-Speed

01 = Hi-Speed

00 = Reserved

bit 21-20 PROTOCOL<1:0>: TX Endpoint Protocol Control bits

11 = Interrupt

10 = Bulk

01 = Isochronous

00 = Control

bit 19-16 TEP<3:0>: TX Target Endpoint Number bits

This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during device enumeration.

bit 15-14 Unimplemented: Read as '0'

bit 13-0 RXCNT<13:0>: Receive Count bits

The number of received data bytes in the endpoint RX FIFO. The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY is set.

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-28 RXFIFOSZ<3:0>: Receive FIFO Size bits

1111 = Reserved

1110 = Reserved

1101 = 8192 bytes

1100 = 4096 bytes

•

0011 = 8 bytes

0010 = Reserved

0001 = Reserved

0000 = Reserved or endpoint has not been configured

This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic FIFO sizing is used.

bit 27-24 TXFIFOSZ<3:0>: Transmit FIFO Size bits

1111 = Reserved

1110 = Reserved

1101 = 8192 bytes

1100 = 4096 bytes

•

0011 = 8 bytes

0010 = Reserved

0001 = Reserved

0000 = Reserved or endpoint has not been configured

This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic FIFO sizing is used.

bit 23-16 Unimplemented: Read as '0'

REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3 (ENDPOINT 1-7) (CONTINUED)

bit 15-8 RXINTERV<7:0>: Endpoint RX Polling Interval/NAK Limit bits

The following table describes the valid values and meaning for this field:

Transfer Type S	Speed Valid Values	(m) Interpretation
Interrupt Low/Full 0x01 to 0xFF Polling interval is ‘m’ frames.


Isochronous Full or High 0x01 to 0x10 Polling interval is 2 (m-1) frames.

Bulk	Full or High	0x02 to 0x10 NAK limit is 2 (m-1) frames/microframes. A value of ‘0’ or ‘1’ disables the NAK time-out function.

bit 7-6 SPEED<1:0>: RX Endpoint Operating Speed Control bits

11 = Low-Speed

10 = Full-Speed

01 = Hi-Speed

00 = Reserved

bit 5-4 PROTOCOL<1:0>: RX Endpoint Protocol Control bits

11 = Interrupt

10 = Bulk

01 = Isochronous

00 = Control

bit 3-0 TEP<3:0>: RX Target Endpoint Number bits

This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during device enumeration.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
31:24	DATA<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
23:16	DATA<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
15:8	DATA<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
7:0	DATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 DATA<31:0>: USB Transmit/Receive FIFO Data bits

Writes to this register loads data into the TxFIFO for the corresponding endpoint. Reading from this register unloads data from the RxFIFO for the corresponding endpoint.

Transfers may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the data accessed is contiguous. However, all transfers associated with one packet must be of the same width so that data is consistently byte-, word- or double-word aligned. The last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	-
31:24	— — —	RXDPB RXFIFOSZ<3:0>
23:16	U-0 U-0 U	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	-
23:16	— — —	TXDPB TXFIFOSZ<3:0>
15:8	U-0 U-0 U	U-0 U-0 U-0	R/W-0	R/W-0
15:8	— — —	— —	— TXEDMA RXEDMA
7:0	R-1 R-0 R	R-0 R-0 R-0 R	W-0, HC	R/W-0
7:0	BDEV	FSDEV	LSDEV	VBUS<1:0>		HOSTMODE	HOSTREQ	SESSION

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28 RXDPB: RX Endpoint Double-packet Buffering Control bit

1 = Double-packet buffer is supported. This doubles the size set in RXFIFOSZ.
0 = Double-packet buffer is not supported

bit 27-24 RXFIFOSZ<3:0>: RX Endpoint FIFO Packet Size bits

The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission)

1111 = Reserved
•
•
•
1010 = Reserved
1001 = 4096 bytes
1000 = 2048 bytes
0111 = 1024 bytes
0110 = 512 bytes
0101 = 256 bytes
0100 = 128 bytes
0011 = 64 bytes
0010 = 32 bytes
0001 = 16 bytes
0000 = 8 bytes

bit 23-21 Unimplemented: Read as '0'

bit 20 TXDPB: TX Endpoint Double-packet Buffering Control bit

1 = Double-packet buffer is supported. This doubles the size set in TXFIFOSZ.
0 = Double-packet buffer is not supported

REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)

bit 19-16 TXFIFOSZ<3:0>: TX Endpoint FIFO packet size bits

The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission)

1111 = Reserved

•

1010 = Reserved

1001 = 4096 bytes

1000 = 2048 bytes

0111 = 1024 bytes

0110 = 512 bytes

0101 = 256 bytes

0100 = 128 bytes

0011 = 64 bytes

0010 = 32 bytes

0001 = 16 bytes

0000 = 8 bytes

bit 15-10 Unimplemented: Read as '0'

bit 9 TXEDMA: TX Endpoint DMA Assertion Control bit

1 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode.
0 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode.

bit 8 RXEDMA: RX Endpoint DMA Assertion Control bit

1 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode.
0 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode.

bit 7 BDEV: USB Device Type bit

1 = USB is operating as a 'B' device
0 = USB is operating as an 'A' device

bit 6 FSDEV: Full-Speed/Hi-Speed device detection bit (Host mode)

1 = A Full-Speed or Hi-Speed device has been detected being connected to the port
0 = No Full-Speed or Hi-Speed device detected

bit 5 LSDEV: Low-Speed Device Detection bit (Host mode)

1 = A Low-Speed device has been detected being connected to the port
0 = No Low-Speed device detected

bit 4-3 VBUS<1:0>: V BUS Level Detection bits

11 = Above VBUS Valid
10 = Above AValid, below VBus Valid
01 = Above Session End, below AValid
00 = Below Session End

bit 2 HOSTMODE: Host Mode bit

1 = USB module is acting as a Host
0 = USB module is not acting as a Host

bit 1 HOSTREQ: Host Request Control bit

'B' device only:

1 = USB module initiates the Host Negotiation when Suspend mode is entered. This bit is cleared when Host Negotiation is completed.
0 = Host Negotiation is not taking place

REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)

bit 0 SESSION: Active Session Control/Status bit

'A' device:

1 = Start a session
0 = End a session

'B' device:

1 = (Read) Session has started or is in progress, (Write) Initiate the Session Request Protocol
0 = When USB module is in Suspend mode, clearing this bit will cause a software disconnect

Clearing this bit when the USB module is not suspended will result in undefined behavior.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	0
31:24	— — —	RXFIFOAD<12:8>
23:16	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	RXFIFOAD<7:0>
15:8	U-0 U-0 U-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	0
15:8	— — —	TXFIFOAD<12:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	TXFIFOAD<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR

'1' = Bit is set

'0' = Bit is cleared

x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28-16 RXFIFOAD<12:0>: Receive Endpoint FIFO Address bits

Start address of the endpoint FIFO in units of 8 bytes as follows:

11111111111111 = 0xFF8

•

0000000000010 = 0x0010

0000000000001 = 0x0008

00000000000000 = 0x0000

bit 15-13 Unimplemented: Read as '0'

bit 12-0 TXFIFOAD<12:0>: Transmit Endpoint FIFO Address bits

Start address of the endpoint FIFO in units of 8 bytes as follows:

11111111111111 = 0xFF8

•

0000000000010 = 0x0010

0000000000001 = 0x0008

00000000000000 = 0x0000

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0
23:16	— — —	— — — — —
15:8	R-0 R-0 R-0	R-0 R-1	R-0 R-0
15:8	RC VERMAJOR<4:0>			VERMINOR<9:8>
7:0	R-0 R-0 R-0	R-0 R-0	R-0 R-0
7:0	VERMINOR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 RC: Release Candidate bit

1 = USB module was created using a release candidate

0 = USB module was created using a full release

bit 14-10 VERMAJOR<4:0>: USB Module Major Version number bits

This read-only number is the Major version number for the USB module.

bit 9-0 VERMINOR<9:0>: USB Module Minor Version number bits

This read-only number is the Minor version number for the USB module.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-1 R/W-1	R/W-1 R/W-1	R/W-0
31:24	VPLEN<7:0>
23:16	R/W-0 R/W-1	R/W-0 R/W-1	R/W-1 R/W-1	R/W-0	R/W-0
23:16	WTCON<3:0> WTID<3:0>
15:8	R-1 R-0 R-0	R-0 R-1	R-0 R-0
15:8	DMACHANS<3:0> RAMBITS<3:0>
7:0	R-0 R-1 R-1	R-1 R-0	R-1 R-1
7:0	RXENDPTS<3:0> TXENDPTS<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-24 VPLEN<7:0>: VBUS pulsing charge length bits

Sets the duration of the VBUS pulsing charge in units of 546.1 s. (The default setting corresponds to 32.77 ms.)

bit 23-20 WTCON<3:0>: Connect/Disconnect filter control bits

Sets the wait to be applied to allow for the connect/disconnect filter in units of 533.3 ns. The default setting corresponds to 2.667 s.

bit 19-6 WTID<3:0>: ID delay valid control bits

Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of 4.369ms. The default setting corresponds to 52.43ms.

bit 15-12 DMACHANS<3:0>: DMA Channels bits

These read-only bits provide the number of DMA channels in the USB module. For the PIC32MZ EC family, this number is 8.

bit 11-8 RAMBITS<3:0>: RAM address bus width bits

These read-only bits provide the width of the RAM address bus. For the PIC32MZ EC family, this number is 12.

bit 7-4 RXENDPTS<3:0>: Included RX Endpoints bits

This read-only register gives the number of RX endpoints in the design. For the PIC32MZ EC family, this number is 7.

bit 3-0 TXENDPTS<3:0>: Included TX Endpoints bits

These read-only bits provide the number of TX endpoints in the design. For the PIC32MZ EC family, this number is 7.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 R/W-0 R/W-0
31:24	— — —	— — — NR$TX NRST
23:16	R/W-0 R/W-1	R/W-1 R/W-1 R/W-0	R/W-0 R.W-0 R/W-1	R/W-0
23:16	LSEOF<7:0>
15:8	R/W-0 R/W-1	R/W-1 R/W-1 R/W-0	R/W-0 R.W-1 R/W-1	R/W-1
15:8	FSEOF<7:0>
7:0	R/W-1 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R.W-0 R/W-0	R/W-0
7:0	HSEOF<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-26 Unimplemented: Read as '0'

bit 25 NRSTX: Reset of XCLK Domain bit

1 = Reset the XCLK domain, which is clock recovered from the received data by the PHY

0 = Normal operation

bit 24 NRST: Reset of CLK Domain bit

1 = Reset the CLK domain, which is clock recovered from the peripheral bus

0 = Normal operation

bit 23-16 LSEOF<7:0>: Low-Speed EOF bits

These bits set the Low-Speed transaction in units of 1.067 s (default setting is 121.6 s) prior to the EOF to stop new transactions from beginning.

bit 15-8 FSEOF<7:0>: Full-Speed EOF bits

These bits set the Full-Speed transaction in units of 533.3 s (default setting is 63.46 s) prior to the EOF to stop new transactions from beginning.

bit 7-0 HSEOF<7:0>: Hi-Speed EOF bits

These bits set the Hi-Speed transaction in units of 133.3 s (default setting is 17.07~ s ) prior to the EOF to stop new transactions from beginning.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 R/W-0	R/W-0 R/W-0 R/W-0 R/W-0 R/W-0		R/W-0
31:24	— TXHUBPRT<6:0>
23:16	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0 R/W-0		R/W-0
23:16	MULTTRAN	TXHUBADD<6:0>
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	—	—	—	—	—	—	—	—
7:0	U-0 R/W-0	R/W-0 R/W-0 R/W-0		R/W-0
7:0	—	TXFADDR<6:0>

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 Unimplemented: Read as '0'

bit 30-24 TXHUBPRT<6:0>: TX Hub Port bits (Host mode)

When a low- or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this field records the port number of that USB 2.0 hub.

bit 23 MULTTRAN: TX Hub Multiple Translators bit (Host mode)

1 = The USB 2.0 hub has multiple transaction translators
0 = The USB 2.0 hub has a single transaction translator

bit 22-16 TXHUBADD<6:0>: TX Hub Address bits (Host mode)

When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these bits record the address of the USB 2.0 hub.

bit 15-7 Unimplemented: Read as '0'

bit 6-0 TXFADDR<6:0>: TX Functional Address bits (Host mode)

Specifies the address for the target function that is be accessed through the associated endpoint. It needs to be defined for each TX endpoint that is used.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 R/W-0	R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24	— RXHUBPRT<6:0>
23:16	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0 R/W-0
23:16	MULTTRAN	RXHUBADD<6:0>
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	—	—	—	—	—	—	—	—
7:0	U-0 R/W-0	R/W-0 R/W-0 R/W-0 R/W-0
7:0	—	RXFADDR<6:0>

Legend:	HC = Hardware Clearable HS = Hardware Settable
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31 Unimplemented: Read as '0'

bit 30-24 RXHUBPRT<6:0>: RX Hub Port bits (Host mode)

When a low- or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this field records the port number of that USB 2.0 hub.

bit 23 MULTTRAN: RX Hub Multiple Translators bit (Host mode)

1 = The USB 2.0 hub has multiple transaction translators

0 = The USB 2.0 hub has a single transaction translator

bit 22-16 TXHUBADD<6:0>: RX Hub Address bits (Host mode)

When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these bits record the address of the USB 2.0 hub.

bit 15-7 Unimplemented: Read as '0'

bit 6-0 RXFADDR<6:0>: RX Functional Address bits (Host mode)

Specifies the address for the target function that is be accessed through the associated endpoint. It needs to be defined for each RX endpoint that is used.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8	— — —	— — — — —
7:0	R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS
7:0	DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as '0'

bit 7-0 DMAxIF: DMA Channel 'x' Interrupt bit

1 = The DMA channel has an interrupt event
0 = No interrupt event

All bits are cleared on a read of the register.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 R/W-0	R/W-0 R/W-0
15:8	— — —	— — — DMABRSTM<1:0>		DMAERR
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
7:0	DMAEP<3:0>			DMAIE DMAMODE	DMADIR	DMAEN

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-11 Unimplemented: Read as '0'

bit 10-9 DMABRSTM<1:0>: DMA Burst Mode Selection bit

11 = Burst Mode 3: INCR16, INCR8, INCR4 or unspecified length
10 = Burst Mode 2: INCR8, INCR4 or unspecified length
01 = Burst Mode 1: INCR4 or unspecified length
00 = Burst Mode 0: Bursts of unspecified length

bit 8 DMAERR: Bus Error bit

1 = A bus error has been observed on the input
0 = The software writes this to clear the error

bit 7-4 DMAEP<3:0>: DMA Endpoint Assignment bits

These bits hold the endpoint that the DMA channel is assigned to. Valid values are 0-7.

bit 3 DMAIE: DMA Interrupt Enable bit

1 = Interrupt is enabled for this channel
0 = Interrupt is disabled for this channel

bit 2 DMAMODE: DMA Transfer Mode bit

1 = DMA Mode1 Transfers
0 = DMA Mode0 Transfers

bit 1 DMADIR: DMA Transfer Direction bit

1 = DMA Read (TX endpoint)
0 = DMA Write (RX endpoint)

bit 0 DMAEN: DMA Enable bit

1 = Enable the DMA transfer and start the transfer
0 = Disable the DMA transfer

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
31:24	DMAADDR<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
23:16	DMAADDR<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
15:8	DMAADDR<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R-0
7:0	DMAADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 DMAADDR<31:0>: DMA Memory Address bits

This register identifies the current memory address of the corresponding DMA channel. The initial memory address written to this register during initialization must have a value such that its modulo 4 value is equal to '0'. The lower two bits of this register are read only and cannot be set by software. As the DMA transfer progresses, the memory address will increment as bytes are transferred.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	DMACOUNT<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	DMACOUNT<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	DMACOUNT<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	DMACOUNT<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-0 DMACOUNT<31:0>: DMA Transfer Count bits

This register identifies the current DMA count of the transfer. Software will set the initial count of the transfer which identifies the entire transfer length. As the count progresses this count is decremented as bytes are transferred.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
15:8	RQPKTCNT<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
7:0	RQPKTCNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 RQPKTCNT<15:0>: Request Packet Count bits

Sets the number of packets of size MAXP that are to be transferred in a block transfer. This register is only available in Host mode when AUTOREQ is set.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
31:24	— —	— —	— —	— —	—
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	U-0
23:16	EP7TXD	EP6TXD	EP5TXD	EP4TXD	EP3TXD	EP2TXD	EP1TXD	—
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	— —	— —	— —	— —	—
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	U-0
7:0	EP7RXD	EP6RXD	EP5RXD	EP4RXD	EP3RXD	EP2RXD	EP1RXD	—

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-17 EP7TXD:EP1TXD: TX Endpoint 'x' Double Packet Buffer Disable bits

1 = TX double packet buffering is disabled for endpoint 'x' 0 = TX double packet buffering is enabled for endpoint 'x'

bit 16 Unimplemented: Read as '0'

bit 15-1 EP7RXD:EP1RXD: RX Endpoint 'x' Double Packet Buffer Disable bits

1 = RX double packet buffering is disabled for endpoint 'x' 0 = RX double packet buffering is enabled for endpoint 'x'

bit 0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-1	R/W-0 R/W-1
31:24	THHSRTN<15:8>
23:16	R/W-1 R/W-1	R/W-1 R/W-0	R/W-0 R/W-1	R/W-1 R/W-0
23:16	THHSRTN<7:0>
15:8	R/W-0 R/W-1	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0
15:8	TUCH<15:8>
7:0	R/W-0 R/W-1	R/W-1 R/W-1	R/W-0 R/W-1	R/W-0 R/W-0
7:0	TUCH<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 THHSRTN:<15:0>: Hi-Speed Resume Signaling Delay bits

These bits set the delay from the end of Hi-Speed resume signaling (acting as a Host) to enable the UTM normal operating mode.

bit 15-0 TUCH<15:0>: Chirp Time-out bits

These bits set the chirp time-out. This number, when multiplied by 4, represents the number of USB module clock cycles before the time-out occurs.

Note: Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum specified in the USB 2.0 specification, making the USB module non-compliant.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
31:24	—	—	—	—	—	—	—	—
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
23:16	—	—	—	—	—	—	—	—
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	—	—	—	—	—	—	—	—
7:0	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	—	THBST<3:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as '0'

bit 3-0 THBST<3:0>: High Speed Time-out Adder bits

These bits represent the value to be added to the minimum high speed time-out period of 736 bit times. The time-out period can be increased in increments of 64 Hi-Speed bit times (133 ns).

Note: Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum specified in the USB 2.0 specification, making the USB module non-compliant.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0			W-0
31:24	— — LPMERRIE LPMRESIE LPMACKIE LPMNYIE LPMSTIE LPMTOIE
23:16	U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0, HC			R/W-0, HC
23:16	—	—	—	LPMNAK	LPMEN<1:0>		LPMRES	LPMXMT
15:8	R-0 R-0 R-0 R-0 U-0 U-0 U-0 R-0
15:8	ENDPOINT<3:0>				—	—	—	RMTWAK
7:0	R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0	HIRD<3:0>				LNKSTATE<3:0>

Legend:	HC = Hardware Clearable
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-30 Unimplemented: Read as '0'

bit 29 LPMERRIE: LPM Error Interrupt Enable bit

1 = LPMERR interrupt is enabled
0 = LPMERR interrupt is disabled

bit 28 LPMRESIE: LPM Resume Interrupt Enable bit

1 = LPMRES interrupt is enabled
0 = LPMRES interrupt is disabled

bit 27 LPMACKIE: LPM Acknowledge Interrupt Enable bit

1 = Enable the LPMACK Interrupt
0 = Disable the LPMACK Interrupt

bit 26 LPMNYIE: LPM NYET Interrupt Enable bit

1 = Enable the LPMNYET Interrupt
0 = Disable the LPMNYET Interrupt

bit 25 LPMSTIE: LPM STALL Interrupt Enable bit

1 = Enable the LPMST Interrupt
0 = Disable the LPMST Interrupt

bit 24 LPMTOIE: LPM Time-out Interrupt Enable bit

1 = Enable the LPMTO Interrupt
0 = Disable the LPMTO Interrupt

bit 23-21 Unimplemented: Read as '0'

bit 20 LPMNAK: LPM-only Transaction Setting bit

1 = All endpoints will respond to all transactions other than a LPM transaction with a NAK
0 = Normal transaction operation

Setting this bit to '1' will only take effect after the USB module as been LPM suspended.

bit 19-18 LPMEN<1:0>: LPM Enable bits (Device mode)

11 = LPM and Extended transactions are supported
10 = LPM is supported and Extended transactions are not supported
01 = LPM is not supported but Extended transactions are supported
00 = LPM and Extended transactions are not supported

bit 17 LPMRES: LPM Resume bit

1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 μs.
0 = No resume operation
This bit is self-clearing.

REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL REGISTER 1 (CONTINUED)

bit 16 LPMXMT: LPM Transition to the L1 State bit When in Device mode:

1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must be set to `0b11. Both LPMXMT and LPMEN must be set in the same cycle.
0 = Maintain current state

When LPMXMT and LPMEN are set, the USB module can respond in the following ways:

If no data is pending (all TX FIFOs are empty), the USB module will respond with an ACK. The bit will self clear and a software interrupt will be generated.
If data is pending (data resides in at least one TX FIFO), the USB module will respond with a NYET. In this case, the bit will not self clear however a software interrupt will be generated.

When in Host mode:

1 = USB module will transmit an LPM transaction. This bit is self clearing, and will be immediately cleared upon receipt of any Token or three time-outs have occurred.
0 = Maintain current state

bit 15-12 ENDPOINT<3:0>: LPM Token Packet Endpoint bits

This is the endpoint in the token packet of the LPM transaction.

bit 11-9 Unimplemented: Read as '0'

bit 8 RMTWAK: Remote Wake-up Enable bit

This bit is applied on a temporary basis only and is only applied to the current suspend state.

1 = Remote wake-up is enabled
0 = Remote wake-up is disabled

bit 7-4 HIRD<3:0>: Host Initiated Resume Duration bits

The minimum time the host will drive resume on the bus. The value in this register corresponds to an actual resume time of:

Resume Time = 50 μs + HIRD * 75 μs. The resulting range is 50 μs to 1200 μs.

bit 3-0 LNKSTATE<3:0>: Link State bits

This value is provided by the host to the peripheral to indicate what state the peripheral must transition to after the receipt and acceptance of a LPM transaction. The only valid value for this register is '1' for Sleep State (L1). All other values are reserved.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0 U-0 U-0 U-0
31:24	—— —	—— — — — — —
23:16	U-0 U-0 U-0 U-0 U-0 U-0
23:16	—— —	—— — — — — —
15:8	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	—	LPMFADDR<6:0>
7:0	U-0 U-0 R-0	R-0, HS			R-0, HS	R-0, HS	R-0, HS	R-0, HS
7:0	—	—	LPMERRIF	LPMRESIF	LPMNCIF	LPMACKIF	LPMNYIF	LPMSTIF

Legend:	HS = Hardware Settable
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-15 Unimplemented: Read as '0'

bit 14-8 LPMFADDR<6:0>: LPM Payload Function Address bits

These bits contain the address of the LPM payload function.

bit 7-6 Unimplemented: Read as '0'

bit 5 LPMERRIF: LPM Error Interrupt Flag bit (Device mode)

1 = An LPM transaction was received that had a LINKSTATE field that is not supported. The response will be a STALL.

0 = No error condition

bit 4 LPMRESIF: LPM Resume Interrupt Flag bit

1 = The USB module has resumed (for any reason)

0 = No Resume condition

bit 3 LPMNCIF: LPM NC Interrupt Flag bit

When in Device mode:

1 = The USB module received a LPM transaction and responded with a NYET due to data pending in the RX FIFOs.

0 = No NC interrupt condition

When in Host mode:

1 = A LPM transaction is transmitted and the device responded with an ACK

0 = No NC interrupt condition

bit 2 LPMACKIF: LPM ACK Interrupt Flag bit

When in Device mode:

1 = A LPM transaction was received and the USB Module responded with an ACK

0 = No ACK interrupt condition

When in Host mode:

1 = The LPM transaction is transmitted and the device responds with an ACK

0 = No ACK interrupt condition

bit 1 LPMNYIF: LPM NYET Interrupt Flag bit

When in Device mode:

1 = A LPM transaction is received and the USB Module responded with a NYET

0 = No NYET interrupt flag

When in Host mode:

1 = A LPM transaction is transmitted and the device responded with an NYET

0 = No NYET interrupt flag

REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2

bit 0 LPMSTIF: LPM STALL Interrupt Flag bit

When in Device mode:

1 = A LPM transaction was received and the USB Module responded with a STALL

0 = No Stall condition

When in Host mode:

1 = A LPM transaction was transmitted and the device responded with a STALL

0 = No Stall condition

12.0 I/O PORTS

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "I/O Ports" (DS60001120), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

General purpose I/O pins are the simplest of peripherals. They allow the PIC32MZ EC family device to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.

Key features of the I/O ports include:

Individual output pin open-drain enable/disable
Individual input pin weak pull-up and pull-down
Monitor selective inputs and generate interrupt when change in pin state is detected
• Operation during Sleep and Idle modes
Fast bit manipulation using CLR, SET, and INV registers

Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port.
FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Microchip PIC32MZ1024ECM124 - I/O PORTS - 1

flowchart

graph TD
    A["Peripheral Module"] --> B["Data Bus"]
    A --> C["WR ODC"]
    A --> D["RD TRIS"]
    A --> E["WR TRIS"]
    A --> F["WR LAT"]
    A --> G["WR PORT"]
    A --> H["RD LAT"]
    A --> I["RD PORT"]
    A --> J["Sleep"]
    A --> K["PBCLK4"]
    A --> L["Peripheral Input"]
    L --> M["Peripheral Input Buffer"]
    M --> N["Output Multiplexers"]
    N --> O["I/O Pin"]
    O --> P["Port Control"]
    P --> Q["PBCLK4"]
    N --> R["Q D Q D"]
    N --> S["Q̅ CK"]
    N --> T["Synchronization"]
    T --> U["Output Multiplexers"]
    U --> V["I/O Cell"]
    V --> W["Output Multiplexers"]
    W --> X["Output Multiplexers"]
    X --> Y["I/O Pin"]
    Y --> Z["Output Multiplexers"]
    Z --> AA["Output Multiplexers"]
    AA --> AB["Output Multiplexers"]
    AB --> AC["I/O Pin"]
    AC --> AD["Output Multiplexers"]
    AD --> AE["I/O Pin"]
    AE --> AF["Output Multiplexers"]
    AF --> AG["I/O Pin"]
    AG --> AH["Output Multiplexers"]
    AH --> AI["I/O Pin"]
    AI --> AJ["Output Multiplexers"]
    AJ --> AK["I/O Pin"]
    AK --> AL["Output Multiplexers"]
    AL --> AM["I/O Pin"]
    AM --> AN["Output Multiplexers"]
    AN --> AO["I/O Pin"]
    AO --> AP["Output Multiplexers"]
    AP --> AQ["I/O Pin"]
    AQ --> AR["Output Multiplexers"]
    AR --> AS["I/O Pin"]
    AS --> AT["Output Multiplexers"]
    AT --> AU["I/O Pin"]
    AU --> AV["Output Multiplexers"]
    AV --> AW["I/O Pin"]
    AW --> AX["Output Multiplexers"]
    AX --> AY["I/O Pin"]
    AY --> AZ["Output Multiplexers"]
    AZ --> BA["I/O Pin"]
    BA --> BB["Output Multiplexers"]
    BB --> BC["I/O Pin"]
    BC --> BD["Output Multiplexers"]
    BD --> BE["I/O Pin"]
    BE --> BF["Output Multiplexers"]
    BF --> BG["I/O Pin"]
    BG --> BH["Output Multiplexers"]
    BH --> BI["I/O Pin"]
    BI --> BJ["Output Multiplexers"]
    BJ --> BK["I/O Pin"]
    BK --> BL["Output Multiplexers"]
    BL --> BM["I/O Pin"]
    BM --> BN["Output Multiplexers"]
    BN --> BO["I/O Pin"]
    BO --> BP["Output Multiplexers"]
    BP --> BQ["I/O Pin"]
    BQ --> BR["Output Multiplexers"]
    BR --> BS["I/O Pin"]
    BS --> BT["Output Multiplexers"]
    BT --> BU["I/O Pin"]
    BU --> BV["Output Multiplexers"]
    BV --> BW["I/O Pin"]
    BW --> BX["Output Multiplexers"]
    BX --> BY["I/O Pin"]
    BY --> BZ["Output Multiplexers"]

Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than shown here.

12.1 Parallel I/O (PIO) Ports

All port pins have ten registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a '1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch.

12.1.1 OPEN-DRAIN CONFIGURATION

In addition to the PORTx, LATx, and TRISx registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output.

The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired 5V-tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification.

Refer to the pin name tables (Table 2 through Table 5) for the available pins and their functionality.

12.1.2 CONFIGURING ANALOG AND DIGITAL PORT PINS

The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSEL and TRIS bits set. In order to use port pins for I/O functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be cleared.

The ANSELx register has a default value of 0xFFFF; therefore, all pins that share analog functions are analog (not digital) by default.

If the TRIS bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or Comparator module.

When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level).

Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications.

12.1.3 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NOP.

12.1.4 INPUT CHANGE NOTIFICATION

The input change notification function of the I/O ports allows the PIC32MZ EC devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a change-of-state.

Five control registers are associated with the CN functionality of each I/O port. The CNENx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins.

The CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit.

Each I/O pin also has a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins.

Note: Pull-ups and pull-downs on change notification pins should always be disabled when the port pin is configured as a digital output.

An additional control register (CNCONx) is shown in Register 12-3.

12.2 CLR, SET, and INV Registers

Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as '1' are modified. Bits specified as '0' are not modified.

Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read.

12.3 Peripheral Pin Select (PPS)

A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option.

PPS configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device.

The PPS configuration feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most digital peripherals to these I/O pins. PPS is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established.

12.3.1 AVAILABLE PINS

The number of available pins is dependent on the particular device and its pin count. Pins that support the PPS feature include the designation "RPn" in their full pin designation, where "RP" designates a remappable peripheral and "n" is the remappable port number.

12.3.2 AVAILABLE PERIPHERALS

The peripherals managed by the PPS are all digital-only peripherals. These include general serial communications (UART, SPI, and CAN), general purpose timer clock inputs, timer-related peripherals (input capture and output compare), interrupt-on-change inputs, and reference clocks (input and output).

In comparison, some digital-only peripheral modules are never included in the PPS feature. This is because the peripheral's function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include among others. A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC).

A key difference between remappable and non-remappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral.

When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin.

12.3.3 CONTROLLING PPS

PPS features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint.

The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is being mapped.

12.3.4 INPUT MAPPING

The inputs of the PPS options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The [pin name]R registers, where [pin name] refers to the peripheral pins listed in Table 12-1, are used to configure peripheral input mapping (see Register 12-1). Each register contains sets of 4 bit fields. Programming these bit fields with an appropriate value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is shown in Table 12-1.

For example, Figure 12-2 illustrates the remappable pin selection for the U1RX input.

FIGURE 12-2: REMAPPABLE INPUT EXAMPLE FOR U1RX
Microchip PIC32MZ1024ECM124 - INPUT MAPPING - 1

flowchart

graph LR
    A["RPD2"] --> B["U1RXR<3:0>"]
    C["RPG8"] --> B
    D["RPF4"] --> B
    E["..."] --> B
    F["RPn"] --> B
    B --> G["U1RX input to peripheral"]

Note: For input only, PPS functionality does not have priority over TRISx settings. Therefore, when configuring RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to '1').

TABLE 12-1: INPUT PIN SELECTION

Peripheral Pin	[pin name]R SFR	[pin name]R bits	[pin name]R Value to RPn Pin Selection
INT3	INT3R	INT3R<3:0>	0000 = RPD2
T2CK T2CKR T2CKR<3:0>			0001 = RPG8
T6CK T6CKR T6CKR<3:0>			0010 = RPF4
IC3 IC3R IC3R<3:0>			0011 = RPD10
IC7 IC7R IC7R<3:0>			0100 = RPF1
U1RX U1RXR	U1RXR<3:0>		0101 = RPB9
2CTS	U2CTSR	U2CTSR<3:0>	0110 = RPB10
U5RX U5RXR	U5RXR<3:0>		0111 = RPC14
6CTS	U6CTSR	U6CTSR<3:0>	1000 = RPB5
SDI1	SDI1R	SDI1R<3:0>	1001 = Reserved
SDI3	SDI3R	SDI3R<3:0>	1010 = RPC1(1)
SDI5^(1)	SDI5R^(1)	SDI5R<3:0>(1)	1011 = RPD14(1)
6^(1)	SS6R^(1)	SS6R<3:0>(1)	1100 = RPG1(1)
REFCLKI1	REFCLKI1R	REFCLKI1R<3:0>	1101 = RPA14(1)
			1110 = RPD6(2)
			1111 = Reserved
INT4	INT4R	INT4R<3:0>	0000 = RPD3
T5CK T5CKR T5CKR<3:0>			0001 = RPG7
T7CK T7CKR T7CKR<3:0>			0010 = RPF5
IC4 IC4R IC4R<3:0>			0011 = RPD11
IC8 IC8R IC8R<3:0>			0100 = RPF0
			0101 = RPB1
			0110 = RPE5
U3RX U3RXR	U3RXR<3:0>		0111 = RPC13
U3RX U3RXR	U3RXR<3:0>		1000 = RPB3
4CTS	U4CTSR	U4CTSR<3:0>	1001 = Reserved
SDI2	SDI2R	SDI2R<3:0>	1010 = RPC4(1)
SDI4	SDI4R	SDI4R<3:0>	1011 = RPD15(1)
C1RX^(3)	C1RXR^(3)	C1RXR<3:0>(3)	1100 = RPG0(1)
REFCLKI4	REFCLKI4R	REFCLKI4R<3:0>	1101 = RPA15(1)
			1110 = RPD7(2)
			1111 = Reserved
INT2	INT2R	INT2R<3:0>	0000 = RPD9
T3CK T3CKR T3CKR<3:0>			0001 = RPG6
T8CK T8CKR T8CKR<3:0>			0010 = RPB8
IC2 IC2R IC2R<3:0>			0011 = RPB15
IC5 IC5R IC5R<3:0>			0100 = RPD4
IC9 IC9R IC9R<3:0>			0101 = RPB0
1CTS	U1CTSR	U1CTSR<3:0>	0110 = RPE3
1CTS	U1CTSR	U1CTSR<3:0>	0111 = RPB7
U2RX U2RXR	U2RXR<3:0>		1000 = Reserved
5CTS	U5CTSR	U5CTSR<3:0>	1001 = RPF12(1)
1	SS1R	SS1R<3:0>	1010 = RPD12(1)
3	SS3R	SS3R<3:0>	1011 = RPF8(1)
4	SS4R	SS4R<3:0>	1100 = RPC3(1)
5^(1)	SS5R^(1)	SS5R<3:0>(1)	1101 = RPE9(1)
C2RX^(3)	C2RXR^(3)	C2RXR<3:0>(3)	1110 = Reserved
C2RX^(3)	C2RXR^(3)	C2RXR<3:0>(3)	1111 = Reserved

Note 1: This selection is not available on 64-pin devices.
2: This selection is not available on 64-pin or 100-pin devices.
3: This selection is not available on devices without a CAN module.

TABLE 12-1: INPUT PIN SELECTION (CONTINUED)

Peripheral Pin	[pin name]R SFR	[pin name]R bits	[pin name]R Value to RPn Pin Selection
INT1	INT1R	INT1R<3:0>	0000 = RPD10001 = RPG90010 = RPB140011 = RPD00100 = Reserved0101 = RPB60110 = RPD50111 = RPB21000 = RPF31001 = RPF13(1)1010 = No Connect1011 = RPF2(1)1100 = RPC2(1)1101 = RPE8(1)1110 = Reserved1111 = Reserved
T4CK T4CKR T4CKR<3:0>
T9CK T9CKR T9CKR<3:0>
IC1 IC1R IC1R<3:0>
IC6 IC6R IC6R<3:0>
3CTS	U3CTSR U3CTSR<3:0>
U4RX U4RXR U4RXR<3:0>
U6RX U6RXR U6RXR<3:0>
2	SS2R SS2R<3:0>
SDI6^(1)	SDI6R^(1)	SDI6R<3:0>(1)
OCFA	OCFAR	OCFAR<3:0>
REFCLKI3	REFCLKI3R	REFCLKI3R<3:0>

Note 1: This selection is not available on 64-pin devices.
2: This selection is not available on 64-pin or 100-pin devices.
3: This selection is not available on devices without a CAN module.

12.3.5 OUTPUT MAPPING

In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 12-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields. The value of the bit field corresponds to one of the peripherals, and that peripheral's output is mapped to the pin (see Table 12-2 and Figure 12-3).

A null output is associated with the output register reset value of '0'. This is done to ensure that remappable outputs remain disconnected from all output pins by default.

FIGURE 12-3: EXAMPLE OF
MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPF0
Microchip PIC32MZ1024ECM124 - OUTPUT MAPPING - 1

text_image

RPF0R<3:0> Default U1TX Output U2RTS Output Output Data REFCLKO1 14 15 RPF0

12.3.6 CONTROLLING CONFIGURATION CHANGES

Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32MZ EC devices include two features to prevent alterations to the peripheral map:

• Control register lock sequence
- Configuration bit select lock

12.3.6.1 Control Register Lock

Under normal operation, writes to the RPnR and [pin name]R registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK Configuration bit (CFGCON<13>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes.

To set or clear the IOLOCK bit, an unlock sequence must be executed. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

12.3.6.2 Configuration Bit Select Lock

As an additional level of safety, the device can be configured to prevent more than one write session to the RPnR and [pin name]R registers. The IOL1WAY Configuration bit (DEVCFG3<29>) blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure does not execute, and the PPS control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset.

In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session.

TABLE 12-2: OUTPUT PIN SELECTION

RPn Port Pin RPnR	SFR RPnR bits		RPnR Value to Peripheral Selection
RPD2 RPD2R	RPD2R<3:0> 0000 = No	Connect
RPG8 RPG8R	RPG8R<3:0>		0001 = U3TX0010 = 4RTS 0011 = Reserved0100 = Reserved0101 = SDO10110 = SDO20111 = SDO31000 = Reserved1001 = SDO5^(1) 1010 = 6^(1) 1011 = OC31100 = OC61101 = REFCLKO41110 = C2OUT1111 = C1TX ^(3)
RPF4 RPF4R	RPF4R<3:0>
RPD10 RPD10R	RPD10R<3:0>
RPF1 RPF1R	RPF1R<3:0>
RPB9	RPB9R	RPB9R<3:0>
RPB10	RPB10R	RPB10R<3:0>
RPC14 RPC14R	RPC14R<3:0>
RPB5	RPB5R	RPB5R<3:0>
RPC1^(1)	RPC1R^(1)	RPC1R<3:0>(1)
RPD14^(1)	RPD14R^(1)	RPD14R<3:0>(1)
RPG1^(1)	RPG1R^(1)	RPG1R<3:0>(1)
RPA14^(1)	RPA14R^(1)	RPA14R<3:0>(1)
RPD6^(2)	RPD6R^(2)	RPD6R<3:0>(2)
RPD3 RPD3R	RPD3R<3:0> 0000 = No	Connect
RPG7 RPG7R	RPG7R<3:0>		0001 = U1TX0010 = 2RTS 0011 = U5TX0100 = 6RTS 0101 = SDO10110 = SDO20111 = SDO31000 = SDO41001 = SDO5^(1) 1010 = Reserved1011 = OC41100 = OC71101 = Reserved1110 = Reserved1111 = REFCLKO1
RPF5 RPF5R	RPF5R<3:0>
RPD11	RPD11R	RPD11R<3:0>
RPF0 RPF0R	RPF0R<3:0>
RPB1	RPB1R	RPB1R<3:0>
RPE5	RPE5R	RPE5R<3:0>
RPC13 RPC13R	RPC13R<3:0>
RPB3	RPB3R	RPB3R<3:0>
RPC4^(1)	RPC4R^(1)	RPC4R<3:0>(1)
RPD15^(1)	RPD15R^(1)	RPD15R<3:0>(1)
RPG0^(1)	RPG0R^(1)	RPG0R<3:0>(1)
RPA15^(1)	RPA15R^(1)	RPA15R<3:0>(1)
RPD7^(2)	RPD7R^(2)	RPD7R<3:0>(2)
RPD9 RPD9R	RPD9R<3:0> 0000 = No	Connect
RPG6 RPG6R	RPG6R<3:0>		0001 = 3RTS 0010 = U4TX0011 = Reserved0100 = U6TX0101 = SS10110 = Reserved0111 = SS31000 = SS41001 = 5^(1) 1010 = SDO6^(1) 1011 = OC51100 = OC81101 = Reserved1110 = C1OUT1111 = REFCLKO3
RPB8	RPB8R	RPB8R<3:0>
RPB15	RPB15R	RPB15R<3:0>
RPD4 RPD4R	RPD4R<3:0>
RPB0	RPB0R	RPB0R<3:0>
RPE3	RPE3R	RPE3R<3:0>
RPB7	RPB7R	RPB7R<3:0>
RPF12^(1)	RPF12R^(1)	RPF12R<3:0>(1)
RPD12^(1)	RPD12R^(1)	RPD12R<3:0>(1)
RPF8^(1)	RPF8R^(1)	RPF8R<3:0>(1)
RPC3^(1)	RPC3R^(1)	RPC3R<3:0>(1)
RPE9^(1)	RPE9R^(1)	RPE9R<3:0>(1)

Note 1: This selection is not available on 64-pin devices.
2: This selection is not available on 64-pin or 100-pin devices.
3: This selection is not available on devices without a CAN module.

TABLE 12-2: OUTPUT PIN SELECTION (CONTINUED)

RPn Port Pin	RPnR SFR	RPnR bits	RPnR Value to Peripheral Selection
RPD1 RPD1R	RPD1R<3:0>		0000 = No Connect
RPG9 RPG9R	RPG9R<3:0>		0001 = U1RTS
RPB14 RPB14R	RPB14R<3:0>		0010 = U2TX
RPD0 RPD0R	RPD0R<3:0>		0011 = U5RTS
RPB6 RPB6R	RPB6R<3:0>		0100 = U6TX
RPD5 RPD5R	RPD5R<3:0>		0101 = Reserved
RPB2 RPB2R	RPB2R<3:0>		0110 = SS2
RPF3 RPF3R	RPF3R<3:0>		0111 = Reserved
RPF13^(1)	RPF13R^(1)	RPF13R<3:0>(1)	1000 = SDO4
RPC2^(1)	RPC2R^(1)	RPC2R<3:0>(1)	1001 = Reserved
RPE8^(1)	RPE8R^(1)	RPE8R<3:0>(1)	1010 = SDO6 ^(1)
RPF2^(1)	RPF2R^(1)	RPF2R<3:0>(1)	1011 = OC2
			1100 = OC1
			1101 = OC9
			1110 = Reserved
			1111 = C2TX ^(3)

Note 1: This selection is not available on 64-pin devices.
2: This selection is not available on 64-pin or 100-pin devices.
3: This selection is not available on devices without a CAN module.

12.4 I/O Ports Control Registers

TABLE 12-3: PORTA REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY

Virtual Address (BF86_#)	Register Name!	Bit Range	Bits																All Resets
Virtual Address (BF86_#)	Register Name!	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
0000	ANSELA	31:16	———	———	———	———	0000
0000	ANSELA	15:0	—	—	—	—	—	ANSA10	ANSA9	—	—	—	ANSA5	—	—	—	ANSA1	ANSA0	0623
0010	TRISA	31:16	———	———	———	———	0000
0010	TRISA	15:0	TRISA15	TRISA14	—	—	—	TRISA10	TRISA9	—	TRISA7	TRISA6	TRISA5	TRISA4	TRISA3	TRISA2	TRISA1	TRISA0	C627
0020	PORTA	31:16	———	———	———	———	0000
0020	PORTA	15:0	RA15	RA14	—	—	—	RA10	RA9	—	RA7	RA6	RA5	RA4	RA3	RA2	RA1	RA0	xxxx
0030	ATA	31:16	———	———	———	———	0000
0030	ATA	15:0	LATA15	LATA14	—	—	—	LATA10	LATA9	—	LATA7	LATA6	LATA5	LATA4	LATA3	LATA2	LATA1	LATA0	xxxx
0040	ODCA	31:16	———	———	———	———	0000
0040	ODCA	15:0	ODCA15	ODCA14	—	—	—	ODCA10	ODCA9	—	ODCA7	ODCA6	ODCA5	ODCA4	ODCA3	ODCA2	ODCA1	ODCA0	0000
0050	CNPUA	31:16	———	———	———	———	0000
0050	CNPUA	15:0	CNPUA15	CNPUA14	—	—	—	CNPUA10	CNPUA9	—	CNPUA7	CNPUA6	CNPUA5	CNPUA4	CNPUA3	CNPUA2	CNPUA1	CNPUA0	0000
0060	CNPDA	31:16	———	———	———	———	0000
0060	CNPDA	15:0	CNPDA15	CNPDA14	—	—	—	CNPDA10	CNPDA9	—	CNPDA7	CNPDA6	CNPDA5	CNPDA4	CNPDA3	CNPDA2	CNPDA1	CNPDA0	0000
0070	CNCONA	31:16	———	———	———	———	0000
0070	CNCONA	15:0	ON	—	SIDL	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0080	CNENA	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0080	CNENA	15:0	CNIEA15	CNIEA14	—	—	—	CNIEA10	CNIEA9	—	CNIEA7	CNIEA6	CNIEA5	CNIEA4	CNIEA3	CNIEA2	CNIEA1	CNIEA0	0000
0090	CNSTATA	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0090	CNSTATA	15:0	CN STATA15	CN STATA14	———			CN STATA10	CN STATA9	—	CN STATA7	CN STATA6	CN STATA5	CN STATA4	CN STATA3	CN STATA2	CN STATA1	CN STATA0	0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-4: PORTB REGISTER MAP

Virtual Address (BF86 #)	Register Name(1)	Bit Range	Bits																	All Resets
Virtual Address (BF86 #)	Register Name(1)	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0		All Resets
0100	ANSELB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0100	ANSELB	15:0	ANSB15	ANSB14	ANSB13	ANSB12	ANSB11	ANSB10	ANSB9	ANSB8	ANSB7	ANSB6	ANSB5	ANSB41	ANSB3	ANSB2	ANSB1	ANSB0	PPTFF
0110	TRISB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0110	TRISB	15:0	TRISB15	TRISB14	TRISB13	TRISB12	TRISB11	TRISB10	TRISB9	TRISB8	TRISB7	TRISB6	TRISB5	TRISB4	TRISB3	TRISB2	TRISB1	TRISB0	PPTFF
0120	PORTB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0120	PORTB	15:0	RB15	RB14	RB13	RB12	RB11	RB10	RB9	RB8	RB7	RB6	RB5	RB4	RB3	RB2	RB1	RB0	xxxx
0130	LATB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0130	LATB	15:0	LATB15	LATB14	LATB13	LATB12	LATB11	LATB10	LATB9	LATB8	LATB7	LATB6	LATB5	LATB4	LATB3	LATB2	LATB1	LATB0	xxxx
0140	ODCB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0140	ODCB	15:0	ODCB15	ODCB14	ODCB13	ODCB12	ODCB11	ODCB10	ODCB9	ODCB8	ODCB7	ODCB6	ODCB5	ODCB4	ODCB3	ODCB2	ODCB1	ODCB0	0000
0150	CNPUB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0150	CNPUB	15:0	CNPUB15	CNPUB14	CNPUB13	CNPUB12	CNPUB11	CNPUB10	CNPUB9	CNPUB8	CNPUB7	CNPUB6	CNPUB5	CNPUB4	CNPUB3	CNPUB2	CNPUB1	CNPUB0	0000
0160	CNPDB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0160	CNPDB	15:0	CNPDB15	CNPDB14	CNPDB13	CNPDB12	CNPDB11	CNPDB10	CNPDB9	CNPDB8	CNPDB7	CNPDB6	CNPDB5	CNPDB4	CNPDB3	CNPDB2	CNPDB1	CNPDB0	0000
0170	CNCONB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0170	CNCONB	15:0	ON	—	SIDL	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0180	CNENB	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0180	CNENB	15:0	CNIEB15	CNIEB14	CNIEB13	CNIEB12	CNIEB11	CNIEB10	CNIEB9	CNIEB8	CNIEB7	CNIEB6	CNIEB5	CNIEB4	CNIEB3	CNIEB2	CNIEB1	CNIEB0	0000
0190	CNSTATE	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0190	CNSTATE	15:0	CN STATB15	CN STATB14	CN STATB13	CN STATB12	CN STATB11	CN STATB10	CN STATB9	CN STATB8	CN STATB7	CN STATB6	CN STATB5	CN STATB4	CN STATB3	CN STATB2	CN STATB1	CN STATB0	0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as 'c'; Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-5: PORTC REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY

TABLE 12-6: PORTC REGISTER MAP FOR 64-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-7: PORTD REGISTER MAP FOR 124-PIN AND 144-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as "0"; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-8: PORTD REGISTER MAP FOR 100-PIN DEVICES ONLY

TABLE 12-9: PORTD REGISTER MAP FOR 64-PIN DEVICES ONLY

TABLE 12-10: PORTE REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-11: PORTE REGISTER MAP FOR 64-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as °0; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-12: PORTF REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY

TABLE 12-13: PORTF REGISTER MAP FOR 64-PIN DEVICES ONLY

TABLE 12-14: PORTG REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-15: PORTG REGISTER MAP FOR 64-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as 00; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-16: PORTH REGISTER MAP FOR 124-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as 'c'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-17: PORTH REGISTER MAP FOR 144-PIN DEVICES ONLY

Virtual Address (BF66_#)	Register Name(1)	Bit Range	Bits																All Resets
Virtual Address (BF66_#)	Register Name(1)	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
0700	ANSELH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0700	ANSELH	15:0	—	—	—	—	—	—	—	—	—	ANSH6	ANSH5	ANSH4	—	—	ANSH1	ANSH0	0073
0710	TRISH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0710	TRISH	15:0	TRISH15	TRISH14	TRISH13	TRISH12	TRISH11	TRISH10	TRISH9	TRISH8	TRISH7	TRISH6	TRISH5	TRISH4	TRISH3	TRISH2	TRISH1	TRISH0	PFFT
0720	PORTH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0720	PORTH	15:0	RH15	RH14	RH13	RH12	RH11	RH10	RH9	RH8	RH7	RH6	RH5	RH4	RH3	RH2	RH1	RH0	xxxxx
0730	LATH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0730	LATH	15:0	LATH15	LATH14	LATH13	LATH12	LATH11	LATH10	LATH9	LATH8	LATH7	LATH6	LATH5	LATH4	LATH3	LATH2	LATH1	LATH0	xxxxx
0740	ODCH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0740	ODCH	15:0	ODCH15	ODCH14	ODCH13	ODCH12	ODCH11	ODCH10	ODCH9	ODCH8	ODCH7	ODCH6	ODCH5	ODCH4	ODCH3	ODCH2	ODCH1	ODCH0	0000
0750	CNPUH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0750	CNPUH	15:0	CNPUH15	CNPUH14	CNPUH13	CNPUH12	CNPUH11	CNPUH10	CNPUH9	CNPUH8	CNPUH7	CNPUH6	CNPUH5	CNPUH4	CNPUH3	CNPUH2	CNPUH1	CNPUH0	0000
0760	CNPDH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0760	CNPDH	15:0	CNPDH15	CNPDH14	CNPDH13	CNPDH12	CNPDH11	CNPDH10	CNPDH9	CNPDH8	CNPDH7	CNPDH6	CNPDH5	CNPDH4	CNPDH3	CNPDH2	CNPDH1	CNPDH0	0000
0770	CNCONH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0770	CNCONH	15:0	ON	—	SIDL	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0780	CNENH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0780	CNENH	15:0	CNIEH15	CNIEH14	CNIEH13	CNIEH12	CNIEH11	CNIEH10	CNIEH9	CNIEH8	CNIEH7	CNIEH6	CNIEH5	CNIEH4	CNIEH3	CNIEH2	CNIEH1	CNIEH0	0000
0790	CNSTATH	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0790	CNSTATH	15:0	CNSTATH15	CNSTATH14	CNSTATH13	CNSTATH12	CNSTATH11	CNSTATH10	CNSTATH9	CNSTATH8	CNSTATH7	CNSTATH6	CNSTATH5	CNSTATH4	CNSTATH3	CNSTATH2	CNSTATH1	CNSTATH0	0000

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-18: PORTJ REGISTER MAP FOR 124-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-19: PORTJ REGISTER MAP FOR 144-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-20: PORTK REGISTER MAP FOR 144-PIN DEVICES ONLY

Legend: x = Unknown value on Reset; — = Unimplemented, read as '0'; Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 12-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: This register is not available on 64-pin devices.
2: This register is not available on devices without a CAN module.

TABLE 12-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
1: This register is not available on 64-pin devices
2: This register is not available on devices without a CAN module.

TABLE 12-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)

Virtual Address (BF80 #)	Register Name	Bit Range	Bits																All Resets
Virtual Address (BF80 #)	Register Name	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
14DC	SS6R (1)	31:16	——	——	——	——	—	0000
14DC	SS6R (1)	15:0	——	——	——	——	—	SS6R<3:0>0000
14E0	C1RXR (2)	31:16	——	——	——	——	——	0000
14E0	C1RXR (2)	15:0	——	——	——	——			C		1		R		X	R		<
14E4	C2RXR (2)	31:16	——	——	——	——	——	0000
14E4	C2RXR (2)	15:0	——	——	——	——			C		2		R		X	R		<
14E8	REFCLKI1R	31:16	——	——	——	——	——	0000
14E8	REFCLKI1R	15:0	—	—	—	—	—	—	—	—	—	—	—	—	—	REFCLKI1R<3:0>			0000
14F0	REFCLKI3R	31:16	——	——	——	——	——	0000
14F0	REFCLKI3R	15:0	—	—	—	—	—	—	—	—	—	—	—	—	—	REFCLKI3R<3:0>			0000
14F4	REFCLKI4R	31:16	——	——	——	——	——	0000
14F4	REFCLKI4R	15:0	—	—	—	—	—	—	—	—	—	—	—	—	—	REFCLKI4R<3:0>			0000

TABLE 12-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP

TABLE 12-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as 'D'. Reset values are shown in hexadecimal.
1: This register is not available on 64-pin devices.
2: This register is not available on 64-pin and 100-pin devices.

TABLE 12-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — —	—	—
7:0	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	—	[pin name]R<3:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-4 Unimplemented: Read as '0'

bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits

Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 12-1 for input pin selection values.

Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — —	—	—
7:0	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	— — —	—		RPnR<3:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-4 Unimplemented: Read as '0'

bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits

See Table 12-2 for output pin selection values.

Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	R/W-0	U-0	R/W-0	U-0 U-0 U-0	U-0 U-0
15:8	ON	—	SIDL	—	—	—	—	—
7:0	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
7:0	— — —	— — —	—	—

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Change Notice (CN) Control ON bit

1 = CN is enabled

0 = CN is disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Control bit

1 = CPU Idle mode halts CN operation

0 = CPU Idle mode does not affect CN operation

bit 12-0 Unimplemented: Read as '0'

NOTES:

13.0 TIMER1

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS60001105), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

PIC32MZ EC devices feature one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for real-time clock applications.

The following modes are supported by Timer1:

• Synchronous Internal Timer
- Synchronous Internal Gated Timer
• Synchronous External Timer
- Asynchronous External Timer

13.1 Additional Supported Features

Selectable clock prescaler
Timer operation during Sleep and Idle modes
Fast bit manipulation using CLR, SET, and INV registers
Asynchronous mode can be used with the S osc to function as a real-time clock
ADC event trigger

FIGURE 13-1: TIMER1 BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - Additional Supported Features - 1

flowchart

graph TD
    A["Trigger to ADC"] --> B["Equal"]
    B --> C["PR1"]
    C --> D["16-bit Comparator"]
    D --> E["TMR1"]
    E --> F["TSYNC"]
    F --> G["Sync"]
    G --> H["T1IF Event Flag"]
    H --> I["TGATE"]
    I --> J["Q"]
    J --> K["D"]
    K --> L["TGATE"]
    L --> M["TCS"]
    M --> N["ON"]
    N --> O["Prescaler 1, 8, 64, 256"]
    O --> P["TCKPS<1:0>"]
    Q["SOSCO/T1CK"] --> R["SOSCEN(1)"]
    S["SOSCI"] --> T["SOSCEN(1)"]
    R --> U["Gate Sync"]
    T --> V["Gate Sync"]
    U --> W["PBCLK3"]
    V --> X["AND Gate"]
    W --> Y["x 1"]
    X --> Z["x 1"]
    Y --> AA["0 0"]
    Z --> AB["0 0"]

Note 1: The default state of the SOSCEN bit (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1.

13.2 Timer1 Control Register

TABLE 13-1: TIMER1 REGISTER MAP

Virtual Address(BF84 #)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

0000

T1CON

31:16

——

0000

15:0

—

SIDL

TWDIS

TWIP

—

TGATE

—

TCKPS<1:0>

—

TSYNC

TCS

—

0000

0010

TMR1

31:16

——

0000

15:0

TMR1<15:0>

0000

0020

PR1

31:16

——

0000

15:0

PR1<15:0>

FFFF

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	R/W-0	U-0	R/W-0	R/W-0	R-0	U-0	U-0	U-0
15:8	ON	—	SIDL	TWDIS	TWIP	—	—	—
7:0	R/W-0	U-0	R/W-0	R/W-0	U-0	R/W-0	R/W-0	U-0
7:0	TGATE	—	TCKPS<1:0>		—	TSYNC	TCS	—

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Timer On bit

1 = Timer is enabled
0 = Timer is disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode

bit 12 TWDIS: Asynchronous Timer Write Disable bit

1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)

bit 11 TWIP: Asynchronous Timer Write in Progress bit

In Asynchronous Timer mode:

1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as '0'.

bit 10-8 Unimplemented: Read as '0'

bit 7 TGATE: Timer Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled

bit 6 Unimplemented: Read as '0'

bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits

11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value

bit 3 Unimplemented: Read as '0'

REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)

bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit

When TCS = 1:

1 = External clock input is synchronized

0 = External clock input is not synchronized

When TCS = 0:

This bit is ignored.

bit 1 TCS: Timer Clock Source Select bit

1 = External clock from T1CKI pin

0 = Internal peripheral clock

bit 0 Unimplemented: Read as '0'

14.0 TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS60001105), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

This family of devices features eight synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events.

The following modes are supported:

Synchronous internal 16-bit timer
Synchronous internal 16-bit gated timer
Synchronous external 16-bit timer

Four 32-bit synchronous timers are available by combining Timer2 with Timer3, Timer4 with Timer5, Timer6 with Timer7, and Timer8 with Timer9.

The 32-bit timers can operate in one of three modes:

Synchronous internal 32-bit timer
Synchronous internal 32-bit gated timer
Synchronous external 32-bit timer

14.1 Additional Features

Selectable clock prescaler
Timers operational during CPU idle
Time base for Input Capture and Output Compare modules (Timer2 through Timer7 only)
ADC event trigger (Timer3 and Timer5 only)
Fast bit manipulation using CLR, SET, and INV registers

FIGURE 14-1: TIMER2 THROUGH TIMER9 BLOCK DIAGRAM (16-BIT)
Microchip PIC32MZ1024ECM124 - Additional Features - 1

flowchart

graph TD
    A["Trigger to ADC(1)"] --> B["Equal"]
    B --> C["TMRx"]
    C --> D["Comparator x 16"]
    D --> E["PRx"]
    E --> F["Sync"]
    F --> G["Prescaler 1, 2, 4, 8, 16, 32, 64, 256"]
    G --> H["TCKPS"]
    I["TxIF Event Flag"] --> J["0/1 TGATE"]
    J --> K["Q/Q̅"]
    K --> L["x 1"]
    L --> M["Gate Sync"]
    M --> N["PBCLK3"]
    N --> O["x 1"]
    O --> P["TGATE"]
    Q["TxCK"] --> R["×"]
    R --> S["Gate Sync"]
    S --> T["x 1"]
    T --> U["TCS"]
    U --> V["ON"]
    V --> W["Prescaler"]
    X["Reset"] --> C

Note 1: The ADC event trigger is available on Timer3 and Timer5 only.

FIGURE 14-2: TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 BLOCK DIAGRAM (32-BIT)
Microchip PIC32MZ1024ECM124 - Additional Features - 2

flowchart

graph TD
    A["ADC Event Trigger(1)"] --> B["Equal"]
    B --> C["TyIF Event Flag(2)"]
    C --> D["TGATE"]
    D --> E["Q D̅"]
    E --> F["x 1"]
    F --> G["Gate Sync"]
    G --> H["PBCLK3"]
    H --> I["0 0"]
    I --> J["x 1"]
    J --> K["TGATE"]
    K --> L["TCS"]
    L --> M["ON"]
    M --> N["Prescaler 1, 2, 4, 8, 16, 32, 64, 256"]
    N --> O["TCKPS"]
    P["Reset"] --> Q["TMRy(2) TMRx(2)"]
    Q --> R["Sync"]
    R --> S["TS"]
    S --> T["PRx(2)"]
    T --> U["3"]
    U --> V["TXCK(2)"]
    V --> W["Gate Sync"]
    W --> X["x 1"]
    X --> Y["x 1"]
    Y --> Z["x 1"]
    Z --> AA["x 1"]
    AA --> AB["x 1"]
    AB --> AC["x 1"]
    AC --> AD["x 1"]
    AD --> AE["x 1"]
    AE --> AF["x 1"]
    AF --> AG["x 1"]
    AG --> AH["x 1"]
    AH --> AI["x 1"]
    AI --> AJ["x 1"]
    AJ --> AK["x 1"]
    AK --> AL["x 1"]
    AL --> AM["x 1"]
    AM --> AN["x 1"]
    AN --> AO["x 1"]
    AO --> AP["x 1"]
    AP --> AQ["x 1"]
    AQ --> AR["x 1"]
    AR --> AS["x 1"]

Note 1: ADC event trigger is available only on the Timer2/3 and Timer4/5 pairs. 2: In this diagram, 'x' represents Timer2, 4, 6, or 8, and 'y' represents Timer3, 5, 7, or 9.

14.2 Timer2-Timer9 Control Registers

TABLE 14-1: TIMER2 THROUGH TIMER9 REGISTER MAP

Virtual Address(BF84 #)	Register Name(1)	Bit Range	Bits																All Resets
Virtual Address(BF84 #)	Register Name(1)	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
0200	T2CON	31:16	——	——	——	——	0000
0200	T2CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			T32	—	TCS	—	0000
0210	TMR2	31:16	——	——	——	——	0000
0210	TMR2	15:0	TMR2<15:0>																0000
0220	PR2	31:16	——	——	——	——	0000
0220	PR2	15:0	PR2<15:0>																FFFF
0400	T3CON	31:16	——	——	——	——	0000
0400	T3CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			—	—	TCS	—	0000
0410	TMR3	31:16	——	——	——	——	0000
0410	TMR3	15:0	TMR3<15:0>																0000
0420	PR3	31:16	——	——	——	——	0000
0420	PR3	15:0	PR3<15:0>																FFFF
0600	T4CON	31:16	——	——	——	——	0000
0600	T4CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			T32	—	TCS	—	0000
0610	TMR4	31:16	——	——	——	——	0000
0610	TMR4	15:0	TMR4<15:0>																0000
0620	PR4	31:16	——	——	——	——	0000
0620	PR4	15:0	PR4<15:0>																FFFF
0800	T5CON	31:16	——	——	——	——	0000
0800	T5CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			—	—	TCS	—	0000
0810	TMR5	31:16	——	——	——	——	0000
0810	TMR5	15:0	TMR5<15:0>																0000
0820	PR5	31:16	——	——	——	——	0000
0820	PR5	15:0	PR5<15:0>																FFFF
0A00	T6CON	31:16	——	——	——	——	0000
0A00	T6CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			T32	—	TCS	—	0000
0A10	TMR6	31:16	——	——	——	——	0000
0A10	TMR6	15:0	TMR2<15:0>																0000
0A20	PR6	31:16	——	——	——	——	0000
0A20	PR6	15:0	PR2<15:0>																FFFF
0C00	T7CON	31:16	——	——	——	——	0000
0C00	T7CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			—	—	TCS	—	0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 14-1: TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED)

Virtual Address(BF84 #)	Register Name(1)	Bit Range	Bits																All Resets
Virtual Address(BF84 #)	Register Name(1)	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
0C10	TMR7	31:16	——	——	——	——	0000
0C10	TMR7	15:0	TMR3<15:0> 0000
0C20	PR7	31:16	——	——	——	——	0000
0C20	PR7	15:0	PR3<15:0> PFFF
0E00	T8CON	31:16	——	——	——	——	0000
0E00	T8CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			T32	—	TCS	—	0000
0E10	TMR8	31:16	——	——	——	——	0000
0E10	TMR8	15:0	TMR4<15:0> 0000
0E20	PR8	31:16	——	——	——	——	0000
0E20	PR8	15:0	PR4<15:0> PFFF
1000	T9CON	31:16	——	——	——	——	0000
1000	T9CON	15:0	ON	—	SIDL	—	—	—	—	—	TGATE	TCKPS<2:0>			—	—	TCS	—	0000
1010	TMR9	31:16	——	——	——	——	0000
1010	TMR9	15:0	TMR5<15:0> 0000
1020	PR9	31:16	——	——	——	——	0000
1020	PR9	15:0	PR5<15:0> PFFF

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	R/W-0 U-0 R/W-0	R/W-0 U-0 U-0 U-0	U-0 U-0
15:8	ON(1)	—	SIDL(2)	— — —	— —
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	U-0	R/W-0	U-0
7:0	TGATE(1)	TCKPS<2:0>(1)			T32(3)	—	TCS(1)	—

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Timer On bit ^(1)

1 = Module is enabled

0 = Module is disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit ^(2)

1 = Discontinue operation when device enters Idle mode

0 = Continue operation even in Idle mode

bit 12-8 Unimplemented: Read as '0'

bit 7 TGATE: Timer Gated Time Accumulation Enable bit ^(1)

When TCS = 1:

This bit is ignored and is read as '0'.

When TCS = 0:

1 = Gated time accumulation is enabled

0 = Gated time accumulation is disabled

bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits ^(1)

111 = 1:256 prescale value

110 = 1:64 prescale value

101 = 1:32 prescale value

100 = 1:16 prescale value

011 = 1:8 prescale value

010 = 1:4 prescale value

001 = 1:2 prescale value

000 = 1:1 prescale value

bit 3 T32: 32-Bit Timer Mode Select bit ^(3)

1 = Odd numbered and even numbered timers form a 32-bit timer

0 = Odd numbered and even numbered timers form a separate 16-bit timer

Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5, Timer7, and Timer9). All timer functions are set through the even numbered timers.

2: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode.

3: This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).

REGISTER 14-1: TxCON: TYPE B TIMER CONTROL REGISTER ('x' = 2-9) (CONTINUED)

bit 2 Unimplemented: Read as '0'

bit 1 TCS: Timer Clock Source Select bit (1)

1 = External clock from TxCK pin

0 = Internal peripheral clock

bit 0 Unimplemented: Read as '0'

Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5, Timer7, and Timer9). All timer functions are set through the even numbered timers.

2: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode.

3: This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).

15.0 DEADMAN TIMER (DMT)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. "Watchdog, Deadman, and Power-up Timers" (DS60001114), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The primary function of the Deadman Timer (DMT) is to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. Instructions are not fetched when the processor is in Sleep mode.

The DMT consists of a 32-bit counter with a time-out count match value as specified by the DMTCNT<3:0> bits in the DEVCFG1 Configuration register.

A Deadman Timer is typically used in mission critical and safety critical applications, where any single failure of the software functionality and sequencing must be detected.

Figure 15-1 shows a block diagram of the Deadman Timer module.

FIGURE 15-1: DEADMAN TIMER BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - DEADMAN TIMER (DMT) - 1

flowchart

graph TD
    A["&quot;Improper sequence&quot; flag"] --> B["Instruction Fetched Strobe"]
    B --> C["System Reset"]
    C --> D{32-bit counter}
    D -->|32| E["(COUNTER) = DMT Max Count^(1)"]
    D -->|32| F["(COUNTER) ≥ DMT Window Interval^(2)"]
    F --> G["Window Interval Open"]
    H["Counter Initialization Value"] --> D
    I["ON"] --> J["Force DMT Event"]
    J --> D
    K["&quot;Proper Clear Sequence&quot; Flag"] --> L["Clock"]
    L --> M["32-bit counter"]
    N["PBCLK7"] --> O["Clock"]
    P["System Reset"] --> Q["DMT Count Reset Load"]
    Q --> D
    R["ON"] --> S["DMT event to NMI^(3)"]
    S --> D

Note 1: DMT Max Count is controlled by the DMTCNT<3:0> bits in the DEVCFG1 Configuration register.
2: DMT Window Interval is controlled by the DMTINTV<2:0> bits in the DEVCFG1 Configuration register.
3: Refer to Section 6.0 "Resets" for more information.

15.1 Deadman Timer Control Registers

TABLE 15-1: DEADMAN TIMER REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'u'. Reset values are shown in hexadecimal.

R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Deadman Timer Module Enable bit ^(1)

1 = Deadman Timer module is enabled
0 = Deadman Timer module is disabled

bit 13-0 Unimplemented: Read as '0'

Note 1: This bit only has control when FDMTEN (DEVCFG1<3>) = 0.

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	—— —	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	—— —	—— — — — —
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	STEP1<7:0>
7:0	U-0 U-0 U-0	U-0 U-0 U-0	U-0
7:0	—— —	—— — — — —

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-8 STEP1<7:0>: Preclear Enable bits

01000000 = Enables the Deadman Timer Preclear (Step 1)

All other write patterns = Set BAD1 flag.

These bits are cleared when a DMT reset event occurs. STEP1<7:0> is also cleared if the

STEP2<7:0> bits are loaded with the correct value in the correct sequence.

bit 7-0 Unimplemented: Read as '0'

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
15:8	— — —	— — — — —
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	STEP2<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-8

Unimplemented: Read as '0'

bit 7-0

STEP2<7:0>: Clear Timer bits

00001000 = Clears STEP1<7:0>, STEP2<7:0> and the Deadman Timer if, and only if, preceded by correct loading of STEP1<7:0> bits in the correct sequence. The write to these bits may be verified by reading DMTCNT and observing the counter being reset.

All other write patterns = Set BAD2 bit, the value of STEP1<7:0> will remain unchanged, and the new value being written STEP2<7:0> will be captured. These bits are also cleared when a DMT reset event occurs.

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— —	—	— —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— —	—	— —
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
15:8	— — —	— —	—	— —
7:0	R-0, HC	R-0, HC	R-0, HC	R/W-0	R/W-0	R/W-0	R/W-0	R-0
7:0	BAD1	BAD2	DMTEVENT					WINOPN

Legend:	HC = Hardware Cleared
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-8 Unimplemented: Read as '0'

bit 7 BAD1: Bad STEP1<7:0> Value Detect bit

1 = Incorrect STEP1<7:0> value was detected

0 = Incorrect STEP1<7:0> value was not detected

bit 6 BAD2: Bad STEP2<7:0> Value Detect bit

1 = Incorrect STEP2<7:0> value was detected

0 = Incorrect STEP2<7:0> value was not detected

bit 5 DMTEVENT: Deadman Timer Event bit

1 = Deadman timer event was detected (counter expired or bad STEP1<7:0> or STEP2<7:0> value was entered prior to counter increment)

0 = Deadman timer even was not detected

bit 4-1 Unimplemented: Read as '0'

bit 0 WINOPN: Deadman Timer Clear Window bit

1 = Deadman timer clear window is open

0 = Deadman timer clear window is not open

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24	COUNTER<31:24>
23:16	R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16	COUNTER<23:16>
15:8	R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8	COUNTER<15:8>
7:0	R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0	COUNTER<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-8

COUNTER<31:0>: Read current contents of DMT counter

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	R-0 R-0 R-0		R-0 R-0 R-0 R-0 R-0
	PSCNT<31:24>
23:16	R-0 R-0 R-0		R-0 R-0 R-0 R-0 R-0
	PSCNT<23:16>
15:8	R-0 R-0 R-0		R-0 R-0 R-0 R-0 R-0
	PSCNT<15:8>
7:0	R-0	R-0	R-0	R-y	R-y	R-y	R-y	R-y
	PSCNT<7:0>

Legend:		y = Value set from Configuration bits on POR
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 PSCNT<31:0>: DMT Instruction Count Value Configuration Status bits

This is always the value of the DMTCNT<3:0> bits in the DEVCFG1 Configuration register.

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24	PSINTV<31:24>
23:16	R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16	PSINTV<23:16>
15:8	R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8	PSINTV<15:8>
7:0	R-0 R-0 R-0 R-0 R-0 R-y R-y
7:0	PSINTV<7:0>

Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-8 PSINTV<31:0>: DMT Window Interval Configuration Status bits

This is always the value of the DMTINTV<2:0> bits in the DEVCFG1 Configuration register.

NOTES:

16.0 WATCHDOG TIMER (WDT)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

When enabled, the Watchdog Timer (WDT) operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode.

Some of the key features of the WDT module are:

Configuration or software controlled
User-configurable time-out period
Can wake the device from Sleep or Idle

FIGURE 16-1: WATCHDOG TIMER BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - WATCHDOG TIMER (WDT) - 1

flowchart

graph TD
    A["Reset Event"] --> B["WDT Counter Reset"]
    C["ON"] --> B
    D["ON"] --> B
    E["ON"] --> B
    F["AND"] --> B
    G["LPRC"] --> H["Clock"]
    H --> I["25-bit Counter"]
    I --> J["25"]
    J --> K["Decoder"]
    K --> L["FWDTPS<4:0> (DEVCFG1<20:16>)"]
    M["Power Save"] --> N["0/1"]
    N --> O["WDT Event to NMI(1)"]
    P["25"] --> Q["AND"]
    Q --> I

Note 1: Refer to Section 6.0 "Resets" for more information.

16.1 Watchdog Timer Control Registers

TABLE 16-1: WATCHDOG TIMER REGISTER MAP

Virtual Address (BF80 #)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

0800

WDTCON (1)

31:16

WDTCLRKEY<15:0>

0000

15:0

—

SWDTPS<4:0>

WDTWINEN

—

x0xx

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	W-0 W-0 W-0 W-0 W-0 W-0 W-0
31:24	WDTCLRKEY<15:8>
23:16	W-0 W-0 W-0 W-0 W-0 W-0 W-0
23:16	WDTCLRKEY<7:0>
15:8	R/W-y U-0 U-0 U-0 U-0 U-0 U-0
15:8	ON(1)	— — —	—	—	—	—
7:0	U-0 R-y R-y R-y R-y R-W-0			U-0
7:0	—	SWDTPS<4:0>					WDTWINEN	—

Legend:	y = Values set from Configuration bits on POR
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 WDTCLRKEY<15:0>: Watchdog Timer Clear Key bits

To clear the Watchdog Timer to prevent a time-out, software must write the value 0x5743 to this location using a single 16-bit write.

bit 15 ON: Watchdog Timer Enable bit ^(1)

1 = The WDT is enabled

0 = The WDT is disabled

bit 14-7 Unimplemented: Read as '0'

bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits On reset, these bits are set to the values of the WDTPS <4:0> Configuration bits in DEVCFG1.

bit 1 WDTWINEN: Watchdog Timer Window Enable bit

1 = Enable windowed Watchdog Timer

0 = Disable windowed Watchdog Timer

bit 0 Unimplemented: Read as '0'

Note 1: This bit only has control when FWDTEN (DEVCFG1<23>) = 0.

NOTES:

17.0 INPUT CAPTURE

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Input Capture" (DS60001122), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Input Capture module is useful in applications requiring frequency (period) and pulse measurement.

The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin.

Capture events are caused by the following:

• Capture timer value on every edge (rising and falling), specified edge first
• Prescaler capture event modes:

- Capture timer value on every 4th rising edge of input at ICx pin

- Capture timer value on every 16th rising edge of input at ICx pin

Each input capture channel can select between one of six 16-bit timers for the time base, or two of six 16-bit timers together to form a 32-bit timer. The selected timer can use either an internal or external clock.

Other operational features include:

• Device wake-up from capture pin during Sleep and Idle modes
- Interrupt on input capture event
- 4-word FIFO buffer for capture values; Interrupt optionally generated after 1, 2, 3, or 4 buffer locations are filled
- Input capture can also be used to provide additional sources of external interrupts

FIGURE 17-1: INPUT CAPTURE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - INPUT CAPTURE - 1

flowchart

graph TD
    A["ICx(1)"] --> B["Specified/Every Edge Mode"]
    B --> C["Prescaler Mode (16th Rising Edge)"]
    C --> D["Prescaler Mode (4th Rising Edge)"]
    D --> E["Rising Edge Mode"]
    E --> F["Falling Edge Mode"]
    F --> G["Edge Detection Mode"]
    G --> H["Sleep/Idle Wake-up Mode"]
    H --> I["ICM<2:0>"]
    I --> J["ICX(1)"]
    J --> K["Specified/Every Edge Mode"]
    K --> L["Prescaler Mode (16th Rising Edge)"]
    L --> M["Prescaler Mode (4th Rising Edge)"]
    M --> N["Rising Edge Mode"]
    N --> O["Falling Edge Mode"]
    O --> P["Edge Detection Mode"]
    P --> Q["Sleep/Idle Wake-up Mode"]
    Q --> R["ICM<2:0>"]
    R --> S["Set Flag ICxIF(1) (In IFSx Register)"]
    S --> T["To CPU"]
    T --> U["FIFO Control"]
    U --> V["ICxBUF(1)"]
    V --> W["ICI<1:0>"]
    W --> X["/N"]
    X --> Y["ICM<2:0>"]
    Y --> Z["To CPU"]
    Z --> AA["PBCLK3"]
    AA --> AB["C32/ICTMR"]
    AB --> AC["Timerx(2)"]
    AC --> AD["Timery(2)"]
    AD --> AE["ICM<2:0>"]
    AE --> AF["To CPU"]
    AF --> AG["To CPU"]
    AG --> AH["To CPU"]
    AH --> AI["To CPU"]
    AI --> AJ["To CPU"]
    AJ --> AK["To CPU"]

The timer source for each Input Capture module depends on the setting of the ICACLK bit in the CFGCON register. The available configurations are shown in Table 17-1.

TABLE 17-1: TIMER SOURCE CONFIGURATIONS

Input Capture Module	Timerx Timery
ICACLK (CFGCON<17>) = 0
IC1	Timer2	Timer3
.	.	.
.	.	.
IC9	Timer 2	Timer 3
ICACLK (CFGCON<17>) = 1
IC1 Timer4	Timer5
IC2 Timer4	Timer5
IC3 Timer4	Timer5
IC4 Timer2	Timer3
IC5 Timer2	Timer3
IC6 Timer2	Timer3
IC7 Timer6	Timer7
IC8 Timer6	Timer7
IC9 Timer6	Timer7

17.1 Input Capture Control Registers

TABLE 17-2: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — — —	—
15:8	R/W-0 U-0	R/W-0	U-0 U-0 U-0	R/W-0	R/W-0
15:8	ON	—	SIDL	—	—	—	FEDGE	C32
7:0	R/W-0	R/W-0	R/W-0	R-0	R-0	R/W-0	R/W-0	R/W-0
7:0	ICTMR	ICI<1:0>		ICOV	ICBNE	ICM<2:0>

Legend:
R = Readable bit	W = Writable bit U = Unimplemented bit
-n = Bit Value at POR: ('0', '1', x = unknown)	P = Programmable bit	r = Reserved bit

bit 31-16	Unimplemented: Read as ‘0’
bit 15	ON: Input Capture Module Enable bit1 = Module enabled0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14	Unimplemented: Read as ‘0’
bit 13	SIDL: Stop in Idle Control bit1 = Halt in CPU Idle mode0 = Continue to operate in CPU Idle mode
bit 12-10	Unimplemented: Read as ‘0’
bit 9	FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)1 = Capture rising edge first0 = Capture falling edge first
bit 8 C32: 32-bit Capture Select bit
	1 = 32-bit timer resource capture0 = 16-bit timer resource capture
bit 7	ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)(1)0 = Timery is the counter source for capture1 = Timerx is the counter source for capture
bit 6-5	ICI<1:0>: Interrupt Control bits11 = Interrupt on every fourth capture event10 = Interrupt on every third capture event01 = Interrupt on every second capture event00 = Interrupt on every capture event
bit 4	ICOV: Input Capture Overflow Status Flag bit (read-only)1 = Input capture overflow occurred0 = No input capture overflow occurred
bit 3	ICBNE: Input Capture Buffer Not Empty Status bit (read-only)1 = Input capture buffer is not empty; at least one more capture value can be read0 = Input capture buffer is empty
bit 2-0	ICM<2:0>: Input Capture Mode Select bits111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter101 = Prescaled Capture Event mode – every sixteenth rising edge100 = Prescaled Capture Event mode – every fourth rising edge011 = Simple Capture Event mode – every rising edge010 = Simple Capture Event mode – every falling edge001 = Edge Detect mode – every edge (rising and falling)000 = Input Capture module is disabled

Note 1: Refer to Table 17-1 for Timerx and Timery selections.

18.0 OUTPUT COMPARE

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. "Output Compare" (DS60001111), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Output Compare module is used to generate a single pulse or a train of pulses in response to selected time base events.

For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer.

When a match occurs, the Output Compare module generates an event based on the selected mode of operation.

The following are some of the key features:

Multiple Output Compare modules in a device
Programmable interrupt generation on compare event
Single and Dual Compare modes
Single and continuous output pulse generation
Pulse-Width Modulation (PWM) mode
Hardware-based PWM Fault detection and automatic output disable
Programmable selection of 16-bit or 32-bit time bases
Can operate from either of two available 16-bit time bases or a single 32-bit time base
ADC event trigger

FIGURE 18-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - OUTPUT COMPARE - 1

flowchart

graph TD
    A["OCxRS(1)"] --> B["Comparator"]
    C["OCxR(1)"] --> B
    D["Timerx(3)"] --> E["0 1"]
    F["Timery(3)"] --> E
    G["Timerx(3) Rollover"] --> H["0 1"]
    I["Timery(3) Rollover"] --> H
    J["Set Flag bit OCxIF(1)"] --> K["Output Logic"]
    L["OCM<2:0> Mode Select"] --> K
    M["OUTPUT Enable Logic"] --> K
    N["Trigger to ADC(4)"] --> K
    O["OCx(1)"] --> P["Output Logic"]
    Q["OCFA or OCFB(2)"] --> P
    P --> K
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style D fill:#f9f,stroke:#333
    style J fill:#f9f,stroke:#333
    style K fill:#ccf,stroke:#333
    style P fill:#ccf,stroke:#333

The timer source for each Output Compare module depends on the setting of the OCACLK bit in the CFGCON register. The available configurations are shown in Table 18-1.

TABLE 18-1: TIMER SOURCE CONFIGURATIONS

Output Compare Module	Timerx Timery
OCACLK (CFGCON<16>) = 0
OC1	Timer2	Timer3
.	.	.
.	.	.
OC9	Timer 2	Timer 3
OCACLK (CFGCON<16>) = 1
OC1 Timer4	Timer5
OC2 Timer4	Timer5
OC3 Timer4	Timer5
OC4 Timer2	Timer3
OC5 Timer2	Timer3
OC6 Timer2	Timer3
OC7 Timer6	Timer7
OC8 Timer6	Timer7
OC9 Timer6	Timer7

18.1 Output Compare Control Registers

TABLE 18-2: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP

Virtual Address (BF84_#)	Registry Name	Bit Range	Bits																All Resets
Virtual Address (BF84_#)	Registry Name	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
4000	OC1CON	31:16	——	——	——	——	——	0000
4000	OC1CON	15:0	ON	—	SIDL	—	—	—	—	—	—	—	OC32	OCFLT	OCTSEL	OCM<2:0>			0000
4010	OC1R	31:16	OC1R<31:0>																xxxxx
4010	OC1R	15:0	OC1R<31:0>																xxxxx
4020	OC1RS	31:16	OC1RS<31:0>																xxxxx
4020	OC1RS	15:0	OC1RS<31:0>																xxxxx
4200	OC2CON	31:16	——	——	——	——	——	0000
4200	OC2CON	15:0	ON	—	SIDL	—	—	—	—	—	—	—	OC32	OCFLT	OCTSEL	OCM<2:0>			0000
4210	OC2R	31:16	OC2R<31:0>																xxxxx
4210	OC2R	15:0	OC2R<31:0>																xxxxx
4220	OC2RS	31:16	OC2RS<31:0>																xxxxx
4220	OC2RS	15:0	OC2RS<31:0>																xxxxx
4400	OC3CON	31:16	——	——	——	——	——	0000
4400	OC3CON	15:0	ON	—	SIDL	—	—	—	—	—	—	—	OC32	OCFLT	OCTSEL	OCM<2:0>			0000
4410	OC3R	31:16	OC3R<31:0>																xxxxx
4410	OC3R	15:0	OC3R<31:0>																xxxxx
4420	OC3RS	31:16	OC3RS<31:0>																xxxxx
4420	OC3RS	15:0	OC3RS<31:0>																xxxxx
4600	OC4CON	31:16	——	——	——	——	——	0000
4600	OC4CON	15:0	ON	—	SIDL	—	—	—	—	—	—	—	OC32	OCFLT	OCTSEL	OCM<2:0>			0000
4610	OC4R	31:16	OC4R<31:0>																xxxxx
4610	OC4R	15:0	OC4R<31:0>																xxxxx
4620	OC4RS	31:16	OC4RS<31:0>																xxxxx
4620	OC4RS	15:0	OC4RS<31:0>																xxxxx
4800	OC5CON	31:16	——	——	——	——	——	0000
4800	OC5CON	15:0	ON	—	SIDL	—	—	—	—	—	—	—	OC32	OCFLT	OCTSEL	OCM<2:0>			0000
4810	OC5R	31:16	OC5R<31:0>																xxxxx
4810	OC5R	15:0	OC5R<31:0>																xxxxx
4820	OC5RS	31:16	OC5RS<31:0>																xxxxx
4820	OC5RS	15:0	OC5RS<31:0>																xxxxx

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 18-2: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP (CONTINUED)

Virtual Address (BF84_#)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

4A00

OC6CON

31:16

——

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

4A10

OC6R

31:16

OC6R<31:0>

xxxxx

15:0

xxxxx

4A20

OC6RS

31:16

OC6RS<31:0>

xxxxx

15:0

xxxxx

4C00

OC7CON

31:16

——

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

4C10

OC7R

31:16

OC7R<31:0>

xxxxx

15:0

xxxxx

4C20

OC7RS

31:16

OC7RS<31:0>

xxxxx

15:0

xxxxx

4E00

OC8CON

31:16

——

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

4E10

OC8R

31:16

OC8R<31:0>

xxxxx

15:0

xxxxx

4E20

OC8RS

31:16

OC8RS<31:0>

xxxxx

15:0

xxxxx

5000

OC9CON

31:16

——

0000

15:0

—

SIDL

—

OC32

OCFLT

OCTSEL

OCM<2:0>

0000

5010

OC9R

31:16

OC9R<31:0>

xxxxx

15:0

xxxxx

5020

OC9RS

31:16

OC9RS<31:0>

xxxxx

15:0

Legend: x = unknown value on Reset; — = unimplemented, read as 'u'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	R/W-0 U-0 R/W-0		U-0 U-0 U-0	U-0 U-0
15:8	ON	—	SIDL	—	—	—	—	—
7:0	U-0	U-0	R/W-0	R-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	— —	OC32	OCFLT	(1)	OCTSEL(2)	OCM<2:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Output Compare Peripheral On bit

1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation in Idle mode

bit 12-6 Unimplemented: Read as '0'

bit 5 OC32: 32-bit Compare Mode bit

1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source
0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source

bit 4 OCFLT: PWM Fault Condition Status bit ^(1)

1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred

bit 3 OCTSEL: Output Compare Timer Select bit ^(2)

1 = Timery is the clock source for this Output Compare module
0 = Timerx is the clock source for this Output Compare module

bit 2-0 OCM<2:0>: Output Compare Mode Select bits

111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current

Note 1: This bit is only used when OCM<2:0> = '111'. It is read as '0' in all other modes.

2: Refer to Table 18-1 for Timerx and Timery selections.

NOTES:

19.0 SERIAL PERIPHERAL INTERFACE (SPI) AND INTER-IC SOUND (I²S)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. "Serial Peripheral Interface (SPI)" (DS60001106), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The SPI/I²S module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices, as well as digital audio devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters (ADC), etc.

The SPI/I²S module is compatible with Motorola® SPI and SIOP interfaces.

The following are some of the key features of the SPI module:

• Master and Slave modes support
- Four different clock formats
• Enhanced Framed SPI protocol support
- User-configurable 8-bit, 16-bit and 32-bit data width
- Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width
- Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer
• Operation during Sleep and Idle modes
• Audio Codec Support:
- I²S protocol
- Left-justified
- Right-justified
- PCM

FIGURE 19-1: SPI/I ^2 S MODULE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - SERIAL PERIPHERAL INTERFACE (SPI) AND INTER-IC SOUND (I²S) - 1

flowchart

graph TD
    A["Internal Data Bus"] <--> B["SPIxBUF"]
    B <--> C["SPIxRXB FIFO"]
    B <--> D["SPIxTXB FIFO"]
    C <--> E["SPIxSR"]
    D <--> E
    E --> F["SDIx"]
    E --> G["SDOx"]
    E --> H["SSx/FSYNC"]
    E --> I["SCKx"]
    E --> J["Slave Select and Frame Sync Control"]
    J --> K["Clock Control"]
    K --> L["Edge Select"]
    L --> M["Baud Rate Generator"]
    M --> N["MCLKSEL"]
    N --> O["REFCLK01"]
    N --> P["PBCLK2"]
    Q["Write"] --> B
    R["Receive"] --> E
    S["Shift Control"] --> K
    T["MSTEN"] --> M
    U["FIFOs Share Address SPIxBUF"] --> B
    V["Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register."] --> M

19.1 SPI Control Registers

TABLE 19-1: SPI1 THROUGH SPI6 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 19-1: SPI1 THROUGH SPI6 REGISTER MAP (CONTINUED)

Virtual Address(BFB2 #)	Register Name?	Bit Range	Bits																All Resets
Virtual Address(BFB2 #)	Register Name?	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
1600	SPI4CON	31:16	FRMEN	FRMSYNC	FRMPOL	MSSEN	FRMSYPW	FRMCNT<2:0>			MCLKSEL	—	—	—	—	—	SPIFE	ENHBUF	0000
1600	SPI4CON	15:0	ON	—	SIDL	DISSDO	MODE32	MODE16	SMP	CKE	SSEN	CKP	MSTEN	DISSDI	STXISEL<1:0>		SRXISEL<1:0>		0000
1610	SPI4STAT	31:16	—	—	—	RXBUFELM<4:0>					—	—	—	TXBUFELM<4:0>					0000
1610	SPI4STAT	15:0	—	—	—	FRMERR	SPIBUSY	—	—	SPITUR	SRMT	SPIROV	SPIRBE	—	SPITBE	—	SPITBF	SPIRBF	0000
1620	SPI4BUF	31:16	DATA<31:0>																0000
1620	SPI4BUF	15:0	DATA<31:0>																0000
1630	SPI4BRG	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
1630	SPI4BRG	15:0	—	—	—	—	—	—	—	BRG<8:0>									0000
1640	SPI4CON2	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
1640	SPI4CON2	15:0	SPI SGNEXT	—	—	FRM ERREN	SPI ROVEN	SPI TUREN	IGNROV	IGNTUR	AUDEN	—	—	—	AUD MONO	—	AUDMOD<1:0>		0000
1800	SPI5CON	31:16	FRMEN	FRMSYNC	FRMPOL	MSSEN	FRMSYPW	FRMCNT<2:0>			MCLKSEL	—	—	—	—	—	SPIFE	ENHBUF	0000
1800	SPI5CON	15:0	ON	—	SIDL	DISSDO	MODE32	MODE16	SMP	CKE	SEN	CKP	MSTEN	DISSDI	STXISEL<1:0>		SRXISEL<1:0>		0000
1810	SPI5STAT	31:16	—	—	—	RXBUFELM<4:0>					—	—	—	TXBUFELM<4:0>					0000
1810	SPI5STAT	15:0	—	—	—	FRMERR	SPIBUSY	—	—	SPITUR	SRMT	SPIROV	SPIRBE	—	SPITBIE	—	SPITBF	SPIRBF	0008
1820	SPI5BUF	31:16	DATA<31:0>																0000
1820	SPI5BUF	15:0	DATA<31:0>																0000
1830	SPI5BRG	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
1830	SPI5BRG	15:0	—	—	—	—	—	—	—	BRG<8:0>									0000
1840	SPI5CON2	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
1840	SPI5CON2	15:0	SPI SGNEXT	—	—	FRM ERREN	SPI ROVEN	SPI TUREN	IGNROV	IGNTUR	AUDEN	—	—	—	AUD MONO	—
1A00	SPI6CON	31:16	FRMEN	FRMSYNC	FRMPOL	MSSEN	FRMSYPW	FRMCNT<2:0>			MCLKSEL	—	—	—	—	—	SPIFE	ENHBUF	0000
1A00	SPI6CON	15:0	ON	—	SIDL	DISSDO	MODE32	MODE16	SMP	CKE	SENN	CKP	MSTEN	DISSDI	STXISEL<1:0>		SRXISEL<1:0>		0000
1A10	SPI6STAT	31:16	—	—	—	RXBUFELM<4:0>					—	—	—	TXBUFELM<4:0>					0000
1A10	SPI6STAT	15:0	—	—	—	FRMERR	SPIBUSY	—	—	SPITUR	SRMT	SPIROV	SPIRBE	—	SPITBBIE	—	SPITBF	SPIRBF	0008
1A20	SPI6BUF	31:16	DATA<31:0>																0000
1A20	SPI6BUF	15:0	DATA<31:0>																0000
1A30	SPI6BRG	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
1A30	SPI6BRG	15:0	—	—	—	—	—	—	—	BRG<8:0>									0000
1A40	SPI6CON2	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
1A40	SPI6CON2	15:0	SPI SGNEXT	—	—	FRM ERREN	SPI ROVEN	SPI TUREN	IGNROV	IGNTUR	AUDEN	—	—	—	AUD MONO	—	—	—	0000

Legend: x = unknown value on Reset; — = unimplemented, read as 'D'. Reset values are shown in hexadecimal.
Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	FRMEN FRMSYNC FRMPOL MSSEN			FRMSYPW	FRMCNT<2:0>
23:16	R/W-0	U-0	U-0	U-0	U-0	U-0	R/W-0	R/W-0
23:16	MCLKSEL^(1)	—	—	—	—	—	SPIFE	ENHBUF^(1)
15:8	R/W-0 U-0	R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
15:8	ON	—	SIDL	DISSDO^(4)	MODE32	MODE16	SMP	CKE^(2)
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	SSEN	CKP^(3)	MSTEN	DISSDI^(4)	STXISEL<1:0>		SRXISEL<1:0>

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 FRMEN: Framed SPI Support bit

1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled

bit 30 FRMSYNC: Frame Sync Pulse Direction Control on pin bit (Framed SPI mode only)

1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)

bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)

1 = Frame pulse is active-high
0 = Frame pulse is active-low

bit 28 MSSEN: Master Mode Slave Select Enable bit

1 = Slave select SPI support enabled. The pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.

bit 27 FRMSYPW: Frame Sync Pulse Width bit

1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide

bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode.

111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character

bit 23 MCLKSEL: Master Clock Enable bit ^(1)

1 = REFCLKO1 is used by the Baud Rate Generator
0 = PBCLK2 is used by the Baud Rate Generator

bit 22-18 Unimplemented: Read as '0'

Note 1: This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for maximum clock frequency requirements.

2: This bit is not used in the Framed SPI mode. The user should program this bit to '0' for the Framed SPI mode (FRMEN = 1).
3: When AUDEN = 1, the SPI/I²S module functions as if the CKP bit is equal to '1', regardless of the actual value of the CKP bit.
4: This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see Section 12.3 "Peripheral Pin Select (PPS)" for more information).

REGISTER 19-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)

bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)

1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock

bit 16 ENHBUF: Enhanced Buffer Enable bit (1)

1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled

bit 15 ON: SPI/I ^2 S Module On bit

1 = SPI/I ^2 S module is enabled
0 = SPI/I 2S module is disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode

bit 12 DISSDO: Disable SDOx pin bit (4)

1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module

bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits

When AUDEN = 1:

MODE32 MODE16 Communication

1	1	24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
1	0	32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
0	1	16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame
0	0	16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame

When AUDEN = 0:

MODE32 MODE16 Communication

1	x	32-bit
0	1	16-bit
0	0	8-bit

bit 9 SMP: SPI Data Input Sample Phase bit

Master mode (MSTEN = 1):

1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.

bit 8 CKE: SPI Clock Edge Select bit (2)

1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)

bit 7 SSEN: Slave Select Enable (Slave mode) bit

1 = pin used for Slave mode
0 = pin not used for Slave mode, pin controlled by port function.

bit 6 CKP: Clock Polarity Select bit (3)

1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level

Note 1: This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for maximum clock frequency requirements.

REGISTER 19-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)

bit 5 MSTEN: Master Mode Enable bit

1 = Master mode

1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)

0 = SDI pin is controlled by the SPI module

bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits

11 = Interrupt is generated when the buffer is not full (has one or more empty elements)

10 = Interrupt is generated when the buffer is empty by one-half or more

01 = Interrupt is generated when the buffer is completely empty

00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete

bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits

11 = Interrupt is generated when the buffer is full

10 = Interrupt is generated when the buffer is full by one-half or more

01 = Interrupt is generated when the buffer is not empty

00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)

Note 1: This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for maximum clock frequency requirements.

2: This bit is not used in the Framed SPI mode. The user should program this bit to '0' for the Framed SPI mode (FRMEN = 1).

3: When AUDEN = 1, the SPI/I²S module functions as if the CKP bit is equal to '1', regardless of the actual value of the CKP bit.

4: This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see Section 12.3 "Peripheral Pin Select (PPS)" for more information).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	R/W-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	SPISGNEXT	—	—	FRMERREN	SPIROVEN	SPITUREN	IGNROV	IGNTUR
7:0	R/W-0	U-0	U-0	U-0	R/W-0	U-0	R/W-0	R/W-0
7:0	AUDEN(1)	— — —	AUDMONO		(1,2)	—	AUDMOD<1:0>(1,2)

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit

1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extended

bit 14-13 Unimplemented: Read as '0'

bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit

1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events

bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit

1 = Receive overflow generates error events
0 = Receive overflow does not generate error events

bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit

1 = Transmit Underrun Generates Error Events
0 = Transmit Underrun Does Not Generate Error Events

bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)

1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data
0 = A ROV is a critical error which stop SPI operation

bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)

1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stop SPI operation

bit 7 AUDEN: Enable Audio CODEC Support bit ^(1)

1 = Audio protocol enabled
0 = Audio protocol disabled

bit 6-5 Unimplemented: Read as '0'

bit 3 AUDMONO: Transmit Audio Data Format bit ^(1,2)

1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo

bit 2 Unimplemented: Read as '0'

bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bit ^(1,2)

11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I²S mode

Note 1: This bit can only be written when the ON bit = 0.

2: This bit is only valid for AUDEN = 1.

Legend: C = Clearable bit	HS = Set in hardware
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)

bit 23-21 Unimplemented: Read as '0'

bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)

bit 15-13 Unimplemented: Read as '0'

bit 12 FRMERR: SPI Frame Error status bit

1 = Frame error detected

0 = No Frame error detected

This bit is only valid when FRMEN = 1.

bit 11 SPIBUSY: SPI Activity Status bit

1 = SPI peripheral is currently busy with some transactions

0 = SPI peripheral is currently idle

bit 10-9 Unimplemented: Read as '0'

bit 8 SPITUR: Transmit Under Run bit

1 = Transmit buffer has encountered an underrun condition

0 = Transmit buffer has no underrun condition

This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling the module.

bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)

1 = When SPI module shift register is empty

0 = When SPI module shift register is not empty

bit 6 SPIROV: Receive Overflow Flag bit

1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register.

0 = No overflow has occurred

This bit is set in hardware; can only be cleared (= 0) in software.

bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)

1 = RX FIFO is empty (CRPTR = SWPTR)

0 = RX FIFO is not empty (CRPTR ≠ SWPTR)

bit 4 Unimplemented: Read as '0'

1 = Transmit buffer, SPIxTXB is empty

0 = Transmit buffer, SPIxTXB is not empty

Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.

Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.

bit 2 Unimplemented: Read as '0'

bit 1 SPITBF: SPI Transmit Buffer Full Status bit

1 = Transmit not yet started, SPITXB is full

0 = Transmit buffer is not full

Standard Buffer Mode:

Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.

Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.

Enhanced Buffer Mode:

Set when CWPTR + 1 = SRPTR; cleared otherwise

bit 0 SPIRBF: SPI Receive Buffer Full Status bit

1 = Receive buffer, SPIxRXB is full

0 = Receive buffer, SPIxRXB is not full

Standard Buffer Mode:

Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.

Enhanced Buffer Mode:

Set when SWPTR + 1 = CRPTR; cleared otherwise

NOTES:

20.0 SERIAL QUAD INTERFACE (SQI)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 46. “Serial Quad Interface (SQI)” (DS60001244), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The SQI module is a synchronous serial interface that provides access to serial Flash memories and other serial devices. The SQI module supports Single Lane (identical to SPI), Dual Lane, and Quad Lane modes.

Note: To avoid cache coherency problems on devices with L1 cache, SQL buffers must only be allocated or accessed from the KSEG1 segment.

The SQI module offers the following key features:

• Supports Single, Dual, and Quad Lane modes
- Programmable command sequence
- eXecute-In-Place (XIP)
- Data transfer:

- Programmed I/O mode (PIO)

- Buffer descriptor DMA

• Supports High-Speed Serial Flash mode and SPI Mode 0 and Mode 3
- Programmable Clock Polarity (CPOL) and Clock Phase (CPHA) bits
• Supports up to two Chip Selects
• Supports up to four bytes of Flash address
- Programmable interrupt thresholds
• 32-byte transmit data buffer
• 32-byte receive data buffer
• 4-word controller buffer

Note: Once the SQI module is configured, external devices are memory mapped into KSEG2 (see Figure 4-1 through Figure 4-4 in Section 4.0 “Memory Organization” for more information). The MMU must be enabled and the TLB must be set up to access this memory (see Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192) in the “PIC32 Family Reference Manual” for more information).

FIGURE 20-1: SQI MODULE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - SERIAL QUAD INTERFACE (SQI) - 1

flowchart

graph TD
    A["PBCLK5(2)"] --> B["Control Buffer"]
    C["REFCLKO2(1) (TBC)"] --> B
    B --> D["Control and Status Registers (PIO)"]
    D --> E["Transmit Buffer"]
    E --> F["SQI Master Interface"]
    G["Bus Slave"] --> D
    H["Bus Master"] --> I["DMA"]
    I --> J["Receive Buffer"]
    J --> F
    K["Control Buffer"] -.-> D
    L["BU Slave"] --> D
    M["BU Master"] --> I
    N["SGI"] --> F
    O["SGI"] --> F
    P["SGI"] --> F
    Q["SGI"] --> F
    R["SGI"] --> F
    S["SGI"] --> F
    T["SGI"] --> F
    U["SGI"] --> F
    V["SGI"] --> F
    W["SGI"] --> F
    X["SGI"] --> F
    Y["SGI"] --> F
    Z["SGI"] --> F

Note 1: When configuring the REFCLKO2 clock source, a value of '0' for the ROTRIM<8:0> bits must be selected.
2: This clock source is only used for SQL Special Function Register (SFR) access.

20.1 SQI Control Registers

TABLE 20-1: SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	—— ——— ———
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	DUMMYBYTES<2:0>			ADDRBYTES<2:0>			READOPCODE<7:6>
15:8	R-0 R-0 R-0	R-0 R-0 R-0		R/W-0	R/W-0
15:8	READOPCODE<5:0>						TYPEDATA<1:0>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	TYPEDUMMY<1:0>		TYPEMODE<1:0>		TYPEADDR<1:0>		TYPECMD<1:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as '0'

bit 23-21 DUMMYBYTES<2:0>: Transmit Dummy Bytes bits

111 = Transmit seven dummy bytes after the address bytes

•

011 = Transmit three dummy bytes after the address bytes

010 = Transmit two dummy bytes after the address bytes

001 = Transmit one dummy bytes after the address bytes

000 = Transmit zero dummy bytes after the address bytes

bit 20-18 ADDRBYTES<2:0>: Address Cycle bits

111 = Reserved

•

101 = Reserved

100 = Four address bytes

011 = Three address bytes

010 = Two address bytes

001 = One address bytes

000 = Zero address bytes

bit 17-10 READOPCODE<7:0>: Op code Value for Read Operation bits

These bits contain the 8-bit op code value for read operation.

bit 9-8 TYPEDATA<1:0>: SQI Type Data Enable bits

The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved

10 = Quad Lane mode data is enabled

01 = Dual Lane mode data is enabled

00 = Single Lane mode data is enabled

bit 7-6 TYPEDUMMY<1:0>: SQL Type Dummy Enable bits

The boot controller will send the dummy in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved

10 = Quad Lane mode dummy is enabled

01 = Dual Lane mode dummy is enabled

00 = Single Lane mode dummy is enabled

REGISTER 20-1: SQI1XCON1: SQI XIP CONTROL REGISTER 1 (CONTINUED)

bit 5-4 TYPEMODE<1:0>: SQI Type Mode Enable bits

The boot controller will send the mode in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved
10 = Quad Lane mode is enabled
01 = Dual Lane mode is enabled
00 = Single Lane mode is enabled

bit 3-2 TYPEADDR<1:0>: SQI Type Address Enable bits

The boot controller will send the address in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved
10 = Quad Lane mode address is enabled
01 = Dual Lane mode address is enabled
00 = Single Lane mode address is enabled

bit 1-0 TYPECMD<1:0>: SQI Type Command Enable bits

The boot controller will send the command in Single Lane, Dual Lane, or Quad Lane.

11 = Reserved
10 = Quad Lane mode command is enabled
01 = Dual Lane mode command is enabled
00 = Single Lane mode command is enabled

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	—	—	—	—	DEVSEL<1:0>		MODEBYTES<1:0>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	MODECODE<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-12 Unimplemented: Read as '0'

bit 11-10 DEVSEL<1:0>: Device Select bits

11 = Reserved
10 = Reserved
01 = Device 1 is selected
00 = Device 0 is selected

bit 9-8 MODEBYTES<1:0>: Mode Byte Cycle Enable bits

11 = Three cycles
10 = Two cycles
01 = One cycle
00 = Zero cycles

bit 7-0 MODECODE<7:0>: Mode Code Value bits

These bits contain the 8-bit code value for the mode bits.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24	SQIEN —	———	CSEN<1:0>
23:16	U-0	U-0	R/W-0	R/W-0	U-0	U-0	U-0	R/W-0, HC
23:16	—	—	DATAEN<1:0>		—	—	—	RESET
15:8	U-0	r-0	r-0	R/W-0	r-0	R/W-0	R/W-0	R/W-0
15:8	———	BURSTEN		(1)	— HOLD	WP	SERMODE
7:0	R/W-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	RXLATCH	—	LSBF	CPOL	CPHA	MODE<2:0>

Legend:	HC = Hardware Cleared	r = Reserved
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 SQIEN: SQL Enable bit

1 = SQL module is enabled

0 = SQL module is disabled

bit 30-26 Unimplemented: Read as '0'

bit 25-24 CSEN<1:0>: Chip Select Output Enable bits

11 = Chip Select 0 and Chip Select 1 are used

10 = Chip Select 1 is used (Chip Select 0 is not used)

01 = Chip Select 0 is used (Chip Select 1 is not used)

00 = Chip Select 0 and Chip Select 1 are not used

bit 23-22 Unimplemented: Read as '0'

bit 21-20 DATAEN<1:0>: Data Output Enable bits

11 = Reserved

10 = SQID3-SQID0 outputs are enabled

01 = SQID1 and SQID0 data outputs are enabled

00 = SQID0 data output is enabled

bit 19-17 Unimplemented: Read as '0'

bit 16 RESET: Software Reset Select bit

This bit is automatically cleared by the SQL module. All of the internal state machines and FIFO pointers are reset by this reset pulse.

1 = A reset pulse is generated

0 = A reset pulse is not generated

bit 15 Unimplemented: Read as '0'

bit 14-13 Reserved: Must be programmed as '0'

bit 12 BURSTEN: Burst Configuration bit ^(1)

1 = Burst is enabled

0 = Burst is not enabled

bit 11 Reserved: Must be programmed as '0'

bit 10 HOLD: Hold bit

In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is connected.

Note 1: This bit must be programmed as '1'.

REGISTER 20-3: SQI1CFG: SQI CONFIGURATION REGISTER (CONTINUED)

bit 9 WP: Write Protect bit

In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is connected.

bit 8 SERMODE: Serial Flash Mode Select bit

1 = Hardware ignores CPHA and CPOL bit settings and sends and latches negative edge of SQI CLK 0 = Clock phase and polarity are controlled by the CPHA and CPOL bit settings

bit 7 RXLATCH: RX Latch Control During TX Mode bit

1 = RX Data sent to RX FIFO when CMDINIT<1:0> (SQICON<17:16>) is set to TX 0 = RX Data is discarded when CMDINIT (SQICON<17:16>) is set to TX

bit 6 Unimplemented: Read as '0'

bit 5 LSBF: Data Format Select bit

1 = LSB is sent or received first 0 = MSB is sent or received first

bit 4 CPOL: Clock Polarity Select bit

1 = Active-low SQICLK (SQICLK high is the Idle state) 0 = Active-high SQICLK (SQICLK low is the Idle state)

bit 3 CPHA: Clock Phase Select bit

1 = SQICLK starts toggling at the start of the first data bit 0 = SQICLK starts toggling at the middle of the first data bit

bit 2-0 MODE<2:0>: Mode Select bits

111 = Reserved • • • 100 = Reserved 011 = XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP), but uses the register data to control timing) 010 = DMA mode is selected 001 = CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered when leaving Boot or XIP mode) 000 = Reserved

Note 1: This bit must be programmed as '1'.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	—	—	—	—
23:16	U-0		R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	—	DASSERT	DEVSEL<1:0>		LANEMODE<1:0>		CMDINIT<1:0>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	TXRXCOUNT<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	TXRXCOUNT<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-23 Unimplemented: Read as '0'

bit 22 DASSERT: Chip Select Assert bit

1 = Chip Select is deasserted after transmission or reception of the specified number of bytes
0 = Chip Select is not deasserted after transmission or reception of the specified number of bytes

bit 21-20 DEVSEL<1:0>: SQL Device Select bits

11 = Reserved
10 = Reserved
01 = Select Device 1
00 = Select Device 0

bit 19-18 LANEMODE<1:0>: SQI Lane Mode Select bits

11 = Reserved
10 = Quad Lane mode
01 = Dual Lane mode
00 = Single Lane mode

bit 17-16 CMDINIT<1:0>: Command Initiation Mode Select bits

If it is Transmit, commands are initiated based on a write to the transmit register or the contents of TX FIFO. If CMDINIT is Receive, commands are initiated based on reads to the read register or RX FIFO availability.

11 = Reserved
10 = Receive
01 = Transmit
00 = Idle

bit 15-0 TXRXCOUNT<15:0>: Transmit/Receive Count bits

These bits specify the total number of bytes to transmit or received (based on CMDINIT)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	—— — — — —
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	CLKDIV<7:0>(1)
7:0	U-0 U-0 U-0	U-0	U-0 U-0 R-0 R/W-0
7:0	———	—— — —	STABLE	EN

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-8 CLKDIV<7:0>: SQI Clock Tsq Frequency Select bit ^(1)

10000000 = Base clock TBC is divided by 512

01000000 = Base clock TBC is divided by 256

00100000 = Base clock TBC is divided by 128

00010000 = Base clock TBC is divided by 64

00001000 = Base clock TBC is divided by 32

00000100 = Base clock TBC is divided by 16

00000010 = Base clock TBC is divided by 8

00000001 = Base clock TBC is divided by 4

00000000 = Base clock TBC is divided by 2

Setting these bits to '00000000' specifies the highest frequency of the SQI clock.

bit 7-2 Unimplemented: Read as '0'

bit 1 STABLE: TsQI Clock Stable Select bit

This bit is set to '1' when the SQL clock, TSQL, is stable after writing a '1' to the EN bit.

1 = TSQL clock is stable

0 = TSQI clock is not stable

bit 0 EN: TSQI Clock Enable Select bit

When clock oscillation is stable, the SQI module will set the STABLE bit to '1'.

1 = Enable the SQI clock (T SQI) (when clock oscillation is stable, the SQI module sets the STABLE bit to '1')

0 = Disable the SQI clock (TsqI) (the SQI module should stop its clock to enter a low power state); SFRs can still be accessed, as they use PBCLK5

Note 1: Refer to Table in Section 37.0 “Electrical Characteristics” for the maximum clock frequency specifications.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —
15:8	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	— — —			TXCMDTHR<4:0>
7:0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	— — —			RXCMDTHR<4:0> (1)

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as '0'

bit 12-8 TXCMDTHR<4:0>: Transmit Command Threshold bits

In transmit initiation mode, the SQI module performs a transmit operation when transmit command threshold bytes are present in the TX FIFO. For 16-bit mode, the value should be multiple of two. These bits should usually be set to '1' for normal Flash commands, and set to a higher value for page programming. For 16-bit mode, the value should be a multiple of two.

bit 7-5 Unimplemented: Read as '0'

bit 4-0 RXCMDTHR<4:0>: Receive Command Threshold bits ^(1)

In receive initiation mode, the SQI module attempts to perform receive operations to fetch the receive command threshold number of bytes in the receive buffer. If space for these bytes is not present in the FIFO, the SQI will not initiate a transfer. For 16-bit mode, the value should be a multiple of two.

If software performs any reads, thereby reducing the FIFO count, hardware would initiate a receive transfer to make the FIFO count equal to the value in these bits. If software would not like any more words latched into the FIFO, command initiation mode needs to be changed to Idle before any FIFO reads by software.

In the case of Boot/XIP mode, the SQI module will use the System Bus burst size, instead of the receive command threshold value.

Note 1: These bits should only be programmed when a receive is not active (i.e., during Idle mode or a transmit).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	—	—	—	TXINTTHR<4:0>
7:0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	———			RXINTTHR<4:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as '0'

bit 12-8 TXINTTHR<4:0>: Transmit Interrupt Threshold bits

A transmit interrupt is set when the transmit FIFO has more space than the transmit interrupt threshold bytes. For 16-bit mode, the value should be a multiple of two.

bit 7-5 Unimplemented: Read as '0'

bit 4-0 RXINTTHR<4:0>: Receive Interrupt Threshold bits

A receive interrupt is set when the receive FIFO count is larger than or equal to the receive interrupt threshold value. RXINTTHR is the number of bytes in the receive FIFO. For 16-bit mode, the value should be a multiple of two.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	—	—	—	—	—	—	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	—	—	—	—	—	—	—	—
15:8	U-0 U-0 U-0	U-0 U-0	R/W-0	R/W-0	R/W-0
15:8	— — —	—	—			PKTCOMPIE	BDDONEIE	CONTHRIE
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CONEMPTYIE	CONFULLIE	RXTHRIE	RXFULLIE	RXEMPTYIE	TXTHRIE	TXFULLIE	TXEMPTYIE

Legend:	HS = Hardware Set
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-11 Unimplemented: Read as '0'

bit 10 PKTCOMPIE: DMA Buffer Descriptor Packet Complete Interrupt Enable bit

1 = Interrupts are enabled
0 = Interrupts are not enabled

bit 9 BDDONEIE: DMA Buffer Descriptor Done Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 8 CONTHRIE: Control Buffer Threshold Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 7 CONEMPTYIE: Control Buffer Empty Interrupt bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 6 CONFULLIE: Control Buffer Full Interrupt Enable bit

This bit enables an interrupt when the receive FIFO buffer is full.

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 5 RXTHRIE: Receive Buffer Threshold Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 4 RXFULLIE: Receive Buffer Full Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 3 RXEMPTYIE: Receive Buffer Empty Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 2 TXTHRIE: Transmit Threshold Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 1 TXFULLIE: Transmit Buffer Full Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

bit 0 TXEMPTYIE: Transmit Buffer Empty Interrupt Enable bit

1 = Interrupt is enabled
0 = Interrupt is disabled

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	———	———
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	———	———
15:8	U-0 U-0 U-0	U-0 U-0 R/W-0,	HS R/W-0,	HS R/W-0,	HS
15:8	———	———				PKT COMPIF	BD DONEIF	CON THRIF
7:0	R/W-1, HS	R/W-0, HS	R/W-1, HS	R/W-0, HS	R/W-1, HS	R/W-1, HS	R/W-0, HS	R/W-1, HS
7:0	CON EMPTYIF	CON FULLIF	RXTHRIF^(1)	RXFULLIF	RX EMPTYIF	TXTHRIF	TXFULLIF	TX EMPTYIF

Legend:	HS = Hardware Set
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-11 Unimplemented: Read as '0'

bit 10 PKTCOMPIF: DMA Buffer Descriptor Processor Packet Completion Interrupt Status bit

1 = DMA BD packet is complete
0 = DMA BD packet is in progress

bit 9 BDDONEIF: DMA Buffer Descriptor Done Interrupt Status bit

1 = DMA BD process is done
0 = DMA BD process is in progress

bit 8 CONTHRIF: Control Buffer Threshold Interrupt Status bit

1 = The control buffer has more than THRES words of space available
0 = The control buffer has less than THRES words of space available

bit 7 CONEMPTYIF: Control Buffer Empty Interrupt Status bit

1 = Control buffer is empty
0 = Control buffer is not empty

bit 6 CONFULLIF: Control Buffer Full Interrupt Status bit

1 = Control buffer is full
0 = Control buffer is not full

bit 5 RXTHRIF: Receive Buffer Threshold Interrupt Status bit ^(1)

1 = Receive buffer has more than RXINTTHR words of space available
0 = Receive buffer has less than RXINTTHR words of space available

bit 4 RXFULLIF: Receive Buffer Full Interrupt Status bit

1 = Receive buffer is full
0 = Receive buffer is not full

bit 3 RXEMPTYIF: Receive Buffer Empty Interrupt Status bit

1 = Receive buffer is empty
0 = Receive buffer is not empty

bit 2 TXTHRIF: Transmit Buffer Interrupt Status bit

1 = Transmit buffer has more than TXINTTHR words of space available
0 = Transmit buffer has less than TXINTTHR words of space available

Note 1: In the case of Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will be set to a '1', immediately after a POR until a read request on the System Bus bus is received.

Note: The bits in the register are cleared by writing a '1' to the corresponding bit position.

REGISTER 20-9: SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED)

bit 1 TXFULLIF: Transmit Buffer Full Interrupt Status bit

1 = The transmit buffer is full
0 = The transmit buffer is not full

bit 0 TXEMPTYIF: Transmit Buffer Empty Interrupt Status bit

1 = The transmit buffer is empty
0 = The transmit buffer has content

Note: The bits in the register are cleared by writing a '1' to the corresponding bit position.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
31:24	TXDATA<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
23:16	TXDATA<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
15:8	TXDATA<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
7:0	TXDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-0 TXDATA<31:0>: Transmit Command Data bits

Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer, the data in TXDATA is loaded into the shift register (SFDR).

Multiple writes to TXDATA can occur even while a transfer is already in progress. There can be a maximum of eight commands that can be queued.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
31:24	RXDATA<31:24>
23:16	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
23:16	RXDATA<23:16>
15:8	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
15:8	RXDATA<15:8>
7:0	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
7:0	RXDATA<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 RXDATA<31:0>: Receive Data Buffer bits

At the end of a data transfer, the data in the shift register is loaded into the RXDATA register. This register works like a FIFO. The depth of the receive buffer is eight words. These bits indicate the starting write block address for an erase operation.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	—— —	—— — — — —
23:16	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
23:16	TXFIFOFREE<7:0>
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	—— —	—— — — — —
7:0	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
7:0	RXFIFOCNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as '0'

bit 23-16 TXFIFOFREE<7:0>: Transmit FIFO Available Word Space bits

bit 15-8 Unimplemented: Read as '0'

bit 7-0 RXFIFOCNT<7:0>: Number of words of read data in the FIFO

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	— — —	— — — —	—
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	— — —	— — — —	—
7:0	U-0 R-0 R-0	R-0 R-0	R-0
7:0	—	SQID3	SQID2	SQID1	SQID0	—	RXUN	TXOV

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-7 Unimplemented: Read as '0'

bit 6 SQID3: SQID3 Status bits

1 = Data is present on SQID3
0 = Data is not present on SQID3

bit 5 SQID2: SQID2 Status bits

1 = Data is present on SQID2
0 = Data is not present on SQID2

bit 4 SQID1: SQID1 Status bits

1 = Data is present on SQID1
0 = Data is not present on SQID1

bit 3 SQID0: SQID0 Status bits

1 = Data is present on SQID0
0 = Data is not present on SQID0

bit 2 Unimplemented: Read as '0'

bit 1 RXUN: Receive FIFO Underflow Status bit

1 = Receive FIFO Underflow has occurred
0 = Receive FIFO underflow has not occurred

bit 0 TXOV: Transmit FIFO Overflow Status bit

1 = Transmit FIFO overflow has occurred
0 = Transmit FIFO overflow has not occurred

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — — — —
7:0	U-0	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	—	—	START	POLLEN	DMAEN

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-3 Unimplemented: Read as '0'

bit 2 START: Buffer Descriptor Processor Start bit

1 = Start the buffer descriptor processor
0 = Disable the buffer descriptor processor

bit 1 POLLEN: Buffer Descriptor Poll Enable bit

1 = BDP poll enabled
0 = BDP poll is not enabled

bit 0 DMAEN: DMA Enable bit

1 = DMA is enabled
0 = DMA is disabled

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
31:24	BDCURRADDR<31:24>
23:16	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
23:16	BDCURRADDR<23:16>
15:8	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
15:8	BDCURRADDR<15:8>
7:0	R-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0
7:0	BDCURRADDR<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BDCURRADDR<31:0>: Current Buffer Descriptor Address bits

These bits contain the address of the current descriptor being processed by the Buffer Descriptor Processor.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
31:24	BDADDR<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
23:16	BDADDR<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
15:8	BDADDR<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
7:0	BDADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 BDADDR<31:0>: DMA Base Address bits

These bits contain the base address of the DMA. This register should be updated only when the DMA is idle.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
31:24	—	—	—	—	—	—	—	—
23:16	U-0	U-0	R-x	R-x	R-x	R-x	R-x	R-x
23:16	—	—	BDSTATE<3:0>				DMASTART	DMAACTV
15:8	R-x	R-x	R-x	R-x	R-x	R-x	R-x	R-x
15:8	BDCON<15:8>
7:0	R-x	R-x	R-x	R-x	R-x	R-x	R-x	R-x
7:0	BDCON<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-22 Unimplemented: Read as '0'

bit 21-18 BDSTATE<3:0>: DMA Buffer Descriptor Processor State Status bits

These bits return the current state of the buffer descriptor processor:

5 = Fetched buffer descriptor is disabled
4 = Descriptor is done
3 = Data phase
2 = Buffer descriptor is loading
1 = Descriptor fetch request is pending
0 = Idle

bit 17 DMASTART: DMA Buffer Descriptor Processor Start Status bit

1 = DMA has started
0 = DMA has not started

bit 16 DMAACTV: DMA Buffer Descriptor Processor Active Status bit

1 = Buffer Descriptor Processor is active
0 = Buffer Descriptor Processor is idle

bit 15-0 BDCON<15:0>: DMA Buffer Descriptor Control Word bits

These bits contain the current buffer descriptor control word.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	POLLCON<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	POLLCON<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-0 POLLCON<15:0>: Buffer Descriptor Processor Poll Status bits

These bits indicate the number of cycles the BDP block would wait before refetching the descriptor control word if the previous descriptor fetched was disabled.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	R-x R-x R-x	R-x U-0
31:24	—	—	—	TXSTATE<3:0>				—
23:16	U-0	U-0	U-0	R-x	R-x	R-x	R-x	R-x
23:16	— — —			TXBUFCNT<4:0>
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	— — —	— — — —
7:0	R-x	R-x	R-x	R-x	R-x	R-x	R-x	R-x
7:0	TXCURBUFLEN<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28-25 TXSTATE<3:0>: Current DMA Transmit State Status bits

These bits provide information on the current DMA receive states.

bit 24-21 Unimplemented: Read as '0'

bit 20-16 TXBUFCNT<4:0>: DMA Buffer Byte Count Status bits

These bits provide information on the internal FIFO space.

bit 15-8 Unimplemented: Read as '0'

bit 7-0 TXCURBUFLEN<7:0>: Current DMA Transmit Buffer Length Status bits

These bits provide the length of the current DMA transmit buffer.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	R-x R-x R-x R-x	U-0
31:24	— — —	RXSTATE<3	0> —
23:16	U-0 U-0 U-0	R-x R-x R-x R-x	R-x
23:16	— — —	RXBUFCNT<4:0>
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	—	—	—	—	—	—	—	—
7:0	R-x R-x R-x	R-x	R-x R-x R-x R-x
7:0	RXCURBUFLEN<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28-25 RXSTATE<3:0>: Current DMA Receive State Status bits

These bits provide information on the current DMA receive states.

bit 24-21 Unimplemented: Read as '0'

bit 20-16 RXBUFCNT<4:0>: DMA Buffer Byte Count Status bits

These bits provide information on the internal FIFO space.

bit 15-8 Unimplemented: Read as '0'

bit 7-0 RXCURBUFLEN<7:0>: Current DMA Receive Buffer Length Status bits

These bits provide the length of the current DMA receive buffer.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — — — —
7:0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	— — —			THRES<4:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-5 Unimplemented: Read as '0'

bit 4-0 THRES<4:0>: SQL Control Threshold Value bits

The SQI control threshold interrupt is asserted when the amount of space in indicated by THRES<4:0> is available in the SQI control buffer.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —	—
15:8	U-0 U-0 U-0	U-0 U-0 R/W-0	R/W-0	R/W-0
15:8	— — —	— —	PKT			DONEISE	BDDONEISE	CONTHRISE
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	CONEMPTYISE	CONFULLISE	RXTHRISE	RXFULLISE	RXEMPTYISE	TXTHRISE	TXFULLISE	TXEMPTYISE

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-11 Unimplemented: Read as '0'

bit 10 PKTDONEISE: Receive Error Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 9 BDDONEISE: Transmit Error Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 8 CONTHRISE: Control Buffer Threshold Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 7 CONEMPTYISE: Control Buffer Empty Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 6 CONFULLISE: Control Buffer Full Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 5 RXTHRISE: Receive Buffer Threshold Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 4 RXFULLISE: Receive Buffer Full Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 3 RXEMPTYISE: Receive Buffer Empty Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 2 TXTHRISE: Transmit Buffer Threshold Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 1 TXFULLISE: Transmit Buffer Full Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

bit 0 TXEMPTYISE: Transmit Buffer Empty Interrupt Signal Enable bit

1 = Interrupt signal is enabled
0 = Interrupt signal is disabled

21.0 INTER-INTEGRATED CIRCUIT (I²C)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Inter-Integrated Circuit (I²C)” (DS60001116), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The I²C module provides complete hardware support for both Slave and Multi-Master modes of the I²C serial communication standard.

Each I²C module has a 2-pin interface:

SCLx pin is clock
SDAx pin is data

Each I²C module offers the following key features:

I²C interface supporting both master and slave operation
I²C Slave mode supports 7-bit and 10-bit addressing
I²C Master mode supports 7-bit and 10-bit addressing
I^2C port allows bidirectional transfers between master and slaves
Serial clock synchronization for the I ^2 C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control)
I²C supports multi-master operation; detects bus collision and arbitrates accordingly
Provides support for address bit masking
SMBus support

Figure 21-1 illustrates the C module block diagram.

FIGURE 21-1: I ^2 C BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - INTER-INTEGRATED CIRCUIT (I²C) - 1

flowchart

graph TD
    A["I2CxRCV"] --> B["Shift Clock"]
    C["I2CxRSR"] --> D["Match Detect"]
    E["I2CxADD"] --> F["Address Match"]
    G["I2CxMSK"] --> H["Write"]
    G --> I["Read"]
    J["Start and Stop Bit Detect"] --> K["Control Logic"]
    L["Start and Stop Bit Generation"] --> K
    M["Collision Detect"] --> K
    N["Acknowledge Generation"] --> K
    O["Clock Stretching"] --> K
    P["I2CxTRN"] --> Q["Shift Clock"]
    R["Reload Control"] --> S["BRG Down Counter"]
    T["I2CxBRG"] --> U["Write"]
    V["PBCLK2"] --> W["Shift Clock"]
    X["SCLx"] --> Y["Shift Clock"]
    Z["SDAx"] --> AA["Shift Clock"]
    AB["Internal Data Bus"] --> AC["Read"]
    AD["Write"] --> AE["Write"]
    AF["Write"] --> AG["Write"]
    AH["Write"] --> AI["Write"]
    AJ["Write"] --> AK["Write"]
    AL["Write"] --> AM["Write"]

21.1 I ^2 C Control Registers

TABLE 21-1: I2C1 THROUGH I2C5 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This register is not available on 64-pin devices.

TABLE 21-1: I2C1 THROUGH I2C5 REGISTER MAP (CONTINUED)

Virtual Address (BF82. #)	Register Name(1)	Bit Range	Bits																	All Resets
Virtual Address (BF82. #)	Register Name(1)	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0		All Resets
0430	I2C3MSK	31:16	——	——	——	——	0000
0430	I2C3MSK	15:0	—	—	—	—	—	—	—	Address Mask Register										0000
0440	I2C3BRG	31:16	——	——	——	——	0000
0440	I2C3BRG	15:0	Baud Rate Generator Register 0000
0450	I2C3TRN	31:16	——	——	——	——	0000
0450	I2C3TRN	15:0	—	—	—	—	—	—	—	—	Transmit Register									0000
0460	I2C3RCV	31:16	——	——	——	——	0000
0460	I2C3RCV	15:0	—	—	—	—	—	—	—	—	Receive Register									0000
0600	I2C4CON	31:16	——	——	—							PCIE	SCIE	BOEN	SDAHT	SBCDE	AHEN	DHEN	0000
0600	I2C4CON	15:0	ON	—	SIDL	SCLREL	STRICT	A10M	DISSLW	SMEN	GCEN	STREN	ACKDT	ACKEN	RCEN	PEN	RSEN	SEN	1000
0610	I2C4STAT	31:16	——	——	——	——	0000
0610	I2C4STAT	15:0	ACKSTAT	TRSTAT	ACKTIM	—	—	BCL	GCSTAT	ADD10	IWCOL	I2COV	D/A	P	S	R/W	RBF	TBF	0000
0620	I2C4ADD	31:16	——	——	——	——	0000
0620	I2C4ADD	15:0	—	—	—	—	—	—	—	Address Register										0000
0630	I2C4MSK	31:16	——	——	——	——	0000
0630	I2C4MSK	15:0	—	—	—	—	—	—	—	Address Mask Register										0000
0640	I2C4BRG	31:16	——	——	——	——	0000
0640	I2C4BRG	15:0	Baud Rate Generator Register 0000
0650	I2C4TRN	31:16	——	——	——	——	0000
0650	I2C4TRN	15:0	—	—	—	—	—	—	—	—	Transmit Register									0000
0660	I2C4RCV	31:16	——	——	——	——	0000
0660	I2C4RCV	15:0	—	—	—	—	—	—	—	—	Receive Register									0000
0800	I2C5CON	31:16	——	——	—							PCIE	SCIE	BOEN	SDAHT	SBCDE	AHEN	DHEN	0000
0800	I2C5CON	15:0	ON	—	SIDL	SCLREL	STRICT	A10M	DISSLW	SMEN	GCEN	STREN	ACKDT	ACKEN	RCEN	PGEN	RSEN	SEN	1000
0810	I2C5STAT	31:16	——	——	——	——	0000
0810	I2C5STAT	15:0	ACKSTAT	TRSTAT	ACKTIM	—	—	BCL	GCSTAT	ADD10	IWCOL	I2COV	D/A	P	S	R/W	RBF	TBF	0000
0820	I2C5ADD	31:16	——	——	——	——	0000
0820	I2C5ADD	15:0	—	—	—	—	—	—	—	Address Register										0000
0830	I2C5MSK	31:16	——	——	——	——	0000
0830	I2C5MSK	15:0	—	—	—	—	—	—	—	Address Mask Register										0000
0840	I2C5BRG	31:16	——	——	——	——	0000
0840	I2C5BRG	15:0	Baud Rate Generator Register 0000
0850	I2C5TRN	31:16	——	——	——	——	0000
0850	I2C5TRN	15:0	—	—	—	—	—	—	—	—	Transmit Register									0000
0860	I2C5RCV	31:16	——	——	——	——	0000
0860	I2C5RCV	15:0	—	—	—	—	—	—	—	—	Receive Register									0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR. SET. and INV registers at their virtual addresses, plus offsets of 0x4. 0x8 and 0xC, respectively. See Section 12.2 °CLR. SET. and
INV Registers" for more information.
2: This register is not available on 64-pin devices.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —	—
23:16	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	—	PCIE	SCIE	BOEN	SDAHT	SBCDE	AHEN	DHEN
15:8	R/W-0	U-0	R/W-0	R/W-1, HC	R/W-0	R/W-0	R/W-0	R/W-0
15:8	ON	—	SIDL	SCKREL	STRICT	A10M	DISSLW	SMEN
7:0	R/W-0	R/W-0	R/W-0	R/W-0, HC	R/W-0, HC	R/W-0, HC	R/W-0, HC	R/W-0, HC
7:0	GCEN	STREN	ACKDT	ACKEN	RCEN	PEN	RSEN	SEN

Legend:	HC = Cleared in Hardware
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 Unimplemented: Read as '0'

bit 22 PCIE: Stop Condition Interrupt Enable bit ( ^2 C Slave mode only)

1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled

bit 21 SCIE: Start Condition Interrupt Enable bit ( ^2 C Slave mode only)

1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled

bit 20 BOEN: Buffer Overwrite Enable bit ( ^12 C Slave mode only)

1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of the I2COV bit (I2CxSTAT<6>) only if the RBF bit (I2CxSTAT<2>) = 0
0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT<6>) is clear

bit 19 SDAHT: SDA Hold Time Selection bit

1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL

bit 18 SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)

1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled

bit 18 AHEN: Address Hold Enable bit (Slave mode only)

1 = Following the 8th falling edge of SCL for a matching received address byte; SCKREL bit will be cleared and the SCL will be held low.
0 = Address holding is disabled

bit 16 DHEN: Data Hold Enable bit (I²C Slave mode only)

1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the SCKREL bit and SCL is held low
0 = Data holding is disabled

bit 15 ON: I²C Enable bit

1 = Enables the I²C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I²C module; all I²C pins are controlled by PORT functions

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode

REGISTER 21-1: I2C xCON: I²C CONTROL REGISTER (CONTINUED)

bit 12 SCLREL: SCLx Release Control bit (when operating as I²C slave)

1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write '0' to initiate stretch and write '1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software can only write '1' to release clock). Hardware clear at beginning of slave transmission.

bit 11 STRICT: Strict I ^2 C Reserved Address Rule Enable bit

1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space.
0 = Strict I 2C Reserved Address Rule not enabled

bit 10 A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address

bit 9 DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled
0 = Slew rate control enabled

bit 8 SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds

bit 7 GCEN: General Call Enable bit (when operating as I ^2 C slave)

1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception)
0 = General call address disabled

bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I²C slave) Used in conjunction with SCLREL bit.

1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching

bit 5 ACKDT: Acknowledge Data bit (when operating as I²C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence.

1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I²C master, applicable during master receive)

1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress

bit 3 RCEN: Receive Enable bit (when operating as I ^2 C master)

1 = Enables Receive mode for I²C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as I²C master)

1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I²C master)

1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence.
0 = Repeated Start condition not in progress

bit 0 SEN: Start Condition Enable bit (when operating as I²C master)

1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —
15:8	R-0, HS, HC	R-0, HS, HC	R/C-0, HS, HC	U-0	U-0	R/C-0, HS	R-0, HS, HC	R-0, HS, HC
15:8	ACKSTAT	TRSTAT	ACKTIM	—	—	BCL	GCSTAT	ADD10
7:0	R/C-0, HS	R/C-0, HS	R-0, HS, HC	R/C-0, HS, HC	R/C-0, HS, HC	R-0, HS, HC	R-0, HS, HC	R-0, HS, HC
7:0	IWCOL	I2COV	D_A	P	S	R_W	RBF	TBF

Legend:	HS = Hardware Set	HC = Hardware Cleared
R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	C = Clearable bit

bit 31-16 Unimplemented: Read as '0'

bit 15 ACKSTAT: Acknowledge Status bit

(when operating as ^2C master, applicable to master transmit operation)

1 = NACK received from slave

0 = ACK received from slave

Hardware set or clear at end of slave Acknowledge.

bit 14 TRSTAT: Transmit Status bit (when operating as I²C master, applicable to master transmit operation)

1 = Master transmit is in progress (8 bits + ACK)

0 = Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13 ACKTIM: Acknowledge Time Status bit (Valid in I²C Slave mode only)

1 = I²C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock

0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock

bit 12-11 Unimplemented: Read as '0'

bit 10 BCL: Master Bus Collision Detect bit

1 = A bus collision has been detected during a master operation

0 = No collision

Hardware set at detection of bus collision.

bit 9 GCSTAT: General Call Status bit

1 = General call address was received

0 = General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

bit 8 ADD10: 10-bit Address Status bit

1 = 10-bit address was matched

0 = 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

bit 7 IWCOL: Write Collision Detect bit

1 = An attempt to write the I2CxTRN register failed because the C module is busy

0 = No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

bit 6 I2COV: Receive Overflow Flag bit

1 = A byte was received while the I2CxRCV register is still holding the previous byte

0 = No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

REGISTER 21-2: I2C xSTAT: ^2 C STATUS REGISTER (CONTINUED)

bit 5 D_A: Data/Address bit (when operating as I ^2 C slave)

1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.

bit 4 P: Stop bit

1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.

bit 3 S: Start bit

1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.

bit 2 R_W: Read/Write Information bit (when operating as I²C slave)

1 = Read - indicates data transfer is output from slave
0 = Write - indicates data transfer is input to slave
Hardware set or clear after reception of I^2C device address byte.

bit 1 RBF: Receive Buffer Full Status bit

1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV.

bit 0 TBF: Transmit Buffer Full Status bit

1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

22.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The UART module is one of the serial I/O modules available in PIC32MZ EC family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN, and IrDA®. The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder.

The following are primary features of the UART module:

• Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
- One or two Stop bits
• Hardware auto-baud feature
• Hardware flow control option
- Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler
- Baud rates ranging from 76 bps to 25 Mbps at 100 MHz (PBCLK2)

- 8-level deep First-In-First-Out (FIFO) transmit data buffer

- 8-level deep FIFO receive data buffer

- Parity, framing and buffer overrun error detection

- Support for interrupt-only on address detect (9th bit = 1)

- Separate transmit and receive interrupts

- Loopback mode for diagnostic support

• LIN Protocol support

- IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support

Figure 22-1 illustrates a simplified block diagram of the UART module.
FIGURE 22-1: UART SIMPLIFIED BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) - 1

flowchart

graph TD
    A["PBCLK2"] --> B["Baud Rate Generator"]
    A --> C["IrDA®"]
    A --> D["Hardware Flow Control"]
    A --> E["UARTx Receiver"]
    A --> F["UARTx Transmitter"]
    B --> G["Inverter"]
    C --> G
    D --> G
    E --> G
    F --> G
    G --> H["UxRTS/BCLKx"]
    G --> I["UxCTS"]
    G --> J["UxRX"]
    G --> K["UxTX"]

22.1 UART Control Registers

TABLE 22-1: UART1 THROUGH UART6 REGISTER MAP

TABLE 22-1: UART1 THROUGH UART6 REGISTER MAP (CONTINUED)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	R/W-0	U-0	R/W-0	R/W-0	R/W-0	U-0	R/W-0	R/W-0
15:8	ON	—	SIDL	IREN	RTSMD	—	UEN<1:0>(1)
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	WAKE	LPBACK	ABAUD	RXINV	BRGH	PDSEL<1:0>		STSEL

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: UARTx Enable bit

1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN control bits
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode

bit 12 IREN: IrDA Encoder and Decoder Enable bit

1 = IrDA is enabled
0 = IrDA is disabled

bit 11 RTSMD: Mode Selection for UxRTS Pin bit

1 = pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode

bit 10 Unimplemented: Read as '0'

bit 9-8 UEN<1:0>: UARTx Enable bits ^(1)

11 = UxTX, UxRX and UxBCLK pins are enabled and used; pin is controlled by corresponding bits in the PORTx register
10 = UxTX, UxRX, and pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register
00 = UxTX and UxRX pins are enabled and used; and /UxBCLK pins are controlled by corresponding bits in the PORTx register

bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit

1 = Wake-up enabled
0 = Wake-up disabled

bit 6 LPBACK: UARTx Loopback Mode Select bit

1 = Loopback mode is enabled
0 = Loopback mode is disabled

Note 1: These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices (see Section 12.3 “Peripheral Pin Select (PPS)” for more information).

REGISTER 22-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 5 ABAUD: Auto-Baud Enable bit

1 = Enable baud rate measurement on the next character (requires reception of Sync character (0x55); cleared by hardware upon completion)
0 = Baud rate measurement disabled or completed

bit 4 RXINV: Receive Polarity Inversion bit

1 = UxRX Idle state is '0'
0 = UxRX Idle state is '1'

bit 3 BRGH: High Baud Rate Enable bit

1 = High-Speed mode - 4x baud clock enabled
0 = Standard Speed mode - 16x baud clock enabled

bit 2-1 PDSEL<1:0>: Parity and Data Selection bits

11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity

bit 0 STSEL: Stop Selection bit

1 = Two Stop bits
0 = One Stop bit

Note 1: These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices (see Section 12.3 “Peripheral Pin Select (PPS)” for more information).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	R/W-0
31:24	———	———	A	D M	_	E N
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	ADDR<7:0>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R-0	R-1
15:8	UTXISEL<1:0>		UTXINV	URXEN	UTXBRK	UTXEN	UTXBF	TRMT
7:0	R/W-0	R/W-0	R/W-0	R-1	R-0	R-0	R/W-0	R-0
7:0	URXISEL<1:0>		ADDEN	RIDLE	PERR	FERR	OERR	URXDA

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-25 Unimplemented: Read as '0'

bit 24 ADM_EN: Automatic Address Detect Mode Enable bit

1 = Automatic Address Detect mode is enabled
0 = Automatic Address Detect mode is disabled

bit 23-16 ADDR<7:0>: Automatic Address Mask bits

When the ADM_EN bit is '1', this value defines the address character to use for automatic address detection.

bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits

11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space

bit 13 UTXINV: Transmit Polarity Inversion bit

If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is '0'):

1 = UxTX Idle state is '0'
0 = UxTX Idle state is '1'

If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is '1'):

1 = IrDA encoded UxTX Idle state is '1'
0 = IrDA encoded UxTX Idle state is '0'

bit 12 URXEN: Receiver Enable bit

1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module

bit 11 UTXBRK: Transmit Break bit

1 = Send Break on next transmission. Start bit followed by twelve '0' bits, followed by Stop bit; cleared by hardware upon completion
0 = Break transmission is disabled or completed

bit 10 UTXEN: Transmit Enable bit

1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset

bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)

1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written

bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)

1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer

REGISTER 22-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit

11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full
00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least one data character)

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled

bit 4 RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle
0 = Data is being received

bit 3 PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character
0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character
0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit.

This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to empty state.

1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty

Figure 22-2 and Figure 22-3 illustrate typical receive and transmit timing for the UART module.
FIGURE 22-2: UART RECEPTION
Microchip PIC32MZ1024ECM124 - REGISTER 22-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) - 1

flowchart

graph TD
    A["Read to UxRXREG"] --> B["Char 1"]
    B --> C["Char 2-4"]
    C --> D["Char 5-10"]
    D --> E["Char 11-13"]

    F["UxRX"] --> G["Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13"]
    H["RIDLE"] --> I["Cleared by Software"]
    J["OERR"] --> K["Cleared by Software"]

    L["UxRXIF URXISEL = 00"] --> M["Cleared by Software"]

    N["UxRXIF URXISEL = 01"] --> O["Cleared by Software"]

    P["UxRXIF URXISEL = 10"] --> Q["Cleared by Software"]

FIGURE 22-3: TRANSMISSION (8-BIT OR 9-BIT DATA)
Microchip PIC32MZ1024ECM124 - REGISTER 22-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) - 2

flowchart

graph TD
    A["Write to UxTXREG"] --> B["8 into TxBUF"]
    B --> C["TSR"]
    C --> D["BCLK/16 (Shift Clock)"]
    D --> E["UxTX"]
    E --> F["Pull from Buffer"]
    F --> G["StartStart Bit Bit 1 Stop"]
    G --> H["UxTXIF UTXISEL = 00"]
    H --> I["UxTXIF UTXISEL = 01"]
    I --> J["UxTXIF UTXISEL = 10"]
    J --> K["SS"]
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#fcc,stroke:#333
    style E fill:#cff,stroke:#333
    style F fill:#ffc,stroke:#333
    style G fill:#cfc,stroke:#333
    style H fill:#fcc,stroke:#333
    style I fill:#ffc,stroke:#333
    style J fill:#fcc,stroke:#333
    style K fill:#ffc,stroke:#333

PIC32MZ Embedded Connectivity (EC) Family

23.0 PARALLEL MASTER PORT (PMP)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Parallel Master Port (PMP)" (DS60001128), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable.

Key features of the PMP module include:

8-bit,16-bit interface
Up to 16 programmable address lines
Up to two Chip Select lines
Programmable strobe options:
Individual read and write strobes, or
Read/write strobe with enable strobe

- Address auto-increment/auto-decrement

- Programmable address/data multiplexing

- Programmable polarity on control signals

• Parallel Slave Port support:

- Legacy addressable

- Address support

- 4-byte deep auto-incrementing buffer

• Programmable Wait states

- Operate during Sleep and Idle modes

- Fast bit manipulation using CLR, SET, and INV registers

Note: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.

FIGURE 23-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES

PBCLK2				Address Bus
				Data Bus
Parallel Master Port	PMA0 PMALL			Control Lines
	PMA1 PMALH
	PMA<13:2>	Up to 16-bit Address		Flash EEPROM SRAM
	PMA14 PMCS1
	PMA15 PMCS2
	PMRD PMRD/PMWR
	PMWR PMENB	Microcontroller	LCD	FIFO Buffer
	PMD<7:0> PMD<15:8>(1)	8-bit/16-bit Data (with or without multiplexed addressing)

Note: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.

23.1 PMP Control Registers

TABLE 23-1: PARALLEL MASTER PORT REGISTER MAP

Virtual Address (BF82_#)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

E000

PMCON

31:16

———

0000

15:0

—

SIDL

ADRMUX<1:0>

PMPCTL

PTWREN

PTRDEN

CSF<1:0>

ALP

CS2P

CS1P

—

WRSP

RDSP

0000

E010

PMMODE

31:16

———

0000

15:0

BUSY

IRQM<1:0>

INCM<1:0>

MODE16

MODE<1:0>

WAITB<1:0>

WAITM<3:0>

WAITE<1:0>

0000

E020

PMADDR

31:16

———

0000

15:0

CS2 CS1

0000

ADDR15

ADDR14

E030

PMDOUT

31:16

DATAOUT<31:0>

0000

15:0

0000

E040

PMDIN

31:16

DATAIN<31:0>

0000

15:0

0000

E050

PMAEN

31:16

———

0000

15:0

PTEN<15:0>

0000

E060

PMSTAT

31:16

———

0000

15:0

IBF

IBOV

—

IB3F

IB2F

IB1F

IB0F

OBE

OBUF

—

OB3E

OB2E

OB1E

OB0E

000E

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	R/W-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
15:8	ON —	S	I	D ADRMUX<1:0>		PMPTTL PTWREN PTRDEN
7:0	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 U-0	R/W-0
7:0	CSF<1:0>(1)		ALP(1)	CS2P(1)	CS1P(1)	— WRSP	RDSP

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Parallel Master Port Enable bit

1 = PMP enabled
0 = PMP disabled, no off-chip access performed

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode

bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11 = Lower 8 bits of address are multiplexed on PMD<15:0> pins; upper 8 bits are not used
10 = All 16 bits of address are multiplexed on PMD<15:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8>
00 = Address and data appear on separate pins

bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit

1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer

bit 9 PTWREN: Write Enable Strobe Port Enable bit

1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled

bit 8 PTRDEN: Read/Write Strobe Port Enable bit

1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled

bit 7-6 CSF<1:0>: Chip Select Function bits (1)

11 = Reserved
10 = PMCS1 and PMCS2 function as Chip Select
01 = PMCS2 functions as Chip Select and PMCS1 functions as address bit 14
00 = PMCS1 and PMCS2 function as address bit 14 and address bit 15

bit 5 ALP: Address Latch Polarity bit ^(1)

1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)

bit 4 CS2P: Chip Select 2 Polarity bit ^(1)

1 = Active-high (PMCS2)
0 = Active-low (PMCS2)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

REGISTER 23-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 3 CS1P: Chip Select 1 Polarity bit (1) 1 = Active-high (PMCS1) 0 = Active - low w (PMCS1 bit 2 Unimplemented: Read as '0' bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (MODE<1:0> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (MODE<1:0> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (MODE<1:0> = 00,01,10): 1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) For Master mode 1 (MODE<1:0> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	——	——	——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	——	——	——
15:8	R-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	W-0 R/W-0 R/W-0	R/W-0
7:0	WAITB<1:0>(1)		WAITM<3:0>(1)				WAITE<1:0>(1)

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy

0 = Port is not busy

bit 14-13 IRQM<1:0>: Interrupt Request Mode bits

11 = Reserved, do not use

10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)

or on a read or write operation when PMA<1:0>=11 (Addressable Slave mode only)

01 = Interrupt generated at the end of the read/write cycle

00 = No Interrupt generated

bit 12-11 INCM<1:0>: Increment Mode bits

11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only)

10 = Decrement ADDR<15:0> and ADDR<14> by 1 every read/write cycle(2)

01 = Increment ADDR<15:0> and ADDR<14> by 1 every read/write cycle(2)

00 = No increment or decrement of address

bit 10 MODE16: 8/16-bit Mode bit

1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer

0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer

bit 9-8 MODE<1:0>: Parallel Port Mode Select bits

11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA, and PMD<15:0>) ^(3)

10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA, and PMD<15:0>) ^(3)

01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCSx, PMD<7:0>, and PMA<1:0>)

00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCSx, and PMD<7:0>)

bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits ^(1)

11 = Data wait of 4 TPBCLK2; multiplexed address phase of 4 T PBCLK2

10 = Data wait of 3 TPBCLK2; multiplexed address phase of 3 T PBCLK2

01 = Data wait of 2 TPBCLK2; multiplexed address phase of 2 T PBCLK2

00 = Data wait of 1 TPBCLK2; multiplexed address phase of 1 T PBCLK2 (default)

Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK2 cycle for a write operation; WAITB = 1 TPBCLK2 cycle, WAITE = 0 TPBCLK2 cycles for a read operation.

2: Address bits 14 and 15 are is not subject to auto-increment/decrement if configured as Chip Select.

3: The PMD<15:8> bits are not active is the MODE16 bit = 1.

REGISTER 23-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits ^(1) 1111 = Wait of 16 TPBCLK2

•

0001 = Wait of 2 TPBCLK2

0000 = Wait of 1 TPBCLK2 (default)

bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits ^(1) 11 = Wait of 4 TPBCLK2

10 = Wait of 3 TPBCLK2

01 = Wait of 2 TPBCLK2

00 = Wait of 1 TPBCLK2 (default)

For Read operations:

11 = Wait of 3 TPBCLK2

10 = Wait of 2 TPBCLK2

01 = Wait of 1 TPBCLK2

00 = Wait of 0 TPBCLK2 (default)

Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK2 cycle for a write operation; WAITB = 1 TPBCLK2 cycle, WAITE = 0 TPBCLK2 cycles for a read operation. 2: Address bits 14 and 15 are is not subject to auto-increment/decrement if configured as Chip Select. 3: The PMD<15:8> bits are not active is the MODE16 bit = 1.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	R/W-0 R/W-0	R/W-0 R/W-0 R/W	W-0 R/W-0 R/W-0	R/W-0
	CS2(1)	CS1(3)	ADDR<13:8>
	ADDR15(2)	ADDR14(4)	ADDR<13:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R/W	W-0 R/W-0 R/W-0	R/W-0
7:0	ADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 CS2: Chip Select 2 bit ^(1)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive

bit 15 ADDR<15>: Target Address bit 15 ^(2)

bit 14 CS1: Chip Select 1 bit ^(3)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive

bit 14 ADDR<14>: Target Address bit 14 ^(4)

bit 13-0 ADDR<13:0>: Address bits

Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.

2: When the CSF<1:0> bits (PMCON<7:6>) = 00.

3: When the CSF<1:0> bits (PMCON<7:6>) = 10.

4: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.

Note: If the DUALBUF bit (PMCON<17>) = 0, the bits in this register control both read and write target addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the PMRADDR register for Read operations and the PMWADDR register for Write operations.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	—— —	—— — — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	—— —	—— — — — — —
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0
15:8	PTEN<15:14> PTEN<13:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0
7:0	PTEN<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as '0'

bit 15-14 PTEN<15:14>: PMCS1 Strobe Enable bits

1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS1 and PMCS2 ^(1) 0 = PMA15 and PMA14 function as port I/O

bit 13-2 PTEN<13:2>: PMP Address Port Enable bits

1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O

bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits

1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL ^(2) 0 = PMA1 and PMA0 pads function as port I/O

Note 1: The use of these pins as PMA15 and PMA14 or CS1 and CS2 is selected by the CSF<1:0> bits in the PMCON register.

2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits ADRMUX<1:0> in the PMCON register.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	— — —	— — — —	—
15:8	R-0 R/W-0, HS, SC U-0 U-0		R-0 R-0 R-0 R-0
15:8	IBF IBOV — — IB3F IB2F IB1F IB0F
7:0	R-1 R/W-0, HS, SC U-0 U-0		R-1 R-1 R-1 R-1
7:0	OBE	OBUF	—	—	OB3E	OB2E	OB1E	OB0E

Legend:	HS = Hardware Set	SC = Software Cleared
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 IBF: Input Buffer Full Status bit

1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty

bit 14 IBOV: Input Buffer Overflow Status bit

1 = A write attempt to a full input byte buffer occurred (must be cleared in software)
0 = No overflow occurred

bit 13-12 Unimplemented: Read as '0'

bit 11-8 IBxF: Input Buffer x Status Full bits

1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data

bit 7 OBE: Output Buffer Empty Status bit

1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full

bit 6 OBUF: Output Buffer Underflow Status bit

1 = A read occurred from an empty output byte buffer (must be cleared in software)
0 = No underflow occurred

bit 5-4 Unimplemented: Read as '0'

bit 3-0 OBxE: Output Buffer x Status Empty bits

1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted

NOTES:

24.0 EXTERNAL BUS INTERFACE (EBI)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 47. “External Bus Interface (EBI)” (DS60001245), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The External Bus Interface (EBI) module provides a high-speed, convenient way to interface external parallel memory devices to the PIC32MZ EC family device.

With the EBI module, it is possible to connect asynchronous SRAM and NOR Flash devices, as well as non-memory devices such as camera sensors and LCDs.

The features of the EBI module depend on the pin count of the PIC32MZ EC device, as shown in Table 24-1.

TABLE 24-1: EBI MODULE FEATURES

Feature	Number of Device Pins
Feature	100 1	24 144
Async SRAM Y Y	Y
Async NOR Flash	Y	Y	Y
Available address lines	20	20	24
8-bit data bus support	Y	Y	Y
16-bit data bus support	Y	Y	Y
Available Chip Selects	1	1 4
Timing mode sets	3	3 3
8-bit R/W from 16-bit bus	N	N	Y
Non-memory device	Y	Y	Y
LCD	Y	Y	Y

Note: Once the EBI module is configured, external devices will be memory mapped and can be access from KSEG2 memory space (see Figure 4-1 through Figure 4-4 in Section 4.0 "Memory Organization" for more information). The MMU must be enabled and the TLB must be set up to access this memory (see Section 50. "CPU for Devices with MIPS32® microAptiv™ and M-Class Cores" (DS60001192) in the "PIC32 Family Reference Manual" for more information).

FIGURE 24-1: EBI SYSTEM BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - EXTERNAL BUS INTERFACE (EBI) - 1

flowchart

graph LR
    PBCLK8 --> BusInterface["Bus Interface"]
    SystemBus["System Bus"] --> BusInterface
    BusInterface --> ControlRegisters["Control Registers"]
    BusInterface --> Data_FIFO["Data FIFO"]
    BusInterface --> Address_FIFO["Address FIFO"]

    ExternalBus["External Bus Interface"] --> MemoryInterface["Memory Interface"]
    MemoryInterface --> AddressDecoder["Address Decoder"]
    MemoryInterface --> ControlRegisters["Control Registers"]
    MemoryInterface --> Static_Memory_Controller["Static Memory Controller"]

    ExternalBus --> EBIA<23:0>[EBIA<23:0>]
    ExternalBus --> EBID<15:0>[EBID<15:0>]
    ExternalBus --> EBIBS<1:0>[EBIBS<1:0>]
    ExternalBus --> EBICS<3:0>[EBICS<3:0>]
    ExternalBus --> EBIOE["EBIOE"]
    ExternalBus --> EBIRP["EBIRP"]
    ExternalBus --> EBIWE["EBIWE"]
    ExternalBus --> EBIRDY<3:1>[EBIRDY<3:1>]

24.1 EBI Control Registers

TABLE 24-2: EBI REGISTER MAP

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W	0 R/W-0
31:24	CSADDR<15:8>
23:16	R/W-0 R/W	0 R/W-0 R/W-0	R/W-0 R/W-0 R/W	0 R/W-0
23:16	CSADDR<7:0>
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
15:8	— — —	— — — — —
7:0	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
7:0	— — —	— — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 CSADDR<15:0>: Base Address for Device bits

Address in physical memory, which will select the external device.

bit 15-0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U	-	0	U	-	0	U	-	0
31:24	——	——	——
23:16	U	-	0	U	-	0	U	-	0
23:16	——	——	——
15:8	U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8	—— — — REGSEL<2:0>
7:0	R/W-0 R/W	0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0	MEMTYPE<2:0> MEMSIZE<4:0> (1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-11 Unimplemented: Read as '0'

bit 10-8 REGSEL<2:0>: Timing Register Set for Chip Select 'x' bits
111 = Reserved
:
.
011 = Reserved
010 = Use EBISMT2
001 = Use EBISMT1
000 = Use EBISMT0

bit 7-5 MEMTYPE<2:0>: Select Memory Type for Chip Select 'x' bits
111 = Reserved
:
.
011 = Reserved
010 = NOR-Flash
001 = SRAM
000 = Reserved

bit 4-0 MEMSIZE<4:0>: Select Memory Size for Chip Select 'x' bits ^(1) 11111 = Reserved

01010 = Reserved

01001 = 16 MB

01000 = 8 MB

00111 = 4 MB

00110 = 2 MB

00101 = 1 MB

00100 = 512 KB

00011 = 256 KB

00010 = 128 KB

00001 = 64 KB (smaller memories alias within this range)

00000 = Chip Select is not used

Note 1: The specified value for these bits depends on the number of available address lines. Refer to the specific device pin table (Table 2 through Table 5) for the available address lines.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 R/W-1	R/W-0 R/W-0
31:24	— — —	— — RDYMODE PAGESI	ZE<1:0>
23:16	R/W-0 R/W-0	R/W-0 R/W-1 R	W-1 R/W-1 R/W-0	R/W-0
23:16	PAGEMODE	TPRC<3:0>	(1)			TBTA<2:0>(1)
15:8	R/W-0 R/W-0	R/W-1 R/W-0 R	W-1 R/W-1 R/W-0	R/W-1
15:8	TWP<5:0>(1)						TWR<1:0>(1)
7:0	R/W-0 R/W-1	R/W-0 R/W-0 R	W-1 R/W-0 R/W-1	R/W-1
7:0	TAS<1:0>(1)		TRC<5:0>(1)

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-27 Unimplemented: Read as '0'

bit 26 RDYMODE: Data Ready Device Select bit

The device associated with register set 'x' is a data-ready device, and will use the EBIRDYx pin.

1 = EBIRDYx input is used

0 = EBIRDYx input is not used

bit 25-24 PAGESIZE<1:0>: Page Size for Page Mode Device bits

11 = 32-word page

10 = 16-word page

01 = 8-word page

00 = 4-word page

bit 23 PAGEMODE: Memory Device Page Mode Support bit

1 = Device supports Page mode

0 = Device does not support Page mode

bit 22-19 TPRC<3:0>: Page Mode Read Cycle Time bits ^(1)

Read cycle time is TPRC + 1 clock cycle.

bit 18-16 TBTA<2:0>: Data Bus Turnaround Time bits ^(1)

Clock cycles (0-7) for static memory between read-to-write, write-to-read, and read-to-read when Chip Select changes.

bit 15-10 TWP<5:0>: Write Pulse Width bits ^(1)

Write pulse width is TWP + 1 clock cycle.

bit 9-8 TWR<1:0>: Write Address/Data Hold Time bits ^(1)

Number of clock cycles to hold address or data on the bus.

bit 7-6 TAS<1:0>: Write Address Setup Time bits ^(1)

Clock cycles for address setup time. A value of '0' is only valid in the case of SSRAM.

bit 5-0 TRC<5:0>: Read Cycle Time bits ^(1)

Read cycle time is TRC + 1 clock cycle.

Note 1: Please refer to Section 47. "External Bus Interface (EBI)" (DS60001245) in the "PIC32 Family Reference Manual" for the EBI timing diagrams and additional information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 R/W-0	R/W-0	R/W-0 R/W-0
15:8	— — —	— TRPD<11:8>
7:0	R/W-0 R/W	0 R/W-0	R/W-0	R/W-0 R/W-0	0 R/W-0
7:0	TRPD<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-12 Unimplemented: Read as '0'

bit 11-0 TRPD<11:0>: Flash Timing bits

These bits define the number of clock cycles to wait after resetting the external Flash memory before any read/write access.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24	— — — —	— — — —
23:16	U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16	— — — —	— — — —
15:8	R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1			R/W-0
15:8	SMDWIDTH2<2:0>			SMDWIDTH1<2:0>			SMDWIDTH0<2:1>
7:0	R/W-0	U-0 U-0 U-0 U-0 U-0 U-0		R/W-1
7:0	SMDWIDTH0<0>	—	—	—	—	—	—	SMRP

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15-13 SMDWIDTH2<2:0>: Static Memory Width for Register EBISMT2 bits

111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits

bit 12-10 SMDWIDTH1<2:0>: Static Memory Width for Register EBISMT1 bits

111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits

bit 9-7 SMDWIDTH0<2:0>: Static Memory Width for Register EBISMT0 bits

111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits

bit 6-1 Unimplemented: Read as '0'

bit 0 SMRP: Flash Reset/Power-down mode Select bit

After a Reset, the controller internally performs a power-down for Flash, and then sets this bit to '1'.

1 = Flash is taken out of Power-down mode
0 = Flash is forced into Power-down mode

NOTES:

25.0 REAL-TIME CLOCK AND CALENDAR (RTCC)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time.

The following are key features of the RTCC module:

• Time: hours, minutes and seconds
• 24-hour format (military time)
- Visibility of one-half second period
- Provides calendar: Weekday, date, month and year
- Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month, and one year
- Alarm repeat with decrementing counter
- Alarm with indefinite repeat: Chime
• Year range: 2000 to 2099
- Leap year correction
• BCD format for smaller firmware overhead
- Optimized for long-term battery operation
• Fractional second synchronization
- User calibration of the clock crystal frequency with auto-adjust
- Calibration range: ±0.66 seconds error per month
- Calibrates up to 260 ppm of crystal error
- Uses external 32.768 kHz crystal or 32 kHz internal oscillator
- Alarm pulse, seconds clock, or internal clock output on RTCC pin

FIGURE 25-1: RTCC BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - REAL-TIME CLOCK AND CALENDAR (RTCC) - 1

flowchart

graph TD
    A["32.768 kHz Input from Secondary Oscillator (SOSC)"] --> B["RTCC Prescalers"]
    C["32 kHz Input from Internal Oscillator (LPRC)"] --> B
    B --> D["0.5 seconds"]
    D --> E["RTCC Timer"]
    E --> F["Comparator"]
    F --> G["Compare Registers with Masks"]
    G --> H["Repeat Counter"]
    H --> I["RTCC Interrupt Logic"]
    I --> J["RTCC Interrupt"]
    J --> K["RTCOE"]
    K --> L["RTCC Pin"]
    M["Year, MTH, DAY"] --> N["RTCVAL"]
    O["WKDAY"] --> N
    P["HR, MIN, SEC"] --> N
    Q["MTH, DAY"] --> R["ALRMVAL"]
    S["WKDAY"] --> R
    T["HR, MIN, SEC"] --> R
    U["RTCOUTSEL<1:0>"] --> V["RTCC Interrupt"]
    W["Alarm Event"] --> I
    X["Alarm Pulse"] --> I
    Y["Seconds Pulse"] --> I
    Z["TRTC"] --> I

25.1 RTCC Control Registers

TABLE 25-1: RTCC REGISTER MAP

Virtual Address(BF80 #)	Register Name(1)	Bit Range	Bits																All Resets
Virtual Address(BF80 #)	Register Name(1)	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
0C00	RTCCON	31:16	—	—	—	—	—	—	CAL<9:0>										0000
0C00	RTCCON	15:0	ON	—	SIDL	—	—	RTCCLKSEL<1:0>		RTCOUTSEL<1:0>	RTCCLKON	—	—	RTCWREN	RTCSYNC	HALFSEC	RTCOE	0000
0C10	RTCALRM	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0C10	RTCALRM	15:0	ALRMEN	CHIME	PIV	ALRMSYNC	AMASK<3:0>				ARPT<7:0>								0000
0C20	RTCTIME	31:16	—	—	HR10<1:0>		HR01<3:0>				—	MIN10<2:0>			MIN01<3:0>				xxxxx
0C20	RTCTIME	15:0	—	SEC10<2:0>			SEC01<3:0>				—	—	—	—	—	—	—	xx00
0C30	RTCDATE	31:16	YEAR10<3:0>				YEAR01<3:0>				—	—	—	MONTH10	MONTH01<3:0>				xxxxx
0C30	RTCDATE	15:0	—	—	DAY10<1:0>		DAY01<3:0>				—	—	—	—	—	WDAY01<2:0>			xx00
0C40	ALRMTIME	31:16	—	—	HR10<1:0>		HR01<3:0>				—	MIN10<2:0>			MIN01<3:0>				xxxxx
0C40	ALRMTIME	15:0	—	SEC10<2:0>			SEC01<3:0>				—	—		—	—	—	—	xx00
0C50	ALRMDATE	31:16	—	—	—	—	—	—	—	—	—	—	—	MONTH10	MONTH01<3:0>				00xx
0C50	ALRMDATE	15:0	—	—	DAY10<1:0>		DAY01<3:0>				—	—	—	—	—	WDAY01<2:0>			xx00x

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 R/W-0	R/W-0
31:24	—— — — —	— — —	C		A	L	< 9
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0	R/W-0 R/W-0
23:16	CAL<7:0>
15:8	R/W-0	U-0	R/W-0	U-0	U-0	R/W-0	R/W-0	R/W-0
15:8	ON(1)	—	SIDL	—	—	RTCCLKSEL<1:0>		RTC OUTSEL<1>(2)
7:0	R/W-0 R-0 U-0	U-0	R/W-0	R-0 R-0 R/W-0
7:0	RTC OUTSEL<0>(2)	RTC CLKON(5)	—	—	RTC WREN(3)	RTC SYNC	HALFSEC(4)	RTCOE

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-26 Unimplemented: Read as '0'

bit 25-16 CAL<9:0>: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value

0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute

0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute
.
.
.
1000000000 = Maximum negative adjustment, subtracts 512 real-time clock pulses every one minute

bit 15 ON: RTCC On bit ^(1)

1 = RTCC module is enabled
0 = RTCC module is disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Stop in Idle Mode bit

1 = Disables RTCC operation when CPU enters Idle mode
0 = Continue normal operation when CPU enters Idle mode

bit 12-11 Unimplemented: Read as '0'

Note 1: The ON bit is only writable when RTCWREN = 1.

2: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.

3: The RTCWREN bit can be set only when the write sequence is enabled.

4: This bit is read-only. It is cleared to '0' on a write to the seconds bit fields (RTCTIME<14:8>).

5: This bit is undefined when RTCCLKSEL<1:0>=00 (LPRC is the clock source).

Note: This register is reset only on a Power-on Reset (POR).

REGISTER 25-1: RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER

bit 10-9 RTCCLKSEL<1:0>: RTCC Clock Select bits

When a new value is written to these bits, the Seconds Value register should also be written to properly reset the clock prescalers in the RTCC.

11 = Reserved

10 = Reserved

01 = RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)

00 = RTCC uses the internal 32 kHz oscillator (LPRC)

bit 8-7 RTCOUTSEL<1:0>: RTCC Output Data Select bits (2)

11 = Reserved

10 = RTCC Clock is presented on the RTCC pin

01 = Seconds Clock is presented on the RTCC pin

00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered

bit 6 RTCCLKON: RTCC Clock Enable Status bit (5)

1 = RTCC Clock is actively running

0 = RTCC Clock is not running

bit 5-4 Unimplemented: Read as '0'

bit 3 RTCWREN: Real-Time Clock Value Registers Write Enable bit ^(3)

1 = Real-Time Clock Value registers can be written to by the user

0 = Real-Time Clock Value registers are locked out from being written to by the user

bit 2 RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit

1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid data read). If the register is read twice and results in the same data, the data can be assumed to be valid.

0 = Real-time clock value registers can be read without concern about a rollover ripple

bit 1 HALFSEC: Half-Second Status bit (4)

1 = Second half period of a second

0 = First half period of a second

bit 0 RTCOE: RTCC Output Enable bit

1 = RTCC output is enabled

0 = RTCC output is not enabled

Note 1: The ON bit is only writable when RTCWREN = 1.

2: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.

3: The RTCWREN bit can be set only when the write sequence is enabled.

4: This bit is read-only. It is cleared to '0' on a write to the seconds bit fields (RTCTIME<14:8>).

5: This bit is undefined when RTCCLKSEL<1:0> = 00 (LPRC is the clock source).

Note: This register is reset only on a Power-on Reset (POR).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— —	—	— —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— —	—	— —
15:8	R/W-0	R/W-0	R/W-0	R-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	ALRMEN(1,2)	CHIME(2)	PIV(2)	ALRMSYNC	AMASK<3:0>(2)
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	ARPT<7:0>(2)

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ALRMEN: Alarm Enable bit ^(1,2)

1 = Alarm is enabled

0 = Alarm is disabled

bit 14 CHIME: Chime Enable bit ^(2)

1 = Chime is enabled - ARPT<7:0> is allowed to rollover from 0x00 to 0xFF

0 = Chime is disabled - ARPT<7:0> stops once it reaches 0x00

bit 13 PIV: Alarm Pulse Initial Value bit ^(2)

When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.

When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.

bit 12 ALRMSYNC: Alarm Sync bit

1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.

The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing.

0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 real-time clocks away from a half-second rollover

bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits ^(2)

0000 = Every half-second

0001 = Every second

0010 = Every 10 seconds

0011 = Every minute

0100 = Every 10 minutes

0101 = Every hour

0110 = Once a day

0111 = Once a week

1000 = Once a month

1001 = Once a year (except when configured for February 29, once every four years)

1010 = Reserved

1011 = Reserved

11xx = Reserved

Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.

2: This field should not be written when the RTCC ON bit = '1' (RTCCON<15>) and ALRMSYNC = 1.

Note: This register is reset only on a Power-on Reset (POR).

REGISTER 25-2: RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED)
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits (2) 11111111 = Alarm will trigger 256 times : . 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.

Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0. 2: This field should not be written when the RTCC ON bit = '1' (RTCCON<15>) and ALRMSYNC = 1.

Note: This register is reset only on a Power-on Reset (POR).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 R/W-x R/W-x R/W-x		R/W-x R/W-x R/W-x
31:24	— — HR10<1:0> HR01<3:0>
23:16	U-0	R/W-x R/W-x R/W-x R/W-x R/W-x
23:16	—	MIN10<2:0>			MIN01<3:0>
15:8	U-0	R/W-x R/W-x R/W-x R/W-x
15:8	—	SEC10<2:0>			SEC01<3:0>
7:0	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
7:0	—	—	—	—	—	—	—	—

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as '0'

bit 29-28 HR10<1:0>: Binary-Coded Decimal Value of Hours bits, tens digit; contains a value from 0 to 2

bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, ones digit; contains a value from 0 to 9

bit 23 Unimplemented: Read as '0'

bit 22-20 MIN10<2:0>: Binary-Coded Decimal Value of Minutes bits, tens digit; contains a value from 0 to 5

bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, ones digit; contains a value from 0 to 9

bit 15 Unimplemented: Read as '0'

bit 14-12 SEC10<2:0>: Binary-Coded Decimal Value of Seconds bits, tens digit; contains a value from 0 to 5

bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, ones digit; contains a value from 0 to 9

bit 7-0 Unimplemented: Read as '0'

Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-x R/W-x	R/W-x R/W-x R/W-x	W-x R/W-x R/W-x	R/W-x
31:24	YEAR10<3:0> YEAR01<3:0>
23:16	U-0 U-0 U-0	R/W-x R/W-x R/W-x	W-x R/W-x R/W-x
23:16	—	—	—	MONTH10	MONTH01<3:0>
15:8	U-0 U-0 R/W-x	R/W-x R/W-x R/W-x	R/W-x R/W-x R/W-x
15:8	—	—	DAY10<1:0>		DAY01<3:0>
7:0	U-0 U-0 U-0	U-0	U-0	R/W-x R/W-x R/W-x
7:0	—	—	—	—	—	WDAY01<2:0>

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, tens digit

bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, ones digit

bit 23-21 Unimplemented: Read as '0'

bit 20 MONTH10: Binary-Coded Decimal Value of Months bit, tens digit; contains a value from 0 to 1

bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, ones digit; contains a value from 0 to 9

bit 15-14 Unimplemented: Read as '0'

bit 13-12 DAY10<1:0>: Binary-Coded Decimal Value of Days bits, tens digit; contains a value from 0 to 3

bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, ones digit; contains a value from 0 to 9

bit 7-3 Unimplemented: Read as '0'

bit 2-0 WDAY01<2:0>: Binary-Coded Decimal Value of Weekdays bits, ones digit; contains a value from 0 to 6

Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 R/W-x R/W-x R/W-x		R/W-x R/W-x R/W-x
31:24	— — HR10<1:0> HR01<3:0>
23:16	U-0	R/W-x R/W-x R/W-x R/W-x R/W-x
23:16	—	MIN10<2:0>			MIN01<3:0>
15:8	U-0	R/W-x R/W-x R/W-x R/W-x
15:8	—	SEC10<2:0>			SEC01<3:0>
7:0	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
7:0	—	—	—	—	—	—	—	—

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as '0'

bit 29-28 HR10<1:0>: Binary Coded Decimal value of hours bits, tens digit; contains a value from 0 to 2

bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, ones digit; contains a value from 0 to 9

bit 23 Unimplemented: Read as '0'

bit 22-20 MIN10<2:0>: Binary Coded Decimal value of minutes bits, tens digit; contains a value from 0 to 5

bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, ones digit; contains a value from 0 to 9

bit 15 Unimplemented: Read as '0'

bit 14-12 SEC10<2:0>: Binary Coded Decimal value of seconds bits, tens digit; contains a value from 0 to 5

bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, ones digit; contains a value from 0 to 9

bit 7-0 Unimplemented: Read as '0'

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	——	——	——
23:16	U-0	U-0	U-0	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x
23:16	——	MONTH10		MONTH01<3:0>
15:8	U-0	U-0	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x
15:8	——	DAY10<1:0>			DAY01<3:0>
7:0	U-0 U-0 U-0	U-0 U-0	R/W-x	R/W-x	R/W-x
7:0	——	——	WDAY01<2:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-21 Unimplemented: Read as '0'

bit 20 MONTH10: Binary Coded Decimal value of months bit, tens digit; contains a value from 0 to 1

bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, ones digit; contains a value from 0 to 9

bit 15-14 Unimplemented: Read as '0'

bit 13-12 DAY10<1:0>: Binary Coded Decimal value of days bits, tens digit; contains a value from 0 to 3

bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, ones digit; contains a value from 0 to 9

bit 7-3 Unimplemented: Read as '0'

bit 2-0 WDAY01<2:0>: Binary Coded Decimal value of weekdays bits, ones digit; contains a value from 0 to 6

26.0 CRYPTO ENGINE

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Crypto Engine is intended to accelerate applications that need cryptographic functions. By executing these functions in the hardware module, software overhead is reduced, and actions such as encryption, decryption, and authentication can execute much more quickly.

The Crypto Engine uses an internal descriptor-based DMA for efficient programming of the security association data and packet pointers (allowing scatter/gather data fetching). An intelligent state machine schedules the Crypto Engines based on the protocol selection and packet boundaries. The hardware engines can perform the encryption and authentication in sequence or in parallel.

Note: To avoid cache coherency problems on devices with L1 cache, Crypto buffers must only be allocated or accessed from the KSEG1 segment.

Key features of the Crypto Engine include:

Bulk ciphers and hash engines
Integrated DMA to off-load processing:
Buffer descriptor-based
Secure association per buffer descriptor
Some functions can execute in parallel

Bulk ciphers that are handled by the Crypto Engine include:

• AES:
- 128-bit, 192-bit, and 256-bit key sizes
- CBC, ECB, CTR, CFB, and OFB modes
• DES/TDES:
- CBC, ECB, CFB, and OFB modes

Authentication engines that are available through the Crypto Engine include:

• S H A - 1
• S H A - 2 5 6
• M D - 5

• AES-GCM

- HMAC operation (for all authentication engines)

The rate of data that can be processed by the Crypto Engine depends on a number of factors, including:

- Which engine is in use

- Whether the engines are used in parallel or in series

- The demands on source and destination memories by other parts of the system (i.e., CPU, DMA, etc.)

- The speed of PBCLK5, which drives the Crypto Engine

Table 26-1 shows typical performance for various engines.

TABLE 26-1: CRYPTO ENGINE PERFORMANCE

Engine/ Algorithm	Performance Factor (Mbps/MHz)	Maximum Mbps (PBCLK5 = 100 MHz)
DES	14.4	1440
TDES	6.6	660
AES-128	9.0	900
AES-192	7.9	790
AES-256	7.2	720
MD5	15.6	1560
SHA-1	13.2	1320
SHA-256	9.3	930

FIGURE 26-1: CRYPTO ENGINE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - CRYPTO ENGINE - 1

flowchart

graph LR
    A["System Bus"] <--> B["SFR System Bus"]
    C["INB FIFO"] --> D["Packet RD"]
    E["DMA Controller"] --> F["Crypto FSM"]
    G["OUTB FIFO"] --> H["Packet WR"]
    I["Local Bus"] --> J["AES"]
    I --> K["TDES"]
    I --> L["SHA-1 SHA-256"]
    I --> M["MD5"]
    A <--> C
    C <--> E
    C <--> G
    C <--> I
    D <--> F
    D <--> H
    F <--> H
    H <--> I
    I <--> J
    I <--> K
    I <--> L
    I <--> M
    P["PBCLK5"] --> A

26.1 Crypto Engine Control Registers

TABLE 26-2: CRYPTO ENGINE REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
31:24	REVISION<7:0>
23:16	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
23:16	VERSION<7:0>
15:8	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
15:8	ID<15:8>
7:0	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
7:0	ID<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-24 REVISION<7:0>: Crypto Engine Revision bits

bit 23-16 VERSION<7:0>: Crypto Engine Version bits

bit 15-0 ID<15:0>: Crypto Engine Identification bits

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	— — —	— — — — —
7:0	U-0	R/W-0, HC	R/W-0	U-0	U-0	R/W-0	R/W-0	R/W-0
7:0	—	SWRST	SWAPEN	—	—	BDPCHST	BDPPLEN	DMAEN

Legend:	HC = Hardware Cleared
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-7 Unimplemented: Read as '0'

bit 6 SWRST: Software Reset bit

1 = Initiate a software reset of the Crypto Engine
0 = Normal operation

bit 5 SWAPEN: I/O Swap Enable bit

1 = Input data is byte swapped when read by dedicated DMA
0 = Input data is not byte swapped when read by dedicated DMA

bit 4-3 Unimplemented: Read as '0'

bit 2 BDPCHST: Buffer Descriptor Processor (BDP) Fetch Enable bit

This bit should be enabled only after all DMA descriptor programming is completed.

1 = BDP descriptor fetch is enabled
0 = BDP descriptor fetch is disabled

bit 1 BDPPLEN: Buffer Descriptor Processor Poll Enable bit

This bit should be enabled only after all DMA descriptor programming is completed.

1 = Poll for descriptor until valid bit is set
0 = Do not poll

bit 0 DMAEN: DMA Enable bit

1 = Crypto Engine DMA is enabled
0 = Crypto Engine DMA is disabled

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
31:24	BDPADDR<31:24>
23:16	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
23:16	BDPADDR<23:16>
15:8	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
15:8	BDPADDR<15:8>
7:0	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
7:0	BDPADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 BDPADDR<31:0>: Current Buffer Descriptor Process Address Status bits

These bits contain the current descriptor address that is being processed by the Buffer Descriptor Processor (BDP).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	BASEADDR<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	BASEADDR<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	BASEADDR<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	BASEADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 BASEADDR<31:0>: Buffer Descriptor Base Address bits

These bits contain the physical address of the first Buffer Descriptor in the Buffer Descriptor chain. When enabled, the Crypto DMA begins fetching Buffer Descriptors from this address.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0 R-0 R-0 R-0 R-0 R-0 R-0		R-0
31:24	ERRMODE<2:0> ERROP<2:0> ERRPHASE<1:0>
23:16	U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16	—	—	BDSTATE				START	ACTIVE
15:8	R-0 R-0 R-0 R-0 R-0 R-0 R-0		R-0
15:8	BDCTRL<15:8>
7:0	R-0 R-0 R-0 R-0 R-0 R-0 R-0		R-0
7:0	BDCTRL<7:0>

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-29 ERRMOD<2:0>: Internal Error Mode Status bits

111 = Reserved

110 = Reserved

101 = Reserved

100 = Reserved

011 = CEK operation

010 = KEK operation

001 = Preboot authentication

000 = Normal operation

bit 28-26 ERROP<2:0>: Internal Error Operation Status bits

111 = Reserved

110 = Reserved

101 = Reserved

100 = Authentication

011 = Reserved

010 = Decryption

001 = Encryption

000 = Reserved

bit 25-24 ERRPHASE<1:0>: Internal Error Phase of DMA Status bits

11 = Destination data

10 = Source data

01 = Security Association (SA) access

00 = Buffer Descriptor (BD) access

bit 23-22 Unimplemented: Read as '0'

bit 21-18 BDSTATE<3:0>: Buffer Descriptor Processor State Status bits

These bits contain a number, which indicates the current state of the BDP:

1111 = Reserved

0111 = Reserved

0110 = SA fetch

0101 = Fetch BDP is disabled

0100 = Descriptor is done

0011 = Data phase

0010 = BDP is loading

0001 = Descriptor fetch request is pending

0000 = BDP is idle

bit 17 START: DMA Start Status bit

1 = DMA start has occurred

0 = DMA start has not occurred

REGISTER 26-5: CESTAT: CRYPTO ENGINE STATUS REGISTER (CONTINUED)

bit 16 ACTIVE: Buffer Descriptor Processor Status bit

1 = BDP is active
0 = BDP is idle

bit 15-0 BDCTRL<15:0>: Descriptor Control Word Status bits

These bits contain the current descriptor control word.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — — — —
7:0	U-0 U-0 U-0	U-0 R-0 R-0 R-0	R-0
7:0	—	—	—	—	AREIF	PKTIF	CBDIF	PENDIF

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as '0'

bit 3 AREIF: Access Response Error Interrupt bit

1 = Error occurred trying to access memory outside the Crypto Engine
0 = No error has occurred

bit 2 PKTIF: DMA Packet Completion Interrupt Status bit

1 = DMA packet was completed
0 = DMA packet was not completed

bit 1 CBDIF: BD Transmit Status bit

1 = Last BD transmit was processed
0 = Last BD transmit has not been processed

bit 0 PENDIF: Crypto Engine Interrupt Pending Status bit

1 = Crypto Engine interrupt is pending (this value is the result of an OR of all interrupts in the Crypto Engine)
0 = Crypto Engine interrupt is not pending

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — — — —
7:0	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	—	AREIE	PKTIE	BDPIE	PENDIE^(1)

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as '0'

bit 3 AREIE: Access Response Error Interrupt Enable bit

1 = Access response error interrupts are enabled
0 = Access response error interrupts are not enabled

bit 2 PKTIE: DMA Packet Completion Interrupt Enable bit

1 = DMA packet completion interrupts are enabled
0 = DMA packet completion interrupts are not enabled

bit 1 BDPIE: DMA Buffer Descriptor Processor Interrupt Enable bit

1 = BDP interrupts are enabled
0 = BDP interrupts are not enabled

bit 0 PENDIE: Master Interrupt Enable bit ^(1)

1 = Crypto Engine interrupts are enabled
0 = Crypto Engine interrupts are not enabled

Note 1: The PENDIE bit is a Global enable bit and must be enabled together with the other interrupts desired.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— —— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	—— —— ——
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	BDPPLCON<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	BDPPLCON<7:0>

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 BDPPLCON<15:0>: Buffer Descriptor Processor Poll Control bits

These bits determine the number of SYSCLK cycles that the Crypto DMA would wait before refetching the descriptor control word if the Buffer Descriptor fetched was disabled.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	———	——— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	———	——— ——
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	———	——— ——
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	HDRLEN<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as '0'

bit 7-0 HDRLEN<7:0>: DMA Header Length bits

For every packet, skip this length of locations and start filling the data.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0		U-0 U-0 U-0 U-0 U-0
31:24	———	——— —— ——
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
23:16	———	——— —— ——
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	———	——— —— ——
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	TRLRLEN<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as '0'

bit 7-0 TRLRLEN<7:0>: DMA Trailer Length bits

For every packet, skip this length of locations at the end of the current packet and start putting the next packet.

26.2 Crypto Engine Buffer Descriptors

Host software creates a linked list of buffer descriptors and the hardware updates them. Table 26-3 provides a list of the Crypto Engine buffer descriptors, followed by format descriptions of each buffer descriptor (see Figure 26-2 through Figure 26-9).

TABLE 26-3: CRYPTO ENGINE BUFFER DESCRIPTORS

Name (see Note 1)		Bit31/2315/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
BD_CTRL	31:24	DESC_EN	—	CRY_MODE<2:0>			—	—	—
	23:16	—	SA_FETCH_EN	—	—	LAST_BD	LIFM	PKT_INT_EN	CBD_INT_EN
	15:8	BD_BUFLEN<15:8>
	7:0	BD_BUFLEN<7:0>
BD_SA_ADDR	31:24	BD_SAADDR<31:24>
	23:16	BD_SAADDR<23:16>
	15:8	BD_SAADDR<15:8>
	7:0	BD_SAADR<7:0>
BD_SCRADDR	31:24	BD_SRCADDR<31:24>
	23:16	BD_SRCADDR<23:16>
	15:8	BD_SRCADDR<15:8>
	7:0	BD_SRCADDR<7:0>
BD_DSTADDR	31:24	BD_DSTADDR<31:24>
	23:16	BD_DSTADDR<23:16>
	15:8	BD_DSTADDR<15:8>
	7:0	BD_DSTADDR<7:0>
BD_NXTPTR	31:24	BD_NXTADDR<31:24>
	23:16	BD_NXTADDR<23:16>
	15:8	BD_NXTADDR<15:8>
	7:0	BD_NXTADDR<7:0>
BD_UPDPTR	31:24	BD_UPDADDR<31:24>
	23:16	BD_UPDADDR<23:16>
	15:8	BD_UPDADDR<15:8>
	7:0	BD_UPDADDR<7:0>
BD_MSG_LEN	31:24	MSG_LENGTH<31:24>
	23:16	MSG_LENGTH<23:16>
	15:8	MSG_LENGTH<15:8>
	7:0	MSG_LENGTH<7:0>
BD_ENC_OFF	31:24	ENCR_OFFSET<31:24>
	23:16	ENCR_OFFSET<23:16>
	15:8	ENCR_OFFSET<15:8>
	7:0	ENCR_OFFSET<7:0>

Note 1: The buffer descriptor must be allocated in memory on a 64-bit boundary.

FIGURE 26-2: FORMAT OF BD_CTRL

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 DESC_EN		— CRY_MODE<2:0> — — —
23-16	—	SA nuclei	—— LAST_BD LIFM				PKT_INT_EN	CBD_INT_EN
15-8	BD_BUFLEN<15:8>
7-0	BD_BUFLEN<7:0>

bit 31 DESC_EN: Descriptor Enable

1 = The descriptor is owned by hardware. After processing the BD, hardware resets this bit to '0'.
0 = The descriptor is owned by software

bit 30 Unimplemented: Must be written as '0'

bit 29-27 CRY_MODE<2:0>: Crypto Mode

111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = CEK operation
010 = KEK operation
001 = Preboot authentication
000 = Normal operation

bit 22 SA_FETCH_EN: Fetch Security Association From External Memory

1 = Fetch SA from the SA pointer. This bit needs to be set to '1' for every new packet.
0 = Use current fetched SA or the internal SA

bit 21-20 Unimplemented: Must be written as '0'

bit 19 LAST_BD: Last Buffer Descriptors

1 = Last Buffer Descriptor in the chain
0 = More Buffer Descriptors in the chain
After the last BD, the CEBDADDR goes to the base address in CEBDPADDR.

bit 18 LIFM: Last In Frame

In case of Receive Packets (from H/W-> Host), this field is filled by the Hardware to indicate whether the packet goes across multiple buffer descriptors. In case of transmit packets (from Host -> H/W), this field indicates whether this BD is the last in the frame.

bit 17 PKT_INT_EN: Packet Interrupt Enable

Generate an interrupt after processing the current buffer descriptor, if it is the end of the packet.

bit 16 CBD_INT_EN: CBD Interrupt Enable

Generate an interrupt after processing the current buffer descriptor.

bit 15-0 BD_BUFLEN<15:0>: Buffer Descriptor Length

This field contains the length of the buffer and is updated with the actual length filled by the receiver.

FIGURE 26-3: FORMAT OF BD_SADDR

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 BD_SAADDR<31:24>
23-16 BD_SAADDR<23:16>
15-8				BD_SAADDR<15:8>
7-0				BD_SAADDR<7:0>

bit 31-0 BD_SAADDR<31:0>: Security Association IP Session Address

The sessions' SA pointer has the keys and IV values.

FIGURE 26-4: FORMAT OF BD_SRCADDR

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 BD_SCRADDR<31:24>
23-16 BD_SCRADDR<23:16>
15-8 BD_SCRADDR<15:8>
7-0 BD_SCRADDR<7:0>

bit 31-0 BD_SCRADDR: Buffer Source Address
The source address of the buffer that needs to be passed through the PE-CRDMA for encryption or authentication. This address must be on a 32-bit boundary.

FIGURE 26-5: FORMAT OF BD_DSTADDR

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 BD_DSTADDR<31:24>
23-16 BD_DSTADDR<23:16>
15-8 BD_DSTADDR<15:8>
7-0 BD_DSTADDR<7:0>

bit 31-0 BD_DSTADDR: Buffer Destination Address
The destination address of the buffer that needs to be passed through the PE-CRDMA for encryption or authentication. This address must be on a 32-bit boundary.

FIGURE 26-6: FORMAT OF BD_NXTADDR

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 BD_NXTADDR<31:24>
23-16 BD_NXTADDR<23:16>
15-8 BD_NXTADDR<15:8>
7-0 BD_NXTADDR<7:0>

bit 31-0 BD_NXTADDR: Next BD Pointer Address Has Next Buffer Descriptor
The next buffer can be a next segment of the previous buffer or a new packet.

FIGURE 26-7: FORMAT OF BD_UPDPTR

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 BD_UPDADDR<31:24>
23-16 BD_UPDADDR<23:16>
15-8 BD_UPDADDR<15:8>
7-0 BD_UPDADDR<7:0>

bit 31-0 BD_UPDADDR: UPD Address Location
The update address has the location where the CRDMA results are posted. The updated results are the ICV values, key output values as needed.

FIGURE 26-8: FORMAT OF BD_MSG_LEN

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 MSG_LENGTH<31:24>
23-16 MSG_LENGTH<23:16>
15-8 MSG_LENGTH<15:8>
7-0 MSG_LENGTH<7:0>

bit 31-0 MSG_LENGTH: Total Message Length
Total message length for the hash and HMAC algorithms in bytes. Total number of crypto bytes in case of GCM algorithm (LEN-C).

FIGURE 26-9: FORMAT OF BD_ENC_OFF

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24 ENCR_OFFSET<31:24>
23-16 ENCR_OFFSET<23:16>
15-8 ENCR_OFFSET<15:8>
7-0 ENCR_OFFSET<7:0>

bit 31-0 ENCR_OFFSET: Encryption Offset
Encryption offset for the multi-task test cases (both encryption and authentication). The number of AAD bytes in the case of GCM algorithm (LEN-A).

26.3 Security Association Structure

Table 26-4 shows the Security Association Structure.

The Crypto Engine uses the Security Association to determine the settings for processing a Buffer Descriptor Processor. The Security Association contains:

• Which algorithm to use
- Whether to use engines in parallel (for both authentication and encryption/decryption)
- The size of the key
- Authentication key
- Encryption/decryption key
- Authentication Initialization Vector (IV)
- Encryption IV

TABLE 26-4: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE

Name		Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
SA_CTRL	31:24	—	—	VERIFY	—	NO_RX	OR_EN	ICVONLY	IRFLAG
	23:16	LNC	LOADIV	FB	FLAGS	—	—	—	ALGO<6>
	15:8	ALGO<5:0>						ENCTYPE	KEYSIZE<1>
	7:0	KEYSIZE<0>	MULTITASK<2:0>			CRYPTOALGO<3:0>
SA_AUTHKEY1	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SA_AUTHKEY2	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SA AUTHKEY3	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SAAUTHKEY4	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SAAuthKEY5	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SA AuthKEY6	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SA_UITHKEY7	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SA_AUTHKEY8	31:24	AUTHKEY<31:24>
	23:16	AUTHKEY<23:16>
	15:8	AUTHKEY<15:8>
	7:0	AUTHKEY<7:0>
SA_ENCKEY1	31:24	ENCKEY<31:24>
	23:16	ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>
SA_ENCKEY2	31:2423:16	ENCKEY<31:24>ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>
SA_ENCKEY3 31	1:24	ENCKEY<31:24>
	23:16	ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>
SA_ENCKEY4 31	1:24	ENCKEY<31:24>
	23:16	ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>
SA_ENCKEY5 31	1:24	ENCKEY<31:24>
	23:16	ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>
SA_ENCKEY6 31	1:24	ENCKEY<31:24>
	23:16	ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>		15:8	ENCKEY<15:8>
SA_ENCKEY7 31	1:24	ENCKEY<31:24>
	23:16	ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>
SA_ENCKEY8 31	1:24	ENCKEY<31:24>
	23:16	ENCKEY<23:16>
	15:8	ENCKEY<15:8>
	7:0	ENCKEY<7:0>
SA_AUTHIV1 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:24>
SA_AUTHIV2 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:31>
SA_AUTHIV3 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:16>
SA_AUTHIV4 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:41>
SA_AUTHIV5 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:51>
SA_AUTHIV6 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:61>
SA_AUTHIV7 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:71>
SA_AUTHIV8 31	24	AUTHIV<31:24>
	23:16	AUTHIV<23:16>
	15:8	AUTHIV<15:8>
	7:0	AUTHIV<7:0>		24	AUTHIV<31:81>
SA_ENCIV1 31:24	ENCIV<31:24>
	23:16	ENCIV<23:16>
	15:8	ENCIV<15:8>
	7:0	ENCIV<7:0>
SA_ENCIV2 31:24	ENCIV<31:24>
	23:16	ENCIV<23:16>
	15:8	ENCIV<15:8>
	7:0	ENCIV<7:0>
SATNCIV3 31:24	ENCIV<31:24>
	23:16	ENCIV<23:16>
	15:8	ENCIV<15:8>
	7:0	ENCIV<7:0>
SANCIV4 31:24	ENCIV<31:24>
	23:16	ENCIV<23:16>
	15:8	ENCIV<15:8>
	7:0	ENCIV<7:0>

Figure 26-10 shows the Security Association control word structure.

The Crypto Engine fetches different structures for different flows and ensures that hardware fetches minimum words from SA required for processing. The structure is ready for hardware optimal data fetches.

FIGURE 26-10: FORMAT OF SA_CTRL

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31-24	—	—	VERIFY	—	NO_RX	OR_EN	ICVONLY	IRFLAG
23-16	LNC	LOADIV	FB	FLAGS	—	—	—	ALGO<6>
15-8	ALGO<5:0>						ENC	KEY SIZE<1>
7-0	KEY SIZE<0>	MULTITASK<2:0>			CRYPTOALGO<3:0>

bit 31-30 Reserved: Do not use

bit 29 VERIFY: NIST Procedure Verification Setting

1 = NIST procedures are to be used
0 = Do not use NIST procedures

bit 28 Reserved: Do not use

bit 27 NO_RX: Receive DMA Control Setting

1 = Only calculate ICV for authentication calculations
0 = Normal processing

bit 26 OR_EN: OR Register Bits Enable Setting

1 = OR the register bits with the internal value of the CSR register
0 = Normal processing

bit 25 ICVONLY: Incomplete Check Value Only Flag

This affects the SHA-1 algorithm only. It has no effect on the AES algorithm.

1 = Only three words of the HMAC result are available
0 = All results from the HMAC result are available

bit 24 IRFLAG: Immediate Result of Hash Setting

This bit is set when the immediate result for hashing is requested.

1 = Save the immediate result for hashing
0 = Do not save the immediate result

bit 23 LNC: Load New Keys Setting

1 = Load a new set of keys for encryption and authentication
0 = Do not load new keys

bit 22 LOADIV: Load IV Setting

1 = Load the IV from this Security Association
0 = Use the next IV

bit 21 FB: First Block Setting

This bit indicates that this is the first block of data to feed the IV value.

1 = Indicates this is the first block of data
0 = Indicates this is not the first block of data

bit 20 FLAGS: Incoming/Outgoing Flow Setting

1 = Security Association is associated with an outgoing flow
0 = Security Association is associated with an incoming flow

bit 19-17 Reserved: Do not use

Figure 26-10: Format of SA_CTRL (Continued)
bit 16-10 ALGO<6:0>: Type of Algorithm to Use 1xxxxxx = HMAC 1 x1xxxxxx = SHA-256 xx1xxxxx = SHA1 xxx1xxx = MD5 xxx1xxx = AES xxxxx1x = TDES xxxxx1x1 = DES

bit 9 ENC: Type of Encryption Setting 1 = Encryption 0 = Decryption

bit 8-7 KEYSIZE<1:0>: Size of Keys in SA_AUTHKEYx or SA_ENCKEYx 11 = Reserved; do not use 10 = 256 bits 01 = 192 bits 00 = 128 bits(1)

bit 6-4 MULTITASK<2:0>: How to Combine Parallel Operations in the Crypto Engine 111 = Parallel pass (decrypt and authenticate incoming data in parallel) 101 = Pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data) 011 = Reserved 010 = Reserved 001 = Reserved 000 = Encryption or authentication or decryption (no pass)

bit 3-0 CRYPTOALGO: Mode of operation for the Crypto Algorithm 1111 = Reserved 1110 = AES_GCM (for AES processing) 1101 = RCTR (for AES processing) 1100 = RCBC_MAC (for AES processing) 1011 = ROFB (for AES processing) 1010 = RCFB (for AES processing) 1001 = RCBC (for AES processing) 1000 = REBC (for AES processing) 0111 = TOFB (for Triple-DES processing) 0110 = TCFB (for Triple-DES processing) 0101 = TCBC (for Triple-DES processing) 0100 = TECB (for Triple-DES processing) 0011 = OFB (for DES processing) 0010 = CFB (for DES processing) 0001 = CBC (for DES processing) 0000 = ECB (for DES processing)
Note 1: This setting does not alter the size of SA_AUTHKEYx or SA_ENCKEYx in the Security Association, only the number of bits of SA_AUTHKEYx and SA_ENCKEYx that are used.

27.0 RANDOM NUMBER GENERATOR (RNG)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49. "Crypto Engine (CE) and Random Number Generator (RNG)" (DS60001246), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Random Number Generator (RNG) core implements a thermal noise-based, True Random Number Generator (TRNG) and a cryptographically secure Pseudo-Random Number Generator (PRNG).

The TRNG uses multiple ring oscillators and the inherent thermal noise of integrated circuits to generate true random numbers that can initialize the PRNG.

The PRNG is a flexible LSFR, which is capable of manifesting a maximal length LFSR of up to 64-bits.

The following are some of the key features of the Random Number Generator:

• TRNG:

Up to 25 Mbps of random bits
Multi-Ring Oscillator based design
Built-in Bias Corrector

- PRNG:

L S F R - b a s e d
Up to 64-bit polynomial length
Programmable polynomial
TRNG can be seed value

TABLE 27-1: RANDOM NUMBER GENERATOR BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - RANDOM NUMBER GENERATOR (RNG) - 1

flowchart

graph TD
    A["System Bus"] --> B["SFR"]
    A --> C["PRNG"]
    B --> D["TRNG"]
    C --> D
    D --> E["BIAS Corrector"]
    E --> F["Edge Comparator"]
    F --> G["Ring Oscillator"]
    F --> H["Ring Oscillator"]
    G --> I["PBCLK5"]
    H --> I
    B <--> C
    D <--> E

27.1 RNG Control Registers

TABLE 27-2: RANDOM NUMBER GENERATOR (RNG) REGISTER MAP

Virtual Address (BF8E_#)	Register Name	Bit Range	Bits																All Resets
Virtual Address (BF8E_#)	Register Name	Bit Range	31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0	All Resets
6000	RNGVER	31:16	ID<15:0>xxxx
6000	RNGVER	15:0	VERSION<7:0>								Revision<7:0>								xxxx
6004	RNGCON	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
6004	RNGCON	15:0	—	—	—	LOAD	—	CONT	PRNGEN	TRNGEN	PLEN<7:0>								0064
6008	RNGPOLY1	31:16	POLY<31:0>																FFFF
6008	RNGPOLY1	15:0	POLY<31:0>																0000
600C	RNGPOLY2	31:16	POLY<31:0>																FFFF
600C	RNGPOLY2	15:0	POLY<31:0>																0000
6010	RNGNUMGEN1	31:16	RNG<31:0>																FFFF
6010	RNGNUMGEN1	15:0	RNG<31:0>																FFFF
6014	RNGNUMGEN2	31:16	RNG<31:0>																FFFF
6014	RNGNUMGEN2	15:0	RNG<31:0>																FFFF
6018	RNGSEED1	31:16	SEED<31:0>																0000
6018	RNGSEED1	15:0	SEED<31:0>																0000
601C	RNGSEED2	31:16	SEED<31:0>																0000
601C	RNGSEED2	15:0	SEED<31:0>																0000
6020	RNGCNT	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
6020	RNGCNT	15:0	—	—	—	—	—	—	—	—	—	—	RCNT<6:0>						0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
31:24	ID<15:8>
23:16	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
23:16	ID<7:0>
15:8	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
15:8	VERSION<7:0>
7:0	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
7:0	REVISION<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 ID<15:0>: Block Identification bits

bit 15-8 VERSION<7:0>: Block Version bits

bit 7-0 REVISION<7:0>: Block Revision bits

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —
15:8	U-0	U-0	U-0	R/W-0	U-0	R/W-0	R/W-0	R/W-0
15:8	—	—	—	LOAD	—	CONT	PRNGEN	TRNGEN
7:0	R/W-0	R/W-1	R/W-1	R/W-0	R/W-0	R/W-1	R/W-0	R/W-0
7:0	PLEN<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as '0'

bit 12 LOAD: Device Select bit

This bit is self-clearing and is used to load the seed from the TRNG (i.e., the random value) as a seed to the PRNG.

bit 11 Unimplemented: Read as '0'

bit 10 CONT: PRNG Number Shift Enable bit

1 = The PRNG random number is shifted every cycle
0 = The PRNG random number is shifted when the previous value is removed

bit 9 PRNGEN: PRNG Operation Enable bit

1 = PRNG operation is enabled
0 = PRNG operation is not enabled

bit 8 TRNGEN: TRNG Operation Enable bit

1 = TRNG operation is enabled
0 = TRNG operation is not enabled

bit 7-0 PLEN<7:0>: PRNG Polynomial Length bits

These bits contain the length of the polynomial used for the PRNG.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-1 R/W-1	R/W-1 R/W-1 R	W-1 R/W-1 R/W-1	R/W-1
31:24	POLY<31:24>
23:16	R/W-1 R/W-1	R/W-1 R/W-1 R	W-1 R/W-1 R/W-1	R/W-1
23:16	POLY<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
15:8	POLY<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0 R	W-0 R/W-0 R/W-0	R/W-0
7:0	POLY<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 POLY<31:0>: PRNG LFSR Polynomial MSb/LSb bits (RNGPOLY1 = LSb, RNGPOLY2 = MSb)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
31:24	RNG<31:24>
23:16	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
23:16	RNG<23:16>
15:8	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
15:8	RNG<15:8>
7:0	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
7:0	RNG<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 RNG<31:0>: Current PRNG MSb/LSb Value bits (RNGNUMGEN1 = LSb, RNGNUMGEN2 = MSb)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
31:24	SEED<31:24>
23:16	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
23:16	SEED<23:16>
15:8	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
15:8	SEED<15:8>
7:0	R-0 R-0 R-0	R-0 R-0 R-0 R-0	R-0
7:0	SEED<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 SEED<31:0>: TRNG MSb/LSb Value bits (RNGSEED1 = LSb, RNGSEED2 = MSb)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0	U-0 U-0 U-0 U-0
31:24	—	—	—	—	—	—	—	—
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
23:16	—	—	—	—	—	—	—	—
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	—	—	—	—	—	—	—	—
7:0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	RCNT<6:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-7 Unimplemented: Read as '0'

bit 6-0 RCNT<6:0>: Number of Valid TRNG MSB 32 bits

28.0 PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC)

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18. "12-bit Pipelined Analog-to-Digital Converter (ADC)" (DS60001194), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The PIC32MZ EC Pipelined Analog-to-Digital Converter (ADC) includes the following features:

10-bit resolution
Six-stage conversion pipeline
External voltage reference input pins
Six Sample and Hold (S&H) circuits, SH0 - SH5:
Five dedicated S&H circuits with individual input selection and individual conversion trigger selection for high-speed conversions
One shared S&H circuit with automatic Input Scan mode and common conversion trigger selection
Up to 48 analog input sources, in addition to the internal voltage reference and an internal temperature sensor
32-bit conversion result registers with dedicated interrupts:
Conversion result can be formatted as unsigned or signed fractional or integer data
Six digital comparators with dedicated interrupts:
Multiple comparison options
Assignable to specific analog input
Six oversampling filters with dedicated interrupts:
Provides increased resolution
Assignable to specific analog input
• Operation during Sleep and Idle modes

Besides the analog inputs that can be converted, there are two analog input pins for external voltage reference connections. These voltage reference inputs can be shared with other analog input pins, and can also be used by other analog module references.

The analog inputs are connected through multiplexers (MUXs) to the S&H circuits. Each of the dedicated S&H circuits, is assigned to analog inputs, and can optionally use another analog input in a differential configuration. The dedicated S&H circuits are used for high-speed and precise sampling/conversion of time sensitive or transient inputs.

The sixth S&H circuit, SH5, can be used in Input Scan mode and is connected to all the available analog inputs on a device, along with internal voltage reference and the temperature sensor signals. Input Scan mode sequentially converts user-specified analog input sources. The control registers specify the analog input sources that are included in the scanning sequence.

A simplified block diagram of the ADC1 module is illustrated in Figure 28-1. Diagrams for the Dedicated and Shared ADC modules are provided in Figure 28-2 and Figure 28-3, respectively.

FIGURE 28-1: ADC1 MODULE BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) - 1

flowchart

graph TD
    A["AN0"] --> B["Sample and Hold 0 (Dedicated)"]
    AN45 --> B
    AN5 --> B
    AN1 --> C["Sample and Hold 1 (Dedicated)"]
    AN46 --> C
    AN6 --> D["Sample and Hold 2 (Dedicated)"]
    AN2 --> E["Sample and Hold 3 (Dedicated)"]
    AN47 --> E
    AN7 --> F["Sample and Hold 4 (Dedicated)"]
    AN3 --> G["Sample and Hold 5 (Shared)"]
    AN48 --> G
    AN9 --> G
    AN5 --> G
    AN42 --> G
    IVREF(AN43) --> G
    IVTEMP(AN44) --> G
    AN10 --> G
    SH0ALT<1:0> --> B
    SH0MOD<1:0> --> B
    SH1ALT<1:0> --> C
    SH1MOD<1:0> --> C
    SH2ALT<1:0> --> D
    SH2MOD<1:0> --> D
    SH3ALT<1:0> --> E
    SH3MOD<1:0> --> E
    SH4ALT<1:0> --> F
    SH4MOD<1:0> --> F
    SH5MOD<1:0> --> G
    ReferenceVoltageSelection["Reference Voltage Selection"] --> B
    AnalogStages["Analog Stages"] --> B
    DigitalStages["Digital Stages"] --> B
    SixDigitalComparators["Six Digital Comparators"] --> Interrupt["Interrupt"]
    SixDigitalFilters["Six Digital Filters"] --> FLTRDATA["FLTRDATA"]
    DigitalFilters --> ResultRegisters["Result Registers"]
    DigitalStages --> ADC1DATA0["ADC1DATA0"]
    DigitalStages --> ADC1DATA44["ADC1DATA44"]
    ADC1DATA0 --> PBCLK3["PBCLK3"]
    ADC1DATA44 --> PBCLK3
    TAD["TAD"] --> Divider["Divider 1, 2, 4, 6,...254"]
    ClockSelection["Clock Selection"] --> ADCDIV["ADCDIV<6:0>"]
    ADCDIV --> ADCSEL["ADCSEL<1:0>"]
    ADCDIV --> FRCSYSCLKREFCLKO3["FRC SYSCLK REFCLKO3"]
    VREFSEL<2:0> --> ReferenceVoltageSelection
    AVDD --> ReferenceVoltageSelection
    AVSS --> ReferenceVoltageSelection
    VREF+ --> ReferenceVoltageSelection
    VREF- --> ReferenceVoltageSelection

FIGURE 28-2: DEDICATED S&H 0-4 BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) - 2

flowchart

graph TD
    A["Positive Input (Class 1)"] --> B["00"]
    C["Alternate Positive Input"] --> D["01"]
    E["Negative Input"] --> F["0x"]
    B --> G["Single-Ended"]
    D --> G
    F --> G
    G --> H["S&H"]
    H --> I["To Analog Stages"]
    G --> J["Differential"]
    J --> K["SHxMOD<1:0>"]
    K --> L["Channel Configuration"]
    L --> M["To Digital Stages"]
    N["VREFL"] --> G
    O["SHxALT<1:0>"] --> L
    P["SHxALT<1:0>"] --> L
    Q["SHxMOD<1:0>"] --> L

FIGURE 28-3: SHARED S&H 5 BLOCK DIAGRAM
Microchip PIC32MZ1024ECM124 - PIPELINED ANALOG-TO-DIGITAL CONVERTER (ADC) - 3

flowchart

graph TD
    A["Positive Input (Class 2)"] --> B["AN5"]
    A --> C["AN11"]
    D["Positive Input (Class 3)"] --> E["AN12"]
    D --> F["AN42"]
    G["IVREF (AN43)"] --> H["Channel Scan Logic"]
    I["IVTEMP (AN44)"] --> H
    H --> J["Single-Ended"]
    J --> K["VREFL 0x"]
    J --> L["Differential 1x"]
    J --> M["SHxMOD<1:0>"]
    N["AN10 (Negative Input)"] --> O["Channel Configuration"]
    P["S&H"] --> Q["To Analog Stages"]
    R["SH5ALT<1:0>"] --> O
    S["SH5MOD<1:0>"] --> O
    O --> T["To Digital Stages"]

28.1 ADC Configuration Requirements

Note: A related code example is available in the latest release of MPLAB Harmony (visit http://www.micochip.com/harmony for more information).

To meet ADC specifications, the following steps must be performed:

Set the ADC Configuration words, as follows:

AD1CAL1 = 0xB3341210;
AD1CAL2 = 0x01FFA769;
AD1CAL3 = 0x0BBBBBB8;
AD1CAL4 = 0x000004AC;
AD1CAL5 = 0x02028002;

Perform self-calibration. The input mode for SH0-SH5 must be set to the unipolar differential input mode by setting the SHxMOD<1:0> bits (AD1MOD<1:0>) = 10.

Note: SH0 through SH4 functionality and ADC Differential mode are not supported; however, both are required for auto-calibration. Sampling must be performed on SH5 only.

In addition, the following restrictions apply:

Supported ADC operating modes:

Scan mode only with DMA interrupt
The maximum number of used ANx inputs are limited by the available DMA channels (maximum of eight)
The first (8) conversion after enabling the ADC must be discarded
• ADC Single-ended mode only
The ADC Clock, T AD, must be limited to 500 kHz ≤ TAD ≤ 1 MHz (i.e., 2 μs ≤ TAD ≤ 1 μs).
HDW Oversampling is supported, but is not required, and will not impair accuracy; however, it will reduce the ADC ANx input throughput by the oversample ratio in use
A N xINVmaximum is limited to ≤ 2.5V
V_REF+ ≤ V_DD = AV_DD ≥ 2.5V
Use of external VREF+ and VREF- pins only for ADC reference (VREFSEL<2:0> bits are equal to 'b011):
VREF- = Can be connected to AVss externally, but not internally
VREF+ can be connected to AVDD externally if required, but not internally

Unsupported ADC operating modes:

Software polling of ADC status bits
Manual software ADC triggering
ADC interrupt modes (use DMA Interrupt mode)
ADC SFR accesses by the CPU while ADC is operating
ADC Boost or low-power mode.
Individual ADC Input Conversion Requests (i.e., RQCNVRT bit in the ADCCON3 register)
Use of ADC S&H Channels 0-4 except for calibration
Any ADC references other than external VREF+ and VREF- pins
ADC Differential mode

28.2 ADC Control Registers

TABLE 28-1: ADC REGISTER MAP

Virtual Address(BFD_1#)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

B000

AD1CON1

31:16

FILTRDLY4:0>

STRGSRC<4:0>

—

EIE<2:0>

0000

15:0

ADCEN

—

ADSIDL

—

FRACT

—

0000

B004

AD1CON2

31:16

ADCRDY

—

SAMC<7:0>

0000

15:0

—

BOOST

LOWPWR

—

ADCSEL<1:0>

—

ADCDIV<6:0>

0000

B008

AD1CON3

31:16

CAL

GSWTRG

RQCNVRT

—

0000

15:0

—

VREFSEL<2:0>

—

ADINSEL<5:0>

0000

B00C

AD1IMOD

31:16

—

SH4ALT<1:0>

SH3ALT<1:0>

SH2ALT<1:0>

SH1ALT<1:0>

SH0ALT<1:0>

0000

15:0

—

SH5MOD<1:0>

SH4MOD<1:0>

SH3MOD<1:0>

SH2MOD<1:0>

SH1MOD<1:0>

SH0MOD<1:0>

0000

B010

AD1GIRQEN1

31:16

AGIEN31

AGIEN30

AGIEN29

AGIEN28

AGIEN27

AGIEN26

AGIEN25

AGIEN24

AGIEN23

AGIEN22

AGIEN21

AGIEN20

AGIEN19

AGIEN18

AGIEN17

AGIEN16

0000

15:0

AGIEN15

AGIEN14

AGIEN13

AGIEN12

AGIEN11

AGIEN10

AGIEN9

AGIEN8

AGIEN7

AGIEN6

AGIEN5

AGIEN4

AGIEN3

AGIEN2

AGIEN1

AGIEN0

0000

B014

AD1GIRQEN2

31:16

—

0000

15:0

—

AGIEN14

AGIEN13

AGIEN12

AGIEN11

AGIEN10

AGIEN9

AGIEN8

AGIEN7

AGIEN6

AGIEN5

AGIEN4

AGIEN3

AGIEN2

0000

B018

AD1CSS1

31:16

CSS31

CSS30

CSS29

CSS28

CSS27

CSS26

CSS25

CSS24

CSS23

CSS22

CSS21

CSS20

CSS19

CSS18

CSS17

CSS16

0000

15:0

CSS15

CSS14

CSS13

CSS12

CSS11

CSS10

CSS9

CSS8

CSS7

CSS6

CSS5

CSS4

CSS3

CSS2

CSS1

CSS0

0000

B01C

AD1CSS2

31:16

—

0000

15:0

—

CSS44

CSS43

CSS42

CSS41

CSS40

CSS39

CSS38

CSS37

CSS36

CSS35

CSS34

CSS33

CSS32

0000

B020

AD1DSTAT1

31:16

ARDY31

ARDY30

ARDY29

ARDY28

ARDY27

ARDY26

ARDY25

ARDY24

ARDY23

ARDY22

ARDY21

ARDY20

ARDY19

ARDY18

ARDY17

ARDY16

0000

15:0

ARDY15

ARDY14

ARDY13

ARDY12

ARDY11

ARDY10

ARDY9

ARDY7

ARDY6

ARDY5

ARDY4

ARDY3

ARDY2

ARDY1

ARDY0

0000

B024

AD1DSTAT2

31:16

—

0000

15:0

—

ARDY44

ARDY43

ARDY42

ARDY41

ARDY40

ARDY39

ARDY38

ARDY37

ARDY36

ARDY35

ARDY34

ARDY33

ARDY32

0000

B028

AD1CMPEN1

31:16

CMPE31

CMPE30

CMPE29

CMPE28

CMPE27

CMPE26

CMPE25

CMPE24

CMPE23

CMPE22

CMPE21

CMPE20

CMPE19

CMPE18

CMPE17

CMPE16

0000

15:0

CMPE15

CMPE14

CMPE13

CMPE12

CMPE11

CMPE10

CMPE9

CMPE8

CMPE7

CMPE6

CMPE5

CMPE4

CMPE3

CMPE2

CMPE1

CMPE0

0000

B02C

AD1CMP1

31:16

ACMPHI<15:0>

0000

15:0

ADCMPLLO<15:0>

0000

B030

AD1CMPEN2

31:16

CMPE31

CMPE30

CMPE29

CMPE28

CMPE27

CMPE26

CMPE25

CMPE24

CMPE23

CMPE22

CMPE21

CMPE20

CMPE19

CMPE18

CMPE17

CMPE16

0000

15.0

CMPE15

CMPE14

CMPE13

CMPE12

CMPE11

CMPE10

CMPE9

CMPE8

CMPE7

CMPE6

CMPE5

CMPE4

CMPE3

CMPE2

CMPE1

CMPE0

0000

B034

AD1CMP2

31:16

ADCMPHI<15:0>

0000

15:0

ADCMPLLO<15:0>

0000

B038

AD1CMPEN3

31:16

CMPE31

CMPE30

CMPE29

CMPE28

CMPE27

CMPE26

CMPE25

CMPE24

CMPE23

CMPE22

CMPE21

CMPE20

CMPE19

CMPE18

CMPE17

CMPE16

0000

15;0

CMPE15

CMPE14

CMPE13

CMPE12

CMPE11

CMPE10

CMPE9

CMPE8

CMPE7

CMPE6

CMPE5

CMPE4

CMPE3

CMPE2

CMPE1

CMPE0

0000

B03C

AD1CMP3

31:16

ADCMPHI<15:0>

0000

15:0

ADCMPLLO<15:0>

0000

B040

AD1CMPEN4

31:16

CMPE31

CMPE30

CMPE29

CMPE28

CMPE27

CMPE26

CMPE25

CMPE24

CMPE23

CMPE22

CMPE21

CMPE20

CMPE19

CMPE18

CMPE17

CMPE16

0000

15,0

CMPE15

CMPE14

CMPE13

CMPE12

CMPE11

CMPE10

CMPE9

CMPE8

CMPE7

CMPE6

CMPE5

CMPE4

CMPE3

CMPE2

CMPE1

CMPE0

0000

B044

AD1CMP4

31:16

ADCMPHI<15:0>

0000

15:0

ADCMPLLO<15:0>

0000

Virtual Address(BP64_#)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

B04B

AD1CMPEN5

31:16

CMPE31

CMPE30

CMPE29

CMPE28

CMPE27

CMPE26

CMPE25

CMPE24

CMPE23

CMPE22

CMPE21

CMPE20

CMPE19

CMPE18

CMPE17

CMPE16

0000

15:0

CMPE15

CMPE14

CMPE13

CMPE12

CMPE11

CMPE10

CMPE9

CMPE8

CMPE7

CMPE6

CMPE5

CMPE4

CMPE3

CMPE2

CMPE1

CMPE0

0000

B04C

AD1CMP5

31:16

ADCMPHI<15:0>

0000

15:0

ADCMPLO<15:0>

0000

B050

AD1CMPEN6

31:16

CMPE31

CMPE30

CMPE29

CMPE28

CMPE27

CMPE26

CMPE25

CMPE24

CMPE23

CMPE22

CMPE21

CMPE20

CMPE19

CMPE18

CMPE17

CMPE16

0000

15.0

CMPE15

CMPE14

CMPE13

CMPE12

CMPE11

CMPE10

CMPE9

CMPE8

CMPE7

CMPE6

CMPE5

CMPE4

CMPE3

CMPE2

CMPE1

CMPE0

0000

B054

AD1CMP6

31:16

ADCMPHI<15:0>

0000

15:0

ADCMPLO<15:0>

0000

B058

AD1FLTR1

31:16

AFEN

—

OVRSAM<2:0>

AFGIEN

AFRDY

—

CHNLID<5:0>

0000

15:0

FLTRDATA<15:0>

0000

B05C

AD1FLTR2

31:16

AFEN

—

OVRSAM<2:0>

AFGIEN

AFRDY

—

CHNLID<5:0>

0000

15:0

FLTRDATA<15:0>

0000

BC60

AD1FLTR3

31:16

AFEN

—

OVRSAM<2:0>

AFGIEN

AFRDY

—

CHNLID<5:0>

0000

15:0

FLTRDATA<15:0>

0000

BO64

AD1FLTR4

31:16

AFEN

—

OVRSAM<2:0>

AFGIEN

AFRDY

—

CHNLID<5:0>

0000

15:0

FLTRDATA<15:0>

0000

BD68

AD1FLTR5

31:16

AFEN

—

OVRSAM<2:0>

AFGIEN

AFRDY

—

CHNLID<5:0>

0000

15:0

FLTRDATA<15:0>

0000

BG6C

AD1FLTR6

31:16

AFEN

—

OVRSAM<2:0>

AFGIEN

AFRDY

—

CHNLID<5:0>

0000

15:0

FLTRDATA<15:0>

0000

BT070

AD1TRG1

31:16

—

TRGSRC3<4:0>

—

TRGSRC2<4:0>

0000

15:0

—

TRGSRC1<4:0>

—

TRGSRC0<4:0>

0000

B074

AD1TRG2

31:16

—

TRGSRC7<4:0>

—

TRGSRC6<4:0>

0000

15:0

—

TRGSRC5<4:0>

—

TRGSRC4<4:0>

0000

B078

AD1TRG3

31:16

—

TRGSRC11<4:0>

—

TRGSRC10<4:0>

0000

15:0

—

TRGSRC9<4:0>

—

TRGSRC8<4:0>

0000

B090

AD1CMPCON1

31:16

—

0000

15:0

—

AINID<4:0>

ENDCMP

DCMPGIEN

DCMPED

IEBTWN

IEHIHI

IEHILO

IELOHI

IELOLO

0000

B094

AD1CMPCON2

31:16

—

0000

15:0

—

AINID<4:0>

ENDCMP

DCMPGIEN

DCMPED

IEBTWN

IEHIHI

IEHILO

IELOHI

B098

AD1CMPCON3

31:16

—

0000

15:0

—

AINID<4:0>

ENDCMP

DCMPGIEN

DCMPED

IEBTWN

IEHIHI

IEHILO

IELOHI, IIELOLO

B09C

AD1CMPCON4

31:16

—

0000

15:0

—

AINID<4:0>

ENDCMP

DCMPGIEN

DCMPED

IEBTWN

IEHIHI

IEHILO

IELOHI IIELOLO

B0A0

AD1CMPCON5

31:16

—

0000

15:0

—

AINID<4:0>

ENDCMP

DCMPGIEN

DCMPED

IEBTWN

IEHIHI

IEHILO

IELOHI IIELOLO

B0A4

AD1CMPCON6

31:16

—

0000

15:0

—

AINID<4:0>

ENDCMP

DCMPGIEN

DCMPED

IEBTWN

IEHIHI

IEHILO

IELOHI . IIELOLO

Virtual Address(BFD_1)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

B0B8

AD1DATA0