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PIC32MZ2048ECH144 - Electronic component Microchip - Free user manual and instructions

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USER MANUAL PIC32MZ2048ECH144 Microchip

32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog

Operating Conditions

- 2.3V to 3.6V, -40°C to +85°C, DC to 200 MHz

Core: 200 MHz (up to 330 DMIPS) microAptiv™

• 16 KB I-Cache, 4 KB D-Cache
- MMU for optimum embedded OS execution
- microMIPS™ mode for up to 35% smaller code size
- DSP-enhanced core:

- Four 64-bit accumulators

- Single-cycle MAC, saturating and fractional math

• Code-efficient (C and Assembly) architecture

Clock Management

Internal oscillator
Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timers (WDT) and Deadman Timer (DMT)
Fast wake-up and start-up

Power Management

Low-power modes (Sleep and Idle)
Integrated Power-on Reset and Brown-out Reset

Memory Interfaces

• 50 MHz External Bus Interface (EBI)
• 50 MHz Serial Quad Interface (SQI)

Audio and Graphics Interfaces

• Graphics interfaces: EBI or PMP
• Audio data communication: I ^2 S, LJ, and RJ
• Audio control interfaces: SPI and I ^2 C
• Audio master clock: Fractional clock frequencies with USB synchronization

High-Speed (HS) Communication Interfaces (with Dedicated DMA)

• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface

Security Features

Crypto Engine with a RNG for data encryption/decryption and authentication (AES, 3DES, SHA, MD5, and HMAC)
Advanced memory protection:

- Peripheral and memory region access control

Direct Memory Access (DMA)

• Eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)

Advanced Analog Features

• 10-bit ADC resolution and up to 48 analog inputs
• Flexible and independent ADC trigger sources
- Two comparators with 32 programmable voltage references
• Temperature sensor with ±2°C accuracy

Communication Interfaces

Two CAN modules (with dedicated DMA channels): - 2.0B Active with DeviceNet™ addressing support
Six UART modules (25 Mbps):
Supports LIN 1.2 and IrDA ^® protocols
Six 4-wire SPI modules
SQI configurable as an additional SPI module (50 MHz)
• F i 2Cmodules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
Peripheral Pin Select (PPS) to enable function remap

Timers/Output Compare/Input Capture

Nine 16-bit or up to four 32-bit timers/counters
• Nine Output Compare (OC) modules
• Nine Input Capture (IC) modules
PPS to enable function remap
• Real-Time Clock and Calendar (RTCC) module

Input/Output

5V-tolerant pins with up to 32 mA source/sink
Selectable open drain, pull-ups, and pull-downs
• External interrupts on all I/O pins

Qualification and Class B Support

• Class B Safety Library, IEC 60730
- Back-up internal oscillator

Debugger Development Support

• In-circuit and in-application programming
• 4 - w i r®EnInMancePJTAG interface
• Unlimited software and 12 complex breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan
• Non-intrusive hardware-based instruction trace

Software and Tools Support

• C/C++ compiler with native DSP/fractional support
• M P L® Harmony Integrated Software Framework
• TCP/IP, USB, Graphics, and mTouch™ middleware
- MFi, Android™, and Bluetooth ^ audio frameworks
- RTOS Kernels: Express Logic ThreadX, FreeRTOS™, OPENRTOS®, Micriμm® μC/OS™, and SEGGER embOS®

Packages

Type QFN TQFP VTLA LQFP
Pin Count	64	64	100		144	124	144
I/O Pins (up to)	53	53	78		120	98	120
Contact/Lead Pitch	0.50 mm	0.50 mm	0.40 mm	0.50 mm	0.40 mm	0.50 mm	0.50 mm
Dimensions	9x9x0.9 mm	10x10x1 mm	12x12x1 mm	14x14x1 mm	16x16x1 mm	9x9x0.9 mm	20x20x1.40 mm

TABLE 1: PIC32MZ EC FAMILY FEATURES

Device

Program Memory (KB)

Data Memory (KB)

Pins

Packages

Boot Flash Memory (KB)

Remappable Peripherals

Crypto

RNG

DMA Channels (Programmable/Dedicated)

ADC (Channels)

Analog Comparators

USB 2.0 HS OTG

I^2C

PMP

EBI

SQI

RTCC

Ethernet

I/O Pins

JTAG

Trace

Remappable Pins

Timers/Capture ^(1) Compare ^(1)

UART

SPIU ^2 S

External Interrupts ^(2)

CAN 2.0B

PIC32MZ1024ECG064

1024

512 64

TQFP, QFN

160 34

9/9/9

6 4 5

/ / 24

1 1 1 1 1

2 5 8 2 5 8

PIC32MZ1024ECH064

PIC32MZ1024ECM064

PIC32MZ2048ECG064

2048

PIC32MZ2048ECH064

PIC32MZ2048ECM064

PIC32MZ1024ECG100

1024

512

100

TQFP

160

9/9/9

/ / 40

1 1 1 1

2 5 8 2 5 8

PIC32MZ1024ECH100

PIC32MZ1024ECM100

PIC32MZ2048ECG100

2048

PIC32MZ2048ECH100

PIC32MZ2048ECM100

PIC32MZ1024ECG124

1024

512

124

VTLA

160

9/9/9

/ / 48

1 1 1 1

2 5 8 2 5 8

PIC32MZ1024ECH124

PIC32MZ1024ECM124

PIC32MZ2048ECG124

2048

PIC32MZ2048ECH124

PIC32MZ2048ECM124

PIC32MZ1024ECG144

1024

512

144

LQFP, TQFP

160 53

9/9/9

6 6 5

/ / 48

1 1 1 1

2 5 8 2 5 8

120

PIC32MZ1024ECH144

PIC32MZ1024ECM144

PIC32MZ2048ECG144

2048

PIC32MZ2048ECH144

PIC32MZ2048ECM144

Note 1: Eight out of nine timers are remappable.
2: Four out of five external interrupts are remappable.

Device Pin Tables

TABLE 2: PIN NAMES FOR 64-PIN DEVICES

64-PIN QFN(4) AND TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)064PIC32MZ1024EC(G/H/M)064PIC32MZ1024EC(E/F/K)064PIC32MZ2048EC(G/H/M)064
Pin # Full Pin Name Pin # Full Pin Name
1 AN 17/ETXEN/RPE5/PMD5/RE5	33	VBUS
2 AN 16/ETXD0/PMD6/RE6 34 V		USB3V3
3 AN 15/ETXD1/PMD7/RE7 35 V		SS
4 AN 14/C1IND/RPG6/SCK2/PMA5/RG6 36 D-
5 AN 13/C1INC/RPG7/SDA4/PMA4/RG7 37 D+
6 AN 12/C2IND/RPG8/SCL4/PMA3/RG8 38 RPF3/USBID/RF3
7 Vss	39	VDD
8 VDD	40	VSS
9 M C L R		41 RPF4/SDA5/PMA9/RF4
10 AN 11/C2INC/RPG9/PMA2/RG9	42 RP	F5/SCL5/PMA8/RF5
11 AN 45/C1INA/RPB5/RB5	43 AER	RXD0/ETXD2/RPD9/SDA1/PMCS2/PMA15/RD9
12 AN 4/C1INB/RB4	44 ECOL	RPD10/SCL1/SCK4/RD10
13 AN 3/C2INA/RPB3/RB3	45 AER	RXCLK/AEREFCLK/ECRS/RPD11/PMCS1/PMA14/RD11
14 AN 2/C2INB/RPB2/RB2	46 AER	RXD1/ETXD3/RPD0/RTCC/INT0/RD0
15 PGE C1/V REF-/CVREF-/AN1/RPB1/RB1	47 SCS	SCI/RPC13/RC13
16 PGED1/V REF+/CVREF+/AN0/RPB0/PMA6/RB0	48 SQ	SCO/RPC14/T1CK/RC14
17 PGE C2/AN46/RPB6/RB6	49 EMDIO/AEMDIO/RPD1/SCK1/RD1
18 PGED2/AN47/RPB7/RB7	50 ETXERR/AETXEN/RPD2/SDA3/RD2
19 AV DD	51	AERXERR/ETXCLK/RPD3/SCL3/RD3
20 AVss	52 SQ	CSO/RPD4/PMWR/RD4
21 AN 48/RPB8/PMA10/RB8	53	SQICS1/RPD5/PMRD/RD5
22 AN 49/RPB9/PMA7/RB9	54 V	DD
23 TMS/CV REFOUT/AN5/RPB10/PMA13/RB10	55	VSS
24 TDO/AN6/PMA12/RB11	56 ERXD3/AETXD1/RPF0/RF0
25 VSS	57	TRCLK/SQICLK/ERXD2/AETXD0/RPF1/RF1
26 VDD	58 TRD0/SQID0/ERXD1/PMD0/RE0
27 TCK/AN7/PMA11/RB12	59 V	SS
28 TDI/AN8/RB13	60 V	DD
29 AN 9/RPB14/SCK3/PMA1/RB14	61 TRD1/SQID1/ERXD0/PMD1/RE1
30 AN 10/EMDC/AEMDC/RPB15/OCFB/PMA0/RB15	62 TRD2/SQID2/ERXDV/ECRSDV/AECRSDV/PMD2/RE2
31 OSC1/CLKI/RC12	63 TRD3/SQID3/ERXCLK/EREFCLK/RPE3/PMD3/RE3
32 OSC2/CLKO/RC15	64 AN18/ERXERR/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to Vss externally.

TABLE 3: PIN NAMES FOR 100-PIN DEVICES

100-PIN TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)100PIC32MZ1024EC(G/H/M)100PIC32MZ1024EC(E/F/K)100PIC32MZ2048EC(G/H/M)100
Pin #	Full Pin Name Pin # Full Pin Name	F13
1 AN23/AERXERR/RG15 36 V				SS
2 EBIA5/AN34/PMA5/RA5 37 V				DD
3 EBID5/AN17/RPE5/PMD5/RE5 38 TCK/EBIA19/AN29/RA1
4 EBID6/AN16/PMD6/RE6 39 TDI/EBIA18/AN30/RPF13/SCK5/R
5 EBID7/AN15/PMD7/RE7 40 TDO/EBIA17/AN31/RPF12/RF12
6 EBIA6/AN22/RPC1/PMA6/RC1 41 EBIA11/AN7/ERXD0/AECRS/PMA11/RB12
7 EBIA12/AN21/RPC2/PMA12/RC2			42 AN8/ERXD1/AECOL/RB13
8 EBWE/AN20/RPC3/PMWR/RC3			43 EBIA1/AN9/ERXD2/AETXD3/RPB14/SCK3/PMA1/RB14
9 EBIOE/AN19/RPC4/PMRD/RC4			44 EBIA0/AN10/ERXD3/AETXD2/RPB15/OCFB/PMA0/RB15
10 AN14/C1IND/ECOL/RPG6/SCK2/RG6			45 V	SS
11 EBIA4/AN13/C1INC/ECRS/RPG7/SDA4/PMA4/RG7			46 V	DD
12 EBIA3/AN12/C2IND/ERXDV/ECRSDV/AERXDV/AECRSDV/RPG8/SCL4/PMA3/RG8			47 AN32/AETXD0/RPD14/RD14
13 Vss			48 AN33/AETXD1/RPD15/SCK6/RD15
14 VDD			49 OSC1/CLKI/RC12
15 MCLR			50 OSC2/CLKO/RC15
16 EBIA2/AN11/C2INC/ERXCLK/EREFCLK/AERXCLK/AEREFCLK/RPG9/PMA2/RG9			51	Vbus
17 TMS/EBIA16/AN24/RA0 52 V				USB3V3
18 AN25/AERXD0/RPE8/RE8			53 V	SS
19 AN26/AERXD1/RPE9/RE9			54 D-
20 AN45/C1INA/RPB5/RB5			55 D+
21 AN4/C1INB/RB4			56 RPF3/USBID/RF3
22 AN3/C2INA/RPB3/RB3			57 EBIRDY3/RPF2/SDA3/RF2
23 AN2/C2INB/RPB2/RB2			58 EBIRDY2/RPF8/SCL3/RF8
24 PGEC1/AN1/RPB1/RB1			59 EBICS0/SCL2/RA2
25 PGED1/AN0/RPB0/RB0			60 EBIRDY1/SDA2/RA3
26 PGEC2/AN46/RPB6/RB6			61 EBIA14/PMCS1/PMA14/RA4
27 PGED2/AN47/RPB7/RB7			62 V	DD
28 VREF-/CVREF-/AN27/AERXD2/RA9			63 V	SS
29 VREF+/CVREF+/AN28/AERXD3/RA10			64 EBIA9/RPF4/SDA5/PMA9/RF4
30 AV DD			65 EBIA8/RPF5/SCL5/PMA8/RF5
31 AV SS			66 AETXCLK/RPA14/SCL1/RA14
32 EBIA10/AN48/RPB8/PMA10/RB8			67 AETXEN/RPA15/SDA1/RA15
33 EBIA7/AN49/RPB9/PMA7/RB9			68 EBIA15/RPD9/PMCS2/PMA15/RD9
34 EBIA13/CV REFOUT/AN5/RPB10/PMA13/RB10			69 RPD10/SCK4/RD10
35 AN6/ERXERR/AETXERR/RB11			70 EMDC/AEMDC/RPD11/RD11

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.

TABLE 3: PIN NAMES FOR 100-PIN DEVICES (CONTINUED)

100-PIN TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)100PIC32MZ1024EC(G/H/M)100PIC32MZ1024EC(E/F/K)100PIC32MZ2048EC(G/H/M)100
Pin #	Full Pin Name	Pin #	Full Pin Name
71 EMDIO/AEMDIO/RPD0/RTCC/INT0/RD0 86 EBID10/ETXD0/RPF1		/PMD10/RF1
72 SOSCI/RPC13/RC13		87 EBID9/ETXERR/RPG1/PMD9/RG1
73 SOSCO/RPC14/T1CK/RC14		88 EBID8/RPG0/PMD8/RG0
74 VDD		89 TRCLK/SQICLK/RA6
75 Vss		90 TRD3/SQID3/RA7
76 RPD1/SCK1/RD1 91 EBID0/PMD0/RE0
77 EBID14/ETXEN/RPD2/PMD14/RD2 92 V			SS
78 EBID15/ETXCLK/RPD3/PMD15/RD3 93 V			DD
79 EBID12/ETXD2/RPD12/PMD12/RD12 94 EBID1/PMD1/RE1
80 EBID13/ETXD3/PMD13/RD13 95 TRD2/SQID2/RG14
81 SQICS0/RPD4/RD4 96 TRD1/SQID1/RG12
82 SQICS1/RPD5/RD5 97 TRD0/SQID0/RG13
83 VDD		98 EBID2/PMD2/RE2
84 Vss		99 EBID3/RPE3/PMD3/RE3
85 EBID11/ETXD1/RPF0/PMD11/RF0 100 EBID4/AN18/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.

TABLE 4: PIN NAMES FOR 124-PIN DEVICES

124-PIN VTLA (BOTTOM VIEW)PIC32MZ0512EC(E/F/K)124PIC32MZ1024EC(G/H/M)124PIC32MZ1024EC(E/F/K)124PIC32MZ2048EC(G/H/M)124		Pola
Package Pin #	Full Pin Name	Package Pin #	Full Pin Name
A1 No Connect		A35 V	BUS
A2 AN23/RG15 A36 V			USB3V3
A3 EBID5/AN17/RPE5/PMD5/RE5 A37 D-
A4 EBID7/AN15/PMD7/RE7 A38 RPF3/USBID/RF3
A5 AN35/ETXD0/RJ8		A39 EBIRDY2/RPF8/SCL3/RF8
A6 EBIA12/AN21/RPC2/PMA12/RC2		A40 ERXD3/RH9
A7 EBIOE /AN19/RPC4/PMRD/RC4 A41 EBICS0/SCL2/RA2
A8 EBIA4/AN13/C1INC/RPG7/SDA4/PMA4/RG7		A42 EBIA14/PMCS1/PMA14/RA4
A9 Vss		A43 V	SS
A10 MCLR A44 EBIA8/RPF5/SCL5/PMA8/RF5
A11 TM5/EBIA16/AN24/RA0		A45 RPA15/SDA1/RA15
A12 AN26/RPE9/RE9		A46 RPD10/SCK4/RD10
A13 AN4/C1INB/RB4		A47 ECRS/RH12
A14 AN3/C2INA/RPB3/RB3		A48 RPD0/RTCC/INT0/RD0
A15 V DD		A49 SOSCO/RPC14/T1CK/RC14
A16 AN2/C2INB/RPB2/RB2 A50 V			DD
A17 PGE C1/AN1/RPB1/RB1		A51 V	SS
A18 PGED1/AN0/RPB0/RB0		A52 RPD1/SCK1/RD1
A19 PGED2/AN47/RPB7/RB7		A53 EBID15/RPD3/PMD15/RD3
A20 VREF+/CV REF+/AN28/RA10		A54 EBID13/PMD13/RD13
A21 AV SS		A55 EMDIQ/RJ1
A22 AN39/ETXD3/RH1		A56 SQCSO/RPD4/RD4
A23 EBIA7/AN49/RPB9/PMA7/RB9		A57 ETXEN/RPD6/RD6
A24 AN6/RB11		A58 V	DD
A25 V DD		A59 EBID11/RPF0/PMD11/RF0
A26 TD/EBIA18/AN30/RPF13/SCK5/RF13		A60 EBID9/RPG1/PMD9/RG1
A27 EBIA11/AN7/PMA11/RB12		A61 TRCLK/SQICLK/RA6
A28 EBIA1/AN9/RPB14/SCK3/PMA1/RB14		A62 RJ4
A29 V SS		A63 V	SS
A30 AN40/ERXERR/RH4		A64 EBID1/PMD1/RE1
A31 AN42/ERXD2/RH6		A65 TRD1/SQID1/RG12
A32 AN33/RPD15/SCK6/RD15		A66 EBID2/SQID2/PMD2/RE2
A33 OSC2/CLKO/RC15		A67 EBID4/AN18/PMD4/RE4
A34 No Connect		A68 No Connect

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to Vss externally.

TABLE 4: PIN NAMES FOR 124-PIN DEVICES (CONTINUED)
124-PIN VTLA (BOTTOM VIEW)
PIC32MZ0512EC(E/F/K)124 PIC32MZ1024EC(G/H/M)124 PIC32MZ1024EC(E/F/K)124 PIC32MZ2048EC(G/H/M)124
Microchip PIC32MZ2048ECH144 - Device Pin Tables - 4

text_image

A17 B13 B29 A34 B1 B56 B41 A51 A1 A68 Parity Indicator

Package Pin #	Full Pin Name
B1 EBIA5/AN34/PMA5/RA5 B29 V
B2 EBID6/AN16/PMD6/RE6 B30 D+
B3 EBIA6/AN22/RPC1/PMA6/RC1
B4 AN36/ETXD1/RJ9
B5 EBIWE /AN20/RPC3/PMWR/RC3 B33 ECOL/RH10
B6 AN14/C1IND/RPG6/SCK2/RG6
B7 EBIA3/AN12/C2IND/RPG8/SCL4/PMA3/RG8
B8	VDD
B9 EBIA2/AN11/C2INC/RPG9/PMA2/RG9
B10 AN25/RPE8/RE8
B11 AN45/C1INA/RPB5/RB5
B12 AN37/ERXCLK/EREFCLK/RJ11
B13 V	SS
B14 PGE C2/AN46/RPB6/RB6
B15 V	REF-/CVREF-/AN27/RA9 B43 EBID12/RPD12/PMD12/RD1
B16 AV	DD
B17 AN38/ETXD2/RH0
B18 EBIA10/AN48/RPB8/PMA10/RB8
B19 EBIA13/CV REFOUT/AN5/RPB10/PMA13/RB10 B47 ETXCLK
B20 V	SS
B21 TCK/EBIA19/AN29/RA1 B49 EBID10/RPF1/PMD10/RF1
B22 TDO/EBIA17/AN31/RPF12/RF12
B23 AN8/RB13
B24 EBIA0/AN10/RPB15/OCFB/PMA0/RB15
B25 V	DD
B26 AN41/ERXD1/RH5 B54 TRD2/SQID2/RG14
B27 AN32/AETXD0/RPD14/RD14
B28 OSC1/CLKI/RC12

Package Pin #	Full Pin Name
	SS

B31 RPF2/SDA3/RF2
B32 ERXD0/RH8

B34 EBIRDY1/SDA2/RA3
B35 V	DD
B36 EBIA9/RPF4/SDA5/PMA9/RF4
B37 RPA14/SCL1/RA14
B38 EBIA15/RPD9/PMCS2/PMA15/RD9
B39 EMDC/RPD11/RD11
B40 ERXDV/ECRSDV/RH13
B41 SOSCI/RPC13/RC13
B42 EBID14/RPD2/PMD14/RD2

B44 ETXERR/RJ0
B45 EBIRDY3/RJ2
B46 SQCS1/RPD5/RD5
I/RD7
B48 V	SS

B50 EBID8/RPG0/PMD8/RG0
B51 TRD3/SQID3/RA7
B52 EBID0/PMD0/RE0
B53 V	DD

B55 TRD0/SQID0/RG13
B56 EBID3/RPE3/PMD3/RE3

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.
4: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

TABLE 5: PIN NAMES FOR 144-PIN DEVICES

144-PIN LQFP AND TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)144PIC32MZ1024EC(G/H/M)144PIC32MZ1024EC(E/F/K)144PIC32MZ2048EC(G/H/M)144
Pin Number	Full Pin Name		Pin Number	Full Pin Name
1 AN23/RG15 37 PGEC2/AN46/RPB6/RB6
2 EBIA5/AN34/PMA5/RA5 38 PGED2/AN47/RPB7/RB7
3 EBID5/AN17/RPE5/PMD5/RE5 39 V			REF-/CVREF-/AN27/RA9
4 EBID6/AN16/PMD6/RE6 40 V			REF+/CVREF+/AN28/RA10
5 EBID7/AN15/PMD7/RE7 41 AV			DD
6 EBIA6/AN22/RPC1/PMA6/RC1 42 AV			SS
7 AN35/ETXD0/RJ8 43 AN38/ETXD2/RH0
8 AN36/ETXD1/RJ9 44 AN39/ETXD3/RH1
9 EBIES0/RJ12 45 EBIRP/RH2			—
10 EBIBS1/RJ10 46 RH3
11 EBIA12/AN21/RPC2/PMA12/RC2		47 EBIA10/AN48/RPB8/PMA10/RB8
12 EBIWE /AN20/RPC3/PMWR/RC3		48 EBIA7/AN49/RPB9/PMA7/RB9
13 EBIOE/AN19/RPC4/PMRD/RC4		49 CV	REFOUT/AN5/RPB10/RB10
14 AN14/C1IND/RPG6/SCK2/RG6		50 AN6/RB11
15 AN13/C1INC/RPG7/SDA4/RG7		51 EBIA1/PMA1/RK1
16 AN12/C2IND/RPG8/SCL4/RG8		52 EBIA3/PMA3/RK2
17 Vss		53 EBIA17/RK3
18 VDD		54	Vss
19 EBIA16/RK0		55 V	DD
20 MCLR		56 TCK/AN29/RA1
21 EBIA2/AN11/C2INC/RPG9/PMA2/RG9		57 TDI/AN30/RPF13/SCK5/RF13
22 TM$/AN24/RA0		58 TDO/AN31/RPF12/RF12
23 AN25/RPE8/RE8		59 AN7/RB12
24 AN26/RPE9/RE9		60 AN8/RB13
25 AN45/C1INA/RPB5/RB5		61 AN9/RPB14/SCK3/RB14
26 AN4/C1INB/RB4		62 AN10/RPB15/OCFB/RB15
27 AN37/ERXCLK/EREFCLK/RJ11		63 V	SS
28 EBIA13/PMA13/RJ13		64 V	DD
29 EBIA11/PMA11/RJ14		65 AN40/ERXERR/RH4
30 EBIA0/PMA0/RJ15		66 AN41/ERXD1/RH5
31 AN3/C2INA/RPB3/RB3		67 AN42/ERXD2/RH6
32 Vss		68 EBIA4/PMA4/RH7
33 VDD		69 AN32/RPD14/RD14
34 AN2/C2INB/RPB2/RB2		70 AN33/RPD15/SCK6/RD15
35 PGEC1/AN1/RPB1/RB1		71 OSC1/CLKI/RC12
36 PGED1/AN0/RPB0/RB0		72 OSC2/CLKO/RC15

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.
2: Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 "I/O Ports" for more information.
3: Shaded pins are 5V tolerant.

TABLE 5: PIN NAMES FOR 144-PIN DEVICES (CONTINUED)

144-PIN LQFP AND TQFP (TOP VIEW)PIC32MZ0512EC(E/F/K)144PIC32MZ1024EC(G/H/M)144PIC32MZ1024EC(E/F/K)144PIC32MZ2048EC(G/H/M)144
Pin Number	Full Pin Name	Pin Number Full Pin Name
73	VBUS	109 RPD1/SCK1/RD1
74	VUSB3V3	110 EBID14/RPD2/PMD14/RD2
75	Vss	111 EBID15/RPD3/PMD15/RD3
76 D-		112 EBID12/RPD12/PMD12/RD12
77 D+	13 EBID13/PMD13/RD13
78 RPF3/USBID/RF3		114 ETXERR/RJ0
79 SDA3/RPF2/RF2 115 EMDIO/RJ1
80 SCL3/RPF8/RF8 116 EBIRDY3/RJ2
81 ERXD0/RH8 117 EBIA22/RJ3
82 ERXD3/RH9 118 SQICS0/RPD4/RD4
83 ECOL/RH10 119 SQICS1/RPD5/RD5
84 EBIRDY2/RH11 120 ETXEN/RPD6/RD6
85 SCL2/RA2		121 ETXCLK/RPD7/RD7
86 EBIRDY1/SDA2/RA3		122 V DD
87 EBIA14/PMCS1/PMA14/RA4		123 V SS
88	VDD	124 EBID11/RPF0/PMD11/RF0
89	VSS	125 EBID10/RPF1/PMD10/RF1
90 EBIA9/RPF4/SDA5/PMA9/RF4		126 EBIA21/RK7
91 EBIA8/RPF5/SCL5/PMA8/RF5		127 EBID9/RPG1/PMD9/RG1
92 EBIA18/RK4		128 EBID8/RPG0/PMD8/RG0
93 EBIA19/RK5		129 TRCLK/SQICLK/RA6
94 EBIA20/RK6		130 TRD3/SQID3/RA7
95 RPA14/SCL1/RA14		131 EBICS0/RJ4
96 RPA15/SDA1/RA15		132 EBICS1/RJ5
97	EBIA15/RPD9/PMCS2/PMA15/RD9	133 EBICS2/RJ6
98 RPD10/SCK4/RD10		134 EBICS3/RJ7
99 EMDC/RPD11/RD11		135 EBID0/PMD0/RE0
100 ECRS/RH12		136 V SS
101 ERXDV/ECRSDV/RH13		137 V DD
102 RH14		138 EBID1/PMD1/RE1
103 EBIA23/RH15		139 TRD2/SQID2/RG14
104 RPDO/RTCC/INT0/RD0		140 TRD1/SQID1/RG12
105 SOSCI/RPC13/RC13		141 TRD0/SQID0/RG13
106 SOSCO/RPC14/T1CK/RC14		142 EBID2/PMD2/RE2
107 V DD		143 EBID3/RPE3/PMD3/RE3
108 V SS		144 EBID4/AN18/PMD4/RE4

Note 1: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.3 "Peripheral Pin Select (PPS)" for restrictions.

2: Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 "I/O Ports" for more information.

3: Shaded pins are 5V tolerant.

NOTES:

1.0 Device Overview 15

2.0 Guidelines for Getting Started with 32-bit Microcontrollers 37

3.0 CPU 47

4.0 Memory Organization....59

5.0 Flash Program Memory....97

6.0 Resets....107

7.0 CPU Exceptions and Interrupt Controller 113

8.0 Oscillator Configuration....149

9.0 Prefetch Module 161

10.0 Direct Memory Access (DMA) Controller 165

11.0 Hi-Speed USB with On-The-Go (OTG) 189

12.0 I/O Ports 237

13.0 Timer1 273

14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9 277

15.0 Deadman Timer (DMT) 283

16.0 Watchdog Timer (WDT) 291

17.0 Input Capture....295

18.0 Output Compare 299

19.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I^2S) 305

20.0 Serial Quad Interface (SQI) 315

21.0 Inter-Integrated Circuit (I ^2 C) 339

22.0 Universal Asynchronous Receiver Transmitter (UART) 347

23.0 Parallel Master Port (PMP) 355

24.0 External Bus Interface (EBI) 365

25.0 Real-Time Clock and Calendar (RTCC) 373

26.0 Crypto Engine 383

27.0 Random Number Generator (RNG) 403

28.0 Pipelined Analog-to-Digital Converter (ADC) 409

29.0 Controller Area Network (CAN) 439

30.0 Ethernet Controller 477

31.0 Comparator 521

32.0 Comparator Voltage Reference (CV REF) 525

33.0 Power-Saving Features 529

34.0 Special Features 535

35.0 Instruction Set 559

36.0 Development Support....561

37.0 Electrical Characteristics....565

38.0 AC and DC Characteristics Graphs 613

39.0 Packaging Information....615

The Microchip Web Site 663

Customer Change Notification Service 663

Customer Support 663

Product Identification System 664

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Errata

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Customer Notification System

Referenced Sources

This device data sheet is based on the following individual sections of the "PIC32 Family Reference Manual". These documents should be considered as the general reference for the operation of a particular module or device feature.

Note: To access the following documents, refer to the Documentation > Reference Manuals section of the Microchip PIC32 website: http://www.microchip.com/pic32.

• Section 1. "Introduction" (DS60001127)
• Section 7. "Resets" (DS60001118)
• Section 8. "Interrupt Controller" (DS60001108)
• Section 9. "Watchdog, Deadman, and Power-up Timers" (DS60001114)
• Section 10. "Power-Saving Features" (DS60001130)
• Section 12. "I/O Ports" (DS60001120)
• Section 13. "Parallel Master Port (PMP)" (DS60001128)
• Section 14. "Timers" (DS60001105)
• Section 15. "Input Capture" (DS60001122)
• Section 16. "Output Compare" (DS60001111)
• Section 18. "12-bit Pipelined Analog-to-Digital Converter (ADC)" (DS60001194)
• Section 19. "Comparator" (DS60001110)
- Section 20. "Comparator Voltage Reference (CV REF)" (DS60001109)
• Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS60001107)
• Section 23. "Serial Peripheral Interface (SPI)" (DS60001106)
- Section 24. "Inter-Integrated Circuit (I ^2 C)" (DS60001116)
• Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
• Section 31. "Direct Memory Access (DMA) Controller" (DS60001117)
• Section 32. "Configuration" (DS60001124)
• Section 33. "Programming and Diagnostics" (DS60001129)
• Section 34. "Controller Area Network (CAN)" (DS60001154)
• Section 35. "Ethernet Controller" (DS60001155)
• Section 41. "Prefetch Module for Devices with L1 CPU Cache" (DS60001183)
• Section 42. "Oscillators with Enhanced PLL" (DS60001250)
• Section 46. "Serial Quad Interface (SQL)" (DS60001244)
• Section 47. "External Bus Interface (EBI)" (DS60001245)
• Section 48. "Memory Organization and Permissions" (DS60001214)
• Section 49. "Crypto Engine (CE) and Random Number Generator (RNG)" (DS60001246)
- Section 50. "CPU for Devices with MIPS32® microAptiv™ and M-Class Cores" (DS60001192)
• Section 51. "Hi-Speed USB with On-The-Go (OTG)" (DS60001326)
• Section 52. "Flash Program Memory with Support for Live Update" (DS60001193)

NOTES:

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the documents provided in the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

This data sheet contains device-specific information for PIC32MZ Embedded Connectivity (EC) devices.

Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MZ EC family of devices.

Table 1-21 through Table 1-22 list the pinout I/O descriptions for the pins shown in the device pin tables (see Table 2 through Table 5).

FIGURE 1-1: PIC32MZ EC FAMILY BLOCK DIAGRAM
Microchip PIC32MZ2048ECH144 - DEVICE OVERVIEW - 1

flowchart

graph TD
    subgraph System Bus
        A["Peripheral Bus 1"] --> B["Flash Controller"]
        C["Peripheral Bus 2"] --> D["Data Ram Bank 1"]
        E["Peripheral Bus 3"] --> F["Data Ram Bank 2"]
        G["Peripheral Bus 4"] --> H["Peripheral Bus 5"]
        I["Peripheral Bus 5"] --> J["Peripheral Bus 6"]
        K["Peripheral Bus 6"] --> L["Peripheral Bus 7"]
        M["Peripheral Bus 7"] --> N["Peripheral Bus 8"]
        O["Peripheral Bus 8"] --> P["Peripheral Bus 9"]
        Q["Peripheral Bus 9"] --> R["Peripheral Bus 10"]
        S["Peripheral Bus 10"] --> T["Peripheral Bus 11"]
        U["Peripheral Bus 11"] --> V["Peripheral Bus 12"]
        W["Peripheral Bus 12"] --> X["Peripheral Bus 13"]
        Y["Peripheral Bus 13"] --> Z["Peripheral Bus 14"]
        AA["Peripheral Bus 14"] --> AB["PFM Flash Wrapper and ECC"]
        AC["Peripheral Bus 14"] --> AD["140-bit Wide Dual Panel Flash Memory"]
        AE["Peripheral Bus 14"] --> AF["CVREF"]
        AG["Peripheral Bus 14"] --> AH["CPG"]
        AI["Peripheral Bus 14"] --> AJ["PPS"]
        AK["Peripheral Bus 14"] --> AL["ICD"]
        AM["Peripheral Bus 14"] --> AN["WDT"]
        AO["Peripheral Bus 14"] --> AP["DMT"]
        AQ["Peripheral Bus 14"] --> AR["RTCC"]
    end

    subgraph System Bus
        AS["EVIC"] --> AT["DMAC"]
        AU["MIPS32® microAptiv™ Core"] --> AV["I-Cache"]
        AW["D-Cache"] --> AX["System Bus I/F"]
        AY["EJTAG"] --> AZ["INT"]
        BA["MIPS32® microAptiv™ Core"] --> BB["I-Cache"]
        BC["D-Cache"] --> BD["System Bus I/F"]
        AE --> BE["T5"]
        AF --> BF["T5"]
        AG --> BG["T5"]
        AH --> BH["T5"]
        AI --> BI["T7"]
        AJ --> BJ["T7"]
        AK --> BK["T7"]
        AL --> BL["T7"]
        AM --> BM["T7"]
        AN --> BN["T7"]
        AO --> BO["T7"]
        AP --> BP["T7"]
        AQ --> BZ["T7"]
        BB --> CA["T7"]
        BC --> CB["T7"]
        AD --> CC["T7"]
        AE --> DD["T7"]
        AF --> DE["T7"]
        AG --> DF["T7"]
        AH --> DG["T7"]
        AI --> DH["T7"]
        AJ --> DI["T7"]
        AK --> DJ["T7"]
        AL --> DK["T7"]
        AM --> DL["T7"]
        AN --> DV["T7"]
        AO --> DW["T7"]
        AP --> DX["T7"]
        AH --> DB["T7"]
        AI --> DC["T7"]
        AJ --> DDY["T7"]
        AK --> DDZ["T7"]
        AL --> DDY
        AM --> DDZ
        AN --> DDZ
        AO --> DDZ
        AP --> DDZ
        AH --> DDZ
        AI --> DDZ
        AJ --> DDZ
        AK --> DDZ
        AL --> DDZ
        AM --> DDZ
    end

    subgraph System Bus
        X["T13"] --> Y["T12"]
        Z["T12"] --> AA["T11"]
        AB["T11"] --> AC["T10"]
        AD["T10"] --> AE["T9"]
    end

    subgraph System Bus
        AF["T13"] --> AG["T12"]
        AH["T12"] --> AI["T11"]
        AA["T11"] --> AB["T9"]
    end

    subgraph System Bus
        AC["T13"] --> AD
        AE["T9"] --> AF
    end

    subgraph System Bus
        AF["T13"] --> AG
        AH["T9"] --> AI
    end

    subgraph System Bus
        AD["T13"] --> AE["T9"]
    end

    subgraph System Bus
        AF["T13"] --> AH
    end

    subgraph System Bus
        AH["T9"] --> AI
    end

    subgraph System Bus
        AD["T13"] --> AE["T9"]
    end

    subgraph System Bus
        AH["T9"] --> AI
    end

    subgraph System Bus
        AF["T13"] --> AH
    end

    subgraph System Bus
        AH["T9"] --> AI
    end

    subgraph System Bus
        AD["T13"] --> AE["T9"]
    end

    subgraph System Bus
        AH["T9"] --> AI
    end

    subgraph System Bus
        AF["T13"] --> AH
    end

    subgraph System Bus
    AH["T9"] --> AI
    end

    subgraph System Bus
    AF["T13"] --> AH
    end

    subgraph System Bus
    AH["T9"] --> AI
    end

    subgraph System Bus
    AF["T13"] --> AH
    end

    subgraph System Bus
    AH["T9"] --> AI
    end

    subgraph System Bus
    AF["T13"] --> AH
    end

    subgraph System Bus
    AH["T9"] --> AI
    end

    style System Bus fill:#f9f,stroke:#333,stroke-width:2px

Note: Not all features are available on all devices. Refer to TABLE 1: "PIC32MZ EC Family Features" for the list of features by device.

TABLE 1-1: ADC1 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AN0 16 25 A	18 36 I Analog	Analog	Input Channels
AN1 15 24 A	17 35 I Analog
AN2 14 23 A	16 34 I Analog
AN3 13 22 A	14 31 I Analog
AN4 12 21 A	13 26 I Analog
AN5 23 34 B	19 49 I Analog
AN6 24 35 A	24 50 I Analog
AN7 27 41 A	27 59 I Analog
AN8 28 42 B	23 60 I Analog
AN9 29 43 A	28 61 I Analog
AN10 30 44 B	24 62 I Analog
AN11	10 16	B9 21 I Analog
AN12	6	12	B7 16 I Analog
AN13	5	11	A8 15 I Analog
AN14	4	10	B6 14 I Analog
AN15	3	5	A4	5	I	Analog
AN16	2	4	B2	4	I	Analog
AN17	1	3	A3	3	I	Analog
AN18 64	100 A67 144		I Analog
AN19	—	9	A7 13 I Analog
AN20	—	8	B5 12 I Analog
AN21	—	7	A6	11	I	Analog
AN22	—	6	B3	6	I	Analog
AN23	—	1	A2	1	I	Analog
AN24	—	17 A11	22 I Analog
AN25	—	18 B10	23 I Analog
AN26	—	19 A12	24 I Analog
AN27	—	28 B15	39 I Analog
AN28	—	29 A20	40 I Analog
AN29	—	38 B21	56 I Analog
AN30	—	39 A26	57 I Analog
AN31	—	40 B22	58 I Analog
AN32	—	47 B27	69 I Analog
AN33	—	48 A32	70 I Analog
AN34	—	2	B1	2	I	Analog
AN35	—	—	A5	7	I	Analog

Legend: CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select

TABLE 1-1: ADC1 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AN36 — —	B4 8 I Analog						Analog Input Channels
AN37 — —	B12 27 I Analog
AN38 — —	B17 43 I Analog
AN39 — —	A22 44 I Analog
AN40 — —	A30 65 I Analog
AN41 — —	B26 66 I Analog
AN42 — —	A31 67 I Analog
AN45 11 20	B11 25 I Analog
AN46	17 26	B14	37 I Analog
AN47	18 27	A19	38 I Analog
AN48	21 32	B18	47 I Analog
AN49	22 33	A23	48 I Analog

TABLE 1-2: OSCILLATOR PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
CLKI 31 49 B28 71 I ST	CMOS External clock			source input.	Always associated with OSC1 pin function.
CLKO	32	50	A33	72	O	—	Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
OSC1 31 49 B28 71 I ST	CMOS Oscillator crystal input.				ST buffer when configured in RC mode; CMOS otherwise.
OSC2	32	50	A33	72	O	—	Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI	47	72	B41	105	I	ST/CMOS	32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO	48	73	A49	106	O	—	32.768 low-power oscillator crystal output.
REFCLKI1	PPS	PPS	PPS	PPS	I	—	Reference Clock Generator Inputs 1-4
REFCLKI3	PPS	PPS	PPS	PPS	I	—
REFCLKI4	PPS	PPS	PPS	PPS	I	—
REFCLKO1	PPS	PPS	PPS	PPS	O	—	Reference Clock Generator Outputs 1-4
REFCLKO3	PPS	PPS	PPS	PPS	O	—
REFCLKO4	PPS	PPS	PPS	PPS	O	—

TABLE 1-3: IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Input Capture
IC1	PPS	PPS	PPS	PPS	I	ST	Input Capture Inputs 1-9
IC2	PPS	PPS	PPS	PPS	I	ST
IC3	PPS	PPS	PPS	PPS	I	ST
IC4	PPS	PPS	PPS	PPS	I	ST
IC5	PPS	PPS	PPS	PPS	I	ST
IC6	PPS	PPS	PPS	PPS	I	ST
IC7	PPS	PPS	PPS	PPS	I	ST
IC8	PPS	PPS	PPS	PPS	I	ST
IC9	PPS	PPS	PPS	PPS	I	ST

TABLE 1-4: OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Output Compare
OC1 PPS PPS PPS PPS S O — Output Compare Outputs 1-9
OC2 PPS PPS PPS PPS S O —
OC3 PPS PPS PPS PPS S O —
OC4 PPS PPS PPS PPS S O —
OC5 PPS PPS PPS PPS S O —
OC6 PPS PPS PPS PPS S O —
OC7 PPS PPS PPS PPS S O —
OC8 PPS PPS PPS PPS S O —
OC9 PPS PPS PPS PPS S O —
OCFA PPS PPS PPS PPS I			ST Output Compare Fault A Input
OCFB	30	44	B24	62	I	ST	Output Compare Fault B Input

TABLE 1-5: EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
External Interrupts
INT0	46	71	A48	104	I	ST	External Interrupt 0
INT1	PPS	PPS	PPS	PPS	I	ST	External Interrupt 1
INT2	PPS	PPS	PPS	PPS	I	ST	External Interrupt 2
INT3	PPS	PPS	PPS	PPS	I	ST	External Interrupt 3
INT4	PPS	PPS	PPS	PPS	I	ST	External Interrupt 4

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PORTA
RA0 — 17 A	11 22 I/O ST	PORTA is a bidirectional I/O port
RA1 — 38 B	21 56 I/O ST
RA2 — 59 A	41 85 I/O ST
RA3 — 60 B	34 86 I/O ST
RA4 — 61 A	42 87 I/O ST
RA5 —	2	B1	2 I/O ST
RA6 — 89 A	61 129	I/O ST
RA7 — 90 B	51 130	I/O ST
RA9 — 28 B	15 39 I/O ST
RA10	— 29	A20 40 I/O ST
RA14	— 66	B37 95 I/O ST
RA15	— 67	A45 96 I/O ST
PORTB
RB0	16	25 A18	36 I/O ST	PORTB is a bidirectional I/O port
RB1	15	24 A17	35 I/O ST
RB2	14	23 A16	34 I/O ST
RB3	13	22 A14	31 I/O ST
RB4	12	21 A13	26 I/O ST
RB5 11 20 B	11 25	I/O ST
RB6	17	26 B14	37 I/O ST
RB7	18	27 A19	38 I/O ST
RB8	21	32 B18	47 I/O ST
RB9	22	33 A23	48 I/O ST
RB10	23	34 B19	49 I/O ST
RB11	24	35 A24	50 I/O ST
RB12	27	41 A27	59 I/O ST
RB13	28	42 B23	60 I/O ST
RB14	29	43 A28	61 I/O ST
RB15	30	44 B24	62 I/O ST
PORTC
RC1	—	6	B3	6	I/O	ST	PORTC is a bidirectional I/O port
RC2	—	7	A6	11	I/O	ST
RC3	—	8	B5 12	I/O ST
RC4	—	9	A7 13	I/O ST
RC12	31	49 B28	71 I/O ST
RC13	47	72	B41	105	I/O	ST
RC14	48	73	A49	106	I/O	ST
RC15	32	50 A33	72 I/O ST

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PORTD
RD0 46 71 A	48 104 I/O	ST PORTD is a bidirectional I/O port
RD1 49 76 A	52 109 I/O	ST
RD2 50 77 B	42 110 I/O	ST
RD3 51 78 A	53 111 I/O	ST
RD4 52 81 A	56 118 I/O	ST
RD5 53 82 B	46 119 I/O	ST
RD6 —	—	A57 120 I/O ST
RD7 —	—	B47 121 I/O ST
RD9 43 68	B38	97	I/O ST
RD10	44 69 A	46 98 I/O ST
RD11	45	70	B39	99	I/O	ST
RD12	—	79 B43	112 I/O ST
RD13	—	80 A54	113 I/O ST
RD14	—	47	B27	69	I/O	ST
RD15	—	48	A32	70	I/O	ST
PORTE
RE0 58 91 B	52 135 I/O	ST PORTE is a bidirectional I/O port
RE1 61 94 A	64 138 I/O	ST
RE2 62 98 A	66 142 I/O	ST
RE3 63 99 B	56 143 I/O	ST
RE4 64	100	A67 144 I/O ST
RE5	1	3	A3	3	I/O	ST
RE6	2	4	B2	4	I/O	ST
RE7	3	5	A4	5	I/O	ST
RE8	—	18	B10	23	I/O	ST
RE9	—	19	A12	24	I/O	ST
PORTF
RF0	56 85 A	59 124 I/O ST PORTF is a bidirectional I/O port
RF1	57 86 B	49 125 I/O ST
RF2	—	57	B31	79	I/O	ST
RF3	38	56	A38	78	I/O	ST
RF4	41	64	B36	90	I/O	ST
RF5	42	65	A44	91	I/O	ST
RF8	—	58	A39	80	I/O	ST
RF12	—	40	B22	58	I/O	ST
RF13	—	39	A26	57	I/O	ST

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PORTG
RG0 — 88 B	50 128 I/O	ST PORTG is a bidirectional I/O port
RG1 — 87 A	60 127 I/O	ST
RG6 4 10 B	14 I/O ST
RG7 5 11	A8 15	I/O ST
RG8 6 12 B	16 I/O ST
RG9	10	16 B9	21 I/O ST
RG12	— 96	A65 140 I/O	ST
RG13	— 97	B55 141 I/O	ST
RG14	— 95	B54 139 I/O	ST
RG15	— 1	A2 1	I/O ST
PORTH
RH0	—	—	B17	43	I/O	ST	PORTH is a bidirectional I/O port
RH1	—	—	A22	44	I/O	ST
RH2	—	—	—	45	I/O	ST
RH3	—	—	—	46	I/O	ST
RH4	—	—	A30	65	I/O	ST
RH5	—	—	B26	66	I/O	ST
RH6	—	—	A31	67	I/O	ST
RH7	—	—	—	68	I/O	ST
RH8	—	—	B32	81	I/O	ST
RH9	—	—	A40	82	I/O	ST
RH10	—	—	B33	83	I/O	ST
RH11	—	—	—	84	I/O	ST
RH12	—	—	A47 100	I/O ST
RH13	—	—	B40 101	I/O ST
RH14	—	—	—	102	I/O	ST
RH15	—	—	—	103	I/O	ST
PORTJ
RJ0	—	—	B44	114	I/O	ST	PORTJ is a bidirectional I/O port
RJ1	—	—	A55	115	I/O	ST
RJ2	—	—	B45	116	I/O	ST
RJ3	—	—	—	117	I/O	ST
RJ4	—	—	A62	131	I/O	ST
RJ5	—	—	—	132	I/O	ST
RJ6	—	—	—	133	I/O	ST
RJ7	—	—	—	134	I/O	ST
RJ8	—	—	A5 7 I/O ST
RJ9	—	—	B4 8 I/O ST
RJ10	—	—	—	10	I/O	ST
RJ11	—	—	B12	27	I/O	ST
RJ12	—	—	—	9	I/O	ST
RJ13	—	—	—	28	I/O	ST
RJ14	—	—	—	29	I/O	ST
RJ15	—	—	—	30	I/O	ST
Legend: CMOS = CMOS-compatible input or output Analog = Analog input P = PowerST = Schmitt Trigger input with CMOS levels O = Output I = InputTTL = Transistor-transistor Logic input buffer PPS = Peripheral Pin SelectPORTK
RK0 — — —	19 I/O ST	PORTK is a bidirectional I/O port
RK1 — — —	51 I/O ST
RK2 — — —	52 I/O ST
RK3 — — —	53 I/O ST
RK4 — — —	92 I/O ST
RK5 — — —	93 I/O ST
RK6 — — —	94 I/O ST
RK7 — — —	126 I/O ST

TABLE 1-7: TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Timer1 through Timer9
T1CK 48 73	A49 106 I	$T Timer1	External Clock Input
T2CK	PPS	PPS	PPS	PPS	I	ST	Timer2 External Clock Input
T3CK	PPS	PPS	PPS	PPS	I	ST	Timer3 External Clock Input
T4CK	PPS	PPS	PPS	PPS	I	ST	Timer4 External Clock Input
T5CK	PPS	PPS	PPS	PPS	I	ST	Timer5 External Clock Input
T6CK	PPS	PPS	PPS	PPS	I	ST	Timer6 External Clock Input
T7CK	PPS	PPS	PPS	PPS	I	ST	Timer7 External Clock Input
T8CK	PPS	PPS	PPS	PPS	I	ST	Timer8 External Clock Input
T9CK	PPS	PPS	PPS	PPS	I	ST	Timer9 External Clock Input
Real-Time Clock and Calendar
RTCC	46	71	A48	104	O	—	Real-Time Clock Alarm/Seconds Output

TABLE 1-8: UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Universal Asynchronous Receiver Transmitter 1
U1RX PPS PPS PPS PPS PPS I ST UA	RT1 Rece	ve
U1TX PPS PPS PPS PPS PPS O	— U	ART1 Tran	smit
U1CTS	PPS PPS PPS PPS I ST UART1 Clear to Send
U1RTS	PPS PPS PPS PPS O	— U	ART1 Ready to Send
Universal Asynchronous Receiver Transmitter 2
U2RX PPS PPS PPS PPS I ST UA	RT2 Rece	ve
U2TX PPS PPS PPS PPS O	— U	ART2 Tran	smit
U2CTS	PPS PPS PPS PPS I ST UART2 Clear To Send
U2RTS	PPS	PPS	PPS	PPS	O	—	UART2 Ready To Send
Universal Asynchronous Receiver Transmitter 3
U3RX PPS PPS PPS PPS I ST UART3 Rece	ve
U3TX PPS PPS PPS PPS O	— U	ART3 Tran	smit
U3CTS	PPS PPS PPS PPS I ST UART3 Clear to Send
U3RTS	PPS PPS PPS PPS O	— U	ART3 Ready to Send
Universal Asynchronous Receiver Transmitter 4
U4RX PPS PPS PPS PPS I ST UART4 Rece	ve
U4TX PPS PPS PPS PPS O	— U	ART4 Tran	smit
U4CTS	PPS PPS PPS PPS I ST UART4 Clear to Send
U4RTS	PPS PPS PPS PPS O	— U	ART4 Ready to Send
Universal Asynchronous Receiver Transmitter 5
U5RX PPS PPS PPS PPS I ST UART5 Rece	ve
U5TX PPS PPS PPS PPS O	— U	ART5 Tran	smit
U5CTS	PPS PPS PPS PPS I ST UART5 Clear to Send
U5RTS	PPS PPS PPS PPS O	— U	ART5 Ready to Send
Universal Asynchronous Receiver Transmitter 6
U6RX PPS PPS PPS PPS I ST UART6 Rece	ve
U6TX PPS PPS PPS PPS O	— U	ART6 Tran	smit
U6CTS	PPS PPS PPS PPS I ST UART6 Clear to Send
U6RTS	PPS PPS PPS PPS O	— U	ART6 Ready to Send

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-9: SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Serial Peripheral Interface 1
SCK1 49 76	A52 109 I/O	ST SPI1 Synchronous	is Serial	Clock Input	Output
SDI1	PPS	PPS	PPS	PPS	I	ST	SPI1 Data In
SDO1	PPS	PPS	PPS	PPS	O	—	SPI1 Data Out
SS1	PPS	PPS	PPS	PPS	I/O	ST	SPI1 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 2
SCK2	4	10	B6	14	I/O	ST	SPI2 Synchronous Serial Clock Input/output
SDI2	PPS	PPS	PPS	PPS	I	ST	SPI2 Data In
SDO2	PPS	PPS	PPS	PPS	O	—	SPI2 Data Out
SS2	PPS	PPS	PPS	PPS	I/O	ST	SPI2 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 3
SCK3	29	43	A28	61	I/O	ST	SPI3 Synchronous Serial Clock Input/Output
SDI3	PPS	PPS	PPS	PPS	I	ST	SPI3 Data In
SDO3	PPS	PPS	PPS	PPS	O	—	SPI3 Data Out
SS3	PPS	PPS	PPS	PPS	I/O	ST	SPI3 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 4
SCK4	44	69	A46	98	I/O	ST	SPI4 Synchronous Serial Clock Input/Output
SDI4	PPS	PPS	PPS	PPS	I	ST	SPI4 Data In
SDO4	PPS	PPS	PPS	PPS	O	—	SPI4 Data Out
SS4	PPS	PPS	PPS	PPS	I/O	ST	SPI4 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 5
SCK5	—	39	A26	57	I/O	ST	SPI5 Synchronous Serial Clock Input/Output
SDI5	—	PPS	PPS	PPS	I	ST	SPI5 Data In
SDO5	—	PPS	PPS	PPS	O	—	SPI5 Data Out
SS5	—	PPS	PPS	PPS	I/O	ST	SPI5 Slave Synchronization Or Frame Pulse I/O
Serial Peripheral Interface 6
SCK6	—	48	A32	70	I/O	ST	SPI6 Synchronous Serial Clock Input/Output
SDI6	—	PPS	PPS	PPS	I	ST	SPI6 Data In
SDO6	—	PPS	PPS	PPS	O	—	SPI6 Data Out
SS6	—	PPS	PPS	PPS	I/O	ST	SPI6 Slave Synchronization Or Frame Pulse I/O

TABLE 1-10: I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP
Inter-Integrated Circuit 1
SCL1 44 66	B37 95 I/O	ST I2C1 Synchronous		Serial Clock Input/Output
SDA1 43 67	A45 96 I/O	ST I2C1 Synchronous		Serial Data Input/Output
Inter-Integrated Circuit 2
SCL2	—	59 A41	85 I/O ST	I2C2 Synchronous	Serial Clock Input/Output
SDA2	—	60 B34	86 I/O ST	I2C2 Synchronous	Serial Data Input/Output
Inter-Integrated Circuit 3
SCL3 51 58	A39 80 I/O	ST I2C3 Synchronous		Serial Clock Input/Output
SDA3 50 57	B31 79 I/O	ST I2C3 Synchronous		Serial Data Input/Output
Inter-Integrated Circuit 4
SCL4	6	12	B7	16	I/O	ST	I2C4 Synchronous Serial Clock Input/Output
SDA4	5	11	A8	15	I/O	ST	I2C4 Synchronous Serial Data Input/Output
Inter-Integrated Circuit 5
SCL5 42 65	A44 91 I/O	ST I2C5 Synchronous		Serial Clock Input/Output
SDA5 41 64	B36 90 I/O	ST I2C5 Synchronous		Serial Data Input/Output

Legend:

CMOS = CMOS-compatible input or outputST = Schmitt Trigger input with CMOS levelsTTL = Transistor-transistor Logic input buffer

Analog = Analog inputO = OutputPPS = Peripheral Pin Select

P = PowerI = Input

TABLE 1-11: COMPARATOR 1, COMPARATOR 2 AND CREF PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Comparator Voltage Reference
CVREF+	16	29	A20	40	I	Analog	Comparator Voltage Reference (High) Input
CVREF-	15	28	B15	39	I	Analog	Comparator Voltage Reference (Low) Input
CVREFOUT	23	34	B19	49	O	Analog	Comparator Voltage Reference Output
Comparator 1
C1INA	11	20	B11	25	I	Analog	Comparator 1 Positive Input
C1INB	12	21	A13	26	I	Analog	Comparator 1 Selectable Negative Input
C1INC	5	11	A8	15	I	Analog
C1IND	4	10	B6	14	I	Analog
C1OUT	PPS	PPS	PPS	PPS	O	—	Comparator 1 Output
Comparator 2
C2INA	13	22	A14	31	I	Analog	Comparator 2 Positive Input
C2INB	14	23	A16	34	I	Analog	Comparator 2 Selectable Negative Input
C2INC	10	16	B9	21	I	Analog
C2IND	6	12	B7	16	I	Analog
C2OUT	PPS	PPS	PPS	PPS	O	—	Comparator 2 Output

Legend:

CMOS = CMOS-compatible input or outputST = Schmitt Trigger input with CMOS levelsTTL = Transistor-transistor Logic input buffer

Analog = Analog inputO = OutputPPS = Peripheral Pin Select

P = PowerI = Input

TABLE 1-12: PMP PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
PMA0 30 44	B24 30 I/O	TTL/ST	Parallel Master	Port Address bit	0 Input (Buffered Slave modes) and Output (Master modes)
PMA1 29 43	A28 51 I/O	TTL/ST	Parallel Master	Port Address bit	1 Input (Buffered Slave modes) and Output (Master modes)
PMA2	10	16	B9	21	O	—	Parallel Master Port Address (Demultiplexed Master modes)
PMA3	6	12 B7	52	O —
PMA4	5	11 A8	68	O —
PMA5	4	2	B1	2	O	—
PMA6	16	6	B3	6	O	—
PMA7	22	33	A23	48	O	—
PMA8	42	65	A44	91	O	—
PMA9	41	64	B36	90	O	—
PMA10	21	32	B18	47	O	—
PMA11	27	41	A27	29	O	—
PMA12	24	7	A6	11	O	—
PMA13	23	34	B19	28	O	—
PMA14	45	61	A42	87	O	—
PMA15	43	68	B38	97	O	—
PMCS1	45	61	A42	87	O	—	Parallel Master Port Chip Select 1 Strobe
PMCS2	43	68	B38	97	O	—	Parallel Master Port Chip Select 2 Strobe
PMD0	58	91	B52	135	I/O	TTL/ST	Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes)
PMD1	61 94	A64	138	I/O TTL/ST
PMD2	62 98	A66	142	I/O TTL/ST
PMD3	63 99	B56	143	I/O TTL/ST
PMD4	64	100	A67	144	I/O	TTL/ST
PMD5	1	3	A3	3	I/O	TTL/ST
PMD6	2	4	B2	4	I/O	TTL/ST
PMD7	3	5	A4	5	I/O	TTL/ST
PMD8	—	88	B50	128	I/O	TTL/ST
PMD9	—	87	A60	127	I/O	TTL/ST
PMD10	—	86	B49	125	I/O	TTL/ST
PMD11	—	85	A59	124	I/O	TTL/ST
PMD12	—	79	B43	112	I/O	TTL/ST
PMD13	—	80	A54	113	I/O	TTL/ST
PMD14	—	77	B42	110	I/O	TTL/ST
PMD15	—	78	A53	111	I/O	TTL/ST
PMALL	30	44	B24	30	O	—	Parallel Master Port Address Latch Enable Low Byte (Multiplexed Master modes)
PMALH	29	43	A28	51	O	—	Parallel Master Port Address Latch Enable High Byte (Multiplexed Master modes)
PMRD	53	9	A7	13	O	—	Parallel Master Port Read Strobe
PMWR	52	8	B5	12	O	—	Parallel Master Port Write Strobe

Legend: CMOS = CMOS-compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-transistor Logic input buffer
Analog = Analog input
O = Output
P = Power
I = Input
PPS = Peripheral Pin Select

TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
EBIA0 — 44	B24 30 O	External	Bus Interface Address		Bus
EBIA1 — 43	A28	51 O	—
EBIA2 — 16	B9	21 O	—
EBIA3 — 12	B7	52 O	—
EBIA4 —	11 A8	68 O	—
EBIA5 —	2 B1	2 O	—
EBIA6 —	6 B3	6 O	—
EBIA7 — 33	A23	48 O	—
EBIA8 — 65	A44	91 O	—
EBIA9 — 64	B36	90 O	—
EBIA10	— 32	B18	47 C	—
EBIA11	— 41	A27	29 O	—
EBIA12	—	7	A6	11	O	—
EBIA13	— 34	B19	28 C	—
EBIA14	— 61	A42	87 C	—
EBIA15	— 68	B38	97 C	—
EBIA16	— 17	A11	19 O	—
EBIA17	— 40	B22	53 C	—
EBIA18	— 39	A26	92 C	—
EBIA19	— 38	B21	93 C	—
EBIA20	—	—	—	94	O	—
EBIA21	—	—	—	126	O	—
EBIA22	—	—	—	117	O	—
EBIA23	—	—	—	103	O	—
EBID0	—	91	B52	135	I/O	ST	External Bus Interface Data I/O Bus
EBID1	—	94	A64	138	I/O	ST
EBID2	—	98	A66	142	I/O	ST
EBID3	—	99	B56	143	I/O	ST
EBID4	—	100	A67	144	I/O	ST
EBID5	—	3	A3	3	I/O	ST
EBID6	—	4	B2	4	I/O	ST
EBID7	—	5	A4	5	I/O	ST
EBID8	—	88	B50	128	I/O	ST
EBID9	—	87	A60	127	I/O	ST
EBID10	—	86	B49	125	I/O	ST
EBID11	— 85	A59	124 I/O ST
EBID12	—	79	B43	112	I/O	ST
EBID13	—	80	A54	113	I/O	ST
EBID14	—	77	B42	110	I/O	ST
EBID15	—	78	A53	111	I/O	ST
EBIBS0	—	—	—	9	O	—	External Bus Interface Byte Select
EBIBS1	—	—	—	10	O	—	External Bus Interface Byte Select
EBICS0	— 59	A41	131 O	— External Bus Interface Chip			Select
EBICS1	—	—	—	132	O	—
EBICS2	—	—	—	133	O	—
EBICS3	—	—	—	134	O	—

TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
EBIOE	— 9 A7	13 O — External Bus Interface	Interface	Output Enable
EBIRDY1 —	60 B34 86	I ST External Bus Interface Ready Input
EBIRDY2 —	58 A39	84 I	ST
EBIRDY3 —	57 B45	116 I ST
EBIRP	— —	— 45 O — External Bus Interface	Flash Reset	Pin
EBIWE	— 8 B5	12 O — External Bus Interface	Write Enable

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-14: USB PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
VBUS	33 51	A35 73 I An	alog USB bus power		monitor
VUSB3V3	34 52	A36 74 P —	USB internal transceiver		supply. If the USB module is not used, this pin must be connected to Vss. When connected, the shared pin functions on USBID will not be available.
D+	37 55	B30 77	I/O	Analog USB D+
D-	36 54	A37 76	I/O	Analog USB D-
USBID	38	56	A38	78	I	ST	USB OTG ID detect

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-15: CAN1 AND CAN2 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
C1TX	PPS	PPS	PPS	PPS	O	—	CAN1 Bus Transmit Pin
C1RX	PPS	PPS	PPS	PPS	I	ST	CAN1 Bus Receive Pin
C2TX	PPS	PPS	PPS	PPS	O	—	CAN2 Bus Transmit Pin
C2RX	PPS	PPS	PPS	PPS	I	ST	CAN2 Bus Receive Pin

Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer

Analog = Analog input O = Output PPS = Peripheral Pin Select

P = Power I = Input

TABLE 1-16: ETHERNET MII I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
ERXD0 61 41	B32 81 I	ST Ethernet	Receive Data 0
ERXD1 58 42	B26 66 I	ST Ethernet	Receive Data 1
ERXD2 57 43	A31 67 I	ST Ethernet	Receive Data 2
ERXD3 56 44	A40 82 I	ST Ethernet	Receive Data 3
ERXERR 64	35 A30 65	I ST Ethernet	Receive Error Input
ERXDV 62 12	B40 101	I ST	Ethernet Receive Data Valid
ERXCLK	63 16	B12 27 I ST	Ethernet Receive Clock
ETXD0	2	86	A5	7	O	—	Ethernet Transmit Data 0
ETXD1	3	85	B4	8	O	—	Ethernet Transmit Data 1
ETXD2	43	79	B17	43	O	—	Ethernet Transmit Data 2
ETXD3	46	80	A22	44	O	—	Ethernet Transmit Data 3
ETXERR	50	87	B44	114	O	—	Ethernet Transmit Error
ETXEN	1	77	A57	120	O	—	Ethernet Transmit Enable
ETXCLK	51	78	B47	121	I	ST	Ethernet Transmit Clock
ECOL	44 10	B33 83 I ST	Ethernet Collision Detect
ECRS	45	11	A47	100	I	ST	Ethernet Carrier Sense
EMDC	30	70	B39	99	O	—	Ethernet Management Data Clock
EMDIO	49	71	A55	115	I/O	—	Ethernet Management Data

TABLE 1-17: ETHERNET RMII PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Ethernet MII Interface
ERXD0	61	41	B32	81	I	ST	Ethernet Receive Data 0
ERXD1	58	42	B26	66	I	ST	Ethernet Receive Data 1
ERXERR	64	35	A30	65	I	ST	Ethernet Receive Error Input
ETXD0	2	86	A5	7	O	—	Ethernet Transmit Data 0
ETXD1	3	85	B4	8	O	—	Ethernet Transmit Data 1
ETXEN	1	77	A57	120	O	—	Ethernet Transmit Enable
EMDC	30	70	B39	99	O	—	Ethernet Management Data Clock
EMDIO	49	71	A55	115	I/O	—	Ethernet Management Data
EREFCLK	63	16	B12	27	I	ST	Ethernet Reference Clock
ECRSDV	62	12	B40	101	I	ST	Ethernet Carrier Sense Data Valid

TABLE 1-18: ALTERNATE ETHERNET MII PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AERXD0 —	18 — — I ST	Alternate	Ethernet	Receive Data 0
AERXD1 —	19 — — I ST	Alternate	Ethernet	Receive Data 1
AERXD2 —	28 — — I ST	Alternate	Ethernet	Receive Data 2
AERXD3 —	29 — — I ST	Alternate	Ethernet	Receive Data 3
AERXERR —	1 — — I ST	Alternate	Ethernet	Receive Error Input
AERXDV	— 12 — — I ST	Alternate Ethernet	Receive Data Valid
AERXCLK	— 16 — — I ST	Alternate Ethernet	Receive Clock
AETXD0	—	47	—	—	O	—	Alternate Ethernet Transmit Data 0
AETXD1	—	48	—	—	O	—	Alternate Ethernet Transmit Data 1
AETXD2	—	44	—	—	O	—	Alternate Ethernet Transmit Data 2
AETXD3	—	43	—	—	O	—	Alternate Ethernet Transmit Data 3
AETXERR	—	35	—	—	O	—	Alternate Ethernet Transmit Error
AECOL	— 42 — — I ST	Alternate Ethernet	Collision Detect
AECRS — 41 — — I ST	Alternate Ethernet Carrier Sense
AETXCLK	— 66 — — I ST	Alternate Ethernet	Transmit Clock
AEMDC	—	70	—	—	O	—	Alternate Ethernet Management Data Clock
AEMDIO	—	71	—	—	I/O	—	Alternate Ethernet Management Data
AETXEN	—	67	—	—	O	—	Alternate Ethernet Transmit Enable

TABLE 1-19: ALTERNATE ETHERNET RMII PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
AERXD0	43	18	—	—	I	ST	Alternate Ethernet Receive Data 0
AERXD1	46	19	—	—	I	ST	Alternate Ethernet Receive Data 1
AERXERR	51	1	—	—	I	ST	Alternate Ethernet Receive Error Input
AETXD0	57	47	—	—	O	—	Alternate Ethernet Transmit Data 0
AETXD1	56	48	—	—	O	—	Alternate Ethernet Transmit Data 1
AEMDC	30	70	—	—	O	—	Alternate Ethernet Management Data Clock
AEMDIO	49	71	—	—	I/O	—	Alternate Ethernet Management Data
AETXEN	50	67	—	—	O	—	Alternate Ethernet Transmit Enable
AEREFCLK	45	16	—	—	I	ST	Alternate Ethernet Reference Clock
AECRSDV	62	12	—	—	I	ST	Alternate Ethernet Carrier Sense Data Valid

TABLE 1-20: SQI1 PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
SQICLK 57 89 A61 129	O — Serial	Quad Interface Clock
SQICS0	52 81 A56 118	O — Serial Quad			Interface	Chip Select 0
SQICS1	53 82 B46 119	O — Serial Quad			Interface	Chip Select 1
SQID0	58	97	B55	141	I/O	ST	Serial Quad Interface Data 0
SQID1	61	96	A65	140	I/O	ST	Serial Quad Interface Data 1
SQID2	62	95	B54	139	I/O	ST	Serial Quad Interface Data 2
SQID3	63	90	B51	130	I/O	ST	Serial Quad Interface Data 3

Legend:

CMOS = CMOS-compatible input or outputST = Schmitt Trigger input with CMOS levelsTTL = Transistor-transistor Logic input buffer

Analog = Analog inputO = OutputPPS = Peripheral Pin Select

P = PowerI = Input

TABLE 1-21: POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
Power and Ground
AVDD	19	30	B16	41	P	P	Positive supply for analog modules. This pin must be connected at all times.
AVss	20	31	A21	42	P	P	Ground reference for analog modules. This pin must be connected at all times
VDD	8, 26, 39, 54, 60	14, 37, 46, 62, 74, 83, 93	B8, A15, A25, B25, B35, A50, A58, B53	18, 33, 55, 64, 88, 107, 122, 137	P	—	Positive supply for peripheral logic and I/O pins. This pin must be connected at all times.
Vss	7, 25, 35, 40, 55, 59	13, 36, 45, 53, 63, 75, 84, 92	A9, B13, B20, B29, A29, A43, A51, B48, A63	17, 32, 54, 63, 75, 89, 108, 123, 136	P	—	Ground reference for logic, I/O pins, and USB. This pin must be connected at all times.
Voltage Reference
VREF+	16	29	A20	40	I	Analog	Analog Voltage Reference (High) Input
VREF-	15	28	B15	39	I	Analog	Analog Voltage Reference (Low) Input

Legend:	CMOS = CMOS-compatible input or output	Analog = Analog input	P = Power
	ST = Schmitt Trigger input with CMOS levels	O = Output	I = Input
	TTL = Transistor-transistor Logic input buffer	PPS = Peripheral Pin Select

TABLE 1-22: JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS

Pin Name	Pin Number				Pin Type	Buffer Type	Description
Pin Name	64-pin QFN/ TQFP	100-pin TQFP	124-pin VTLA	144-pin TQFP/ LQFP	Pin Type	Buffer Type	Description
JTAG
TCK 27 38 B	21 56 I ST	JTAG Test	Clock Input	Pin
TDI	28 39	A26 57 I ST	JTAG Test	Data Input	Pin
TDO	24	40	B22	58	O	—	JTAG Test Data Output Pin
TMS	23 17	A11	22 I ST JTAG	Test Mode	Select Pin
Trace
TRCLK	57	89	A61	129	O	—	Trace Clock
TRD0	58	97	B55	141	O	—	Trace Data bits 0-3
TRD1	61	96	A65	140	O	—
TRD2	62	95	B54	139	O	—
TRD3	63	90	B51	130	O	—
Programming/Debugging
PGED1	16	25	A18	36	I/O	ST	Data I/O pin for Programming/Debugging Communication Channel 1
PGEC1	15 24	A17 35 I ST	Clock input	pin for Programming/Debugging	I/O	ST	Data I/O pin for Programming/Debugging Communication Channel 2
PGED2	18	27	A19	38	I/O	ST	Data I/O pin for Programming/Debugging Communication Channel 2
PGEC2	17 26	B14 37 I ST	Clock input	pin for Programming/Debugging	I/P	ST	Master Clear (Reset) input. This pin is an active-low Reset to the device.
MCLR	9	15	A10	20	I/P	ST	Master Clear (Reset) input. This pin is an active-low Reset to the device.

NOTES:

2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS

2.1 Basic Connection Requirements

Note: The PIC32MZ EC family of devices require a unique VDD ramp-up time. Please refer to parameter DC17 in Table 37-4 of 37.0 "Electrical Characteristics" before finalizing regulator design.

Getting started with the PIC32MZ EC family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected:

A I DD and Vss pins (see 2.2 "Decoupling Capacitors")
A I DD and AVSS pins, even if the ADC module is not used (see 2.2 "Decoupling Capacitors")
MCLR pin (see 2.3 "Master Clear (MCLR) Pin")
PGECx/PGEDx pins, used for In-Circuit Serial Programming (ICSP™) and debugging purposes (see 2.4 "ICSP Pins")
OSC1 and OSC2 pins, when external oscillator source is used (see 2.7 "External Oscillator Pins")

The following pin(s) may be required as well:

VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented.

Note: The AV DD and AVss pins must be connected, regardless of ADC use and the ADC voltage reference source.

2.2 Decoupling Capacitors

The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1.

Consider the following criteria when using decoupling capacitors:

Value and type of capacitor: A value of 0.1 F (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used.

- Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

- Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F . Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F .

- Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

Note: The PIC32MZ EC family of devices require a unique VDD ramp-up time. Please refer to parameter DC17 in Table 37-4 of 37.0 "Electrical Characteristics" before finalizing regulator design.

FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
Microchip PIC32MZ2048ECH144 - Decoupling Capacitors - 1

text_image

VDD R1 MCLR VSS VDD VDD VSS 0.1 μF Ceramic VSS VDD PIC32 VUSB3v(1) VSS VDD VSS 0.1 μF Ceramic 0.1 μF Ceramic VDD VSS AVDD AVSS VDD VSS 0.1 μF Ceramic Connect(2) 0.1 μF Ceramic 0.1 μF Ceramic L1(2)

Note 1: If the USB module is not used, this pin must not be connected to VDD.
2: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1 and the inductor capacity greater than 10 mA.

Where:

$$ f = \frac {F _ {C N V}}{2} \quad (\text { i . e . }, \mathrm{ADCconversionrate/2}) $$

$$ f = \frac {1}{(2 \pi \sqrt {L C})} $$

$$ L = \left(\frac {1}{(2 \pi f \sqrt {C})}\right) ^ {2} $$

2.2.1 BULK CAPACITORS

The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible.

2.3 Master Clear (MCLR) Pin

The MCLR pin provides for two specific device functions:

Device Reset
• Device programming and debugging

Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements.

For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations.

Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS ^(1,2,3)
Microchip PIC32MZ2048ECH144 - Master Clear (MCLR) Pin - 1

text_image

VDD R 10k 0.1 μF(2) C R1(1) 1 kΩ MCLR PIC32 5 4 2 VDD 3 Vss 6 NC PGECx(3) PGEDx(3)

Note 1: 470 ≤ R1 ≤ 1 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VH and VII specifications are met without interfering with the Debug/Programmer tools.
2: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR.
3: No pull-ups or bypass capacitors are allowed on active debug/program PGECx/PGEDx pins.

2.4 ICSP Pins

The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements.

Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™.

For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available from the Microchip web site.

"Using MPLAB ^ ICD 3" (poster) (DS50001765)
"MPLAB ^ ICD 3 Design Advisory" (DS50001764)
"MPLAB ^ REAL ICE ^TM In-Circuit Debugger User's Guide" (DS50001616)
"Using MPLAB ^ REAL ICE ^TM Emulator" (poster) (DS50001749)

2.5 JTAG

The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VL) requirements.

2.6 Trace

The trace pins can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. When used for trace, the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 Ohm series resistor between the trace pins and the trace connector.

2.7 External Oscillator Pins

Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details).

The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3.

FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT
Microchip PIC32MZ2048ECH144 - External Oscillator Pins - 1

text_image

Oscillator Secondary Guard Trace Guard Ring Main Oscillator

2.7.1 CRYSTAL OSCILLATOR DESIGN CONSIDERATION

The following example assumptions are used to calculate the Primary Oscillator loading capacitor values:

• CIN = PIC32_OSC2_Pin Capacitance = \~4-5 pF
• COUT = PIC32_OSC1_Pin Capacitance = \~4-5 pF
- C1 and C2 = XTAL manufacturing recommended loading capacitance
- Estimated PCB stray capacitance, (i.e., 12 mm length) = 2.5 pF

Crystals with a speed of 4 MHz to 12 MHz that meet the following requirements will meet the PIC32MZ EC oscillation requirements when configured, as depicted in Figure 8-1.

Manufacturer Drive Level (min) ≤ 10 μW (hard requirements, 1 μW preferred).
Manufacturer ESR ≤ 50Ω (hard requirement, lower is better).

2.7.1.1 Calculating XTAL Capacitive Loading:

PIC32 C IN = COUT = \~4 pF (PIC32 OSCI and OSCO package pin capacitance).
C1 MFG = C2MFG = Manufacturer Recommended Load Capacitance.
CLOAD = {{[CIN + C1MFG] [C2MFG + COUT]) / [CIN + C1MFG + C2MFG + COUT]} + estimated PCB stray capacitance (2.5 pF). (Simplified) CLOAD = (((CIN + C1 MFG) / 2) + 2.5 pF).

Actual C1, C2 Load value to use:

• C 2 ±OAD
• C 1 =LO(ADC-2 pF)

Note: These recommendations are atypical, and are only applicable to the PIC32MZ EC family.

2.7.1.2 Validated Crystals

Temperature Range: (-45°C to +110°C)
V_DD=2.4V to 3.6V, RP=1M , RK=10k
• ABLS-12.000 MHz-L4Q-T (12 MHz surface mount)

Note: These recommendations are atypical, and only applicable to the PIC32MZ EC family.

2.7.1.3 Additional Microchip References

• A N 5 8 8 "P1 Microcontroller Oscillator Design Guide"
- A N 8 2 6 "Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices"
• A N 8 4 9 "Basic P1O5mator Design"

2.8 Unused I/Os

Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state.

Alternatively, inputs can be reserved by connecting the pin to Vss through a 1k to 10k resistor and configuring the pin as an input.

2.9 Designing for High-Speed Peripherals

The PIC32MZ EC family devices have peripherals that operate at frequencies much higher than typical for an embedded environment. Table 2-1 lists the peripherals that produce high-speed signals on their external pins:

TABLE 2-1: PERIPHERALS THAT PRODUCE HS SIGNALS ON EXTERNAL PINS

Peripheral	High-Speed Signal Pins	Maximum Speed on Signal Pin
EBI	EBIAx, EBIDx	50 MHz
SQI1	SQICLK, , SQIDx	50 MHz
HS USB	D+, D-	480 MHz

Due to these high-speed signals, it is important to take into consideration several factors when designing a product that uses these peripherals, as well as the PCB on which these components will be placed. Adhering to these recommendations will help achieve the following goals:

Minimize the effects of electromagnetic interference to the proper operation of the product
Ensure signals arrive at their intended destination at the same time
Minimize crosstalk
Maintain signal integrity
Reduce system noise
Minimize ground bounce and power sag

2.9.1 SYSTEM DESIGN

2.9.1.1 Impedance Matching

When selecting parts to place on high-speed buses, particularly the SQI bus, if the impedance of the peripheral device does not match the impedance of the pins on the PIC32MZ EC device to which it is connected, signal reflections could result, thereby degrading the quality of the signal.

If it is not possible to select a product that matches impedance, place a series resistor at the load to create the matching impedance. See Figure 2-4 for an example.

FIGURE 2-4: SERIES RESISTOR
Microchip PIC32MZ2048ECH144 - Impedance Matching - 1

text_image

PIC32MZ 50Ω SQI Flash Device

2.9.1.2 PCB Layout Recommendations

The following list contains recommendations that will help ensure the PCB layout will promote the goals previously listed.

- Component Placement

Place bypass capacitors as close to their component power and ground pins as possible, and place them on the same side of the PCB
Devices on the same bus that have larger setup times should be placed closer to the PIC32MZ EC device

- Power and Ground

Multi-layer PCBs will allow separate power and ground planes
Each ground pin should be connected to the ground plane individually
Place bypass capacitor vias as close to the pad as possible (preferably inside the pad)
If power and ground planes are not used, maximize width for power and ground traces
Use low-ESR, surface-mount bypass capacitors

- Clocks and Oscillators

Place crystals as close as possible to the PIC32MZ EC device OSC/SOSC pins
Do not route high-speed signals near the clock or oscillator
Avoid via usage and branches in clock lines (SQICLK)
Place termination resistors at the end of clock lines

- Traces

Higher-priority signals should have the shortest traces
Match trace lengths for parallel buses (EBIAx, EBIDx, SQIDx)
Avoid long run lengths on parallel traces to reduce coupling
Make the clock traces as straight as possible
Use rounded turns rather than right-angle turns
Have traces on different layers intersect on right angles to minimize crosstalk
Maximize the distance between traces, preferably no less than three times the trace width
Power traces should be as short and as wide as possible
High-speed traces should be placed close to the ground plane

2.10 Considerations When Interfacing to Remotely Powered Circuits

2.10.1 NON-5V TOLERANT INPUT PINS

A quick review of the absolute maximum rating section in 37.0 "Electrical Characteristics" will indicate that the voltage on any non-5v tolerant pin may not exceed AVDD/VDD + 0.3V. Figure 2-5 shows an example of a remote circuit using an independent power source, which is powered while connected to a PIC32 non-5V tolerant circuit that is not powered.

FIGURE 2-5: PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE
Microchip PIC32MZ2048ECH144 - NON-5V TOLERANT INPUT PINS - 1

flowchart

graph TD
    A["Remote 0.3V ≤ VIH ≤ 3.6V"] --> B["AN2/RB0"]
    C["Remote GND"] --> B
    B --> D["AnSEL"]
    D --> E["I/O IN"]
    D --> F["I/O OUT"]
    D --> G["TRIS"]
    H["VDD"] --> I["On/Off"]
    I --> J["CPU LOGIC"]
    J --> K["VSS"]
    L["PIC32 POWER SUPPLY"] --> M["On/Off"]
    N["Note: When V DD power is OFF."] --> O["Current Flow"]
    O --> P["AND Gate"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style H fill:#ccf,stroke:#333
    style L fill:#cfc,stroke:#333

Without proper signal isolation, on non-5V tolerant pins, the remote signal can power the PIC32 device through the high side ESD protection diodes. Besides violating the absolute maximum rating specification when VDD of the PIC32 device is restored and ramping up or ramping down, it can also negatively affect the internal Power-on Reset (POR) and Brown-out Reset (BOR) circuits, which can lead to improper initialization of internal PIC32 logic circuits. In these cases, it is recommended to implement digital or analog signal isolation as depicted in Figure 2-6, as appropriate. This is indicative of all industry microcontrollers and not just Microchip products.

TABLE 2-2: EXAMPLES OF DIGITAL/ ANALOG ISOLATORS WITH OPTIONAL LEVEL TRANSLATION

Example Digital/Analog Signal Isolation Circuits	Inductive Coupling	Capacitive Coupling	Opto Coupling	Analog/Digital Switch
ADuM7241 / 40 ARZ (1 Mbps) X	— —	—
ADuM7241 / 40 CRZ (25 Mbps)	X —	— —
ISO721 — X — —
LTV-829S (2 Channel)	— —	X —
LTV-849S (4 Channel)	— —	X —
FSA266 / NC7WB66	— —	— X

FIGURE 2-6: DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS
Microchip PIC32MZ2048ECH144 - NON-5V TOLERANT INPUT PINS - 2

flowchart

graph TD
    subgraph Digital Isolator
        A["External VDD"] --> B["Inverter"]
        C["Remote_IN"] --> B
        B --> D["PIC32 VDD"]
        D --> E["VSS"]
    end

    subgraph Digital Isolator
        F["External VDD"] --> G["Inverter"]
        H["Remote_IN"] --> I["Inverter"]
        J["Remote_OUT"] --> K["Inverter"]
        L["OUT1"] --> M["Inverter"]
        N["PIC32 VDD"] --> O["VSS"]
    end

    subgraph Analog / Digital Isolator
        P["Analog_OUT2"] --> Q["ENB"]
        R["External_VDD1"] --> S["ENB"]
        T["Analog_IN1"] --> U["Analog Switch"]
        V["PIC32"] --> W["VSS"]
        X["Analog_IN2"] --> Y["Analog Switch"]
        Z["Analog Switch"] --> AA["S"]
    end

2.10.2 5V TOLERANT INPUT PINS

The internal high side diode on 5V tolerant pins are bussed to an internal floating node, rather than being connected to VDD, as shown in Figure 2-7. Voltages on these pins, if VDD < 2.3V, should not exceed roughly 3.2V relative to Vss of the PIC32 device. Voltage of 3.6V or higher will violate the absolute maximum specification, and will stress the oxide layer separating the high side floating node, which impacts device reliability. If a remotely powered "digital-only" signal can be guaranteed to always be ≤ 3.2V relative to Vss on the PIC32 device side, a 5V tolerant pin could be used without the need for a digital isolator. This is assuming there is not a ground loop issue, logic ground of the two circuits not at the same absolute level, and a remote logic low input is not less than Vss - 0.3V.

FIGURE 2-7: PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
Microchip PIC32MZ2048ECH144 - 5V TOLERANT INPUT PINS - 1

flowchart

graph TD
    A["Remote GND"] --> B["Remote VIH = 2.5V"]
    B --> C["RG10"]
    C --> D["Floating Bus Oxide BV = 3.6V if VDD < 2.3V"]
    D --> E["OXIDE"]
    E --> F["ANSEL"]
    F --> G["I/O IN"]
    F --> H["I/O OUT"]
    F --> I["TRIS"]
    G --> J["CPU LOGIC"]
    H --> J
    I --> J
    J --> K["VSS"]
    L["PIC32 POWER SUPPLY"] --> M["On/Off"]
    N["5V Tolerant Pin Architecture"] --> O["VDD"]
    O --> P["On/Off"]

2.10.2.1 EMI Suppression Considerations

The use of LDO regulators is preferred to reduce overall system noise and provide a cleaner power source. However, when utilizing switching Buck/Boost regulators as the local power source for PIC32MZ EF devices, as well as in electrically noisy environments, users should evaluate the use of T-Filters (i.e., L-C-L) on the power pins, as shown in Figure 2-8. In addition to a more stable power source, use of this type of T-Filter can greatly reduce susceptibility to EMI sources and events.

FIGURE 2-8:
Microchip PIC32MZ2048ECH144 - EMI Suppression Considerations - 1

text_image

Ferrite Chip SMD DCR = 0.15Ω (max) 600 ma ISAT 300Ω @ 100 MHz PN#: 1-1624117-3 VDD Ferrite Chips 0.01 μF 0.1 μF VDD VSS VSS VDD PIC32MZ VSS VDD 0.1 μF 0.1 μF VSS VDD 0.1 μF 0.1 μF VSS VDD 0.1 μF 0.1 μF AVDD AVSS VSS VDD 0.1 μF 0.1 μF 0.1 μF Ferrite Chips VDD 0.01 μF

2.11 Typical Application Connection

Examples

Examples of typical application connections are shown

in Figure 2-9 and Figure 2-10.

FIGURE 2-9: AUDIO PLAYBACK APPLICATION
Microchip PIC32MZ2048ECH144 - Examples - 1

flowchart

graph LR
    A["USB Host"] <--> B["USB"]
    B --> C["PMP"]
    C --> D["Display"]
    B --> E["PMD<7:0>"]
    E --> D
    B --> F["PMWR"]
    F --> D
    B --> G["I²S"]
    G --> H["Audio Codec"]
    H --> I["Stereo Headphones"]
    H --> J["Speaker"]
    B --> K["REFCLKO"]
    K --> H
    B --> L["SPI"]
    L --> M["MMC SD"]
    M --> N["SDI"]
    N --> H

FIGURE 2-10: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH PROJECTED CAPACITIVE TOUCH
Microchip PIC32MZ2048ECH144 - Examples - 2

flowchart

graph TD
    A["Microchip mTouch™ Library"] --> B["Microchip GFX Library"]
    B --> C["DMA"]
    B --> D["EBI"]
    D --> E["LED Display"]
    E --> F["LCD Display"]
    F --> G["Projected Capacitive Touch Overlay"]
    G --> H["External Frame Buffer"]
    H --> I["SRAM"]
    I --> J["AND"]
    J --> K["ADC"]
    K --> L["Microchip mTouch™ Library"]
    L --> M["Microchip GFX Library"]
    M --> N["Refresh"]
    N --> O["DMA"]
    O --> P["EBI"]
    P --> Q["LED Display"]
    Q --> R["LCD Display"]
    R --> S["Projected Capacitive Touch Overlay"]
    S --> T["External Frame Buffer"]
    T --> U["SRAM"]
    U --> V["LED Display"]
    V --> W["LCD Display"]
    W --> X["Projected Capacitive Touch Overlay"]
    X --> Y["External Frame Buffer"]
    Y --> Z["SRAM"]
    Z --> AA["LCD Display"]
    AA --> AB["LCD Display"]
    AB --> AC["Projected Capacitive Touch Overlay"]
    AC --> AD["External Frame Buffer"]
    AD --> AE["LCD Display"]
    AE --> AF["LCD Display"]
    AF --> AG["Projected Capacitive Touch Overlay"]
    AG --> AH["LCD Display"]
    AH --> AI["LCD Display"]
    AI --> AJ["LCD Display"]
    AJ --> AK["LCD Display"]
    AK --> AL["LCD Display"]
    AL --> AM["LCD Display"]
    AM --> AN["LCD Display"]
    AN --> AO["LCD Display"]
    AO --> AP["LCD Display"]
    AP --> AQ["LCD Display"]
    AQ --> AR["LCD Display"]
    AR --> AS["LCD Display"]
    AS --> AT["LCD Display"]
    AT --> AU["LCD Display"]
    AU --> AV["LCD Display"]
    AV --> AW["LCD Display"]
    AW --> AX["LCD Display"]
    AX --> AY["LCD Display"]

3.0 CPU

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 50. "CPU for Devices with MIPS32 ^ microAptiv ^TM and M-Class Cores" (DS60001192), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

MIPS32 ^® microAptiv ^TM Microprocessor Core resources are available at: www.imgtec.com.

The MIPS32 ^® microAptiv ^™ Microprocessor Core is the heart of the PIC32MZ EC family device processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations.

3.1 Features

PIC32MZ EC family processor core key features:

5-stage pipeline
• 32-bit address and data paths
• MIPS32 ^® Enhanced Architecture (Release 2):
Multiply-accumulate and multiply-subtract instructions
Targeted multiply instruction
Zero/One detect instructions
WAIT instruction
Conditional move instructions (MOVN, MOVZ)
Vectored interrupts
Programmable exception vector base
Atomic interrupt enable/disable
GPR shadow registers to minimize latency for interrupt handlers
Bit field manipulation instructions
Virtual memory support

- microMIPS™ compatible instruction set:

- Improves code size density over MIPS32, while maintaining MIPS32 performance.

- Supports all MIPS32 instructions (except branch- likely instructions)

- Fifteen additional 32-bit instructions and 39 16-bit instructions corresponding to commonly-used MIPS32 instructions

- Stack pointer implicit in instruction

- MIPS32 assembly and ABI compatible

MMU with Translation Lookaside Buffer (TLB) mechanism:
16 dual-entry fully associative Joint TLB
4-entry fully associative Instruction TLB
4-entry fully associative Data TLB
4 KB pages
Separate L1 data and instruction caches:
16 KB 4-way Instruction Cache (I-Cache)
4 KB 4-way Data Cache (D-Cache)
• Autonomous Multiply/Divide Unit (MDU):
Maximum issue rate of one 32x32 multiply per clock
Early-in iterative divide. Minimum 12 and maximum 38 clock latency (dividend (rs) sign extension-dependent)
Power Control:
Minimum frequency: 0 MHz
Low-Power mode (triggered by WAIT instruction)
Extensive use of local gated clocks
EJTAG Debug and Instruction Trace:
Support for single stepping
Virtual instruction and data address/value breakpoints
Hardware breakpoint supports both address match and address range triggering.
Eight instruction and four data complex breakpoints
iFlowtrace ^ version 2.0 support:
Real-time instruction program counter
Special events trace capability
Two performance counters with 34 user-selectable countable events
Disabled if the processor enters Debug mode
Four Watch registers:
Instruction, Data Read, Data Write options
Address match masking options
DSPASE Extension:
Native fractional format data type operations
Register Single Instruction Multiple Data (SIMD) operations (add, subtract, multiply, shift)
GPR-based shift
Bit manipulation
Compare-Pick
DSP Control Access
Indexed-Load
Branch
Multiplication of complex operands
Variable bit insertion and extraction
Virtual circular buffers
Arithmetic saturation and overflow handling
Zero-cycle overhead saturation and rounding operations

A block diagram of the PIC32MZ EC family processor core is shown in Figure 3-1.

FIGURE 3-1: PIC32MZ EC FAMILY MICROPROCESSOR CORE
BLOCK DIAGRAM
Microchip PIC32MZ2048ECH144 - Features - 1

flowchart

graph TD
    A["PBCLK7"] --> B["Decode (MIPS32®/microMIPSTM)"]
    B --> C["Execution Unit"]
    C --> D["ALU/Shift Atomic/LdSt DSP ASE"]
    D --> E["System Coprocessor"]
    E --> F["Debug/Profiling Break Points iFlowtrace® Fast Debug Channel Performance Counters Sampling Secure Debug"]
    F --> G["EJTAG"]
    G --> H["2-wire Debug"]
    H --> I["Power Management"]
    I --> J["D-Cache Controller"]
    J --> K["MMU (TLB)"]
    K --> L["I-Cache Controller"]
    L --> M["BIU"]
    M --> N["System Bus"]
    C --> O["GPR (8 sets)"]
    C --> P["Enhanced MDU (with DSP ASE)"]
    C --> Q["System Interface"]
    C --> R["Interrupt Interface"]
    R --> S["System Coprocessor"]
    S --> T["Debug/Profiling Break Points iFlowtrace® Fast Debug Channel Performance Counters Sampling Secure Debug"]
    T --> U["D-Cache Controller"]
    U --> V["I-Cache Controller"]
    V --> W["BIU"]
    W --> X["System Bus"]

3.2 Architecture Overview

The MIPS32 microAptiv Microprocessor core in PIC32MZ EC family devices contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core:

Execution unit
• General Purpose Register (GPR)
Multiply/Divide Unit (MDU)
• System control coprocessor (CP0)
• Memory Management Unit (MMU)
Instruction/Data cache controllers
• Power Management
Instructions and data caches
microMIPS support
• Enhanced JTAG (EJTAG) controller

3.2.1 EXECUTION UNIT

The processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. Seven additional register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.

The execution unit includes:

• 32-bit adder used for calculating the data address
- Address unit for calculating the next instruction address
- Logic for branch determination and branch target address calculation
- Load aligner
- Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results

Leading Zero/One detect unit for implementing the CLZ and CLO instructions
Arithmetic Logic Unit (ALU) for performing arithmetic and bitwise logical operations
Shifter and store aligner
DSP ALU and logic block for performing DSP instructions, such as arithmetic/shift/compare operations

3.2.2 MULTIPLY/DIVIDE UNIT (MDU)

The processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions.

The high-performance MDU consists of a 32x32 booth recoded multiplier, four pairs of result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown ('32' of 32x32) represents the rs operand. The second number ('32' of 32x32) represents the rt operand.

The MDU supports execution of one multiply or multiply-accumulate operation every clock cycle.

Divide operations are implemented with a simple 1-bit-per-clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation has completed.

Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the processor core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks.

TABLE 3-1: MIPS32 microAptiv MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES

Opcode	Operand Size (mul rt) (div rs)	Latency	Repeat Rate
MULT/MULTU, MADD/MADDU,MSUB/MSUBU (HI/LO destination)	16 bits	5	1
MULT/MULTU, MADD/MADDU,MSUB/MSUBU (HI/LO destination)	32 bits	5	1
MUL (GPR destination)	16 bits	5	1
MUL (GPR destination)	32 bits	5	1
DIV/DIVU	8 bits	12/14	12/14
	16 bits	20/22	20/22
	24 bits	28/30	28/30
	32 bits	36/38	36/38

The MIPS architecture defines that the result of a multiply or divide operation be placed in one of four pairs of HI and LO registers. Using the Move-From-HI (MFHI) and Move-From-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file.

In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased.

Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms.

The MDU also implements various shift instructions operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all of the data types required for this purpose and includes three extra HI/LO registers as defined by the ASE.

Table 3-2 lists the latencies and repeat rates for the DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of pipeline clocks.

TABLE 3-2: DSP-RELATED LATENCIES AND REPEAT RATES

Op code Latency		Repeat Rate
Multiply and dot-product without saturation after accumulation	5	1
Multiply and dot-product with saturation after accumulation	5	1
Multiply without accumulation	5	1

3.2.3 SYSTEM CONTROL COPROCESSOR (CP0)

In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation and cache protocols, the exception control system, the processor's diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as cache size and set associativity, and the presence of options like microMIPS, is also available by accessing the CP0 registers, listed in Table 3-3.

TABLE 3-3: COPROCESSOR 0 REGISTERS

Register Number	Register Name	Function
0 Index	Index into the TLB array (microAptiv MPU only).
1 Random	Randomly generated index into the TLB array (microAptiv MPU only).
2 Entry	Lo0 Low-order portion of the TLB entry for even-numbered virtual pages (microAptiv MPU only).
3 Entry	Lo1 Low-order portion of the TLB entry for odd-numbered virtual pages (microAptiv MPU only).
4	C o n UserLocal	Pointer to the page table entry in memory (microAptiv MPU only).User information that can be written by privileged software and read via the RDHWR instruction.
5 Page	Mask/ PageGrain	PageMask controls the variable page sizes in TLB entries. PageGrain enables support of 1 KB pages in the TLB (microAptiv MPU only).
6 Wired	Controls the number of fixed (i.e., wired) TLB entries (microAptiv MPU only).
7	HWREna	Enables access via the RDHWR instruction to selected hardware registers in Non-privileged mode.
8 Bad	VAddr Reports the address for the most recent address-related exception.
9 Count	Processor cycle count.
10 Entry	Hi High-order portion of the TLB entry (microAptiv MPU only).
11	Compare Core timer interrupt control.
12 Status	Processor status and control.
	IntCtl	Interrupt control of vector spacing.
	SRSCtl	Shadow register set control.
	SRSMap Shadow register mapping control.
	View_IPL	Allows the Priority Level to be read/written without extracting or inserting that bit from/to the Status register.
	SRSMAP2	Contains two 4-bit fields that provide the mapping from a vector number to the shadow set number to use when servicing such an interrupt.
13 Cause	Describes the cause of the last exception.
	NestedExc	Contains the error and exception level status bit values that existed prior to the current exception.
	View_RIPL	Enables read access to the RIPL bit that is available in the Cause register.
14	EPC	Program counter at last exception.
14	NestedEPC	Contains the exception program counter that existed prior to the current exception.
15	PRID	Processor identification and revision
	Ebase	Exception base address of exception vectors.
	CDMMBase	Common device memory map base.
16	Config	Configuration register.
	Config1	Configuration register 1.
	Config2	Configuration register 2.
	Config3	Configuration register 3.
	Config4	Configuration register 4.
	Config5	Configuration register 5.
	Config7	Configuration register 7.
17 LLa	Addr Load link address (microAptiv MPU only).
18 WatchLo	Low-order watchpoint address (microAptiv MPU only).
19 WatchHi	High-order watchpoint address (microAptiv MPU only).
20-22	Reserved	Reserved in the PIC32 core.
23	Debug EJTAG debug register.
	TraceControl EJTAG trace control.
	TraceControl2 EJTAG trace control 2.
	UserTraceData1 EJTAG user trace data 1 register.
	TraceBPC EJTAG trace breakpoint register.
	Debug2 Debug control/exception status 1.
24	DEPC Program counter at last debug exception.
24	UserTraceData2 EJTAG user trace data 2 register.
25	PerfCtl0 Performance counter 0 control.
	PerfCnt0	Performance counter 0.
	PerfCtl1	Performance counter 1 control.
	PerfCnt1	Performance counter 1.
26	ErrCtl	Software test enable of way-select and data RAM arrays for I-Cache and D-Cache (microAptiv MPU only).
27	Reserved	Reserved in the PIC32 core.
28	TagLo/DataLo	Low-order portion of cache tag interface (microAptiv MPU only).
29	Reserved	Reserved in the PIC32 core.
30	ErrorEPC	Program counter at last error exception.
31	DeSave Debug exception save.

3.3 Power Management

The processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during Idle periods.

3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT

The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 33.0 "Power-Saving Features".

The majority of the power consumed by the processor core is in the clock tree and clocking registers. The PIC32MZ family makes extensive use of local gated-clocks to reduce this dynamic power consumption.

3.4 L1 Instruction and Data Caches

3.4.1 INSTRUCTION CACHE (I-CACHE)

The I-Cache is an on-core memory block of 16 Kbytes. Because the I-Cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access rather than having to wait for the physical address translation. The tag holds 22 bits of physical address, a valid bit, and a lock bit. The LRU replacement bits are stored in a separate array.

The I-Cache block also contains and manages the instruction line fill buffer. Besides accumulating data to be written to the cache, instruction fetches that reference data in the line fill buffer are serviced either by a bypass of that data, or data coming from the external interface. The I-Cache control logic controls the bypass function.

The processor core supports I-Cache locking. Cache locking allows critical code or data segments to be locked into the cache on a per-line basis, enabling the system programmer to maximize the efficiency of the system cache.

The cache locking function is always available on all I-Cache entries. Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction.

3.4.2 DATA CACHE (D-CACHE)

The D-Cache is an on-core memory block of 4 Kbytes. This virtually indexed, physically tagged cache is protected. Because the D-Cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access. The tag holds 22 bits of physical address, a valid bit, and a lock bit. There is an additional array holding dirty bits and LRU replacement algorithm bits for each set of the cache.

In addition to I-Cache locking, the processor core also supports a D-Cache locking mechanism identical to the I-Cache. Critical data segments are locked into the cache on a per-line basis. The locked contents can be updated on a store hit, but cannot be selected for replacement on a cache miss.

The D-Cache locking function is always available on all D-Cache entries. Entries can then be marked as locked or unlocked on a per-entry basis using the CACHE instruction.

3.4.3 ATTRIBUTES

The processor core I-Cache and D-Cache attributes are listed in the Configuration registers (see Register 3-1 through Register 3-4).

3.5 EJTAG Debug Support

The processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine.

The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification specify which registers are selected and how they are used.

3.6 MIPS DSP ASE Extension

The MIPS DSP Application-Specific Extension Revision 2 is an extension to the MIPS32 architecture. This extension comprises new integer instructions and states that include new HI/LO accumulator register pairs and a DSP control register. This extension is crucial in a wide range of DSP, multimedia, and DSP-like algorithms covering Audio and Video processing applications. The extension supports native fractional format data type operations, register Single Instruction Multiple Data (SIMD) operations, such as add, subtract, multiply, and shift. In addition, the extension includes the following features that are essential in making DSP algorithms computationally efficient:

• Support for multiplication of complex operands
- Variable bit insertion and extraction
- Implementation and use of virtual circular buffers
- Arithmetic saturation and overflow handling support
- Zero cycle overhead saturation and rounding operations

3.7 microAptiv™ Core Configuration

Register 3-1 through Register 3-4 show the default configuration of the microAptiv core, which is included on PIC32MZ EC family devices.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	r-1 U-0 U-0	U-0 U-0 U-0 U-0	R-0
31:24	—	—	—	—	—	—	—	ISP
23:16	R-0	R-0 R-1 R-0	U-0 R-1 R-0	R-0
23:16	DSP	UDI	SB	MDU	—	MM<1:0>		BM
15:8	R-0	R-0 R-0 R-0	R-0 R-1	R-0	R-0
15:8	BE	AT<1:0>		AR<2:0>			MT<2:1>
7:0	R-1	U-0	U-0	U-0	U-0	R/W-0	R/W-1	R/W-0
7:0	MT<0>	—	—	—	—	K0<2:0>

Legend:	r = Reserved bit
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31 Reserved: This bit is hardwired to '1' to indicate the presence of the Config1 register.

bit 30-25 Unimplemented: Read as '0'

bit 24 ISP: Instruction Scratch Pad RAM bit 0 = Instruction Scratch Pad RAM is not implemented

bit 23 DSP: Data Scratch Pad RAM bit 0 = Data Scratch Pad RAM is not implemented

bit 22 UDI: User-defined bit 0 = CorExtend User-Defined Instructions are not implemented

bit 21 SB: SimpleBE bit 1 = Only Simple Byte Enables are allowed on the internal bus interface

bit 20 MDU: Multiply/Divide Unit bit 0 = Fast, high-performance MDU

bit 19 Unimplemented: Read as '0'

bit 18-17 MM<1:0>: Merge Mode bits 10 = Merging is allowed

bit 16 BM: Burst Mode bit 0 = Burst order is sequential

bit 15 BE: Endian Mode bit 0 = Little-endian

bit 14-13 AT<1:0>: Architecture Type bits 00 = MIPS32

bit 12-10 AR<2:0>: Architecture Revision Level bits 001 = MIPS32 Release 2

bit 9-7 MT<2:0>: MMU Type bits 001 = microAptiv MPU Microprocessor core uses a TLB-based MMU

bit 6-3 Unimplemented: Read as '0'

bit 2-0 K0<2:0>: Kseg0 Coherency Algorithm bits 011 = Cacheable, non-coherent, write-back, write allocate 010 = Uncached 001 = Cacheable, non-coherent, write-through, write allocate 000 = Cacheable, non-coherent, write-through, no write allocate All other values are not used and are mapped to other values. Values 100, 101, and 110 are mapped to 010. Value 111 is mapped to 010.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	r-1 R-0 R-0	R-1 R-1 R-1 R-1	R-0
31:24	— MMU	Size<5:0> IS<2>
23:16	R-1 R-0 R-0	R-1 R-1 R-0 R-1	R-1
23:16	IS<1:0> IL<2:0> IA<2:0>
15:8	R-0 R-0 R-0	R-0 R-1 R-1 R-0	R-1
15:8	DS<2:0> DL<2:0> DA<2:1>
7:0	R-1 U-0 U-0	R-1 R-1 R-0 R-1	R-0
7:0	DA<0>	—	—	PC	WR	CA	EP	FP

Legend:	r = Reserved bit
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31 Reserved: This bit is hardwired to a '1' to indicate the presence of the Config2 register.

bit 30-25 MMU Size<5:0>: Contains the number of TLB entries minus 1

001111 = 16 TLB entries

bit 24-22 IS<2:0>: Instruction Cache Sets bits

010 = Contains 256 instruction cache sets per way

bit 21-19 IL<2:0>: Instruction-Cache Line bits

011 = Contains instruction cache line size of 16 bytes

bit 18-16 IA<2:0: Instruction-Cache Associativity bits

011 = Contains 4-way instruction cache associativity

bit 15-13 DS<2:0>: Data-Cache Sets bits

000 = Contains 64 data cache sets per way

bit 12-10 DL<2:0>: Data-Cache Line bits

011 = Contains data cache line size of 16 bytes

bit 9-7 DA<2:0>: Data-Cache Associativity bits

011 = Contains the 4-way set associativity for the data cache

bit 6-5 Unimplemented: Read as '0'

bit 4 PC: Performance Counter bit

1 = The processor core contains Performance Counters

bit 3 WR: Watch Register Presence bit

1 = No Watch registers are present

bit 2 CA: Code Compression Implemented bit

0 = No MIPS16e® present

bit 1 EP: EJTAG Present bit

1 = Core implements EJTAG

bit 0 FP: Floating Point Unit bit

0 = Floating Point Unit is not implemented

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	r-1 U-0 U-0	U-0 U-0	U-0 U-0	U-0
31:24	— — —	— — — —	— — — —	—
23:16	U-0 R-0 R-1	R-0 R-0	R-0 R-1	R/W-y
23:16	—	IPLW<1:0>		MMAR<2:0>			MCU	ISAONEXC^(1)
15:8	R-y	R-y R-1	R-1 R-1	R-1 U-0 R-1
15:8	ISA<1:0>(^1)		ULRI	RXI	DSP2P	DSPP	—	ITL
7:0	U-0 R-1 R-1	R-0 R-1	U-0 U-0	R-0
7:0	—	VEIC	VINT	SP	CDMM	—	—	TL

Legend:	r = Reserved bit	y = Value set from Configuration bits on POR
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: This bit is hardwired as '1' to indicate the presence of the Config4 register

bit 30-23 Unimplemented: Read as '0'

bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits 01 = IPL and RIPL bits are 8-bits in width

bit 20-18 MMAR<2:0>: microMIPS Architecture Revision Level bits 000 = Release 1

bit 17 MCU: MIPS MCU ASE Implemented bit 1 = MCU ASE is implemented

bit 16 ISAONEXC: ISA on Exception bit ^(1) 1 = microMIPS is used on entrance to an exception vector 0 = MIPS32 ISA is used on entrance to an exception vector

bit 15-14 ISA<1:0>: Instruction Set Availability bits ^(1) 11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of reset

10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of reset

bit 13 ULRI: UserLocal Register Implemented bit 1 = UserLocal Coprocessor 0 register is implemented

bit 12 RXI: RIE and XIE Implemented in PageGrain bit 1 = RIE and XIE bits are implemented

bit 11 DSP2P: MIPS DSP ASE Revision 2 Presence bit 1 = DSP Revision 2 is present

bit 10 DSPP: MIPS DSP ASE Presence bit 1 = DSP is present

bit 9 Unimplemented: Read as '0'

bit 8 ITL: Indicates that iFlowtrace hardware is present 1 = The iFlowtrace is implemented in the core

bit 7 Unimplemented: Read as '0'

bit 6 VEIC: External Vector Interrupt Controller bit 1 = Support for an external interrupt controller is implemented.

bit 5 VINT: Vector Interrupt bit 1 = Vector interrupts are implemented

bit 4 SP: Small Page bit 0 = 4 KB page size

bit 3 CDMM: Common Device Memory Map bit 1 = CDMM is implemented

bit 2-1 Unimplemented: Read as '0'

bit 0 TL: Trace Logic bit 0 = Trace logic is not implemented

Note 1: These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0<6>).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — — — —
7:0	U-0 U-0 U-0	U-0 U-0 U-0 U-0	R-1
7:0	— — —	— — — —	N	F

Legend:	r = Reserved
R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-1 Unimplemented: Read as '0'

bit 0 NF: Nested Fault bit

1 = Nested Fault feature is implemented

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R-1	U-0	U-0	U-0	U-0	U-0	U-0	U-0
31:24	WII — —	— — — — —
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
23:16	— — —	— — — — —
15:8	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
15:8	— — —	— — — — —
7:0	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
7:0	— — —	— — — — —

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31 WII: Wait IE Ignore bit

1 = Indicates that this processor will allow an interrupt to unblock a WAIT instruction

bit 30-0 Unimplemented: Read as '0'

NOTES:

4.0 MEMORY ORGANIZATION

Note:

This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. This document is not intended to be a comprehensive reference source. For detailed information, refer to Section 48. "Memory Organization and Permissions" (DS60001214), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

PIC32MZ EC microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, Special Function Registers (SFRs) and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, PIC32MZ EC devices allow execution from data memory.

Key features include:

• 32-bit native data width
- Separate User (KUSEG) and Kernel (KSEG0/KSEG1/KSEG2/KSEG3) mode address space
- Separate boot Flash memory for protected code
- Robust bus exception handling to intercept runaway code
- Cacheable (KSEG0/KSEG2) and non-cacheable (KSEG1/KSEG3) address regions
- Read-Write permission access to predefined memory regions

4.1 Memory Layout

PIC32MZ EC microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU.

The main memory maps for the PIC32MZ EC devices are illustrated in Figure 4-1 through Figure 4-4. Figure 4-5 provides memory map information for boot Flash and boot alias. Table 4-1 provides memory map information for SFRs.

FIGURE 4-1: MEMORY MAP FOR DEVICES WITH 512 KB OF PROGRAM MEMORY
(1,2)
Microchip PIC32MZ2048ECH144 - Memory Layout - 1
Note 1: Memory areas are not shown to scale.
2: The Cache, MMU, and TLB are initialized by compiler start-up code.
3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
4: The MMU must be enabled and the TLB must be set up to access this segment.

FIGURE 4-2: MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND 256 KB OF RAM ^(1,2)
Microchip PIC32MZ2048ECH144 - Memory Layout - 2
Note 1: Memory areas are not shown to scale.
2: The Cache, MMU, and TLB are initialized by compiler start-up code.
3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
4: The MMU must be enabled and the TLB must be set up to access this segment.

FIGURE 4-3: MEMORY MAP FOR DEVICES WITH 1024 KB OF PROGRAM MEMORY AND 512 KB OF RAM ^(1,2)
Microchip PIC32MZ2048ECH144 - Memory Layout - 3
Note 1: Memory areas are not shown to scale.
2: The Cache, MMU, and TLB are initialized by compiler start-up code.
3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
4: The MMU must be enabled and the TLB must be set up to access this segment.

FIGURE 4-4: MEMORY MAP FOR DEVICES WITH 2048 KB OF PROGRAM MEMORY (1,2)
Microchip PIC32MZ2048ECH144 - Memory Layout - 4
Note 1: Memory areas are not shown to scale.
2: The Cache, MMU, and TLB are initialized by compiler start-up code.
3: RAM memory is divided into two equal banks: RAM Bank 1 and RAM Bank 2 on a half boundary.
4: The MMU must be enabled and the TLB must be set up to access this segment.

FIGURE 4-5: BOOT AND ALIAS MEMORY MAP

Physical Memory Map(1)	0x1FC74000
Sequence/Configuration Space(3)	0x1FC700000x1FC6FF00
Boot Flash 2	0x1FC60000
Reserved 0x1FC54028
Serial Number(5)	0x1FC54020
ADC Calibration Space (3)	0x1FC54000
Sequence/Configuration Space(4)	0x1FC500000x1FC4FF00
Boot Flash 1	0x1FC40000
Reserved	0x1FC34000
Unused Configuration Space(6)	0x1FC300000x1FC2FF00
Upper Boot Alias	0x1FC20000
Reserved	0x1FC14000
Configuration Space(2,3)	0x1FC100000x1FC0FF00
Lower Boot Alias	0x1FC00000

Note 1: Memory areas are not shown to scale.
2: Memory locations 0x1FC0FF40 through 0x1FC0FFFC are used to initialize Configuration registers (see Section 34.0 "Special Features").
3: Memory locations 0x1FC54000 through 0x1FC54010 are used to initialize the ADC Calibration registers (see Section 34.0 "Special Features").
4: Refer to Section 4.1.1 "Boot Flash Sequence and Configuration Spaces" for more information.
5: Memory locations 0x1FC54020 and 0x1FC54024 contain a unique device serial number (see Section 34.0 "Special Features").
6: This configuration space cannot be used for executing code in the upper boot alias.

TABLE 4-1: SFR MEMORY MAP

Peripheral	Virtual Address
Peripheral	Base	Offset Start
System Bus(1)	0xBF8F0000	0x0000
RNG	0xBF8E0000	0x6000
Crypto 0x5000
USB 0x3000
SQI1 0x2000
EBI 0x1000
Prefetch 0x0000
Ethernet	0xBF880000	0x2000
CAN1 and CAN2 0x0000	0xBF880000
PORTA-PORTK	0xBF860000	0x0000
Comparator 1, 2	0xBF840000	0xC000
ADC1		0xB000
OC1-OC9		0x4000
IC1-IC9		0x2000
Timer1-Timer9		0x0000
PMP	0xBF820000	0xE000
UART1-UART6		0x2000
SPI1-SPI6		0x1000
I2C1-I2C5		0x0000
DMA	0xBF810000	0x1000
Interrupt Controller	0xBF810000	0x0000
PPS	0xBF800000	0x1400
Oscillator		0x1200
CVREF		0x0E00
RTCC		0x0C00
Deadman Timer		0x0A00
Watchdog Timer		0x0800
Flash Controller		0x0600
Configuration		0x0000

Note 1: Refer to 4.2 "System Bus Arbitration" for important legal information.

4.1.1 BOOT FLASH SEQUENCE AND CONFIGURATION SPACES

Sequence space is used to identify which boot Flash is aliased by aliased regions. If the value programmed into the TSEQ<15:0> bits of the BF1SEQ0 word is equal to or greater than the value programmed into the TSEQ<15:0> bits of the BF2SEQ0 word, Boot Flash 1 is aliased by the lower boot alias region, and Boot Flash 2 is aliased by the upper boot alias region. If TSEQ<15:0> bits of BF2SEQ0 is greater than TSEQ<15:0> bits of BF1SEQ0, the opposite is true (see Table 4-2 and Table 4-3 for BFxSEQ0 word memory locations).

The CSEQ<15:0> bits must contain the complement value of the TSEQ<15:0> bits; otherwise, the value of TSEQ<15:0> is considered invalid, and an alternate sequence is used. See Section 4.1.2 "Alternate Sequence and Configuration Words" for more information.

Once boot Flash memories are aliased, configuration space located in the lower boot alias region is used as the basis for the Configuration words, DEVSIGN0, DEVCP0, and DEVCFGx (and the associated alternate configuration registers). This means that the boot Flash region to be aliased by lower boot alias region memory must contain configuration values in the appropriate memory locations.

Note: Do not use word program operation (NVMOP<3:0>=0001) when programming data into the sequence and configuration spaces.

4.1.2 ALTERNATE SEQUENCE AND CONFIGURATION WORDS

Every word in the configuration space and sequence space has an associated alternate word (designated by the letter A as the first letter in the name of the word). During device start-up, primary words are read and if uncorrectable ECC errors are found, the BCFGERR (RCON<27>) flag is set and alternate words are used. If uncorrectable ECC errors are found in primary and alternate words, the BCFGFAIL (RCON<26>) flag is set and the default configuration is used.

TABLE 4-2: BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY

Legend: x = unknown value on Reset; — = Reserved, read as '1'. Reset values are shown in hexadecimal.

TABLE 4-3: BOOT FLASH 2 SEQUENCE AND CONFIGURATION WORDS SUMMARY

Virtual Address(BFC6_#)

Bit Range

Bits

All Resets

31/15 30

14 29/13

28/12 27/11

26/10 25/9

24/8 23/7

22/6 21/5

20/4 19/3

18/2 17/1

16/0

FF40

ABF2DEVCFG3 31:0

Note: See Table 34-2 for the bit descriptions.

xxxxx

FF44

ABF2DEVCFG2 31:0 xxxx

FF48

ABF2DEVCFG1 31:0 xxxx

FF4C

ABF2DEVCFG0 31:0 xxxx

FF50

ABF2DEVCP3 31:0 xxxx

FF54

ABF2DEVCP2 31:0 xxxx

FF58

ABF2DEVCP1 31:0 xxxx

FF5C

ABF2DEVCP0 31:0 xxxx

FF60

ABF2DEVSIGN3 31:0 xxxx

FF64

ABF2DEVSIGN2 31:0 xxxx

FF68

ABF2DEVSIGN1 31:0 xxxx

FF6C

ABF2DEVSIGN0 31:0 xxxx

FF70

ABF2SEQ3

31:16

——

xxxxx

15:0

——

xxxxx

FF74

ABF2SEQ2

31:16

——

xxxxx

15:0

——

xxxxx

FF78

ABF2SEQ1

31:16

——

xxxxx

15:0

——

xxxxx

FF7C

ABF2SEQ0

31:16

CSEQ<15:0>

xxxxx

15:0

TSEQ<15:0>

xxxxx

FFC0

BF2DEVCFG3

31:0

Note: See Table 34-1 for the bit descriptions.

xxxxx

FFC4

BF2DEVCFG2

31:0 xxxx

FFC8

BF2DEVCFG1

31:0 xxxx

FFCC

BF2DEVCFG0

31:0 xxxx

FFD0

BF2DEVCP3 31:0 xxxx

FFD4

BF2DEVCP2 31:0 xxxx

FFD8

BF2DEVCP1 31:0 xxxx

FFDC

BF2DEVCP0 31:0 xxxx

FFE0

BF2DEVSIGN3

31:0 xxxx

FFE4

BF2DEVSIGN2

31:0 xxxx

FFE8

BF2DEVSIGN1

31:0 xxxx

FFEC

BF2DEVSIGN0

31:0 xxxx

FFF0

BF2SEQ3

31:16

——

xxxxx

15:0

——

xxxxx

FFF4

BF2SEQ2

31:16

——

xxxxx

15:0

——

xxxxx

FFF8

BF2SEQ1

31:16

——

xxxxx

15:0

——

xxxxx

FFFC

BF2SEQ0

31:16

CSEQ<15:0>

xxxxx

15:0

TSEQ<15:0>

xxxxx

Legend: x = unknown value on Reset; — = Reserved, read as '1'. Reset values are shown in hexadecimal.

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-16 CSEQ<15:0>: Boot Flash Complement Sequence Number bits

bit 15-0 TSEQ<15:0>: Boot Flash True Sequence Number bits

Note: The BFxSEQ1 through BFxSEQ3 and ABFxSEQ1 through ABFxSEQ3 registers are used for Quad Word programming operation when programming the BFxSEQ0/ABFxSEQ0 registers, and do not contain any valid information.

4.2 System Bus Arbitration

Note: The System Bus interconnect implements one or more instantiations of the SonicsSX® interconnect from Sonics, Inc. This document contains materials that are (c) 2003-2015 Sonics, Inc., and that constitute proprietary information of Sonics, Inc. SonicsSX is a registered trademark of Sonics, Inc. All such materials and trademarks are used under license from Sonics, Inc.

As shown in the PIC32MZ EC Family Block Diagram (see Figure 1-1), there are multiple initiator modules (I1 through I14) in the system that can access various target modules (T1 through T13). Table 4-4 illustrates which initiator can access which target. The System Bus supports simultaneous access to targets by initiators, so long as the initiators are accessing different targets. The System Bus will perform arbitration, if multiple initiators attempt to access the same target.

TABLE 4-4: INITIATORS TO TARGETS ACCESS ASSOCIATION

Target #

I n i

Name CPU DMA Read DMA Write USB

Ethernet Read

Ethernet Write

CAN1

CAN2

SQI1

Flash Controller

Crypto

Flash Memory:Program FlashBoot FlashPrefetch Module

RAM Bank 1 Memory

RAM Bank 2 Memory

External Memory via EBI and EBI Module

Peripheral Set 1:System Control, Flash Control, DMT, RTCC, CVR, PPS Input, PPS Output, Interrupts, DMA, WDT

Peripheral Set 2:SPI1-SPI6I2C1-I2C5UART1-UART6PMP

Peripheral Set 3:Timer1-Timer9IC1-IC9OC1-OC9ADC1Comparator 1Comparator 2

Peripheral Set 4:PORTA-PORTK

Peripheral Set 5:CAN1CAN2Ethernet Controller

Peripheral Set 6:USB

External Memory via SQI1 and SQI1 Module

Peripheral Set 7:Crypto Engine

Peripheral Set 8:RNG Module

The System Bus arbitration scheme implements a non-programmable, Least Recently Serviced (LRS) priority, which provides Quality Of Service (QOS) for most initiators. However, some initiators can use Fixed High Priority (HIGH) arbitration to guarantee their access to data.

The arbitration scheme for the available initiators is shown in Table 4-5.

TABLE 4-5: INITIATOR ID AND QOS

Name	ID	QOS
CPU	1	LRS^(1)
CPU	2	HIGH^(1,2)
DMA Read	3	LRS^(1)
DMA Read	4	HIGH^(1,2)
DMA Write	5	LRS^(1)
DMA Write	6	HIGH^(1,2)
USB	7	LRS
Ethernet Read	8	LRS
Ethernet Write	9	LRS
CAN1	10	LRS
CAN2	11	LRS
SQI1	12	LRS
Flash Controller	13	HIGH^(2)
Crypto	14	LRS

Note 1: When accessing SRAM, the DMAPRI bit (CFGCON<25>) and the CPUPRI bit (CFGCON<24>) provide arbitration control for the DMA and CPU (when servicing an interrupt (i.e., EXL = 1)), respectively, by selecting the use of LRS or HIGH When using HIGH, the DMA and CPU get arbitration preference over all initiators using LRS.

2: Using HIGH arbitration can have serious negative effects on other initiators. Therefore, it is recommended to not enable this type of arbitration for an initiator that uses significant system bandwidth. HIGH arbitration is intended to be used for low bandwidth applications that require low latency, such as LCC graphics applications.

4.3 Permission Access and System Bus Registers

The System Bus on PIC32MZ EC family of microcontrollers provides access control capabilities for the transaction initiators on the System Bus.

The System Bus divides the entire memory space into fourteen target regions and permits access to each target by initiators via permission groups. Four Permission Groups (0 through 3) can be assigned to each initiator. Each permission group is independent of the others and can have exclusive or shared access to a region.

Using the CFGPG register (see Register 34-10 in Section 34.0 "Special Features"), Boot firmware can assign a permission group to each initiator, which can make requests on the System Bus.

The available targets and their regions, as well as the associated control registers to assign protection, are described and listed in Table 4-6.

To change these registers, they must be unlocked in hardware. The register lock is controlled by the PGLOCK Configuration bit (CFGCON<11>). Setting PGLOCK prevents writes to the control registers; clearing PGLOCK allows writes.

To set or clear the PGLOCK bit, an unlock sequence must be executed. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

TABLE 4-6: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS

Target Number

Target Description^(5)

SBTxREGy Register SBTxRDy Register SBTxWRy Register

Name

Region Base (BASE<21:0>) (see Note 2)

Physical Start Address

Region Size (SIZE<4:0>) (see Note 3)

Region Size

Priority (PRI)

Priority Level

Name

Read Permission (GROUP3, GROUP2, GROUP1, GROUP0)

Name

Write Permission (GROUP3, GROUP2, GROUP1, GROUP0)

System Bus

SBT0REG0 R

0x1F8F0000 R 64 KB

— 0

SBT0RD0 R/W

(1)

SBT0WR0

R/W(1)

SBT0REG1 R

0x1F8F8000 R 32 KB

— 3

SBT0RD1 R/W

(1)

SBT0WR1

R/W(1)

Flash Memory(6):Program FlashBoot FlashPrefetch Module

SBT1REG0 R

0x1D000000

(4)

R(4)

— 0

SBT1RD0 R/W

(1)

SBT1WR0

0, 0, 0, 0

SBT1REG2

0x1F8E0000

4 KB

SBT1RD2

R/W(1)

SBT1WR2

R/W(1)

SBT1REG3

R/W

SBT1RD3

R/W(1)

SBT1WR3

0, 0, 0, 0

SBT1REG4

R/W

SBT1RD4

R/W(1)

SBT1WR4

0, 0, 0, 0

SBT1REG5

R/W

SBT1RD5

R/W(1)

SBT1WR5

0, 0, 0, 0

SBT1REG6

R/W

SBT1RD6

R/W(1)

SBT1WR6

0, 0, 0, 0

SBT1REG7

R/W

SBT1RD7

R/W(1)

SBT1WR7

0, 0, 0, 0

SBT1REG8

R/W

SBT1RD8

R/W(1)

SBT1WR8

0, 0, 0, 0

RAM Bank 1 Memory

SBT2REG0 R

0x00000000

(4)

R(4)

— 0

SBT2RD0 R/W

(1)

SBT2WR0

R/W(1)

SBT2REG1

R/W

—

SBT2RD1

R/W(1)

SBT2WR1

R/W(1)

SBT2REG2

R/W

SBT2RD2

R/W(1)

SBT2WR2

R/W(1)

RAM Bank 2 Memory

SBT3REG0

R(4)

— 0

SBT3RD0 R/W

(1)

SBT3WR0

R/W(1)

SBT3REG1

R/W

—

SBT3RD1

R/W(1)

SBT3WR1

R/W(1)

SBT3REG2

R/W

SBT3RD2

R/W(1)

SBT3WR2

R/W(1)

External Memory via EBI and EBI Module^(6)

SBT4REG0

0x20000000

64 MB

—

SBT4RD0

R/W(1)

SBT4WR0

R/W(1)

SBT4REG2

0x1F8E1000

4 KB

SBT4RD2

R/W(1)

SBT4WR2

R/W(1)

Peripheral Set 1:System ControlFlash ControlDMT/WDTRTCCCVRPPS InputPPS OutputInterruptsDMA

SBT5REG0

R 0x1F800000 R 128 KB

— 0

SBT5RD0 R/W

(1)

SBT5WR0

R/W(1)

SBT5REG1

R/W

—

SBT5RD1

R/W(1)

SBT5WR1

R/W(1)

SBT5REG2

R/W

SBT5RD2

R/W(1)

SBT5WR2

R/W(1)

Legend: R = Read; R/W = Read/Write; 'x' in a register name = 0-13; 'y' in a register name = 0-8.
Note 1: Reset values for these bits are '0', '1', '1', '1', respectively.
2: The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
3: The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2 ^(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
4: Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
5: See Table 4-1 for information on specific target memory size and start addresses.
6: The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.

TABLE 4-6: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)

Target Number

Target Description^(5)

SBTxREGy Register

SBTxRDy Register

SBTxWRy Register

Name

Region Base (BASE<21:0>) (see Note 2)

Physical Start Address

Region Size (SIZE<4:0>) (see Note 3)

Region Size

Priority (PRI)

Priority Level

Name

Read Permission (GROUP3, GROUP2, GROUP1, GROUP0)

Name

Write Permission (GROUP3, GROUP2, GROUP1, GROUP0)

Peripheral Set 2:SP11-SPI6I2C1-I2C5UART1-UART6PMP

SBT6REG0 R

0x1F820000 R 64 KB

— 0 SBT6RD0 R/W

(1)

SBT6WR0 R/W

(1)

SBT6REG1 R/W

R/W R/W R/W — 3 SBT6RD1 R/W

(1)

SBT6WR1 R/W

(1)

Peripheral Set 3:Timer1-Timer9IC1-IC9OC1-OC9ADC1Comparator 1Comparator 2

SBT7REG0 R

0x1F840000 R 64 KB

— 0 SBT7RD0 R/W

(1)

SBT7WR0 R/W

(1)

SBT7REG1 R/W

R/W R/W R/W — 3 SBT7RD1 R/W

(1)

SBT7WR1 R/W

(1)

Peripheral Set 4:PORTA-PORTK

SBT8REG0 R

0x1F860000 R 64 KB

— 0 SBT8RD0 R/W

(1)

SBT8WR0 R/W

(1)

SBT8REG1 R/W

R/W R/W R/W — 3 SBT8RD1 R/W

(1)

SBT8WR1 R/W

(1)

Peripheral Set 5:CAN1CAN2Ethernet Controller

SBT9REG0 R

0x1F880000 R 64 KB

— 0 SBT9RD0 R/W

(1)

SBT9WR0 R/W

(1)

SBT9REG1 R/W

R/W R/W R/W — 3 SBT9RD1 R/W

(1)

SBT9WR1 R/W

(1)

Peripheral Set 6:USB

SBT10REG0

R 0x1F8E 3000 R

4 KB

— 0 SBT10RD0

R/W

(1)

SBT10WR0

R/W^(1)

External Memory via SQI1 and SQI1 Module

SBT11REG0

R 0x30000 0000 R

64 MB

— 0 SBT11RD0

R/W

(1)

SBT11WR0

R/W^(1)

SBT11REG1

0x1F8E2000

4 KB

—

SBT11RD1

R/W^(1)

SBT11WR1

R/W^(1)

Peripheral Set 7:Crypto Engine

SBT12REG0

R 0x1F8E 5000 R

4 KB

— 0 SBT12RD0

R/W

(1)

SBT12WR0

R/W^(1)

Peripheral Set 8:RNG Module

SBT13REG0

R 0x1F8E 6000 R

4 KB

— 0 SBT13RD0

R/W

(1)

SBT13WR0

R/W^(1)

Legend: R = Read; R/W = Read/Write; 'x' in a register name = 0-13; 'y' in a register name = 0-8.
Note 1: Reset values for these bits are '0', '1', '1', '2', respectively.
2: The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
3: The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
4: Refer to the Device Memory Maps (Figure 4-1 through Figure 4-4) for specific device memory sizes and start addresses.
5: See Table 4-1 for information on specific target memory size and start addresses.
6: The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.

TABLE 4-7: SYSTEM BUS REGISTER MAP

Virtual Address(BF08_#)	Register Name	Bit Range	Bits																	All Resets
Virtual Address(BF08_#)	Register Name	Bit Range	31/15	30/14 29	13 28/12 27	11 26/10 25	9 24/8 23	7 22/6 21/5	20/4 19/3	18/2 17/1 16	0									All Resets
0510	SBFLAG	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0510	SBFLAG	15:0	—	—	T13PGV	T12PGV	T11PGV	T10PGV	T9PGV	T8PGV	T7PGV	T6PGV	T5PGV	T4PGV	T3PGV	T2PGV	T1PGV	T0PGV	0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.

TABLE 4-8: SYSTEM BUS TARGET 0 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-9: SYSTEM BUS TARGET 1 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'c'. Reset values are shown in hexadecimal.
Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-9: SYSTEM BUS TARGET 1 REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-10: SYSTEM BUS TARGET 2 REGISTER MAP

TABLE 4-11: SYSTEM BUS TARGET 3 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'a'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-12: SYSTEM BUS TARGET 4 REGISTER MAP

TABLE 4-13: SYSTEM BUS TARGET 5 REGISTER MAP

TABLE 4-14: SYSTEM BUS TARGET 6 REGISTER MAP

TABLE 4-15: SYSTEM BUS TARGET 7 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-16: SYSTEM BUS TARGET 8 REGISTER MAP

TABLE 4-17: SYSTEM BUS TARGET 9 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-18: SYSTEM BUS TARGET 10 REGISTER MAP

TABLE 4-19: SYSTEM BUS TARGET 11 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-20: SYSTEM BUS TARGET 12 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

TABLE 4-21: SYSTEM BUS TARGET 13 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal. Note: For reset values listed as 'xxxx', please refer to Table 4-6 for the actual reset values.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — — —	—
15:8	U-0 U-0 R-0	R-0 R-0	R-0 R-0
15:8	—	—	T13PGV	T12PGV	T11PGV	T10PGV	T9PGV	T8PGV
7:0	R-0 R-0 R-0	R-0 R-0	R-0 R-0
7:0	T7PGV	T6PGV	T5PGV	T4PGV	T3PGV	T2PGV	T1PGV	T0PGV

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared

bit 31-14 Unimplemented: Read as '0'

bit 13-0 TxPGV: Target 'x' Permission Group Violation Status bits ('x' = 0-13)

Refer to Table 4-6 for the list of available targets and their descriptions.

1 = Target is reporting a Permission Group (PG) violation

0 = Target is not reporting a PG violation

Note: All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM registers).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0, C U-0	U-0 U-0 R/W-0, C	R/W-0, C R/W-0, C R/W-0, C
31:24	MULTI —	— —		C	O			D
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	—	— — —	—
15:8	R-0 R-0 R-0	R-0 R-0 R-0	R-0 R-0
15:8	INITID<7:0>
7:0	R-0 R-0 R-0	R-0 U-0 R-0 R-0	R-0
7:0	REGION<3:0>				—	CMD<2:0>

Legend:	C = Clearable bit
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared

bit 31 MULTI: Multiple Permission Violations Status bit

This bit is cleared by writing a '1'.

1 = Multiple errors have been detected

0 = No multiple errors have been detected

bit 30-28 Unimplemented: Read as '0'

bit 27-24 CODE<3:0>: Error Code bits

Indicates the type of error that was detected. These bits are cleared by writing a '1'.

1111 = Reserved

1101 = Reserved

•

0011 = Permission violation

0010 = Reserved

0001 = Reserved

0000 = No error

bit 23-16 Unimplemented: Read as '0'

bit 15-8 INITID<7:0>: Initiator ID of Requester bits

11111111 = Reserved

•

00001111 = Reserved

00001110 = Crypto Engine

00001101 = Flash Controller

00001100 = SQI1

00001011 = CAN2

00001010 = CAN1

00001001 = Ethernet Write

00001000 = Ethernet Read

00000111 = USB

00000110 = DMA Write (DMAPRI (CFGCON<25>) = 1)

00000101 = DMA Write (DMAPRI (CFGCON<25>) = 0)

00000100 = DMA Read (DMAPRI (CFGCON<25>) = 1)

00000011 = DMA Read (DMAPRI (CFGCON<25>) = 0)

00000010 = CPU (CPUPRI (CFGCON<24>) = 1)

00000001 = CPU (CPUPRI (CFGCON<25>) = 0)

00000000 = Reserved

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

REGISTER 4-3: SBTxELOG1: SYSTEM BUS TARGET 'x' ERROR LOG REGISTER 1
('x' = 0-13) (CONTINUED)
bit 7-4 REGION<3:0>: Requested Region Number bits 1111 - 0000 = Target's region that reported a permission group violation bit 3 Unimplemented: Read as '0' bit 2-0 CMD<2:0>: Transaction Command of the Requester bits 111 = Reserved 110 = Reserved 101 = Write (a non-posted write) 100 = Reserved 011 = Read (a locked read caused by a Read-Modify-Write transaction) 010 = Read 001 = Write 000 = Idle

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	—— —	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
23:16	—— —	—— — — — —
15:8	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
15:8	—— —	—— — — — —
7:0	U-0 U-0 U-0	U-0 U-0	U-0 R-0 R-0
7:0	—— —	—— — — — GROUP<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared

bit 31-3 Unimplemented: Read as '0'

bit 1-0 GROUP<1:0>: Requested Permissions Group bits

11 = Group 3
10 = Group 2
01 = Group 1
00 = Group 0

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	R/W-0
31:24	— — —	— — — —	ERRP
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — — —
15:8	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
15:8	— — —	— — — —
7:0	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
7:0	— — —	— — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared

bit 31-25 Unimplemented: Read as '0'

bit 24 ERRP: Error Control bit

1 = Report protection group violation errors
0 = Do not report protection group violation errors

bit 23-0 Unimplemented: Read as '0'

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	—— —	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	—— —	—— — — — —
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	—— —	—— — — — —
7:0	U-0 U-0 U-0	U-0 U-0 U-0	U-0 R-0
7:0	—— —	—— — — — —	CLEAR

Legend:

R = Readable bit W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared

bit 31-1 Unimplemented: Read as '0'

bit 0 CLEAR: Clear Single Error on Read bit

A single error as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	—— —	—— — — — —
23:16	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
23:16	—— —	—— — — — —
15:8	U-0 U-0 U-0	U-0 U-0	U-0 U-0 U-0
15:8	—— —	—— — — — —
7:0	U-0 U-0 U-0	U-0 U-0	U-0 U-0 R-0
7:0	—— —	—— — — — — CLEAR

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared

bit 31-1 Unimplemented: Read as '0'

bit 0 CLEAR: Clear Multiple Errors on Read bit

Multiple errors as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.

Note: Refer to Table 4-6 for the list of available targets and their descriptions.

('x' = 0-13; 'y' = 0-8)

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W0 R/W-0	R/W0 R/W-0 R/W0	R/W0 R/W-0 R/W0	R/W-0
31:24	BASE<21:14>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0
23:16	BASE<13:6>
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R-0	U-0
15:8	BASE<5:0>						PRI	—
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	U-0	U-0	U-0
7:0	SIZE<4:0>					—	—	—

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared

bit 31-10 BASE<21:0>: Region Base Address bits

bit 9 PRI: Region Priority Level bit

1 = Level 2

0 = Level 1

bit 8 Unimplemented: Read as '0'

bit 7-3 SIZE<4:0>: Region Size bits

Permissions for a region are only active is the SIZE is non-zero.

11111 = Region size = 2(SIZE - 1) x 1024 (bytes)

•

00001 = Region size = 2(SIZE - 1) x 1024 (bytes)

00000 = Region is not present

bit 2-0 Unimplemented: Read as '0'

Note 1: Refer to Table 4-6 for the list of available targets and their descriptions.

2: For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	———	——— —— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	———	——— —— ——
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	———	——— —— ——
7:0	U-0 U-0 U-0	U-0 R/W-0 R/W-1	R/W-1 R/W-1
7:0	—	—	—	—	GROUP3	GROUP2	GROUP1	GROUP0

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared

bit 31-4 Unimplemented: Read as '0'

bit 3 Group3: Group3 Read Permissions bits

1 = Privilege Group 3 has read permission
0 = Privilege Group 3 does not have read permission

bit 2 Group2: Group2 Read Permissions bits

1 = Privilege Group 2 has read permission
0 = Privilege Group 2 does not have read permission

bit 1 Group1: Group1 Read Permissions bits

1 = Privilege Group 1 has read permission
0 = Privilege Group 1 does not have read permission

bit 0 Group0: Group0 Read Permissions bits

1 = Privilege Group 0 has read permission
0 = Privilege Group 0 does not have read permission

Note 1: Refer to Table 4-6 for the list of available targets and their descriptions.

2: For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0
31:24	———	——— —— ——
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0
23:16	———	——— —— ——
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0
15:8	———	——— —— ——
7:0	U-0 U-0 U-0	U-0 R/W-0 R/W-1	R/W-1 R/W-1
7:0	—	—	—	—	GROUP3	GROUP2	GROUP1	GROUP0

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set '0' = Bit is cleared

bit 31-4 Unimplemented: Read as '0'

bit 3 Group3: Group 3 Write Permissions bits

1 = Privilege Group 3 has write permission
0 = Privilege Group 3 does not have write permission

bit 2 Group2: Group 2 Write Permissions bits

1 = Privilege Group 2 has write permission
0 = Privilege Group 2 does not have write permission

bit 1 Group1: Group 1 Write Permissions bits

1 = Privilege Group 1 has write permission
0 = Privilege Group 1 does not have write permission

bit 0 Group0: Group 0 Write Permissions bits

1 = Privilege Group 0 has write permission
0 = Privilege Group 0 does not have write permission

Note 1: Refer to Table 4-6 for the list of available targets and their descriptions.

2: For some target regions, certain bits in this register are read-only with preset values. See Table 4-6 for more information.

5.0 FLASH PROGRAM MEMORY

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 52. “Flash Program Memory with Support for Live Update” (DS60001193), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

PIC32MZ EC devices contain an internal Flash program memory for executing user code, which includes the following features:

Two Flash banks for live update support
Dual boot support
Write protection for program and boot Flash
ECC support

There are three methods by which the user can program this memory:

- Run-Time Self-Programming (RTSP)

- EJTAG Programming

- In-Circuit Serial Programming™ (ICSP™)

RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 52. "Flash Program Memory with Support for Live Update" (DS60001193) in the "PIC32 Family Reference Manual".

EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer.

ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP.

The EJTAG and ICSP methods are described in the "PIC32 Flash Programming Specification" (DS60001145), which is available for download from the Microchip website.

Note: In PIC32MZ EC devices, the Flash page size is 16 KB (4096 IW) and the row size is 2 KB (512 IW).

5.1 Flash Control Registers

TABLE 5-1: FLASH CONTROLLER REGISTER MAP

Virtual Address(BF00_f)	Register Name	Bit Range	Bits																All Resets
Virtual Address(BF00_f)	Register Name	Bit Range	31/15 30	4 29/13 28	12 27/11 26	10 25/9 24	8 23/7 22/6	21/5 20/4	19/3 18/2 17	1/1 16/0									All Resets
0600	NVMCON(1)	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0600	NVMCON(1)	15:0	WR	WREN	WRERR	LVDERR	—	—	—	—	SWAP	—	—	—	NVMOP<31:0>				0000
0610	NVMKEY	31:16	NVMKEY<31:0>																0000
0610	NVMKEY	15:0	NVMKEY<31:0>																0000
0620	NVMADDR(1)	31:16	NVMADDR<31:0>																0000
0620	NVMADDR(1)	15:0	NVMADDR<31:0>																0000
0630	NVMDATA0	31:16	NVMDATA0<31:0>																0000
0630	NVMDATA0	15:0	NVMDATA0<31:0>																0000
0640	NVMDATA1	31:16	NVMDATA1<31:0>																0000
0640	NVMDATA1	15:0	NVMDATA1<31:0>																0000
0650	NVMDATA2	31:16	NVMDATA2<31:0>																0000
0650	NVMDATA2	15:0	NVMDATA2<31:0>																0000
0660	NVMDATA3	31:16	NVMDATA3<31:0>																0000
0660	NVMDATA3	15:0	NVMDATA3<31:0>																0000
0670	NVMSRC ADDR	31:16	NVMSRCADDR<31:0>																0000
0670	NVMSRC ADDR	15:0	NVMSRCADDR<31:0>																0000
0680	NVMPWP(1)	31:16	PWPULOCK	—	—	—	—	—	—	—	PWP<23:16>								0000
0680	NVMPWP(1)	15:0	PWP<15:0>																0000
0690	NVMBWP(1)	31:16	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	0000
0690	NVMBWP(1)	15:0	LBWPULOCK	—	—	LBWP4	LBWP3	LBWP2	LBWP1	LBWP0	UBWPULOCK	—	—	UBWP4	UBWP3	UBWP2	UBWP1	UBWP0	9TDF

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —	—
15:8	R/W-0, HC	R/W-0	R-0, HS, HC	R-0, HS, HC	U-0	U-0	U-0	U-0
15:8	WR(1)	WREN(1)	WRERR(1)	LVDERR(1)	— — —	—
7:0	R/W-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	SWAP	—	—	—	NVMOP<3:0>

Legend:	HS = Hardware Set	HC = Hardware Cleared
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 WR: Write Control bit ^(1)

This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been performed.

1 = Initiate a Flash operation

0 = Flash operation is complete or inactive

bit 14 WREN: Write Enable bit ^(1)

1 = Enable writes to the WR bit and disables writes to the NVMOP<3:0> bits

0 = Disable writes to WR bit and enables writes to the NVMOP<3:0> bits

bit 13 WRERR: Write Error bit ^(1)

This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.

1 = Program or erase sequence did not complete successfully

0 = Program or erase sequence completed normally

bit 12 LVDERR: Low-Voltage Detect Error bit ^(1)

This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.

1 = Low-voltage detected (possible data corruption, if WRERR is set)

0 = Voltage level is acceptable for programming

bit 11-8 Unimplemented: Read as '0'

bit 7 SWAP: Program Flash Bank Swap Control bit

This bit can be modified only when the WREN bit is '0' and the unlock sequence has been performed.

1 = Program Flash Bank 2 is mapped to the lower mapped region and program Flash Bank 1 is mapped to the upper mapped region

0 = Program Flash Bank 1 is mapped to the lower mapped region and program Flash Bank 2 is mapped to the upper mapped region

bit 6-4 Unimplemented: Read as '0'

Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

2: This operation results in a "no operation" (NOP) when the Dynamic Flash ECC Configuration bits = 00 (FECCCON<1:0> (DVCFG0<9:8>)), which enables ECC at all times. For all other FECCCON<1:0> bit settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors if dynamic Flash ECC is enabled (FECCCON<1:0> = 01). Refer to Section 52. "Flash Program Memory with Support for Live Update" (DS60001193) for information regarding ECC and Flash programming.

REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)

bit 3-0 NVMOP<3:0>: NVM Operation bits

These bits are only writable when WREN = 0.

1111 = Reserved

•

1000 = Reserved

0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected, PWP<23:0> = 0x000000)

0110 = Upper program Flash memory erase operation: erases only the upper mapped region of program Flash (all pages in that region must be unprotected)

0101 = Lower program Flash memory erase operation: erases only the lower mapped region of program Flash (all pages in that region must be unprotected)

0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected

0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected

0010 = Quad Word (128-bit) program operation: programs the 128-bit Flash word selected by NVMADDR, if it is not write-protected

0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected ^(2)

0000 = No operation

Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
31:24	NVMKEY<31:24>
23:16	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
23:16	NVMKEY<23:16>
15:8	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
15:8	NVMKEY<15:8>
7:0	W-0 W-0 W-0 W-0 W-0 W-0		W-0 W-0
7:0	NVMKEY<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMKEY<31:0>: Unlock Register bits

These bits are write-only, and read as '0' on any read

Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	NVMADDR<31:24>(1)
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	NVMADDR<23:16>(1)
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	NVMADDR<15:8>(1)
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	NVMADDR<7:0>(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMADDR<31:0>: Flash Address bits (1)

NVMOP<3:0>Selection	Flash Address Bits (NVMADDR<31:0>)
Page Erase	Address identifies the page to erase (NVMADDR<13:0> are ignored).
Row Program	Address identifies the row to program (NVMADDR<11:0> are ignored).
Word Program	Address identifies the word to program (NVMADDR<1:0> are ignored).
Quad Word Program	Address identifies the quad word (128-bit) to program (NVMADDR<3:0> bits are ignored).

Note 1: For all other NVMOP<3:0> bit settings, the Flash address is ignored. See the NVMCON register (Register 5-1) for additional information on these bits.

Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	NVMDATA<31:24>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	NVMDATA<23:16>
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	NVMDATA<15:8>
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	NVMDATA<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMDATA<31:0>: Flash Data bits

Word Program: Writes NVMDATA0 to the target Flash address defined in NVMADDR

Quad Word Program: Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address defined in NVMADDR. NVMDATA0 contains the Least Significant Instruction Word.

Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	NVMSRCADDR<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	NVMSRCADDR<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	NVMSRCADDR<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	NVMSRCADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0' -n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits (NVMCON<3:0>) are set to perform row programming.

Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset sources.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-1 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	PWPULOCK —	— — — —	—	—
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	PWP<23:16>
15:8	R/W-0	R/W-0	R-0 R-0 R-0	0 R-0 R-0 R-0
15:8	PWP<15:8>
7:0	R-0	R-0 R-0 R-0	0 R-0 R-0 R-0	0
7:0	PWP<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31 PWPULOCK: Program Flash Memory Page Write-protect Unlock bit

1 = Register is not locked and can be modified

0 = Register is locked and cannot be modified

This bit is only clearable and cannot be set except by any reset.

bit 30-24 Unimplemented: Read as '0'

bit 23-0 PWP<23:0>: Flash Program Write-protect (Page) Address bits

Physical memory below address 0x1Dxxxxxx is write protected, where 'xxxxxx' is specified by PWP<23:0>. When PWP<23:0> has a value of '0', write protection is disabled for the entire program Flash. If the specified address falls within the page, the entire page and all pages below the current page will be protected.

Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —
15:8	R/W-1	U-0	U-0	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
15:8	LBWPULOCK	—	—	LBWP4(1)	LBWP3(1)	LBWP2(1)	LBWP1(1)	LBWP0(1)
7:0	R/W-1	r-1	U-0	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
7:0	UBWPULOCK	—	—	UBWP4(1)	UBWP3(1)	UBWP2(1)	UBWP1(1)	UBWP0(1)

Legend:		r = Reserved
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 LBWPULOCK: Lower Boot Alias Write-protect Unlock bit

1 = LBWPx bits are not locked and can be modified

0 = LBWPx bits are locked and cannot be modified

This bit is only clearable and cannot be set except by any reset.

bit 14-13 Unimplemented: Read as '0'

bit 12 LBWP4: Lower Boot Alias Page 4 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled

bit 11 LBWP3: Lower Boot Alias Page 3 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled

bit 10 LBWP2: Lower Boot Alias Page 2 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled

bit 9 LBWP1: Lower Boot Alias Page 1 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF enabled
0 = Write protection for physical address 0x01FC04000 through 0x1FC07FFF disabled

bit 8 LBWP0: Lower Boot Alias Page 0 Write-protect bit ^(1)

1 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF enabled
0 = Write protection for physical address 0x01FC00000 through 0x1FC03FFF disabled

bit 7 UBWPULOCK: Upper Boot Alias Write-protect Unlock bit

1 = UBWPx bits are not locked and can be modified
0 = UBWPx bits are locked and cannot be modified

This bit is only user-clearable and cannot be set except by any reset.

bit 6 Reserved: This bit is reserved for use by development tools
bit 5 Unimplemented: Read as '0'

Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock bit (LBWPULOCK or UBWPULOCK) is set.

Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.

REGISTER 5-7: NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER

bit 4 UBWP4: Upper Boot Alias Page 4 Write-protect bit (1)

1 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF enabled
0 = Write protection for physical address 0x01FC30000 through 0x1FC33FFF disabled

bit 3 UBWP3: Upper Boot Alias Page 3 Write-protect bit (1)

1 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF enabled
0 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF disabled

bit 2 UBWP2: Upper Boot Alias Page 2 Write-protect bit (1)

1 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF enabled
0 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF disabled

bit 1 UBWP1: Upper Boot Alias Page 1 Write-protect bit (1)

1 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF enabled
0 = Write protection for physical address 0x01FC24000 through 0x1FC27FFF disabled

bit 0 UBWP0: Upper Boot Alias Page 0 Write-protect bit (1)

1 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF enabled
0 = Write protection for physical address 0x01FC20000 through 0x1FC23FFF disabled

Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock bit (LBWPULOCK or UBWPULOCK) is set.

Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.

NOTES:

6.0 RESETS

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS60001118), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The device Reset sources are as follows:

• Power-on Reset (POR)
- Master Clear Reset pin (MCLR)
- Software Reset (SWR)
- Watchdog Timer Reset (WDTR)
- Brown-out Reset (BOR)
- Configuration Mismatch Reset (CMR)
- Deadman Timer Reset (DMTR)

A simplified block diagram of the Reset module is illustrated in Figure 6-1.

FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM
Microchip PIC32MZ2048ECH144 - RESETS - 1

flowchart

graph TD
    A["MCLR"] --> B["Amplifier"]
    B --> C["Glitch Filter"]
    C --> D["MCLR"]
    E["Sleep or Idle"] --> F["WDT Time-out"]
    E --> G["DMT Time-out"]
    F --> H["NMI Time-out"]
    G --> H
    H --> I["AND"]
    I --> J["DMTR/WDTR"]
    K["Voltage Regulator Enabled"] --> L["Power-up Timer"]
    L --> M["AND"]
    M --> N["POR"]
    O["VDD"] --> P["VDD Rise Detect"]
    P --> Q["Brown-out Reset"]
    Q --> R["BOR"]
    S["Configuration Mismatch Reset"] --> T["CMR"]
    U["Software Reset"] --> V["SWR"]
    W["SYSRST"] --> X["Output"]

6.1 Reset Control Registers

TABLE 6-1: RESETS REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as 'D'. Reset values are shown in hexadecimal.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 RW-0, HS	R/W-0, HS U-0	U-0
31:24	—	—	—	—	BCFGERR	BCFGFAIL	—	—
23:16	U-0 U-0 U-0	U-0	U-0	U-0	U-0 U-0
23:16	— — —	— —	—	—	—
15:8	U-0 U-0 U-0	U-0 U-0	U-0	R/W-0, H$				U-0
15:8	—	—	—	—	—	—	CMR	—
7:0	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-0, HS	R/W-1, HS	R/W-1, HS
7:0	EXTR	SWR	DMTO	WDTO	SLEEP	IDLE	BOR(1)	POR(1)

Legend:	HS = Hardware Set HC = Hardware Cleared
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-28 Unimplemented: Read as '0'

bit 27 BCFGERR: Primary Configuration Registers Error Flag bit

1 = An error occurred during a read of the primary configuration registers
0 = No error occurred during a read of the primary configuration registers

bit 26 BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit

1 = An error occurred during a read of the primary and alternate configuration registers
0 = No error occurred during a read of the primary and alternate configuration registers

bit 25-10 Unimplemented: Read as '0'

bit 9 CMR: Configuration Mismatch Reset Flag bit

1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred

bit 8 Unimplemented: Read as '0'

bit 7 EXTR: External Reset (MCLR) Pin Flag bit

1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred

bit 6 SWR: Software Reset Flag bit

1 = Software Reset was executed
0 = Software Reset was not executed

bit 5 DMTO: Deadman Timer Time-out Flag bit

1 = A DMT time-out has occurred
0 = A DMT time-out has not occurred

bit 4 WDTO: Watchdog Timer Time-out Flag bit

1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred

bit 3 SLEEP: Wake From Sleep Flag bit

1 = Device was in Sleep mode
0 = Device was not in Sleep mode

bit 2 IDLE: Wake From Idle Flag bit

1 = Device was in Idle mode
0 = Device was not in Idle mode

bit 1 BOR: Brown-out Reset Flag bit ^(1)

1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit ^(1)

1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred

Note 1: User software must clear this bit to view the next detection.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — —	—	—
7:0	U-0 U-0 U-0	U-0 U-0 U-0 U-0	0					W-0, HC
7:0	—	—	—	—	—	—	—	SWRST(1,2)

Legend:	HC = Hardware Cleared
R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-1 Unimplemented: Read as '0'

bit 0 SWRST: Software Reset Trigger bit ^(1,2)

1 = Enable software Reset event
0 = No effect

Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

2: Once this bit is set, any read of the RSWRST register will cause a reset to occur.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	R/W-0 R/W-0
31:24	— — —	— — —	D	M	T	O W	D	T
23:16	R/W-0	U-0 U-0 U-0	U-0 U-0				R/W-0 R/W-0
23:16	SWNMI	—	—	—	—	—	CF	WDTS
15:8	U-0 U-0 U-0	U-0 U-0 U-0	U-0	U-0
15:8	— — —	— — —	—	—
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	NMICNT<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-26 Unimplemented: Read as '0'

bit 25 DMTO: Deadman Timer Time-out Flag bit

1 = DMT time-out has occurred and caused a NMI

0 = DMT time-out has not occurred

Setting this bit will cause a DMT NMI event, and NMICNT will begin counting.

bit 24 WDTO: Watchdog Timer Time-Out Flag bit

1 = WDT time-out has occurred and caused a NMI

0 = WDT time-out has not occurred

Setting this bit will cause a WDT NMI event, and MNICNT will begin counting.

bit 23 SWNMI: Software NMI Trigger.

1 = An NMI will be generated

0 = An NMI will not be generated

bit 22-18 Unimplemented: Read as '0'

bit 17 CF: Clock Fail Detect bit

1 = FSCM has detected clock failure and caused an NMI

0 = FSCM has not detected clock failure

Setting this bit will cause a CF NMI event, but will not cause a clock switch to the BFRC.

bit 16 WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit

1 = WDT time-out has occurred during Sleep mode and caused a wake-up from sleep

0 = WDT time-out has not occurred during Sleep mode

Setting this bit will cause a WDT NMI.

bit 15-8 Unimplemented: Read as '0'

bit 7-0 NMICNT<7:0>: NMI Reset Counter Value bits

These bits specify the reload value used by the NMI reset counter.

11111111-00000001 = Number of SYSCLK cycles before a device Reset occurs ^(1)

00000000 = No delay between NMI assertion and device Reset event

Note 1: When a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is triggered the NMICNT will start decrementing. When NMICNT reaches zero, the device is Reset. This NMI reset counter is only applicable to these two specific NMI events.

Note: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — —	—	—
15:8	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
15:8	— — —	— — —	—	—
7:0	U-0 U-0 U-0	U-0 U-0 U-0 U-0	0					R/W-0
7:0	—	—	—	—	—	—	—	VREGS

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-1 Unimplemented: Read as '0'

bit 0 VREGS: Voltage Regulator Stand-by Enable bit

1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep

7.0 CPU EXCEPTIONS AND INTERRUPT CONTROLLER

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupt Controller" (DS60001108) and Section 50. "CPU for Devices with MIPS32® microAptiv™ and M-Class Cores" (DS60001192), which are available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

PIC32MZ EC devices generate interrupt requests in response to interrupt events from peripheral modules. The Interrupt Controller module exists outside of the CPU and prioritizes the interrupt events before presenting them to the CPU.

The CPU handles interrupt events as part of the exception handling mechanism, which is described in Section 7.1 "CPU Exceptions".

The Interrupt Controller module includes the following features:

Up to 190 interrupt sources and vectors with dedicated programmable offsets, eliminating the need for redirection
Single and multi-vector mode operations
Five external interrupts with edge polarity control
Interrupt proximity timer
Seven user-selectable priority levels for each vector
Four user-selectable subpriority levels within each priority
Seven shadow register sets that can be used for any priority level, eliminating software context switch and reducing interrupt latency
Software can generate any interrupt

Figure 7-1 shows the block diagram for the Interrupt Controller and CPU exceptions.
FIGURE 7-1: CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Microchip PIC32MZ2048ECH144 - CPU EXCEPTIONS AND INTERRUPT CONTROLLER - 1

flowchart

graph LR
    A["Interrupt Requests"] --> B["Interrupt Controller"]
    C["SYSCLK"] --> B
    B --> D["Vector Number and Offset"]
    B --> E["Priority Level"]
    B --> F["Shadow Set Number"]
    D --> G["CPU Core (Exception Handling)"]
    E --> G
    F --> G

7.1 CPU Exceptions

CPU coprocessor 0 contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including boundary cases in data, external events or program errors. Table 7-1 lists the exception types in order of priority.

TABLE 7-1: MIPS32 ^ microAptiv™ MICROPROCESSOR CORE EXCEPTION TYPES

Exception Type(In Order of Priority)	Description Branches to		StatusBits Set	Debug BitsSet	EXCCODE	XC32 Function Name
Highest Priority
Reset	Assertion MCLR or a Power-on Reset (POR).	0xBFC0_0000	BEV, ERL	—	—	_on_reset
Soft Reset	Assertion of a software Reset.	0xBFC0_0000	BEV, SR, ERL	—	—	_on_reset
DSS	EJTAG debug single step.	0xBFC0_0480	—	DSS	—	—
DINT	EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register.	0xBFC0_0480	—	DINT	—	—
NMI	Assertion of NMI signal.	0xBFC0_0000	BEV, NMI, ERL	—	—	_nmi_handler
Machine Check	TLB write that conflicts with an existing entry.	EBASE+0x180	MCHECK, EXL	—	0x18 _general_exception_handler
Interrupt	Assertion of unmasked hardware or software interrupt signal.	See Table 7-2.	IPL<2:0>	—	0x00	See Table 7-2.
Deferred Watch	Deferred watch (unmasked by K\|DM=>!(K\|DM) transition).	EBASE+0x180	WP, EXL	—	0x17	_general_exception_handler
DIB	EJTAG debug hardware instruction break matched.	0xBFC0_0480	—	DIB	—	—
WATCH	A reference to an address that is in one of the Watch registers (fetch).	EBASE+0x180	EXL	—	0x17	_general_exception_handler
AdEL	Fetch address alignment error. Fetch reference to protected address.	EBASE+0x180	EXL	—	0x04	_general_exception_handler
TLBL	Fetch TLB miss or fetch TLB hit to page with V = 0.	EBASE if Status.EXL = 0	—	—	0x02	—
TLBL	Fetch TLB miss or fetch TLB hit to page with V = 0.	EBASE+0x180 if Status.EXL == 1	—	—	0x02	_general_exception_handler
TLBL Execute Inhibit	An instruction fetch matched a valid TLB entry that had the XI bit set.	EBASE+0x180	EXL	—	0x14	_general_exception_handler
IBE	Instruction fetch bus error.	EBASE+0x180	EXL	—	0x06	_general_exception_handler
Exception Type(In Order of Priority)	Description	Branches to	StatusBits Set	Debug BitsSet	EXCCODE	XC32 Function Name
Instruction Validity Exceptions	An instruction could not be completed because it was not allowed to access the required resources (Coprocessor Unusable) or was illegal (Reserved Instruction). If both exceptions occur on the same instruction, the Coprocessor Unusable Exception takes priority over the Reserved Instruction Exception.	EBASE+0x180 EXL	— 0x0A or		0x0B	_general_exception_handler
Execute Exception	An instruction-based exception occurred: Integer overflow, trap, system call, breakpoint, floating point, or DSP ASE state disabled exception.	EBASE+0x180	EXL	—	0x08-0x0C	_general_exception_handler
Tr	Execution of a trap (when trap condition is true).	EBASE+0x180	EXL	—	0x0D	_general_exception_handler
DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).		0xBFC0_0480 —	DDBL or DDBS	—	—	—
WATCH	A reference to an address that is in one of the Watch registers (data).	EBASE+0x180	EXL	—	0x17	_general_exception_handler
AdEL	Load address alignment error. User mode load reference to kernel address.	EBASE+0x180	EXL	—	0x04	_general_exception_handler
AdES	Store address alignment error. User mode store to kernel address.	EBASE+0x180	EXL	—	0x05	_general_exception_handler
TLBL	Load TLB miss or load TLB hit to page with V = 0.	EBASE+0x180	EXL	—	0x02	_general_exception_handler
TLBS	Store TLB miss or store TLB hit to page with V = 0.	EBASE+0x180	EXL	—	0x03	_general_exception_handler
DBE	Load or store bus error.	EBASE+0x180	EXL	—	0x07	_general_exception_handler
DDBL	EJTAG data hardware breakpoint matched in load data compare.	0xBFC0_0480	—	DDBL	—	—
CBrk	EJTAG complex breakpoint.	0xBFC0_0480	—	DIBIMPR,DDBLIMPR,and/orDDBSIMPR	—	—
Lowest Priority

7.2 Interrupts

The PIC32MZ EC family uses variable offsets for vector spacing. This allows the interrupt vector spacing to be configured according to application needs. A unique interrupt vector offset can be set for each vector using its associated OFFx register.

For details on the Variable Offset feature, refer to 8.5.2 "Variable Offset" in Section 8. "Interrupt Controller" (DS60001108) of the "PIC32 Family Reference Manual".

Table 7-2 provides the Interrupt IRQ, vector and bit location information.

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag Enable Priority Sub-priority				Persistent Interrupt
Highest Natural Order Priority
Core Timer Interrupt	_CORE_TIMER_VECTOR	0	OFF000<17:1>	IFS0<0>	IEC0<0>	IPC0<4:2>	IPC0<1:0>	No
Core Software Interrupt 0	_CORE_SOFTWARE_0_VECTOR	1	OFF001<17:1>	IFS0<1>	IEC0<1>	IPC0<12:10>	IPC0<9:8>	No
Core Software Interrupt 1	_CORE_SOFTWARE_1_VECTOR	2	OFF002<17:1>	IFS0<2>	IEC0<2>	IPC0<20:18>	IPC0<17:16>	No
External Interrupt	_EXTERNAL_0_VECTOR	3	OFF003<17:1>	IFS0<3>	IEC0<3>	IPC0<28:26>	IPC0<25:24>	No
Timer1	_TIMER_1_VECTOR	4	OFF004<17:1>	IFS0<4>	IEC0<4>	IPC1<4:2>	IPC1<1:0>	No
Input Capture 1 Error	_INPUT_CAPTURE_1_ERROR_VECTOR	5	OFF005<17:1>	IFS0<5>	IEC0<5>	IPC1<12:10>	IPC1<9:8>	Yes
Input Capture 1	_INPUT_CAPTURE_1_VECTOR	6	OFF006<17:1>	IFS0<6>	IEC0<6>	IPC1<20:18>	IPC1<17:16>	Yes
Output Compare 1	_OUTPUT_COMPARE_1_VECTOR	7	OFF007<17:1>	IFS0<7>	IEC0<7>	IPC1<28:26>	IPC1<25:24>	No
External Interrupt 1	_EXTERNAL_1_VECTOR	8	OFF008<17:1>	IFS0<8>	IEC0<8>	IPC2<4:2>	IPC2<1:0>	No
Timer2	_TIMER_2_VECTOR	9	OFF009<17:1>	IFS0<9>	IEC0<9>	IPC2<12:10>	IPC2<9:8>	No
Input Capture 2 Error	_INPUT_CAPTURE_2_ERROR_VECTOR	10	OFF010<17:1>	IFS0<10>	IEC0<10>	IPC2<20:18>	IPC2<17:16>	Yes
Input Capture 2	_INPUT_CAPTURE_2_VECTOR	11	OFF011<17:1>	IFS0<11>	IEC0<11>	IPC2<28:26>	IPC2<25:24>	Yes
Output Compare 2	_OUTPUT_COMPARE_2_VECTOR	12	OFF012<17:1>	IFS0<12>	IEC0<12>	IPC3<4:2>	IPC3<1:0>	No
External Interrupt 2	_EXTERNAL_2_VECTOR	13	OFF013<17:1>	IFS0<13>	IEC0<13>	IPC3<12:10>	IPC3<9:8>	No
Timer3	_TIMER_3_VECTOR	14	OFF014<17:1>	IFS0<14>	IEC0<14>	IPC3<20:18>	IPC3<17:16>	No
Input Capture 3 Error	_INPUT_CAPTURE_3_ERROR_VECTOR	15	OFF015<17:1>	IFS0<15>	IEC0<15>	IPC3<28:26>	IPC3<25:24>	Yes
Input Capture 3	INPUT_CAPTURE_3_VECTOR	16	OFF016<17:1>	IFS0<16>	IEC0<16>	IPC4<4:2>	IPC4<1:0>	Yes
Output Compare 3	_OUTPUT_COMPARE_3_VECTOR	17	OFF017<17:1>	IFS0<17>	IEC0<17>	IPC4<12:10>	IPC4<9:8>	No
External Interrupt 3	_EXTERNAL_3_VECTOR	18	OFF018<17:1>	IFS0<18>	IEC0<18>	IPC4<20:18>	IPC4<17:16>	No
Timer4	_TIMER_4_VECTOR	19	OFF019<17:1>	IFS0<19>	IEC0<19>	IPC4<28:26>	IPC4<25:24>	No
Input Capture 4 Error	_INPUT_CAPTURE_4_ERROR_VECTOR	20	OFF020<17:1>	IFS0<20>	IEC0<20>	IPC5<4:2>	IPC5<1:0>	Yes

Note 1: Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MZ EC Family Features" for the list of available peripherals.
2: This interrupt source is not available on 64-pin devices.
3: This interrupt source is not available on 100-pin devices.
4: This interrupt source is not available on 124-pin devices.

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
Input Capture 4	_INPUT_CAPTURE_4_VECTOR	21	OFF021<17:1>	IFS0<21>	IEC0<21>	IPC5<12:10>	IPC5<9:8>	Yes
Output Compare 4	_OUTPUT_COMPARE_4_VECTOR	22	OFF022<17:1>	IFS0<22>	IEC0<22>	IPC5<20:18>	IPC5<17:16>	No
External Interrupt 4	_EXTERNAL_4_VECTOR	23	OFF023<17:1>	IFS0<23>	IEC0<23>	IPC5<28:26>	IPC5<25:24>	No
Timer5	_TIMER_5_VECTOR	24	OFF024<17:1>	IFS0<24>	IEC0<24>	IPC6<4:2>	IPC6<1:0>	No
Input Capture 5 Error	_INPUT_CAPTURE_5_ERROR_VECTOR	25	OFF025<17:1>	IFS0<25>	IEC0<25>	IPC6<12:10>	IPC6<9:8>	Yes
Input Capture 5	_INPUT_CAPTURE_5_VECTOR	26	OFF026<17:1>	IFS0<26>	IEC0<26>	IPC6<20:18>	IPC6<17:16>	Yes
Output Compare 5	_OUTPUT_COMPARE_5_VECTOR	27	OFF027<17:1>	IFS0<27>	IEC0<27>	IPC6<28:26>	IPC6<25:24>	No
Timer6	_TIMER_6_VECTOR	28	OFF028<17:1>	IFS0<28>	IEC0<28>	IPC7<4:2>	IPC7<1:0>	No
Input Capture 6 Error	_INPUT_CAPTURE_6_ERROR_VECTOR	29	OFF029<17:1>	IFS0<29>	IEC0<29>	IPC7<12:10>	IPC7<9:8>	Yes
Input Capture 6	_INPUT_CAPTURE_6_VECTOR	30	OFF030<17:1>	IFS0<30>	IEC0<30>	IPC7<20:18>	IPC7<17:16>	Yes
Output Compare 6	_OUTPUT_COMPARE_6_VECTOR	31	OFF031<17:1>	IFS0<31>	IEC0<31>	IPC7<28:26>	IPC7<25:24>	No
Timer7	_TIMER_7_VECTOR	32	OFF032<17:1>	IFS1<0>	IEC1<0>	IPC8<4:2>	IPC8<1:0>	No
Input Capture 7 Error	_INPUT_CAPTURE_7_ERROR_VECTOR	33	OFF033<17:1>	IFS1<1>	IEC1<1>	IPC8<12:10>	IPC8<9:8>	Yes
Input Capture 7	INPUT_CAPTURE_7_VECTOR	34	OFF034<17:1>	IFS1<2>	IEC1<2>	IPC8<20:18>	IPC8<17:16>	Yes
Output Compare 7	_OUTPUT_COMPARE_7_VECTOR	35	OFF035<17:1>	IFS1<3>	IEC1<3>	IPC8<28:26>	IPC8<25:24>	No
Timer8	_TIMER_8_VECTOR	36	OFF036<17:1>	IFS1<4>	IEC1<4>	IPC9<4:2>	IPC9<1:0>	No
Input Capture 8 Error	_INPUT_CAPTURE_8_ERROR_VECTOR	37	OFF037<17:1>	IFS1<5>	IEC1<5>	IPC9<12:10>	IPC9<9:8>	Yes
Input Capture 8	_INPUT_CAPTURE_8_VECTOR	38	OFF038<17:1>	IFS1<6>	IEC1<6>	IPC9<20:18>	IPC9<17:16>	Yes
Output Compare 8	_OUTPUT_COMPARE_8_VECTOR	39	OFF039<17:1>	IFS1<7>	IEC1<7>	IPC9<28:26>	IPC9<25:24>	No
Timer9	_TIMER_9_VECTOR	40	OFF040<17:1>	IFS1<8>	IEC1<8>	IPC10<4:2>	IPC10<1:0>	No
Input Capture 9 Error	_INPUT_CAPTURE_9_ERROR_VECTOR	41	OFF041<17:1>	IFS1<9>	IEC1<9>	IPC10<12:10>	IPC10<9:8>	Yes
Input Capture 9	_INPUT_CAPTURE_9_VECTOR	42	OFF042<17:1>	IFS1<10>	IEC1<10>	IPC10<20:18>	IPC10<17:16>	Yes
Output Compare 9	_OUTPUT_COMPARE_9_VECTOR	43	OFF043<17:1>	IFS1<11>	IEC1<11>	IPC10<28:26>	IPC10<25:24>	No
ADC1 Global Interrupt	_ADC1_VECTOR	44	OFF044<17:1>	IFS1<12>	IEC1<12>	IPC11<4:2>	IPC11<1:0>	Yes
Reserved	—	45	—	—	—	—	—	—
ADC1 Digital Comparator 1	_ADC1_DC1_VECTOR	46	OFF046<17:1>	IFS1<14>	IEC1<14>	IPC11<20:18>	IPC11<17:16>	Yes
ADC1 Digital Comparator 2	_ADC1_DC2_VECTOR	47	OFF047<17:1>	IFS1<15>	IEC1<15>	IPC11<28:26>	IPC11<25:24>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
ADC1 Digital Comparator 3	_ADC1_DC3_VECTOR	48	OFF048<17:1>	IFS1<16>	IEC1<16>	IPC12<4:2>	IPC12<1:0>	Yes
ADC1 Digital Comparator 4	_ADC1_DC4_VECTOR	49	OFF049<17:1>	IFS1<17>	IEC1<17>	IPC12<12:10>	IPC12<9:8>	Yes
ADC1 Digital Comparator 5	_ADC1_DC5_VECTOR	50	OFF050<17:1>	IFS1<18>	IEC1<18>	IPC12<20:18>	IPC12<17:16>	Yes
ADC1 Digital Comparator 6	_ADC1_DC6_VECTOR	51	OFF051<17:1>	IFS1<19>	IEC1<19>	IPC12<28:26>	IPC12<25:24>	Yes
ADC1 Digital Filter 1	_ADC1_DF1_VECTOR	52	OFF052<17:1>	IFS1<20>	IEC1<20>	IPC13<4:2>	IPC13<1:0>	Yes
ADC1 Digital Filter 2	_ADC1_DF2_VECTOR	53	OFF053<17:1>	IFS1<21>	IEC1<21>	IPC13<12:10>	IPC13<9:8>	Yes
ADC1 Digital Filter 3	_ADC1_DF3_VECTOR	54	OFF054<17:1>	IFS1<22>	IEC1<22>	IPC13<20:18>	IPC13<17:16>	Yes
ADC1 Digital Filter 4	_ADC1_DF4_VECTOR	55	OFF055<17:1>	IFS1<23>	IEC1<23>	IPC13<28:26>	IPC13<25:24>	Yes
ADC1 Digital Filter 5	_ADC1_DF5_VECTOR	56	OFF056<17:1>	IFS1<24>	IEC1<24>	IPC14<4:2>	IPC14<1:0>	Yes
ADC1 Digital Filter 6	_ADC1_DF6_VECTOR	57	OFF057<17:1>	IFS1<25>	IEC1<25>	IPC14<12:10>	IPC14<9:8>	Yes
Reserved	—	58	—	—	—	—	—	—
ADC1 Data 0	_ADC1_DATA0_VECTOR	59	OFF059<17:1>	IFS1<27>	IEC1<27>	IPC14<28:26>	IPC14<25:24>	Yes
ADC1 Data 1	_ADC1_DATA1_VECTOR	60	OFF060<17:1>	IFS1<28>	IEC1<28>	IPC15<4:2>	IPC15<1:0>	Yes
ADC1 Data 2	_ADC1_DATA2_VECTOR	61	OFF061<17:1>	IFS1<29>	IEC1<29>	IPC15<12:10>	IPC15<9:8>	Yes
ADC1 Data 3	_ADC1_DATA3_VECTOR	62	OFF062<17:1>	IFS1<30>	IEC1<30>	IPC15<20:18>	IPC15<17:16>	Yes
ADC1 Data 4	_ADC1_DATA4_VECTOR	63	OFF063<17:1>	IFS1<31>	IEC1<31>	IPC15<28:26>	IPC15<25:24>	Yes
ADC1 Data 5	_ADC1_DATA5_VECTOR	64	OFF064<17:1>	IFS2<0>	IEC2<0>	IPC16<4:2>	IPC16<1:0>	Yes
ADC1 Data 6	_ADC1_DATA6_VECTOR	65	OFF065<17:1>	IFS2<1>	IEC2<1>	IPC16<12:10>	IPC16<9:8>	Yes
ADC1 Data 7	_ADC1_DATA7_VECTOR	66	OFF066<17:1>	IFS2<2>	IEC2<2>	IPC16<20:18>	IPC16<17:16>	Yes
ADC1 Data 8	_ADC1_DATA8_VECTOR	67	OFF067<17:1>	IFS2<3>	IEC2<3>	IPC16<28:26>	IPC16<25:24>	Yes
ADC1 Data 9	_ADC1_DATA9_VECTOR	68	OFF068<17:1>	IFS2<4>	IEC2<4>	IPC17<4:2>	IPC17<1:0>	Yes
ADC1 Data 10	_ADC1_DATA10_VECTOR	69	OFF069<17:1>	IFS2<5>	IEC2<5>	IPC17<12:10>	IPC17<9:8>	Yes
ADC1 Data 11	_ADC1_DATA11_VECTOR	70	OFF070<17:1>	IFS2<6>	IEC2<6>	IPC17<20:18>	IPC17<17:16>	Yes
ADC1 Data 12	_ADC1_DATA12_VECTOR	71	OFF071<17:1>	IFS2<7>	IEC2<7>	IPC17<28:26>	IPC17<25:24>	Yes
ADC1 Data 13	_ADC1_DATA13_VECTOR	72	OFF072<17:1>	IFS2<8>	IEC2<8>	IPC18<4:2>	IPC18<1:0>	Yes
ADC1 Data 14	_ADC1_DATA14_VECTOR	73	OFF073<17:1>	IFS2<9>	IEC2<9>	IPC18<12:10>	IPC18<9:8>	Yes
ADC1 Data 15	_ADC1_DATA15_VECTOR	74	OFF074<17:1>	IFS2<10>	IEC2<10>	IPC18<20:18>	IPC18<17:16>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
ADC1 Data 16	_ADC1_DATA16_VECTOR	75	OFF075<17:1>	IFS2<11>	IEC2<11>	IPC18<28:26>	IPC18<25:24>	Yes
ADC1 Data 17	_ADC1_DATA17_VECTOR	76	OFF076<17:1>	IFS2<12>	IEC2<12>	IPC19<4:2>	IPC19<1:0>	Yes
ADC1 Data 18	_ADC1_DATA18_VECTOR	77	OFF077<17:1>	IFS2<13>	IEC2<13>	IPC19<12:10>	IPC19<9:8>	Yes
ADC1 Data 19(2)	_ADC1_DATA19_VECTOR	78	OFF078<17:1>	IFS2<14>	IEC2<14>	IPC19<20:18>	IPC19<17:16>	Yes
ADC1 Data 20(2)	_ADC1_DATA20_VECTOR	79	OFF079<17:1>	IFS2<15>	IEC2<15>	IPC19<28:26>	IPC19<25:24>	Yes
ADC1 Data 21(2)	_ADC1_DATA21_VECTOR	80	OFF080<17:1>	IFS2<16>	IEC2<16>	IPC20<4:2>	IPC20<1:0>	Yes
ADC1 Data 22(2)	_ADC1_DATA22_VECTOR	81	OFF081<17:1>	IFS2<17>	IEC2<17>	IPC20<12:10>	IPC20<9:8>	Yes
ADC1 Data 23(2)	_ADC1_DATA23_VECTOR	82	OFF082<17:1>	IFS2<18>	IEC2<18>	IPC20<20:18>	IPC20<17:16>	Yes
ADC1 Data 24(2)	_ADC1_DATA24_VECTOR	83	OFF083<17:1>	IFS2<19>	IEC2<19>	IPC20<28:26>	IPC20<25:24>	Yes
ADC1 Data 25(2)	_ADC1_DATA25_VECTOR	84	OFF084<17:1>	IFS2<20>	IEC2<20>	IPC21<4:2>	IPC21<1:0>	Yes
ADC1 Data 26(2)	_ADC1_DATA26_VECTOR	85	OFF085<17:1>	IFS2<21>	IEC2<21>	IPC21<12:10>	IPC21<9:8>	Yes
ADC1 Data 27(2)	_ADC1_DATA27_VECTOR	86	OFF086<17:1>	IFS2<22>	IEC2<22>	IPC21<20:18>	IPC21<17:16>	Yes
ADC1 Data 28(2)	_ADC1_DATA28_VECTOR	87	OFF087<17:1>	IFS2<23>	IEC2<23>	IPC21<28:26>	IPC21<25:24>	Yes
ADC1 Data 29(2)	_ADC1_DATA29_VECTOR	88	OFF088<17:1>	IFS2<24>	IEC2<24>	IPC22<4:2>	IPC22<1:0>	Yes
ADC1 Data 30(2)	_ADC1_DATA30_VECTOR	89	OFF089<17:1>	IFS2<25>	IEC2<25>	IPC22<12:10>	IPC22<9:8>	Yes
ADC1 Data 31(2)	_ADC1_DATA31_VECTOR	90	OFF090<17:1>	IFS2<26>	IEC2<26>	IPC22<20:18>	IPC22<17:16>	Yes
ADC1 Data 32(2)	_ADC1_DATA32_VECTOR	91	OFF091<17:1>	IFS2<27>	IEC2<27>	IPC22<28:26>	IPC22<25:24>	Yes
ADC1 Data 33(2)	_ADC1_DATA33_VECTOR	92	OFF092<17:1>	IFS2<28>	IEC2<28>	IPC23<4:2>	IPC23<1:0>	Yes
ADC1 Data 34(2)	_ADC1_DATA34_VECTOR	93	OFF093<17:1>	IFS2<29>	IEC2<29>	IPC23<12:10>	IPC23<9:8>	Yes
ADC1 Data 35(2,3)	_ADC1_DATA35_VECTOR	94	OFF094<17:1>	IFS2<30>	IEC2<30>	IPC23<20:18>	IPC23<17:16>	Yes
ADC1 Data 36(2,3)	_ADC1_DATA36_VECTOR	95	OFF095<17:1>	IFS2<31>	IEC2<31>	IPC23<28:26>	IPC23<25:24>	Yes
ADC1 Data 37(2,3)	_ADC1_DATA37_VECTOR	96	OFF096<17:1>	IFS3<0>	IEC3<0>	IPC24<4:2>	IPC24<1:0>	Yes
ADC1 Data 38(2,3)	_ADC1_DATA38_VECTOR	97	OFF097<17:1>	IFS3<1>	IEC3<1>	IPC24<12:10>	IPC24<9:8>	Yes
ADC1 Data 39(2,3)	_ADC1_DATA39_VECTOR	98	OFF098<17:1>	IFS3<2>	IEC3<2>	IPC24<20:18>	IPC24<17:16>	Yes
ADC1 Data 40(2,3)	_ADC1_DATA40_VECTOR	99	OFF099<17:1>	IFS3<3>	IEC3<3>	IPC24<28:26>	IPC24<25:24>	Yes
ADC1 Data 41(2,3)	_ADC1_DATA41_VECTOR	100	OFF100<17:1>	IFS3<4>	IEC3<4>	IPC25<4:2>	IPC25<1:0>	Yes
ADC1 Data 42(2,3)	_ADC1_DATA42_VECTOR	101	OFF101<17:1>	IFS3<5>	IEC3<5>	IPC25<12:10>	IPC25<9:8>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
ADC1 Data 43	_ADC1_DATA43_VECTOR	102	OFF102<17:1>	IFS3<6>	IEC3<6>	IPC25<20:18>	IPC25<17:16>	Yes
ADC1 Data 44	_ADC1_DATA44_VECTOR	103	OFF103<17:1>	IFS3<7>	IEC3<7>	IPC25<28:26>	IPC25<25:24>	Yes
Core Performance Counter Interrupt	_CORE_PERF_COUNT_VECTOR	104	OFF104<17:1>	IFS3<8>	IEC3<8>	IPC26<4:2>	IPC26<1:0>	No
Core Fast Debug Channel Interrupt	CORE_FAST_DEBUG_CHAN_VECTOR	105	OFF105<17:1>	IFS3<9>	IEC3<9>	IPC26<12:10>	IPC26<9:8>	Yes
System Bus Protection Violation	_SYSTEM_BUS_PROTECTION_VECTOR	106	OFF106<17:1>	IFS3<10>	IEC3<10>	IPC26<20:18>	IPC26<17:16>	Yes
Crypto Engine Event	_CRYPTO_VECTOR	107	OFF107<17:1>	IFS3<11>	IEC3<11>	IPC26<28:26>	IPC26<25:24>	Yes
Reserved	—	108	—	—	—	—	—	—
SPI1 Fault	_SPI1_FAULT_VECTOR	109	OFF109<17:1>	IFS3<13>	IEC3<13>	IPC27<12:10>	IPC27<9:8>	Yes
SPI1 Receive Done	_SPI1_RX_VECTOR	110	OFF110<17:1>	IFS3<14>	IEC3<14>	IPC27<20:18>	IPC27<17:16>	Yes
SPI1 Transfer Done	_SPI1_TX_VECTOR	111	OFF111<17:1>	IFS3<15>	IEC3<15>	IPC27<28:26>	IPC27<25:24>	Yes
UART1 Fault	_UART1_FAULT_VECTOR	112	OFF112<17:1>	IFS3<16>	IEC3<16>	IPC28<4:2>	IPC28<1:0>	Yes
UART1 Receive Done	_UART1_RX_VECTOR	113	OFF113<17:1>	IFS3<17>	IEC3<17>	IPC28<12:10>	IPC28<9:8>	Yes
UART1 Transfer Done	_UART1_TX_VECTOR	114	OFF114<17:1>	IFS3<18>	IEC3<18>	IPC28<20:18>	IPC28<17:16>	Yes
I2C1 Bus Collision Event	_I2C1_BUS_VECTOR	115	OFF115<17:1>	IFS3<19>	IEC3<19>	IPC28<28:26>	IPC28<25:24>	Yes
I2C1 Slave Event	_I2C1_SLAVE_VECTOR	116	OFF116<17:1>	IFS3<20>	IEC3<20>	IPC29<4:2>	IPC29<1:0>	Yes
I2C1 Master Event	_I2C1_MASTER_VECTOR	117	OFF117<17:1>	IFS3<21>	IEC3<21>	IPC29<12:10>	IPC29<9:8>	Yes
PORTA Input Change Interrupt(2)	_CHANGE_NOTICE_A_VECTOR	118	OFF118<17:1>	IFS3<22>	IEC3<22>	IPC29<20:18>	IPC29<17:16>	Yes
PORTB Input Change Interrupt	_CHANGE_NOTICE_B_VECTOR	119	OFF119<17:1>	IFS3<23>	IEC3<23>	IPC29<28:26>	IPC29<25:24>	Yes
PORTC Input Change Interrupt	CHANGE_NOTICE_C_VECTOR	120	OFF120<17:1>	IFS3<24>	IEC3<24>	IPC30<4:2>	IPC30<1:0>	Yes
PORTD Input Change Interrupt	CHANGE_NOTICE_D_VECTOR	121	OFF121<17:1>	IFS3<25>	IEC3<25>	IPC30<12:10>	IPC30<9:8>	Yes
PORTE Input Change Interrupt	_CHANGE_NOTICE_E_VECTOR	122	OFF122<17:1>	IFS3<26>	IEC3<26>	IPC30<20:18>	IPC30<17:16>	Yes
PORTF Input Change Interrupt	CHANGE_NOTICE_F_VECTOR	123	OFF123<17:1>	IFS3<27>	IEC3<27>	IPC30<28:26>	IPC30<25:24>	Yes
PORTG Input Change Interrupt	CHANGE_NOTICE_G_VECTOR	124	OFF124<17:1>	IFS3<28>	IEC3<28>	IPC31<4:2>	IPC31<1:0>	Yes
PORTH Input Change Interrupt(2,3)	CHANGE_NOTICE_H_VECTOR	125	OFF125<17:1>	IFS3<29>	IEC3<29>	IPC31<12:10>	IPC31<9:8>	Yes
PORTJ Input Change Interrupt(2,3)	_CHANGE_NOTICE_J_VECTOR	126	OFF126<17:1>	IFS3<30>	IEC3<30>	IPC31<20:18>	IPC31<17:16>	Yes
PORTK Input Change Interrupt(2,3,4)	_CHANGE_NOTICE_K_VECTOR	127	OFF127<17:1>	IFS3<31>	IEC3<31>	IPC31<28:26>	IPC31<25:24>	Yes
Parallel Master Port	PMP_VECTOR	128	OFF128<17:1>	IFS4<0>	IEC4<0>	IPC32<4:2>	IPC32<1:0>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
Parallel Master Port Error	_PMP_ERROR_VECTOR	129	OFF129<17:1>	IFS4<1>	IEC4<1>	IPC32<12:10>	IPC32<9:8>	Yes
Comparator 1 Interrupt	_COMPARATOR_1_VECTOR	130	OFF130<17:1>	IFS4<2>	IEC4<2>	IPC32<20:18>	IPC32<17:16>	No
Comparator 2 Interrupt	_COMPARATOR_2_VECTOR	131	OFF131<17:1>	IFS4<3>	IEC4<3>	IPC32<28:26>	IPC32<25:24>	No
USB General Event	_USB1_VECTOR	132	OFF132<17:1>	IFS4<4>	IEC4<4>	IPC33<4:2>	IPC33<1:0>	Yes
USB DMA Event	_USB1_DMA_VECTOR	133	OFF133<17:1>	IFS4<5>	IEC4<5>	IPC33<12:10>	IPC33<9:8>	Yes
DMA Channel 0	_DMA0_VECTOR	134	OFF134<17:1>	IFS4<6>	IEC4<6>	IPC33<20:18>	IPC33<17:16>	No
DMA Channel 1	_DMA1_VECTOR	135	OFF135<17:1>	IFS4<7>	IEC4<7>	IPC33<28:26>	IPC33<25:24>	No
DMA Channel 2	_DMA2_VECTOR	136	OFF136<17:1>	IFS4<8>	IEC4<8>	IPC34<4:2>	IPC34<1:0>	No
DMA Channel 3	_DMA3_VECTOR	137	OFF137<17:1>	IFS4<9>	IEC4<9>	IPC34<12:10>	IPC34<9:8>	No
DMA Channel 4	_DMA4_VECTOR	138	OFF138<17:1>	IFS4<10>	IEC4<10>	IPC34<20:18>	IPC34<17:16>	No
DMA Channel 5	_DMA5_VECTOR	139	OFF139<17:1>	IFS4<11>	IEC4<11>	IPC34<28:26>	IPC34<25:24>	No
DMA Channel 6	_DMA6_VECTOR	140	OFF140<17:1>	IFS4<12>	IEC4<12>	IPC35<4:2>	IPC35<1:0>	No
DMA Channel 7	_DMA7_VECTOR	141	OFF141<17:1>	IFS4<13>	IEC4<13>	IPC35<12:10>	IPC35<9:8>	No
SPI2 Fault	_SPI2_FAULT_VECTOR	142	OFF142<17:1>	IFS4<14>	IEC4<14>	IPC35<20:18>	IPC35<17:16>	Yes
SPI2 Receive Done	_SPI2_RX_VECTOR	143	OFF143<17:1>	IFS4<15>	IEC4<15>	IPC35<28:26>	IPC35<25:24>	Yes
SPI2 Transfer Done	_SPI2_TX_VECTOR	144	OFF144<17:1>	IFS4<16>	IEC4<16>	IPC36<4:2>	IPC36<1:0>	Yes
UART2 Fault	_UART2_FAULT_VECTOR	145	OFF145<17:1>	IFS4<17>	IEC4<17>	IPC36<12:10>	IPC36<9:8>	Yes
UART2 Receive Done	_UART2_RX_VECTOR	146	OFF146<17:1>	IFS4<18>	IEC4<18>	IPC36<20:18>	IPC36<17:16>	Yes
UART2 Transfer Done	_UART2_TX_VECTOR	147	OFF147<17:1>	IFS4<19>	IEC4<19>	IPC36<28:26>	IPC36<25:24>	Yes
I2C2 Bus Collision Event^(2)	_I2C2_BUS_VECTOR	148	OFF148<17:1>	IFS4<20>	IEC4<20>	IPC37<4:2>	IPC37<1:0>	Yes
I2C2 Slave Event^(2)	_I2C2_SLAVE_VECTOR	149	OFF149<17:1>	IFS4<21>	IEC4<21>	IPC37<12:10>	IPC37<9:8>	Yes
I2C2 Master Event^(2)	_I2C2_MASTER_VECTOR	150	OFF150<17:1>	IFS4<22>	IEC4<22>	IPC37<20:18>	IPC37<17:16>	Yes
Control Area Network 1	_CAN1_VECTOR	151	OFF151<17:1>	IFS4<23>	IEC4<23>	IPC37<28:26>	IPC37<25:24>	Yes
Control Area Network 2	_CAN2_VECTOR	152	OFF152<17:1>	IFS4<24>	IEC4<24>	IPC38<4:2>	IPC38<1:0>	Yes
Ethernet Interrupt	_ETHERNET_VECTOR	153	OFF153<17:1>	IFS4<25>	IEC4<25>	IPC38<12:10>	IPC38<9:8>	Yes
SPI3 Fault	_SPI3_FAULT_VECTOR	154	OFF154<17:1>	IFS4<26>	IEC4<26>	IPC38<20:18>	IPC38<17:16>	Yes
SPI3 Receive Done	_SPI3_RX_VECTOR	155	OFF155<17:1>	IFS4<27>	IEC4<27>	IPC38<28:26>	IPC38<25:24>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
SPI3 Transfer Done	_SPI3_TX_VECTOR	156	OFF156<17:1>	IFS4<28>	IEC4<28>	IPC39<4:2>	IPC39<1:0>	Yes
UART3 Fault	_UART3_FAULT_VECTOR	157	OFF157<17:1>	IFS4<29>	IEC4<29>	IPC39<12:10>	IPC39<9:8>	Yes
UART3 Receive Done	_UART3_RX_VECTOR	158	OFF158<17:1>	IFS4<30>	IEC4<30>	IPC39<20:18>	IPC39<17:16>	Yes
UART3 Transfer Done	_UART3_TX_VECTOR	159	OFF159<17:1>	IFS4<31>	IEC4<31>	IPC39<28:26>	IPC39<25:24>	Yes
I2C3 Bus Collision Event	_I2C3_BUS_VECTOR	160	OFF160<17:1>	IFS5<0>	IEC5<0>	IPC40<4:2>	IPC40<1:0>	Yes
I2C3 Slave Event	_I2C3_SLAVE_VECTOR	161	OFF161<17:1>	IFS5<1>	IEC5<1>	IPC40<12:10>	IPC40<9:8>	Yes
I2C3 Master Event	_I2C3_MASTER_VECTOR	162	OFF162<17:1>	IFS5<2>	IEC5<2>	IPC40<20:18>	IPC40<17:16>	Yes
SPI4 Fault	_SPI4_FAULT_VECTOR	163	OFF163<17:1>	IFS5<3>	IEC5<3>	IPC40<28:26>	IPC40<25:24>	Yes
SPI4 Receive Done	_SPI4_RX_VECTOR	164	OFF164<17:1>	IFS5<4>	IEC5<4>	IPC41<4:2>	IPC41<1:0>	Yes
SPI4 Transfer Done	_SPI4_TX_VECTOR	165	OFF165<17:1>	IFS5<5>	IEC5<5>	IPC41<12:10>	IPC41<9:8>	Yes
Real Time Clock	_RTCC_VECTOR	166	OFF166<17:1>	IFS5<6>	IEC5<6>	IPC41<20:18>	IPC41<17:16>	No
Flash Control Event	_FLASH_CONTROL_VECTOR	167	OFF167<17:1>	IFS5<7>	IEC5<7>	IPC41<28:26>	IPC41<25:24>	No
Prefetch Module SEC Event	_PREFETCH_VECTOR	168	OFF168<17:1>	IFS5<8>	IEC5<8>	IPC42<4:2>	IPC42<1:0>	Yes
SQI1 Event	_SQI1_VECTOR	169	OFF169<17:1>	IFS5<9>	IEC5<9>	IPC42<12:10>	IPC42<9:8>	Yes
UART4 Fault	_UART4_FAULT_VECTOR	170	OFF170<17:1>	IFS5<10>	IEC5<10>	IPC42<20:18>	IPC42<17:16>	Yes
UART4 Receive Done	_UART4_RX_VECTOR	171	OFF171<17:1>	IFS5<11>	IEC5<11>	IPC42<28:26>	IPC42<25:24>	Yes
UART4 Transfer Done	_UART4_TX_VECTOR	172	OFF172<17:1>	IFS5<12>	IEC5<12>	IPC43<4:2>	IPC43<1:0>	Yes
I2C4 Bus Collision Event	_I2C4_BUS_VECTOR	173	OFF173<17:1>	IFS5<13>	IEC5<13>	IPC43<12:10>	IPC43<9:8>	Yes
I2C4 Slave Event	_I2C4_SLAVE_VECTOR	174	OFF174<17:1>	IFS5<14>	IEC5<14>	IPC43<20:18>	IPC43<17:16>	Yes
I2C4 Master Event	_I2C4_MASTER_VECTOR	175	OFF175<17:1>	IFS5<15>	IEC5<15>	IPC43<28:26>	IPC43<25:24>	Yes
SPI5 Fault(2)	_SPI5_FAULT_VECTOR	176	OFF176<17:1>	IFS5<16>	IEC5<16>	IPC44<4:2>	IPC44<1:0>	Yes
SPI5 Receive Done(2)	_SPI5_RX_VECTOR	177	OFF177<17:1>	IFS5<17>	IEC5<17>	IPC44<12:10>	IPC44<9:8>	Yes
SPI5 Transfer Done(2)	_SPI5_TX_VECTOR	178	OFF178<17:1>	IFS5<18>	IEC5<18>	IPC44<20:18>	IPC44<17:16>	Yes
UART5 Fault	_UART5_FAULT_VECTOR	179	OFF179<17:1>	IFS5<19>	IEC5<19>	IPC44<28:26>	IPC44<25:24>	Yes
UART5 Receive Done	_UART5_RX_VECTOR	180	OFF180<17:1>	IFS5<20>	IEC5<20>	IPC45<4:2>	IPC45<1:0>	Yes
UART5 Transfer Done	_UART5_TX_VECTOR	181	OFF181<17:1>	IFS5<21>	IEC5<21>	IPC45<12:10>	IPC45<9:8>	Yes
I2C5 Bus Collision Event	_I2C5_BUS_VECTOR	182	OFF182<17:1>	IFS5<22>	IEC5<22>	IPC45<20:18>	IPC45<17:16>	Yes

TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)

Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Interrupt Bit Location				Persistent Interrupt
Interrupt Source^(1)	XC32 Vector Name	IRQ #	Vector #	Flag	Enable	Priority	Sub-priority	Persistent Interrupt
I2C5 Slave Event	I2C5_SLAVE_VECTOR	183	OFF183<17:1>	IFS5<23>	IEC5<23>	IPC45<28:26>	IPC45<25:24>	Yes
I2C5 Master Event	I2C5_MASTER_VECTOR	184	OFF184<17:1>	IFS5<24>	IEC5<24>	IPC46<4:2>	IPC46<1:0>	Yes
SPI6 Fault(2)	_SPI6_FAULT_VECTOR	185	OFF185<17:1>	IFS5<25>	IEC5<25>	IPC46<12:10>	IPC46<9:8>	Yes
SPI6 Receive Done(2)	_SPI6_RX_VECTOR	186	OFF186<17:1>	IFS5<26>	IEC5<26>	IPC46<20:18>	IPC46<17:16>	Yes
SPI6 Transfer Done(2)	_SPI6_TX_VECTOR	187	OFF187<17:1>	IFS5<27>	IEC5<27>	IPC46<28:26>	IPC46<25:24>	Yes
UART6 Fault	_UART6_FAULT_VECTOR	188	OFF188<17:1>	IFS5<28>	IEC5<28>	IPC47<4:2>	IPC47<1:0>	Yes
UART6 Receive Done	_UART6_RX_VECTOR	189	OFF189<17:1>	IFS5<29>	IEC5<29>	IPC47<12:10>	IPC47<9:8>	Yes
UART6 Transfer Done	_UART6_TX_VECTOR	190	OFF190<17:1>	IFS5<30>	IEC5<30>	IPC47<20:18>	IPC47<17:16>	Yes
Lowest Natural Order Priority

7.3 Interrupt Control Registers

TABLE 7-3: INTERRUPT REGISTER MAP

Virtual Address(BF61_2)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

0000

INTCON

31:16

—

0000

15:0

—

MVEC

—

TPC<2:0>

—

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

0000

0010

PRISS

31:16

PRI7SS<3:0>

PRI6SS<3:0>

PRI5SS<3:0>

PRI4SS<3:0>

0000

15:0

PRI3SS<3:0>

PRI2SS<3:0>

PRI1SS<3:0>

—

SS0

0000

0020

INTSTAT

31:16

—

0000

15:0

—

SRIPL<2:0>

SIRQ<7:0>

0000

0030

IPTMR

31:16

IPTMR<31:0>

0000

15:0

0000

0040

IFS0

31:16

OC6IF

IC6IF

IC6EIF

T6IF

OC5IF

IC5IF

IC5EIF

T5IF

INT4IF

OC4IF

IC4IF

IC4EIF

T4IF

INT3IF

OC3IF

IC3IF

0000

15:0

IC3EIF

T3IF

INT2IF

OC2IF

IC2IF

IC2EIF

T2IF

INT1IF

OC1IF

IC1IF

IC1EIF

T1IF

INT0IF

CS1IF

CS0IF

CTIF

0000

0050

IFS1

31:16

AD1D4IF

AD1D3IF

AD1D2IF

AD1D1IF

AD1D0IF

—

AD1DF6IF

AD1DF5IF

AD1DF4IF

AD1DF3IF

AD1DF2IF

AD1DF1IF

AD1DC6IF

AD1DC5IF

AD1DC4IF

AD1DC3IF

0000

15:0

AD1DC2IF

AD1DC1IF

—

AD1IF

OC9IF

IC9IF

IC9EIF

T9IF

OC8IF

IC8IF

IC8EIF

T8IF

OC7IF

IC7IF

IC7EIF

T7IF

0000

0060

IFS2(5)

31:16

AD1D36IF

AD1D35IF

AD1D34IF

AD1D33IF

AD1D32IF

AD1D31IF

AD1D30IF

AD1D29IF

AD1D28IF

AD1D27IF

AD1D26IF

AD1D25IF

AD1D24IF

AD1D23IF

AD1D22IF

AD1D21IF

0000

15:0

AD1D20IF

AD1D19IF

AD1D18IF

AD1D17IF

AD1D16IF

AD1D15IF

AD1D14IF

AD1D13IF

AD1D12IF

AD1D11IF

AD1D10IF

AD1D9IF

AD1D8IF

AD1D7IF

AD1D6IF

0000

0070

IFS3(6)

31:16

CNKIF

CNJIF

CNHIF

CNGIF

CNFIF

CNEIF

CNDIF

CNCIF

CNBIF

CNAIF

I2C1MIF

I2C1SIF

I2C1BIF

U1TXIF

U1RXIF

U1EIF

0000

15:0

SPI1TXIF

SPI1RXIF

SPI1EIF

—

CRPTIF

SBIF

CFDCIF

CPCIF

AD1D44IF

AD1D43IF

AD1D42IF

AD1D41IF

AD1D40IF

AD1D39IF

AD1D38IF

AD1D37IF

0000

0080

IFS4

31:16

U3TXIF

U3RXIF

U3EIF

SPI3TXIF

SPI3RXIF

SPI3EIF

ETHIF

CAN2IF(3)

CAN1IF(3)

I2C2MIF(2)

I2C2SIF(2)

I2C2BIF(2)

U2TXIF

U2RXIF

U2EIF

SPI2TXIF

0000

15:0

SPI2RXIF

SPI2EIF

DMA7IF

DMA6IF

DMA5IF

DMA4IF

DMA3IF

DMA2IF

DMA1IF

DMA0IF

USBDMAIF

USBIF

CMP2IF

CMP1IF

PMPEIF

PMPIF

0000

0090

IFS5

31:16

—

U6TXIF

U6RXIF

U6EIF

SPI6TX(2)

SPI6RXIF(2)

SPI5IF(2)

I2C5MIF

I2C5SIF

I2C5BIF

U5TXIF

U5RXIF

U5EIF

SPI5TXIF(2)

SPI5RXIF(2)

SPI5EIF(2)

0000

15:0

I2C4MIF

I2C4SIF

I2C4BIF

U4TXIF

U4RXIF

U4EIF

SQI1IF

PREIF

FCEIF

RTCCIF

SPI4TXIF

SPI4RXIF

SPI4EIF

I2C3MIF

I2C3SIF

I2C3BIF

0000

00C0

IEC0

31:16

OC6IE

IC6EIE

T6IE

OC5IE

IC5IE

IC5EIE

T5IE

INT4IE

OC4IE

IC4IE

IC4EIE

T4IE

INT3IE

OC3IE

IC3IE

0000

15:0

IC3EIE

T3IE

INT2IE

OC2IE

IC2IE

IC2EIE

T2IE

INT1IE

OC1IE

IC1IE

IC1EIE

T1IE

INT0IE

CS1IE

CS0IE

CTIE

0000

00D0

IEC1

31:16

AD1D4IE

AD1D3IE

AD1D2IE

AD1D1IE

AD1D0IE

—

AD1DF6IE

AD1DF5IE

AD1DF4IE

AD1DF3IE

AD1DF2IE

AD1DF1IE

AD1DC6IE

AD1DC5IE

AD1DC4IE

AD1DC3IE

0000

15:0

AD1DC2IE

AD1DC1IE

—

AD1IE

OC9IE

IC9IE

IC9EIE

T9IE

OC8IE

IC8IE

IC8EIE

T8IE

OC7IE

IC7IE

IC7EIE

T7IE

0000

00E0

IEC2(5)

31:16

AD1D36IE

AD1D35IE

AD1D34IE

AD1D33IE

AD1D32IE

AD1D31IE

AD1D30IE

AD1D29IE

AD1D28IE

AD1D27IE

AD1D26IE

AD1D25IE

AD1D24IE

AD1D23IE

AD1D22IE

AD1D21IE

0000

15:0

AD1D20IE

AD1D19IE

AD1D18IE

AD1D17IE

AD1D16IE

AD1D15IE

AD1D14IE

AD1D13IE

AD1D12IE

AD1D11IE

AD1D10IE

AD1D9IE

AD1D8IE

AD1D7IE

AD1D6IE

AD1D5IE

0000

00F0

IEC3(6)

31:16

CNKIE

CNJIE

CNHIE

CNGIE

CNFIE

CNEIE

CNDIE

CNCIE

CNBIE

CNAIE

I2C1MIE

I2C1SIE

I2C1BIE

U1TXIE

U1RXIE

U1EIE

0000

15:0

SPI1TXIE

SPI1RXIE

SPI1EIE

—

CRPTIE

SBIE

CFDCIE

CPCIE

AD1D44IE

AD1D43IE

AD1D42IE

AD1D41IE

AD1D40IE

AD1D39IE

AD1D38IE

AD1D37IE

0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Virtual Address(BF31_2)	Register Name(1)	Bit Range	Bits																All Resets
			31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0
0100	IEC4	31:16	U3TXIE	U3RXIE	U3EIE	SPI3TXIE	SPI3RXIE	SPI3EIE	ETHIE	CAN2IE(3)	CAN1IE(3)	I2C2MIE(2)	I2C2SIE(2)	I2C2BIE(2)	U2TXIE	U2RXIE	U2EIE	SPI2TXIE	0000
		15:0	SPI2RXIE	SPI2EIE	DMA7IE	DMA6IE	DMA5IE	DMA4IE	DMA3IE	DMA2IE	DMA1IE	DMA0IE	USBDMAIE	USBIE	CMP2IE	CMP1IE	PMP1IE	PMP1IE	0000
0110	IEC5	31:16	—	U6TXIE	U6RXIE	U6EIE	SPI6TXIE(2)	SPI6RXIE(2)	SPI6IE(2)	I2C5MIE	I2C5SIE	I2C5BIE	U5TXIE	U5RXIE	U5EIE	SPI6TXIE(2)	SPI5RXIE(2)	SPI5EIE(2)	0000
		15:0	I2C4MIE	I2C4SIE	I2C4BIE	U4TXIE	U4RXIE	U4EIE	SQLIE	PREIE	FCEIE	RTCCIE	SPI4TXIE	SPI4RXIE	SPI4EIE	I2C3MIE	I2C3SIE	I2C3BIE	0000
0140	IPC0	31:16	—	—	—	INT0IP<2.0>			INT0IS<1.0>		—	—	—	CS1IP<2.0>			CS1IS<1.0>		0000
		15:0	—	—	—	CS0IP<2.0>			CS0IS<1.0>		—	—	—	CTIP<2.0>			CTIS<1.0>		0000
0150	IPC1	31:16	—	—	—	OC1IP<2.0>			OC1IS<1.0>		—	—	—	IC1IP<2.0>			IC1IS<1.0>		0000
		15:0	—	—	—	IC1EIP<2.0>			IC1IS<1.0>		—	—	—	T1IP<2.0>			T1IS<1.0>		0000
0160	IPC2	31:16	—	—	—	IC2IP<2.0>			IC2IS<1.0>		—	—	—	IC2EIP<2.0>			IC2EIS<1.0>		0000
		15:0	—	—	—	T2IP<2.0>			T2IS<1.0>		—	—	—	INT1IP<2.0>			INT1IS<1.0>		0000
0170	IPC3	31:16	—	—	—	IC3EIP<2.0>			IC3EIS<1.0>		—	—	—	T3IP<2.0>			T3IS<1.0>		0000
		15:0	—	—	—	INT2IP<2.0>			INT2IS<1.0>		—	—	—	OC2IP<2.0>			OC2IS<1.0>		0000
0180	IPC4	31:16	—	—	—	T4IP<2.0>			T4IS<1.0>		—	—	—	INT3IP<2.0>			INT3IS<1.0>		0000
		15:0	—	—	—	OC3IP<2.0>			OC3IS<1.0>		—	—	—	IC3IP<2.0>			IC3IS<1.0>		0000
0190	IPC5	31:16	—	—	—	INT4IP<2.0>			INT4IS<1.0>		—	—	—	OC4IP<2.0>			OC4IS<1.0>		0000
		15:0	—	—	—	IC4IP<2.0>			IC4IS<1.0>		—	—	—	IC4EIP<2.0>			IC4EIS<1.0>		0000
01A0	IPC6	31:16	—	—	—	OC5IP<2.0>			OC5IS<1.0>		—	—	—	IC5IP<2.0>			IC5IS<1.0>		0000
		15:0	—	—	—	IC5EIP<2.0>			IC5EIS<1.0>		—	—	—	T5IP<2.0>			T5IS<1.0>		0000
01B0	IPC7	31:16	—	—	—	OC6IP<2.0>			OC6IS<1.0>		—	—	—	IC6IP<2.0>			IC6IS<1.0>		0000
		15:0	—	—	—	IC6EIP<2.0>			IC6EIS<1.0>		—	—	—	T6IP<2.0>			T6IS<1.0>		0000
01C0	IPC8	31:16	—	—	—	OC7IP<2.0>			OC7IS<1.0>		—	—	—	IC7IP<2.0>			IC7IS<1.0>		0000
		15:0	—	—	—	IC7EIP<2.0>			IC7EIS<1.0>		—	—	—	T7IP<2.0>			T7IS<1.0>		0000
01D0	IPC9	31:16	—	—	—	OC8IP<2.0>			OC8IS<1.0>		—	—	—	IC8IP<2.0>			IC8IS<1.0>		0000
		15:0	—	—	—	IC8EIP<2.0>			IC8EIS<1.0>		—	—	—	T8IP<2.0>			T8IS<1.0>		0000
01E0	IPC10	31:16	—	—	—	OC9IP<2.0>			OC9IS<1.0>		—	—	—	IC9IP<2.0>			IC9IS<1.0>		0000
		15:0	—	—	—	IC9EIP<2.0>			IC9EIS<1.0>		—	—	—	T9IP<2.0>			T9IS<1.0>		0000
01F0	IPC11	31:16	—	—	—	AD1DC2IP<2.0>			AD1DC2IS<1.0>		—	—	—	AD1DC1IP<2.0>			AD1DC1IS<1.0>		0000
		15:0	—	—	—	—	—	—	—	—	—	—	—	AD1IP<2.0>			AD1IS<1.0>		0000
0200	IPC12	31:16	—	—	—	AD1DC6IP<2.0>			AD1DC6IS<1.0>		—	—	—	AD1DC5IP<2.0>			AD1DC5IS<1.0>		0000
		15:0	—	—	—	AD1DC4IP<2.0>			AD1DC4IS<1.0>		—	—	—	AD1DC3IP<2.0>			AD1DC3IS<1.0>		0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Virtual Address(BF61_2)	Register Name(1)	Bit Range	Bits																All Resets
			31/15	30/14	29/13	28/12	27/11	26/10	25/9	24/8	23/7	22/6	21/5	20/4	19/3	18/2	17/1	16/0
0210	IPC13	31:16	—	—	—	AD1DF4IP<2.0>			AD1DF4IS<1.0>		—	—	—	AD1DF3IP<2.0>			AD1DF3IS<1.0>		0000
		15:0	—	—	—	AD1DF2IP<2.0>			AD1DF2IS<1.0>		—	—	—	AD1DF1IP<2.0>			AD1DF1IS<1.0>		0000
0220	IPC14	31:16	—	—	—	AD1D0IP<2.0>			AD1D0IS<1.0>		—	—	—	—	—	—	—	—	0000
		15:0	—	—	—	AD1DF8IP<2.0>			AD1DF8IS<1.0>		—	—	—	AD1DF5IP<2.0>			AD1DF5IS<1.0>		0000
0230	IPC15	31:16	—	—	—	AD1D4IP<2.0>			AD1D4IS<1.0>		—	—	—	AD1D3IP<2.0>			AD1D3IS<1.0>		0000
		15:0	—	—	—	AD1D2IP<2.0>			AD1D2IS<1.0>		—	—	—	AD1D1IP<2.0>			AD1D1IS<1.0>		0000
0240	IPC16	31:16	—	—	—	AD1D8IP<2.0>			AD1D8IS<1.0>		—	—	—	AD1D7IP<2.0>			AD1D7IS<1.0>		0000
		15:0	—	—	—	AD1D6IP<2.0>			AD1D6IS<1.0>		—	—	—	AD1D5IP<2.0>			AD1D5IS<1.0>		0000
0250	IPC17	31:16	—	—	—	AD1D12IP<2.0>			AD1D12IS<1.0>		—	—	—	AD1D11IP<2.0>			AD1D11IS<1.0>		0000
		15:0	—	—	—	AD1D10IP<2.0>			AD1D10IS<1.0>		—	—	—	AD1D9IP<2.0>			AD1D9IS<1.0>		0000
0260	IPC18	31:16	—	—	—	AD1D16IP<2.0>			AD1D16IS<1.0>		—	—	—	AD1D15IP<2.0>			AD1D15IS<1.0>		0000
		15:0	—	—	—	AD1D14IP<2.0>			AD1D14IS<1.0>		—	—	—	AD1D13IP<2.0>			AD1D13IS<1.0>		0000
0270	IPC19	31:16	—	—	AD1D20IP<2.0>			(2)	AD1D20IS<1.0>(2)		—	—	AD1D19IP<2.0>			(2)	AD1D19IS<1.0>(2)		0000
		15:0	—	—	—	AD1D18IP<2.0>			AD1D18IS<1.0>		—	—	—	AD1D17IP<2.0>			AD1D17IS<1.0>		0000
0280	IPC20	31:16	—	—	AD1D24IP<2.0>			(2)	AD1D24IS<1.0>(2)		—	—	AD1D23IP<2.0>			(2)	AD1D23IS<1.0>(2)		0000
		15:0	—	—	AD1D22IP<2.0>			(2)	AD1D22IS<1.0>(2)		—	—	AD1D21IP<2.0>			(2)	AD1D21IS<1.0>(2)		0000
0290	IPC21	31:16	—	—	AD1D28IP<2.0>			(2)	AD1D28IS<1.0>(2)		—	—	AD1D27IP<2.0>			(2)	AD1D27IS<1.0>(2)		0000
		15:0	—	—	AD1D25IP<2.0>			(2)	AD1D26IS<1.0>(2)		—	—	AD1D25IP<2.0>			(2)	AD1D25IS<1.0>(2)		0000
02A0	IPC22	31:16	—	—	AD1D32IP<2.0>			(2)	AD1D32IS<1.0>(2)		—	—	AD1D31IP<2.0>			(2)	AD1D31IS<1.0>(2)		0000
		15:0	—	—	AD1D30IP<2.0>			(2)	AD1D30IS<1.0>(2)		—	—	AD1D29IP<2.0>			(2)	AD1D29IS<1.0>(2)		0000
02B0	IPC23	31:16	—	—	AD1D36IP<2.0>			(2,4)	AD1D36IS<1.0>(2,4)		—	—	AD1D35IP<2.0>			(2,4)	AD1D35IS<1.0>(2,4)		0000
		15:0	—	—	AD1D34IP<2.0>			(2)	AD1D34IS<1.0>(2)		—	—	AD1D33IP<2.0>			(2)	AD1D33IS<1.0>(2)		0000
02C0	IPC24	31:16	—	—	AD1D40IP<2.0>			(2,4)	AD1D40IS<1.0>(2,4)		—	—	AD1D39IP<2.0>			(2,4)	AD1D39IS<1.0>(2,4)		0000
		15:0	—	—	AD1D38IP<2.0>			(2,4)	AD1D38IS<1.0>(2,4)		—	—	AD1D37IP<2.0>			(2,4)	AD1D37IS<1.0>(2,4)		0000
02D0	IPC25	31:16	—	—	—	AD1D44IP<2.0>			AD1D44IS<1.0>		—	—	—	AD1D43IP<2.0>			AD1D43IS<1.0>		0000
		15:0	—	—	AD1D42IP<2.0>			(2,4)	AD1D42IS<1.0>(2,4)		—	—	AD1D41IP<2.0>			(2,4)	AD1D41IS<1.0>(2,4)		0000
02E0	IPC26	31:16	—	—	CRPTIP<2.0>			(7)	CRPTIS<1.0>(7)		—	—	—	SBIP<2.0>			SBIS<1.0>		0000
		15:0	—	—	—	CFDCIP<2.0>			CFDCIS<1.0>		—	—	—	CPCIP<2.0>			CPCIS<1.0>		0000
02F0	IPC27	31:16	—	—	—	SPIITXIP<2.0>			SPIITXIS<1.0>		—	—	—	SPI1RXIP<2.0>			SPI1RXIS<1.0>		0000
		15:0	—	—	—	SPIIIEIP<2.0>			SPIIIEIS<1.0>		—	—	—	—	—	—	—	—	0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: AI registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4* This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31. 30. 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Coprin module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: AI registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 54-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices: bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Registers" for more information.

2: This bit or register is not available on 64-pin devices.

3: This bit or register is not available on devices without a CAN module.

4: This bit as register is not available on 105 pin devices.

This on or register is not available on 100-pin devices.

5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.

6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.

7: This bit or register is not available on devices without a Crypto module.

8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices: bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices: bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR. SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
3: This bit or register is not available on devices without a CAN module.
4: This bit or register is not available on 100-pin devices.
5: Bits 31 and 30 are not available on 64-pin and 100-pin devices: bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29. and bits 5 through 0 are not available on 64-pin and 100-pin devices: bit 31 is not available on 124-pin devices: bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
8: This bit or register is not available on 124-pin devices.

TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV
Registers" for more information.
2: This bit or register is not available on 64-pin devices.
2: This bit or register is not available on devices without a CAN module.
4: This bit as registers is not available on 100-pin devices.
4. This ON OF Register is not available on 100-pin devices. 5. Site 21 and 22 are not available on 24 pins and 100 pins, device 22 through 14 are not available on 26 pins, devices
5: Bits 31 and 36 are not available on 64-pin and 100-pin devices; Bits 29 through 14 are not available on 64-pin devices.
6: Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices.
7: This bit or register is not available on devices without a Crypto module.
B* This bit or register is not available on 124-pin devices

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	— — —	— — —	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— — —	—	—
15:8	U-0	U-0	U-0	R/W-0	U-0	R/W-0	R/W-0	R/W-0
15:8	—	—	—	MVEC	—	TPC<2:0>
7:0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	INT4EP	INT3EP	INT2EP	INT1EP	INT0EP

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-13 Unimplemented: Read as '0'

bit 12 MVEC: Multi Vector Configuration bit

1 = Interrupt controller configured for multi vectored mode
0 = Interrupt controller configured for single vectored mode

bit 11 Unimplemented: Read as '0'

bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits

111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer

bit 7-5 Unimplemented: Read as '0'

bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit

bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit

bit 0 INTOEP: External Interrupt 0 Edge Polarity Control bit

Legend:
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-28 PRI7SS<3:0>: Interrupt with Priority Level 7 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0)

0111 = Interrupt with a priority level of 7 uses Shadow Set 7

0110 = Interrupt with a priority level of 7 uses Shadow Set 6

。

•

0001 = Interrupt with a priority level of 7 uses Shadow Set 1

0000 = Interrupt with a priority level of 7 uses Shadow Set 0

bit 27-24 PRI6SS<3:0>: Interrupt with Priority Level 6 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0)

0111 = Interrupt with a priority level of 6 uses Shadow Set 7

0110 = Interrupt with a priority level of 6 uses Shadow Set 6

广力云智慧零售收银系统

•

0001 = Interrupt with a priority level of 6 uses Shadow Set 1

0000 = Interrupt with a priority level of 6 uses Shadow Set 0

bit 23-20 PRI5SS<3:0>: Interrupt with Priority Level 5 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0)

0111 = Interrupt with a priority level of 5 uses Shadow Set 7

0110 = Interrupt with a priority level of 5 uses Shadow Set 6

0001 = Interrupt with a priority level of 5 uses Shadow Set 1

0000 = Interrupt with a priority level of 5 uses Shadow Set 0

bit 19-16 PRI4SS<3:0>: Interrupt with Priority Level 4 Shadow Set bits ^(1)

1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0)

0111 = Interrupt with a priority level of 4 uses Shadow Set 7

0110 = Interrupt with a priority level of 4 uses Shadow Set 6

0001 = Interrupt with a priority level of 4 uses Shadow Set 1

0000 = Interrupt with a priority level of 4 uses Shadow Set 0

Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)
bit 15-12 PRI3SS<3:0>: Interrupt with Priority Level 3 Shadow Set bits ^(1) 1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0)

0111 = Interrupt with a priority level of 3 uses Shadow Set 7

0110 = Interrupt with a priority level of 3 uses Shadow Set 6

0001 = Interrupt with a priority level of 3 uses Shadow Set 1

0000 = Interrupt with a priority level of 3 uses Shadow Set 0

bit 11-8 PRI2SS<3:0>: Interrupt with Priority Level 2 Shadow Set bits ^(1) 1xxx = Reserved (by default, an interrupt with a priority level of 2 uses Shadow Set 0)

0111 = Interrupt with a priority level of 2 uses Shadow Set 7

0110 = Interrupt with a priority level of 2 uses Shadow Set 6

0001 = Interrupt with a priority level of 2 uses Shadow Set 1

0000 = Interrupt with a priority level of 2 uses Shadow Set 0

bit 7-4 PRI1SS<3:0>: Interrupt with Priority Level 1 Shadow Set bits ^(1) 1xxx = Reserved (by default, an interrupt with a priority level of 1 uses Shadow Set 0)

0111 = Interrupt with a priority level of 1 uses Shadow Set 7

0110 = Interrupt with a priority level of 1 uses Shadow Set 6

0001 = Interrupt with a priority level of 1 uses Shadow Set 1

0000 = Interrupt with a priority level of 1 uses Shadow Set 0

bit 3-1 Unimplemented: Read as '0'

bit 0 SS0: Single Vector Shadow Register Set bit

1 = Single vector is presented with a shadow set

0 = Single vector is not presented with a shadow set

Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— —	—	—	—
23:16	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
23:16	— — —	— —	—	—	—
15:8	U-0 U-0 U-0	U-0 U-0 R-0	R-0 R-0
15:8	—	—	—	—	—	SRIPL<2:0>
7:0	R-0 R-0 R-0	R-0 R-0 R-0	R-0 R-0
7:0	SIRQ<7:0>

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-11 Unimplemented: Read as '0'

bit 10-8 SRIPL<2:0>: Requested Priority Level bits for Single Vector Mode bits

111-000 = The priority level of the latest interrupt presented to the CPU

bit 7-6 Unimplemented: Read as '0'

bit 7-0 SIRQ<7:0>: Last Interrupt Request Serviced Status bits

11111111-00000000 = The last interrupt request number serviced by the CPU

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
31:24	IPTMR<31:24>
23:16	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23:16	IPTMR<23:16>
15:8	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
15:8	IPTMR<15:8>
7:0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	IPTMR<7:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits

Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by an interrupt event.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
31:24	IFS31 IFS	IFS29 IFS	28 IFS27 IFS	26 IFS25 IFS	24
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0	R/W-0
23:16	IFS23 IFS	IFS21 IFS	20 IFS19 IFS	18 IFS17 IFS	16
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	IFS15	IFS14	IFS13	IFS12	IFS11	IFS10	IFS9	IFS8
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	IFS7	IFS6	IFS5	IFS4	IFS3	IFS2	IFS1	IFS0

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-0 IFS31-IFS0: Interrupt Flag Status bits

1 = Interrupt request has occurred
0 = No interrupt request has occurred

Note: This register represents a generic definition of the IFSx register. Refer to Table 7-2 for the exact bit definitions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	IEC31	IEC30	IEC29	IEC28	IEC27	IEC26	IEC25	IEC24
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	IEC23	IEC22	IEC21	IEC20	IEC19	IEC18	IEC17	IEC16
15:8	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
15:8	IEC15	IEC14	IEC13	IEC12	IEC11	IEC10	IEC9	IEC8
7:0	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
7:0	IEC7	IEC6	IEC5	IEC4	IEC3	IEC2	IEC1	IEC0

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-0 IEC31-IEC0: Interrupt Enable bits

1 = Interrupt is enabled
0 = Interrupt is disabled

Note: This register represents a generic definition of the IECx register. Refer to Table 7-2 for the exact bit definitions.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
31:24	— — —	IP3<2:0>		IS3<1:0>
23:16	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
23:16	— — —	IP2<2:0>		IS2<1:0>
15:8	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
15:8	— — —	IP1<2:0>		IS1<1:0>
7:0	U-0 U-0 U-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0
7:0	— — —	IP0<2:0>		ISO<1:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as '0'

bit 28-26 IP3<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 25-24 IS3<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 23-21 Unimplemented: Read as '0'

bit 20-18 IP2<2:0>: Interrupt Priority bits

111 = Interrupt priority is 7

•

010 = Interrupt priority is 2

001 = Interrupt priority is 1

000 = Interrupt is disabled

bit 17-16 IS2<1:0>: Interrupt Subpriority bits

11 = Interrupt subpriority is 3

10 = Interrupt subpriority is 2

01 = Interrupt subpriority is 1

00 = Interrupt subpriority is 0

bit 15-13 Unimplemented: Read as '0'

Note: This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit definitions.

bit 12-10 IP1<2:0>: Interrupt Priority bits
    111 = Interrupt priority is 7
    :
    010 = Interrupt priority is 2
    001 = Interrupt priority is 1
    000 = Interrupt is disabled
bit 9-8 IS1<1:0>: Interrupt Subpriority bits
    11 = Interrupt subpriority is 3
    10 = Interrupt subpriority is 2
    01 = Interrupt subpriority is 1
    00 = Interrupt subpriority is 0
bit 7-5 Unimplemented: Read as '0'
bit 4-2 IP0<2:0>: Interrupt Priority bits
    111 = Interrupt priority is 7
    :
    010 = Interrupt priority is 2
    001 = Interrupt priority is 1
    000 = Interrupt is disabled
bit 1-0 ISO<1:0>: Interrupt Subpriority bits
    11 = Interrupt subpriority is 3
    10 = Interrupt subpriority is 2
    01 = Interrupt subpriority is 1
    00 = Interrupt subpriority is 0

Note: This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit definitions.

Legend:
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 17-1 VOFF<17:1>: Interrupt Vector 'x' Address Offset bits

bit 0 Unimplemented: Read as '0'

8.0 OSCILLATOR CONFIGURATION

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The PIC32MZ EC oscillator system has the following modules and features:

A total of five external and internal oscillator options as clock sources
On-Chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources
On-Chip user-selectable divisor postscaler on select oscillator sources
Software-controllable switching between various clock sources
A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown with dedicated Back-up FRC (BFRC)
• Dedicated On-Chip PLL for USB peripheral
Flexible reference clock output
Multiple clock branches for peripherals for better performance flexibility

A block diagram of the oscillator system is provided in Figure 8-1. Table 8-1 shows the clock distribution.

FIGURE 8-1: PIC32MZ EC FAMILY OSCILLATOR DIAGRAM
Microchip PIC32MZ2048ECH144 - OSCILLATOR CONFIGURATION - 1

flowchart

graph TD
    A["USB PLL"] --> B["UPPLLSELUPLLEN"]
    B --> C["System PLL"]
    C --> D["PLLCLK"]
    D --> E["÷N"]
    E --> F["FIN(6)"]
    F --> G["PLL x M"]
    G --> H["PLL RANGE<2:0>(M)"]
    H --> I["÷N"]
    I --> J["FPLL(6)"]
    J --> K["REFCLKIx"]
    K --> L["POSC"]
    K --> M["FRC"]
    K --> N["LPRC"]
    K --> O["Sosc"]
    K --> P["PBCCLK1"]
    K --> Q["SYSCLK"]
    K --> R["BFRC"]
    L --> S["Reference Clock(5)"]
    M --> T["REFOxCON"]
    M --> U["REFOxTRIM"]
    T --> V["ROTRIM<8:0>(M)"]
    U --> W["OE"]
    V --> X["÷2×(N M/512)"]
    W --> Y["REFCLKOx"]
    X --> Z["RODIV<14:0>(N)"]
    Y --> AA["REFCLKOx"]
    Z --> AB["To SPI, ADC, SQI"]
    AA --> AC["'x' = 1-4'"]
    D --> AD["To USB PLL"]
    AD --> AE["VDD"]
    AE --> AF["XTAL"]
    AF --> AG["1 MΩ"]
    AG --> AH["OSC1"]
    AH --> AI["10 KΩ"]
    AI --> AJ["RF(2)"]
    AJ --> AK["Enable"]
    AK --> AL["OSC2(4)"]
    AL --> AM["Primary Oscillator (Posc)"]
    AM --> AN["To SYSCLK Mux"]
    AN --> AO["SPLL"]
    AO --> AP["SPLL"]
    AP --> AQ["POSC (HS, EC)"]
    AQ --> AR["Peripheral Bus Clock(5)"]
    AR --> AS["Postscaler"]
    AS --> AT["Peripherals, CPU"]
    AT --> AU["PBCCLKx"]
    AU --> AV["'x' = 1-5, 7, 8'"]
    AQ --> AW["SYSCLK"]
    AW --> AX["Fsys(6)"]
    AL --> AY["To ADC and Flash"]
    AL --> AZ["Postscaler ÷ N"]
    AZ --> BA["FRCDIV"]
    BA --> BB["BERC"]
    BB --> BC["LPRC"]
    BC --> BD["LPSCK"]
    BD --> BE["SOSC"]
    BE --> BF["SOSCI"]
    BE --> BG["SOSCEN"]
    BG --> BH["SOSCO"]
    BH --> BI["SOSCI"]
    BI --> BJ["SOSCO"]
    BJ --> BK["SOSCI"]
    BK --> BL["SOSCO"]
    BL --> BM["SOSCI"]
    BM --> BN["SOSCO"]
    BN --> BO["SOSCI"]
    BO --> BP["SOSCO"]
    BP --> BQ["SOSCI"]

Notes: 1. A series resistor, RS, may be required for AT strip cut crystals, or to eliminate clipping. Alternately, to increase oscillator circuit gain, add a parallel resistor, RP.
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
3. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for help in determining the best oscillator components.
4. PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
5. Shaded regions indicate multiple instantiations of a peripheral or feature.
6. Refer to Table 37-19 in Section 37.0 "Electrical Characteristics" for frequency limitations.

TABLE 8-1: SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION

Peripheral

Clock Source

FRC

LPRC

SOSC

SYSCLK

USBCLK

PBCLK1^(1)

PBCLK2

PBCLK3

PBCLK4

PBCLK5

PBCLK7

PBCLK8

REFCLK01

REFCLK02

REFCLK03

CPU X

WDT X X

(2)

Deadman Timer X

(2)

Flash X

(2)

X^(2)

ADC

X X

(3)

Comparator

Crypto

RNG

USB

X^(3)

CAN

Ethernet

X^(3)

PMP

I2C

UART

RTCC

X^(2)

EBI

SQI

X^(3)

SPI

Timers

X^(4)

Output Compare

Input Capture

Ports

DMA

Interrupts

Prefetch

OSC2 Pin

X^(5)

Note 1: PBCLK1 is used by system modules and cannot be turned off.
2: SYSCLK/PBCLK1 is used to fetch data from/to the Flash Controller, while the FRC clock is used for programming.
3: Special Function Register (SFR) access only.
4: Timer1 only.
5: PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.

8.1 Fail-Safe Clock Monitor (FSCM)

The PIC32MZ EC oscillator system includes a Fail-safe Clock Monitor (FSCM). The FSCM monitors the SYSCLK for continuous operation. If it detects that the SYSCLK has failed, it switches the SYSCLK over to the BFRC oscillator and triggers a NMI. The BFRC is an untuned 8 MHz oscillator that will drive the SYSCLK during FSCM event. When the NMI is executed, soft -ware can attempt to restart the main oscillator or shut down the system.

In Sleep mode both the SYSCLK and the FSCM halt, which prevents FSCM detection.

8.2 Oscillator Control Registers

TABLE 8-2: OSCILLATOR CONFIGURATION REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 R/W-0	R/W-0 R/W-0
31:24	— — —	— — FRCD	IV<2:0>
23:16	R/W-0 R-0	U-0 U-0 U-0	U-0	U-0	U-0
23:16	DRMEN	SOSCRDY	—	—	—	—	—	—
15:8	U-0 R-0 R-0	R-0 U-0 R/W-y	R/W-y	R/W-y
15:8	—	COSC<2:0>			—	NOSC<2:0>
7:0	R/W-0	R-0	R-0	R/W-0	R/W-0, HS	U-0	R/W-y	R/W-y
7:0	CLKLOCK	ULOCK	SLOCK	SLPEN	CF	—	SOSCEN	OSWEN^(1)

Legend:	y = Value set from Configuration bits on POR	HS = Hardware Set
R = Readable bit	W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set ‘0’ = Bit is cleared	x = Bit is unknown

bit 31-27 Unimplemented: Read as '0'

bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits

111 = FRC divided by 256

110 = FRC divided by 64

101 = FRC divided by 32

100 = FRC divided by 16

011 = FRC divided by 8

010 = FRC divided by 4

001 = FRC divided by 2

000 = FRC divided by 1 (default setting)

bit 23 DRMEN: Dream Mode Enable bit

1 = Dream mode is enabled

0 = Dream mode is disabled

bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit

1 = Indicates that the Secondary Oscillator is running and is stable

0 = Secondary Oscillator is still warming up or is turned off

bit 21-15 Unimplemented: Read as '0'

bit 14-12 COSC<2:0>: Current Oscillator Selection bits

111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

110 = Back-up Fast RC (BFRC) Oscillator

101 = Internal Low-Power RC (LPRC) Oscillator

100 = Secondary Oscillator (SOSC)

011 = Reserved

010 = Primary Oscillator (Posc) (HS or EC)

001 = System PLL (SPLL)

000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)

bit 11 Unimplemented: Read as '0'

Note 1: The reset value for this bit depends on the setting of the IESO (DEVCFG1<7>) bit. When IESO = 1, the reset value is '1'. When IESO = 0, the reset value is '0'.

Note: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV) 110 = Reserved 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (S osc) 011 = Reserved 010 = Primary Oscillator (P osc) (HS or EC) 001 = System PLL (SPLL) 000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV) On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (DEVCFG1<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified
bit 6 ULOCK: USB PLL Lock Status bit 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled bit 5 SLOCK: System PLL Lock Status bit 1 = System PLL module is in lock or module start-up timer is satisfied 0 = System PLL module is out of lock, start-up timer is running or system PLL is disabled bit 4 SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 Unimplemented: Read as '0' bit 1 SOSCEN: Secondary Oscillator (S osc) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit (1) 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete
Note 1: The reset value for this bit depends on the setting of the IESO (DEVCFG1<7>) bit. When IESO = 1, the reset value is '1'. When IESO = 0, the reset value is '0'.

Note: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
31:24	—— —	—— — — — —
23:16	U-0 R-0 U-0	U-0 U-0	U-0 U-0 U-0
23:16	—— —	—— — — — —
15:8	U-0 R-0 U-0	U-0 U-0	U-0 U-0 U-0
15:8	—— —	—— — — — —
7:0	U-0 U-0 R-0	W-0 R/W-0	R/W-0 R/W-0 R/W-0
7:0	—— TUN<5:0>		(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR '1' = Bit is set '0' = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as '0'
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits ^(1) 100000 = Center frequency -12.5%

100001 =

•

111111 =

000000 = Center frequency; Oscillator runs at minimal frequency (8 MHz)

000001 =

•

011110 =

011111 = Center frequency +12.5%

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized, nor tested.

Note: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 R/W-y	R/W-y R/W-y
31:24	— — —	— — PLLODIV<2:0>
23:16	U-0 R/W-y	R/W-y R/W-y R/W-y	R/W-y R/W-y R/W-y	R/W-y
23:16	— PLLMULT<6:0>
15:8	U-0 U-0 U-0	U-0 U-0 R/W-y	R/W-y R/W-y
15:8	— PLLIDIV<2:0>
7:0	R/W-y U-0	U-0 U-0 R/W-y	R/W-y R/W-y
7:0	PLLICLK —	— — — PLLRANGE<2:0>

Legend: y = Value set from Configuration bits on POR
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-27 Unimplemented: Read as '0'

bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits

111 = Reserved

110 = Reserved

101 = PLL Divide by 32

100 = PLL Divide by 16

011 = PLL Divide by 8

010 = PLL Divide by 4

001 = PLL Divide by 2

000 = Reserved

The default setting is specified by the FPLLODIV<2:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

bit 23 Unimplemented: Read as '0'

bit 22-16 PLLMULT<6:0>: System PLL Multiplier bits

1111111 = Multiply by 128

1111110 = Multiply by 127

1111101 = Multiply by 126

1111100 = Multiply by 125

•

0000000 = Multiply by 1

The default setting is specified by the FPLLMULT<6:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

bit 15-11 Unimplemented: Read as '0'

Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.

2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0>=001).

REGISTER 8-3: SPLLCON: SYSTEM PLL CONTROL REGISTER

bit 10-8 PLLIDIV<2:0>: System PLL Input Clock Divider bits

111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1

The default setting is specified by the FPLLIDIV<2:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information. If the PLLICLK bit is set for FRC, this setting is ignored by the PLL and the divider is set for Divide-by-1.

bit 7 PLLICLK: System PLL Input Clock Source bit

1 = FRC is selected as the input to the System PLL
0 = Posc is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

bit 6-3 Unimplemented: Read as '0'

bit 2-0 PLLRANGE<2:0>: System PLL Frequency Range Selection bits

111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass

The default setting is specified by the FPLL RNG<2:0> Configuration bits in the DEVCFG2 register. Refer to Register 34-5 in Section 34.0 "Special Features" for information.

Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details.

2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0>=001).

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	— RODIV<14:8>
23:16	R/W-0 R/W-0	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
23:16	RODIV<7:0>
15:8	R/W-0 U-0	R/W-0 R/W-0	R/W-0 U-0 R/W-0, HC	R-0, HS, HC
15:8	ON(1)	—	SIDL	OE	RSLP^(2)	—	DIVSWEN	ACTIVE(1)
7:0	U-0	U-0	U-0	U-0	R/W-0	R/W-0	R/W-0	R/W-0
7:0	—	—	—	—	ROSEL<3:0>^(3)

Legend:	HC = Hardware Clearable	HS = Hardware Settable
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared x = Bit is unknown

bit 31 Unimplemented: Read as '0'

bit 30-16 RODIV<14:0> Reference Clock Divider bits

The value selects the reference clock divider bits (see Figure 8-1 for details). A value of '0' selects no divider.

bit 15 ON: Output Enable bit ^(1)

1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled

bit 14 Unimplemented: Read as '0'

bit 13 SIDL: Peripheral Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode

bit 12 OE: Reference Clock Output Enable bit

1 = Reference clock is driven out on REFCLKOx pin
0 = Reference clock is not driven out on REFCLKOx pin

bit 11 RSLP: Reference Oscillator Module Run in Sleep bit ^(2)

1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep

bit 10 Unimplemented: Read as '0'

bit 9 DIVSWEN: Divider Switch Enable bit

1 = Divider switch is in progress
0 = Divider switch is complete

bit 8 ACTIVE: Reference Clock Request Status bit ^(1)

1 = Reference clock request is active
0 = Reference clock request is not active

bit 7-4 Unimplemented: Read as '0'

bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits ^(3)

1111 = Reserved

•

1001 = BFRC
1000 = REFCLKIx
0111 = System PLL output
0110 = Reserved
0101 = SOSC
0100 = LPRC
0011 = FRC
0010 = Posc
0001 = PBCLK1
0000 = SYSCLK

Note 1: Do not write to this register when the ON bit is not equal to the ACTIVE bit.

2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.

3: The ROSEL<3:0> bits should not be written while the ACTIVE bit is '1', as undefined behavior may result.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0 R/W-0 R/W-0	R/W-0
31:24	ROTRIM<8:1>
23:16	R/W-0 R-0 U-0	U-0 U-0 U-0 U-0	U-0 U-0
23:16	ROTRIM<0>	— — — — —	— —
15:8	U-0 R-0 U-0	U-0 U-0 U-0	U-0 U-0
15:8	— — —	— — — — —
7:0	U-0 U-0 U-0	U-0 U-0 U-0	U-0 U-0
7:0	— — —	— — — — —

Legend:	y = Value set from Configuration bits on POR
R = Readable bit	W = Writable bit	U = Unimplemented bit, read as ‘0’
-n = Value at POR	‘1’ = Bit is set	‘0’ = Bit is cleared	x = Bit is unknown

bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits

111111111 = 511/512 divisor added to RODIV value

111111110 = 510/512 divisor added to RODIV value

•

100000000 = 256/512 divisor added to RODIV value

•

000000010 = 2/512 divisor added to RODIV value

000000001 = 1/512 divisor added to RODIV value

000000000 = 0 divisor added to RODIV value

bit 22-0 Unimplemented: Read as '0'

Note 1: While the ON bit (REFOxCON<15>) is '1', writes to this register do not take effect until the DIVSWEN bit is also set to '1'.
2: Do not write to this register when the ON bit (REFOxCON<15>) is not equal to the ACTIVE bit (REFOxCON<8>).
3: Specified values in this register do not take effect if RODIV<14:0> (REFOxCON<30:16>) = 0.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
31:24	— — —	— — — —
23:16	U-0 U-0 U-0	U-0 U-0 U-0 U-0	U-0
23:16	— — —	— — — —
15:8	R/W-1 U-0 U-0	U-0 R-1 U-0	U-0 U-0
15:8	ON(1)	— — —	PBDIVRDY		— — —
7:0	U-0	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x	R/W-x
7:0	—	PBDIV<6:0>

Legend:

R = Readable bit	W = Writable bit	U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as '0'

bit 15 ON: Peripheral Bus 'x' Output Clock Enable bit ^(1)

1 = Output clock is enabled
0 = Output clock is disabled

bit 14-12 Unimplemented: Read as '0'

bit 11 PBDIVRDY: Peripheral Bus 'x' Clock Divisor Ready bit

1 = Clock divisor logic is not switching divisors and the PBxDIV<6:0> bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV<6:0> bits cannot be written

bit 10-7 Unimplemented: Read as '0'

bit 6-0 PBDIV<6:0>: Peripheral Bus 'x' Clock Divisor Control bits

1111111 = PBCLKx is SYSCLK divided by 128
1111110 = PBCLKx is SYSCLK divided by 127

•
•
•

0000011 = PBCLKx is SYSCLK divided by 4

0000010 = PBCLKx is SYSCLK divided by 3
0000001 = PBCLKx is SYSCLK divided by 2 (default value for x ≠ 7)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x = 7)

Note 1: The clock for peripheral bus 1 cannot be turned off. Therefore, the ON bit in the PB1DIV register cannot be written as a '0'.

Note: Writes to this register require an unlock sequence. Refer to Section 42. "Oscillators with Enhanced PLL" (DS60001250) in the "PIC32 Family Reference Manual" for details.

9.0 PREFETCH MODULE

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 41. "Prefetch Module for Devices with L1 CPU Cache" (DS60001183), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Prefetch module is a performance enhancing module that is included in PIC32MZ EC family devices. When running at high-clock rates, Wait states must be inserted into Program Flash Memory (PFM) read transactions to meet the access time of the PFM. Wait states can be hidden to the core by prefetching and storing instructions in a temporary holding area that the CPU can access quickly. Although the data path to the CPU is 32 bits wide, the data path to the PFM is 128 bits wide. This wide data path provides the same bandwidth to the CPU as a 32-bit path running at four times the frequency.

The Prefetch module holds a subset of PFM in temporary holding spaces known as lines. Each line contains a tag and data field. Normally, the lines hold a copy of what is currently in memory to make instructions or data available to the CPU without Flash Wait states.

9.1 Features

4x16 byte fully-associative lines
• One line for CPU instructions
• One line for CPU data
Two lines for peripheral data
• 16-byte parallel memory fetch
Configurable predictive prefetch
Error detection and correction

A simplified block diagram of the Prefetch module is shown in Figure 9-1.

FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM
Microchip PIC32MZ2048ECH144 - Features - 1

flowchart

graph TD
    CPU["CPU"] --> BusControl["Bus Control"]
    BusControl --> PrefetchBuffer["Prefetch Buffer"]
    BusControl --> LineControl["Line Control"]
    BusControl --> ProgramFlashMemory["Program Flash Memory (PFM)"]
    BusControl --> SYSCLK["SYSCLK"]
    BusControl --> Tag["Tag"]
    BusControl --> Data["Data"]
    BusControl --> CPU2["CPU"]
    BusControl --> Data2["Data"]
    BusControl --> Data3["Data"]
    BusControl --> Data4["Data"]
    BusControl --> Data5["Data"]
    BusControl --> Data6["Data"]
    BusControl --> Data7["Data"]
    BusControl --> Data8["Data"]
    BusControl --> Data9["Data"]
    BusControl --> Data10["Data"]
    BusControl --> Data11["Data"]
    BusControl --> Data12["Data"]
    BusControl --> Data13["Data"]
    BusControl --> Data14["Data"]
    BusControl --> Data15["Data"]
    BusControl --> Data16["Data"]
    BusControl --> Data17["Data"]
    BusControl --> Data18["Data"]
    BusControl --> Data19["Data"]
    BusControl --> Data20["Data"]
    BusControl --> Data21["Data"]
    BusControl --> Data22["Data"]
    BusControl --> Data23["Data"]
    BusControl --> Data24["Data"]
    BusControl --> Data25["Data"]
    BusControl --> Data26["Data"]
    BusControl --> Data27["Data"]
    BusControl --> Data28["Data"]
    BusControl --> Data29["Data"]
    BusControl --> Data30["Data"]
    BusControl --> Data31["Data"]
    BusControl --> Data32["Data"]
    BusControl --> Data33["Data"]
    BusControl --> Data34["Data"]
    BusControl --> Data35["Data"]
    BusControl --> Data36["Data"]
    BusControl --> Data37["Data"]
    BusControl --> Data38["Data"]
    BusControl --> Data39["Data"]
    BusControl --> Data40["Data"]
    BusControl --> Data41["Data"]
    BusControl --> Data42["Data"]
    BusControl --> Data43["Data"]
    BusControl --> Data44["Data"]
    BusControl --> Data45["Data"]
    BusControl --> Data46["Data"]
    BusControl --> Data47["Data"]
    BusControl --> Data48["Data"]
    BusControl --> Data49["Data"]
    BusControl --> Data50["Data"]
    BusControl --> Data51["Data"]
    BusControl --> Data52["Data"]
    BusControl --> Data53["Data"]
    BusControl --> Data54["Data"]
    BusControl --> Data55["Data"]
    BusControl --> Data56["Data"]
    BusControl --> Data57["Data"]
    BusControl --> Data58["Data"]
    BusControl --> Data59["Data"]
    BusControl --> Data60["Data"]
    BusControl --> Data61["Data"]
    BusControl --> Data62["Data"]
    BusControl --> Data63["Data"]
    BusControl --> Data64["Data"]
    BusControl --> Data65["Data"]
    BusControl --> Data66["Data"]
    BusControl --> Data67["Data"]
    BusControl --> Data68["Data"]
    BusControl --> Data69["Data"]
    BusControl --> Data70["Data"]
    BusControl --> Data71["Data"]
    BusControl --> Data72["Data"]
    BusControl --> Data73["Data"]
    BusControl --> Data74["Data"]
    BusControl --> Data75["Data"]
    BusControl --> Data76["Data"]
    BusControl --> Data77["Data"]
    BusControl --> Data78["Data"]
    BusControl --> Data79["Data"]
    BusControl --> Data80["Data"]
    BusControl --> Data81["Data"]
    BusControl --> Data82["Data"]
    BusControl --> Data83["Data"]
    BusControl --> Data84["Data"]
    BusControl --> Data85["Data"]
    BusControl --> Data86["Data"]
    BusControl --> Data87["Data"]
    BusControl --> Data88["Data"]
    BusControl --> Data89["Data"]
    BusControl --> Data90["Data"]
    BusControl --> Data91["Data"]
    BusControl --> Data92["Data"]
    BusControl --> Data93["Data"]
    BusControl --> Data94["Data"]
    BusControl --> Data95["Data"]
    BusControl --> Data96["Data"]
    BusControl --> Data97["Data"]
    BusControl --> Data98["Data"]
    BusControl --> Data99["Data"]

9.2 Prefetch Control Registers

TABLE 9-1: PREFETCH REGISTER MAP

Legend: x = unknown value on Reset, — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

Bit Range	Bit31/23/15/7	Bit30/22/14/6	Bit29/21/13/5	Bit28/20/12/4	Bit27/19/11/3	Bit26/18/10/2	Bit25/17/9/1	Bit24/16/8/0
31:24	U-0 U-0	U-0 U-0 U-0 R/W	U-0					U-0
31:24	— — —	— — PFMSECEN	—	—
23:16	U-0 U-0	U-0 U-0 U-0	U-0	U-0	U-0
23:16	— — —	— —	—	—	—
15:8	U-0 U-0	U-0 U-0 U-0	U-0	U-0	U-0
15:8	— — —	— —	—	—	—
7:0	U-0	U-0	R/W-0	R/W-0	U-0	R/W-1	R/W-1	R/W-1
7:0	—	—	PREFEN<1:0>		—	PFMWS<2:0>(1)

Legend:

R = Readable bit	W = Writable bit U = Unimplemented bit, read as '0'
-n = Value at POR	'1' = Bit is set	'0' = Bit is cleared	x = Bit is unknown

bit 31-27 Unimplemented: Read as '0'

bit 26 PFMSECEN: Flash SEC Interrupt Enable bit

1 = Generate an interrupt when the PFMSEC bit (PRESTAT<26>) is set

0 = Do not generate an interrupt when the PFMSEC bit is set

bit 25-6 Unimplemented: Read as '0'

bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits

11 = Enable predictive prefetch for any address

10 = Enable predictive prefetch for CPU instructions and CPU data

01 = Enable predictive prefetch for CPU instructions only

00 = Disable predictive prefetch

bit 3 Unimplemented: Read as '0'

bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSCLK Wait States bits ^(1)

111 = Seven Wait states

•

010 = Two Wait states

001 = One Wait state

000 = Zero Wait states

Note 1: For the Wait states to SYSCLK relationship, refer to Table 37-13 in Section37.0 “Electrical Characteristics”.

Bit Range	Bit 31/23/15/7	Bit 30/22/14/6	Bit 29/21/13/5	Bit 28/20/12/4	Bit 27/19/11/3	Bit 26/18/10/2	Bit 25/17/9/1	Bit 24/16/8/0
31:24	U-0 U-0	U-0 U-0			R/W-0, HS	R/W-0, HS	U-0	U-0
31:24	— — —	— PFMDED	PFMSEC —	—
23:16	U-0 U-0	U-0 U-0	U-0 U-0	U-0 U-0
23:16	— — —	— — — —	—
15:8	U-0 U-0	U-0 U-0	U-0 U-0	U-0 U-0
15:8	— — —	— — — —	—
7:0	R/W-0 R/W	R/W-0	R/W-0	R/W-0 R/W-0	R/W-0 R/W-0
7:0	PFMSECCNT<7:0>

Legend: HS = Hardware Set

R = Readable bit W = Writable bit U = Unimplemented bit, read as '0'

-n = Value at POR

'1' = Bit is set

'0' = Bit is cleared

x = Bit is unknown

bit 31-28 Unimplemented: Read as '0'

bit 27 PFMDED: Flash Double-bit Error Detected (DED) Status bit

This bit is set in hardware and can only be cleared (i.e., set to '0') in software.

1 = A DED error has occurred

0 = A DED error has not occurred

bit 26 PFMSEC: Flash Single-bit Error Corrected (SEC) Status bit

1 = A SEC error occurred when PFMSECCNT<7:0> was equal to '0'

0 = A SEC error has not occurred

bit 25-8 Unimplemented: Read as '0'

bit 7-0 PFMSECCNT<7:0>: Flash SEC Count bits

11111111 - 00000000 = SEC count

This field decrements by one each time an SEC error occurs. It will hold at zero on the two-hundred and fifty-sixth error. When an SEC error occurs, when PFMSECCNT = 0, the PFMSEC status bit is set. If PFMSECEN is also set, an interrupt is generated.

Note: These bits count all SEC errors and are not limited to SEC errors on unique addresses.

10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER

Note: This data sheet summarizes the features of the PIC32MZ Embedded Connectivity (EC) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS60001117), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32).

The Direct Memory Access (DMA) Controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the device such as SPI, UART, PMP, etc., or memory itself.

Note: To avoid cache coherency problems on devices with L1 cache, DMA buffers must only be allocated or accessed from the KSEG1 segment.

Following are some of the key features of the DMA Controller module:

• Eight identical channels, each featuring:
- Auto-increment source and destination address registers
- Source and destination pointers
- Memory to memory and memory to peripheral transfers

• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and destination
• Fixed priority channel arbitration
- Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA requests
- One-Shot or Auto-Repeat Block Transfer modes
- Channel-to-channel chaining

- Flexible DMA requests:

A DMA request can be selected from any of the peripheral interrupt sources
Each channel can select any (appropriate) observable interrupt as its DMA request source
A DMA transfer abort can be selected from any of the peripheral interrupt sources
Up to 2-byte Pattern (data) match transfer termination

- Multiple DMA channel status interrupts:

- DMA channel block transfer complete

- Source empty or half empty

- Destination full or half full

- DMA transfer aborted due to an external event

- Invalid DMA address generated

• DMA debug support features:

Most recent error address accessed by a DMA channel
Most recent DMA channel to transfer data

• CRC Generation module:

- CRC module can be assigned to any of the available channels

- CRC module is highly configurable

FIGURE 10-1: DMA BLOCK DIAGRAM
Microchip PIC32MZ2048ECH144 - DIRECT MEMORY ACCESS (DMA) CONTROLLER - 1

flowchart

graph TD
    A["INT Controller"] --> B["System IRQ"]
    B --> C["Address Decoder"]
    C --> D["Channel 0 Control"]
    C --> E["Channel 1 Control"]
    C --> F["Channel n Control"]
    D --> G["SEL"]
    E --> H["I0"]
    F --> I["I1"]
    G --> J["SEL"]
    H --> K["Bus Interface"]
    I --> K
    K --> L["System Bus + Bus Arbitration"]
    M["Peripheral Bus"] --> C
    N["Global Control (DMACON)"] --> C
    O["Channel Priority Arbitration"] --> K
    P["SysCLK"] --> Q["DMA"]
    Q --> R["System Bus + Bus Arbitration"]

10.1 DMA Control Registers

TABLE 10-1: DMA GLOBAL REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-2: DMA CRC REGISTER MAP

Virtual Address(BF81_#)

Bit Range

Bits

All Resets

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

1030

DCRCCON

31:16

—

BYTEO<1:0>

WBO

—

BITO

—

0000

15:0

—

PLEN<4:0>

CRCEN

CRCAPP

CRCTYP

—

CRCCH<2:0>

0000

1040

DCRCDATA

31:16

DCRCDATA<31:0>

0000

15:0

0000

1050

DCRCXOR

31:16

DCRCXOR<31:0>

0000

15:0

0000

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registlers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP

Legend: x = unknown value on Reset; — = unimplemented, read as '0'. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 "CLR, SET, and INV Registers" for more information.

TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)