X7DWA-N - Motherboard Supermicro - Free user manual and instructions

USER MANUAL X7DWA-N Supermicro

The information in this User's Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note: For the most up-to-date version of this manual, please see our web site at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product described in this manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any medium or machine without prior written consent.

IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC. SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the manufacturer's instruction manual, may cause interference with radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, you are encouraged to try to correct the interference by one or more of the following measures:

Reorient or relocate the receiving antenna.

Increase the separation between the equipment and the receiver.

Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

Consult the dealer or an experienced radio/television technician for help.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. "Perchlorate Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate".

WARNING: Handling of lead solder materials used in this product may expose you to lead, a chemical known to the State of California to cause birth defects and other reproductive harm.

Manual Revision 1.1c

Release Date: July 29, 2009

Unless you request and receive written permission from Super Micro Computer, Inc., you may not copy any part of this document.

Information in this document is subject to change without notice. Other products and companies referred to herein are trademarks or registered trademarks of their respective companies or mark holders.

Copyright © 2009 by Super Micro Computer, Inc.

All rights reserved.

Printed in the United States of America

Preface

About This Manual

This manual is written for system integrators, PC technician knowledgeable PC users. It provides information for the installation and use of the SUPERX7DWA-N motherboard. The SUPERX7DWA-N supports dual Intel® Quad-Core and Dual-Core Xeon™ 5400/5300/5200/5100 Series processors with a front side bus speed of 1.6 GHz/1.333 GHz/1.066 GHz. With two Xeon™ 5400/5300/5200/5100 Series processors built in, the X7DWA-N offers superior performance, system reliability, and power efficiency for high-end workstation platforms. The features supported by this motherboard include Intel Core Microarchitecture, Intel Virtualization Technology, Intel Extended Memory 64 Technology (EM64), and Intel I/O Acceleration Technology (Intel I/OAT). The X7DWA-N offers a superb solution for intense computing and complex I/O environments, and is ideal for high-end workstations. Please refer to the motherboard specifications page on our web site (http://www.supermicro.com/Product/) for updates on processor support. This product is intended to be installed and serviced by professional technicians only.

Manual Organization

Chapter 1 describes features, specifications and performance of the motherboard and provides detailed information about the chipset.

Chapter 2 provides hardware installation instructions. Read this chapter when installing the processor, memory modules and other hardware components into the system. If you encounter any problems, see Chapter 3, which describes troubleshooting procedures for video, memory and system setup stored in CMOS.

Chapter 4 includes an introduction to BIOS and provides detailed information on running the CMOS Setup utility.

Appendix A provides BIOS Error Beep Codes. Appendix B and Appendix C list Windows OS and Other Software Programs Installation Instructions.

Conventions Used in the Manual:

Special attention should be given to the following symbols for proper installation and to prevent damage done to the components or injury to yourself:

Danger/Caution: Instructions to be strictly followed to prevent catastrophic system failure or to avoid bodily injury.

Warning: Important information given to ensure proper system installation or to prevent damage done to the components.

Note: Additional Information given to ensure correct system setup.

Table of Contents

Preface

About This Manual .... iii

Manual Organization .... iii

Conventions Used in the Manual ....iii

Chapter 1: Introduction

1-1 Overview 1-1

Checklist 1-1

Contacting Supermicro 1-2

SUPER●X7DWA-N Image 1-3

SUPER●X7DWA-N Layout 1-4

Quick Reference 1-5

Motherboard Features 1-6

Intel 5400 Chipset: System Block Diagram 1-8

1-2 Chipset Overview 1-9

1--3 Special Features 1-10

1-4 PC Health Monitoring 1-10

1-5 ACPI Features 1-11

1-6 Power Supply 1-12

1-7 Super I/O 1-12

Chapter 2: Installation

2-1 Static-Sensitive Devices 2-1

Precautions 2-1

Unpacking 2-1

2-2 Motherboard Installation 2-1

2-3 Processor and Heatsink Installation 2-2

2-4 Installing DIMM Modules 2-6

2-5 Control Panel Connectors and IO Ports 2-8

Back Panel Connectors/IO Ports....2-8

Front Control Panel 2-9

Front Control Panel Pin Definitions 2-10

NMI Button 2-10

Power LED 2-10

HDD LED 2-11

NIC1/NIC2 LED Indicators 2-11

Overheat/Fan Fail LED 2-12

Power Fail LED 2-12

Reset Button 2-13

Power Button 2-13

2-6 Connecting Cables 2-14

ATX Power Connector 2-14

Processor Power Connector 2-14

Universal Serial Bus (USB) 2-15

Chassis Intrusion 2-15

Fan Headers 2-16

ATX PS/2 Keyboard and Mouse Ports 2-17

Serial Ports 2-17

Wake-On-Ring 2-18

Wake-On-LAN 2-18

GLAN 1/2 (Ethernet) Ports 2-19

Speaker/Power LED Header 2-19

Power Fault 2-20

Overheat/Fan Fail LED 2-20

Alarm Reset 2-21

Power SMB Connector 2-21

Compact Flash Card PWR Connector 2-22

SGPIO Headers 2-22

HD Audio 2-23

CD Header 2-23

Front Panel Audio Control 2-24

1394-1/1394-2 Connections 2-25

2-7 Jumper Settings 2-26

Explanation of Jumpers 2-26

GLAN Enable/Disable 2-26

CMOS Clear 2-27

Watch Dog 2-27

3rd PWR Supply PWR Fault 2-28

SMB to PCI-X/PCI-E Slot Speeds 2-28

Compact Flash Master/Slave Enable/Disable 2-29

2-8 Onboard Indicators 2-30

GLAN LEDs 2-30

Overheat LED 2-31

Onboard Power LED 2-31

2-9 Parallel Port, Floppy, SIMLP IPMI and Hard Disk Drive Connections ..... 2-32

Parallel Port Connector 2-32

Floppy Connector.... 2-33

IPMI Slot 2-34

PCI-U Universal Slot 2-34

IDE Connectors 2-35

Chapter 3: Troubleshooting

3-1 Troubleshooting Procedures 3-1

Before Power On 3-1

No Power 3-1

No Video 3-1

Losing the System's Setup Configuration 3-2

Memory Errors 3-2

3-2 Technical Support Procedures 3-2

3-3 Frequently Asked Questions 3-3

3-4 Returning Merchandise for Service 3-4

Chapter 4: BIOS

4-1 Introduction.... 4-1

4-2 Running Setup 4-2

4-3 Main BIOS Setup 4-2

4-4 Advanced Setup 4-6

4-5 Security Setup 4-24

4-6 Boot Setup....4-25

4-7 Exit....4-26

Appendices:

Appendix A: BIOS POST Error Beep Codes ......A-1

Appendix B: Installing the Windows OS ......B-1

Appendix C: Installing Other Software Programs and Drivers ......C-1

Chapter 1

Introduction

1-1 Overview

Checklist

Congratulations on purchasing your computer motherboard from an acknowledged leader in the industry. Supermicro boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance. Check that the following items have all been included with your motherboard. If anything listed here is damaged or missing, contact your retailer.

All the following items are included in the retail box:

One (1) Supermicro Mainboard

One (1) ribbon cable for IDE devices (CBL-036L)

One (1) fl oppy ribbon cable (CBL-022L)

Six (6) SATA cable (CBL-044L x 6)

One (1) I/O backpanel shield (MCP-260-74301-OH)

One (1) Supermicro CD containing drivers and utilities

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information) [e-mail] (Technical Support)

Web Site: www.supermicro.com

Europe

Email: [e-mail] (General Information) [e-mail] (Technical Support) [e-mail] (Customer Support)

Asia-Pacific

Address: Super Micro Computer, Inc. 4F, No. 232-1 Liancheng Road Chung-Ho 235, Taipei Hsien, Taiwan, R.O.C.

Tel: [phone]

Fax: [phone]

Web Site: www.supermicro.com.tw

Technical Support:

Email: [e-mail]

Tel: [phone], ext.132 or 139

SX7DWA-N Image

Close-up of a green computer motherboard with multiple CPU and RAM slots (no visible text or labels)

Note: The drawings and pictures shown in this manual were based on the latest PCB Revision available at the time of publishing of the manual. The motherboard you've received may or may not look exactly the same as the graphics shown in the manual.

SX70WA-N Motherboard Layout

(not drawn to scale)

Circuit board layout diagram with labeled components including CPU, memory, and power modules

Notes:

1. Jumpers not indicated are for test purposes only.
2. See Chapter 2 for detailed information on jumpers, I/O ports and JF1 front panel connections.
3. "■" indicates the location of Pin 1.
4. JIDE2 is for Compact Flash Card use only. Be sure to connect JWF1 to a power supply to provide power to the Compact Flash Card.
5. Slot 0 (PCI-U) slot is specially designed for Supermicro's UIO cards only.

Quick Reference (X7DWA-N)
Jumper Description Default Setting

J3P	3rd PWR Failure Detect	Off (Disabled)
JBT1	CMOS Clear	See Chapter 2
JCF1	Compact Card Master/Slave Select	Off (Slave)
JI ^2 C1/JI ^2 C2	SMB to PCI-X Slots	Pins 1-2 (Enabled)
JI ^2 C3/JI ^2 C4	SMB to PCI-E Slots	Pins 1-2 (Enabled)
JPL1	GLAN1/GLAN2 Enable	Pins 1-2 (Enabled)
JWD	Watch Dog	Pins 1-2 (Reset)

Connector Description

1394-1/1394-2	1394-1/1394-2 Fire-Wire Connectors
CD1	CD-In Header
COM1/COM2	BP COM1 Port/FP Accessible COM2 Serial Connector
FAN 1-8	Fans 1-8 (Fan7: CPU Fan1, Fan8: CPU Fan2)
Floppy	Floppy Disk Drive Connector (J22)
HD Audio/FP Audio	Backplane HD Audio (JC1), Front Panel Audio (JC2)
IDE1/IDE2	IDE1 Hard Drive (JIDE1)/Compact Flash Card (JIDE2)
I-SATA0~SATA5	Intel SATA Connectors
J17	Power System Management (I ^2C ) Header
J29,J30	Serial General Purpose I/O Headers (T-SGPIO 1/2)
JAR	Alarm Reset Header
JD1	PWR LED(pins1-3)/Speaker Header (pins 4-7)
JF1	Front Control Panel Connector
JL1	Chassis Intrusion Header
JOH1	Overheat LED
JPW1	Primary 24-Pin ATX PWR Connector (Req'd for MB)
JPW2	+12V 4-pin PWR (Required for South Bridge, North Bridge & VRMs)
JPW3	+12V 8-pin PWR (Required for processors)
JPW4	+12V/+5V 4-pin PWR (Additional PWR supply for PCI-E slots, used if needed)
JWF1	Compact Card PWR Connector (Note 5 on Pg.1-4)
JWOL	Wake-on-LAN Header
JWOR	Wake-on-Ring Header
KB/MS	PS2 Keyboard/Mouse (JKM1)
LAN1	G-bit Ethernet Ports (JLAN1)
LE1	PWR LED Indicator (Note 4 on Pg.1-4)
PSF	Power Supply Failure (JP3)
Printer	Parallel (Printer) Port (J21)
SIMLP	SIMLP IPMI Connector (Slot 7: J16)
Slot 0	PCI-U Slot (J31)
USB 0/1/2/3	Back Panel USB 0/1/2/3 (JUSB1)
USB 4/5	Front Panel USB4/5 (JUSB2)

Motherboard Features

CPU

- Dual Inte64-bit Xeon LGA 771 Quad-Core/Dual-Core Xeon 5400/5300/5200/5100 Series processors at a front side bus speed of 1.6 GHz/1.333 GHz/1.066 GHz

Memory

- Eight 240-pin DIMM sockets with support up to 64 GB ECC DDR2 FBD 800/667/533 Memory (See Section 2-3 in Chapter 2 for DIMM Slot Population.)

Chipset

- Intel 5400 chipset, including: the 5400 Memory Control Hub (MCH) and the Enterprise South Bridge 2 (ESB2)

Expansion Slots

• Two PCI-E x16 (Gen. 2) slots (Slot 4/Slot 6)
  • Two PCI-X 133/100 MHz Slot (Slot 1/Slot 2)
• Two PCI-33 MHz (3.3 V) slots (Slot 3/Slot 5)
  • One IPMI slot (Slot 7)
  • One PCI-U slot (Slot 0) (For Supermicro's UIO card only)

BIOS

• 8 Mb Phoenix ^® Flash ROM
• DMI 2.3, PCI 2.2, ACPI 1.0, Plug and Play (PnP) and SMBIOS 2.3

PC Health Monitoring

• Onboard voltage monitors for CPU cores, chipset voltage, memory voltage, +1.8V, +3.3V, +5V, +12V, -12V, 3.3V standby, 5V standby and VBAT
  • Fan status monitor with firmware speed on/off control
  • CPU/chassis temperature monitors
• Platform Environment Control Interface (PECI)
  • CPU slow-down on temperature overheat
  • CPU thermal trip support for processor protection
  • Power-up mode control for recovery from AC power loss
  • Auto-switching voltage regulator for CPU core
  • System overheat LED and control
• Chassis intrusion detection

- System resource alert

ACPI Features

- Slow blinking LED for suspend state indicator

- Main switch override mechanism

Onboard I/O

• Adaptec Host RAID support (RAID 0, RAID1, RAID 10)
• One IPMI slot
  • Intel 82575EB Gigabit Ethernet controllers support two GLAN ports w/IOAT
  • 2 EIDE Ultra DMA/100 bus master interfaces w/Compact Flash supported
• 6 SATA ports (w/RAID0, RAID1, RAID5, RAID 10 support for Windows OS)
  • 1 fl oppy port interface
  • 1 Serial Port and 1 Header
  • 1 EPP/ECP Parallel Port
  • High Definition Audio and Front Panel Accessible Audio
  • Super I/O: Winbond W83627HF w/Hardware Monitor support: W83793
  • PS/2 mouse and PS/2 keyboard ports
• Up to 6 USB 2.0 (Universal Serial Bus) (4 ports, 2 Headers)
  • Dual IEEE 1394a headers

Other

• External modem ring-on
- Wake-on-LAN (WOL)
- Wake-on-Ring (WOR)
- Console redirection
- Onboard Fan Speed Control by Thermal Management via BIOS

CD/Diskette Utilities

• BIOS f1 ash upgrade utility and device drivers

Dimensions

- Ext. ATX 13" x 12" (330.2 mmx 304.8 mm)

graph TD
    A["VRM ISL6307"] <--> B["PROCESSOR#2"]
    C["PROCESSOR#1"] <--> D["PROCESSOR#1"]
    B <--> E["MCH"]
    D <--> E
    E --> F["Port #1,2,3,4"]
    E --> G["Port #5,6,7,8"]
    E --> H["Port #9"]
    E --> I["Port ESI"]
    F --> J["PCI-E x16"]
    G --> K["PCI-E x16"]
    H --> L["PCI-E x4"]
    I --> M["PCI-E x4"]
    J <--> N["GB LAN"]
    K <--> N
    L <--> N
    M <--> N
    N --> O["Port #0"]
    N --> P["Port #4"]
    N --> Q["Port #3"]
    O --> R["ESB2"]
    P --> R
    Q --> R
    R --> S["PCI-E x8 Bus"]
    R --> T["PCI-E x8"]
    R --> U["PCI-X 133MHz"]
    R --> V["PCI-X 133MHz Slot"]
    R --> W["PCI-X 133/100MHz Slot"]
    R --> X["PCI-X 133/100MHz Slot"]
    R --> Y["PCI-X 133/100MHz Slot"]
    R --> Z["PCI-X 133/100MHz Slot"]
    R --> AA["PCI-X 133/100MHz Slot"]
    R --> AB["PCI-X 133/100MHz Slot"]
    R --> AC["PCI-X 133/100MHz Slot"]
    R --> AD["PCI-X 133/100MHz Slot"]
    R --> AE["PCI-X 133/100MHz Slot"]
    R --> AF["PCI-X 133/100MHz Slot"]
    R --> AG["PCI-X 133/100MHz Slot"]
    R --> AH["PCI-X 133/100MHz Slot"]
    R --> AI["PCI-X 133/100MHz Slot"]
    R --> AJ["PCI-X 133/100MHz Slot"]
    R --> AK["PCI-X 133/100MHz Slot"]
    R --> AL["PCI-X 133/100MHz Slot"]
    R --> AM["PCI-X 133/100MHz Slot"]
    R --> AN["PCI-X 133/100MHz Slot"]
    R --> AO["PCI-X 133/100MHz Slot"]
    R --> AP["PCI-X 133/100MHz Slot"]
    R --> AQ["PCI-X 133/100MHz Slot"]
    R --> AR["PCI-X 133/100MHz Slot"]
    R --> AS["PCI-X 133/100MHz Slot"]
    R --> AT["PCI-X 133/100MHz Slot"]
    R --> AU["PCI-X 133/100MHz Slot"]
    R --> AV["PCI-X 133/100MHz Slot"]
    R --> AW["PCI-X 133/100MHz Slot"]
    R --> AX["PCI-X 133/100MHz Slot"]
    R --> AY["PCI-X 133/100MHz Slot"]
    R --> AZ["PCI-X 133/100MHz Slot"]
    R --> BA["PCI-X 133/100MHz Slot"]
    R --> BB["PCI-X 133/100MHz Slot"]
    R --> BC["PCI-X 133/100MHz Slot"]
    R --> BD["PCI-X 133/100MHz Slot"]
    R --> BE["PCI-X 133/100MHz Slot"]
    R --> BF["PCI-X 133/100MHz Slot"]
    R --> BG["PCI-X 133/100MHz Slot"]
    R --> BH["PCI-X 133/100MHz Slot"]
    R --> BI["PCI-X 133/100MHz Slot"]
    R --> BJ["PCI-X 133/100MHz Slot"]
    R --> BK["PCI-X 133/100MHz Slot"]
    R --> BL["PCI-X 133/100MHz Slot"]
    R --> BM["PCI-X 133/100MHz Slot"]
    R --> BN["PCI-X 133/100MHz Slot"]
    R --> BO["PCI-X 133/100MHz Slot"]
    R --> BP["PCI-X 133/100MHz Slot"]
    R --> BQ["PCI-X 133/100MHz Slot"]
    R --> BR["PCI-X 133/100MHz Slot"]
    R --> BS["PCI-X 133/100MHz Slot"]
    R --> BT["PCI-X 133/100MHz Slot"]
    R --> BU["PCI-X 133/100MHz Slot"]
    R --> BV["PCI-X 133/100MHz Slot"]
    R --> BW["PCI-X 133/100MHz Slot"]
    R --> BX["PCI-X 133/100MHz Slot"]
    R --> BY["PCI-X 133/100MHz Slot"]
    R --> BZ["PCI-X 133/100MHz Slot"]
    R --> CA["PCI-X 133/100MHz Slot"]
    R --> CB["PCI-X 133/100MHz Slot"]
    R --> CC["PCI-X 133/100MHz Slot"]
    R --> CD["PCI-X 133/100MHz Slot"]
    R --> CE["PCI-X 133/100MHz Slot"]
    R --> CF["PCI-X 133/100MHz Slot"]
    R --> CG["PCI-X 133/100MHz Slot"]
    R --> CH["PCI-X 133/100MHz Slot"]
    R --> CI["PCI-X 133/100MHz Slot"]
    R --> CJ["PCI-X 133/100MHz Slot"]
    R --> CK["PCI-X 133/100MHz Slot"]
    R --> CL["PCI-X 133/100MHz Slot"]
    R --> CM["PCI-X 133/100MHz Slot"]
    R --> CN["PCI-X 133/100MHz Slot"]
    R --> CO["PCI-X 133/100MHz Slot"]
    R --> CP["PCI-X 133/100MHz Slot"]
    R --> CS["PCI-X 133/100MHz Slot"]
    R --> CT["PCI-X 133/100MHz Slot"]
    R --> CU["PCI-X 133/100MHz Slot"]
    R --> CV["PCI-X 133/100MHz Slot"]
    R --> CW["PCI-X 133/100MHz Slot"]
    R --> CX["PCI-X 133/100MHz Slot"]
    R --> CY["PCI-X 133/100MHz Slot"]
    R --> CZ["PCI-X 133/100MHz Slot"]
    R --> DA["PCI-X 133/100MHz Slot"]
    R --> DB["PCI-X 133/100MHz Slot"]
    R --> DC["PCI-X 133/100MHz Slot"]
    R --> DD["PCI-X 133/100MHz Slot"]
    R --> DE["PCI-X 133/100MHz Slot"]
    R --> DF["PCI-X 133/100MHz Slot"]
    R --> DG["PCI-X 133/100MHz Slot"]

Block Diagram of the 5400 Chipset
Note: This is a general block diagram. Please see the previous Motherboard Features pages for details on the features of the motherboard.

1-2 Chipset Overview

Built upon the functionality and the capability of the 5400 chipset, the X7DWA-N motherboard provides the performance and feature set required for quad-core-processor- or dual-core-processor-based high-end workstations with configuration options optimized for complex system platforms. The 5400 chipset supports single or dual Intel Quad-Core/Dual-Core Xeon 5400/5300/5200/5100 Series processors with front side bus speeds of up to 1.6 GHz. The chipset consists of the 5400 Memory Controller Hub (MCH) for the host bridge and the 631xESB/632xESB I/O Controller Hub (Enterprise South Bridge 2-ESB2) for the I/O subsystem.

The Intel 5400 MCH (North Bridge)

The 5400 MCH (North Bridge) provides two FSB processing interfaces, four fully buffered (FBD) DIMM memory channels, PCI-Express x4 bus interfaces configurable to form x8 or x16 ports, an EB2 South Bridge Interface (ESI) and SMBus Interfaces for system management, and DIMM Serial Presence Detect (SPD). The PCI-Express x4 interfaces can be configured to form x8 or x16 ports that can operate up to Gen-2 speeds in x16 configuration for enhanced graphics applications.

The Intel 631xESB/632x ESB I/O Controller Hub-ESB2 (South Bridge)

The 631xESB/632xESB I/O Controller Hub (Enterprise South Bridge 2) integrates an Ultra ATA 100 Controller, six Serial ATA host controller ports, one EHCI host controller, six USB 2.0 ports, an LPC interface controller, and a flash BIOS interface controller. Additionally, the ESB 2 chip also contains a PCI interface controller, Azalia/'97 digital controller, integrated LAN controller, an ASF controller, and an ESI for communication with the MCH. The Intel ESB2 offers the data buffering and interface arbitration capabilities required for a high-end system to constantly operate efficiently and maintain peak performance.

Compliant with the ACPI platform, the ESB2 supports the Full-On, Stop-Grant, Suspend-to-RAM, Suspend-to-Disk, and Soft-Off power management states. Combined with the functionality offered by the onboard LAN controller, the ESB2 also supports alert systems for remote management.

With the 5400 chipset built in, the X7DWA-N offers a superb solution for intense computing and complex I/O environments, and is ideal for high-end server systems.

1-3 Special Features

Recovery from AC Power Loss

BIOS provides a setting for you to determine how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must hit the power switch to turn it back on) or for it to automatically return to a power-on state. See the Power Lost Control setting in the Advanced BIOS Setup section to change the setting. The default setting is Last State.

1-4 PC Health Monitoring

This section describes the PC health monitoring features of the X7DWA-N. All have an onboard System Hardware Monitor chip that supports PC health monitoring.

Onboard Voltage Monitors for the CPU Cores, Chipset Voltage, Memory Voltage, +1.8V, +3.3V, +5V, +12V, -12V, +3.3V Standby, +5V Standby and Vbat

An onboard voltage monitor will scan these voltages continuously. Once a voltage becomes unstable, a warning is given or an error message is sent to the screen.

Fan Status Monitor with Firmware Control

The PC health monitor can check the RPM status of the cooling fans. The onboard CPU and chassis fans are controlled by Thermal Management via BIOS (under Hardware Monitoring in the Advanced Setting).

Environmental Temperature Control

The thermal control sensor monitors the CPU temperature in real time and will increase fan speed whenever the CPU temperature reaches a user-defined threshold. The onboard chassis thermal circuitry can monitor the overall system temperature and alert users when the chassis temperature is too high.

CPU Fan Auto-Off in Sleep Mode

When the power is turned on, the CPU fan becomes active. It stops to operate when the system enters Standby mode. When in sleep mode, the CPU will not run at full power, thereby generating less heat.

System Resource Alert

This feature is available when used with Supero Doctor III in the Windows OS environment or used with Supero Doctor II in Linux. Supero Doctor is used to notify the user of certain system events. For example, if the system is running

low on virtual memory and there is insufficient hard drive space for saving the data, you can be alerted of the potential problem. You can also configure Supero Doctor to provide you with warnings when the system temperature goes beyond a pre-defined range.

1-5 ACPI Features

ACPI stands for Advanced Configuration and Power Interface. The ACPI specification defines a flexible and abstract hardware interface that provides a standard to integrate power management features throughout a PC system, including its hardware, operating system and application software. This enables the system to automatically turn on and off peripherals such as CD-ROMs, network cards, hard disk drives and printers. This also includes consumer devices connected to the PC such as VCRs, TVs, telephones and stereos.

In addition to enabling operating system-directed power management, ACPI provides a generic system event mechanism for Plug and Play and an operating-system-independent interface for configuration control. ACPI leverages the Plug and Play BIOS data structures while providing a processor architecture-independent implementation that is compatible with Windows 2000, Windows XP, Windows 2003, Windows 2003 Servers and Windows Vista.

Slow Blinking LED for Suspend-State Indicator

When the CPU goes into a suspend state, the chassis power LED will start blinking to indicate that the CPU is in suspend mode. When the CPU is in the S1 mode, the Power LED blinks every second. When in the S3 mode, the Power LED will blink every 5-second. When the user presses any key, the CPU will wake-up and the LED will automatically stop blinking and remain on.

Main Switch Override Mechanism

When an ATX power supply is used, the power button can function as a system suspend button to make the system enter SoftOff state. The monitor will be suspended and the hard drive will spin down. Pressing the power button again will cause the whole system to wake-up. During the SoftOff state, the ATX power supply provides power to keep the required circuitry in the system alive. In case the system malfunctions and you want to turn off the power, just press and hold power button for 4 seconds. This option can be set in the Advanced Setup section of the BIOS Setup routine.

External Modem Ring-On

Wake-up events can be triggered by a device such as the external modem ringing when the system is in the SoftOff state. Note that external modem ring-on can only be used with an ATX 2.01 (or above) compliant power supply.

Wake-On-LAN (WOL)

Wake-On-LAN is defined as the ability of a management application to remotely power up a computer that is powered off. Remote PC setup, up-dates and asset tracking can occur after hours and on weekends so that daily LAN traffic is kept to a minimum and users are not interrupted. The motherboard has a 3-pin header (WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has WOL capability. In addition, an onboard LAN controller can also support WOL without any connection to the WOL header. The 3-pin WOL header is to be used with a LAN add-on card only.

Note: Wake-On-LAN requires an ATX 2.01 (or above) compliant power supply.

1-6 Power Supply

As with all computer products, a stable power source is necessary for proper and reliable operation. It is even more important for processors that have high CPU clock rates.

The X7DWA-N can only accommodate 24-pin ATX power supplies. Although most power supplies generally meet the specifications required by the CPU, some are inadequate. You should use one that will supply at least 500W of power. In addition, the 12V 4-pin power and the 12V 8-pin are also required for adequate power supply to the system. Also your power supply must supply 1.5A for the Ethernet ports.

It is strongly recommended that you use a high quality power supply that meets ATX power supply Specification 2.01 or above. It must also be SSI compliant (Refer to the web site at http://www.ssiforum.org/ for more information). Additionally, in areas where noisy power transmission is present, you may choose to install a line filter to shield the computer from noise. It is recommended that you also install a power surge protector to help avoid problems caused by power surges.

1-7 Super I/O

The disk drive adapter functions of the Super I/O chip include a floppy disk drive controller that is compatible with industry standard 82077/765, a data separator, write pre-compensation circuitry, decode logic, data rate selection, a clock generator, drive interface control logic and interrupt and DMA logic. The wide range of functions integrated onto the Super I/O greatly reduces the number of components required for interfacing with floppy disk drives. The Super I/O supports 360 K, 720 K, 1.2 M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s, 500 Kb/s or 1 Mb/s. It also provides two high-speed, 16550 compatible serial communication ports (UARTs). Each UART includes a 16-byte send/receive FIFO. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps as well as

an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which support higher speed modems.

The Super I/O supports one PC-compatible printer port (SPP), Bi-directional Printer Port (BPP), Enhanced Parallel Port (EPP) or Extended Capabilities Port (ECP).

The Super I/O provides functions that comply with ACPI (Advanced Configuration and Power Interface), which includes support of legacy and ACPI power management through an SMI or SCI function pin. It also features auto power management to reduce power consumption.

Notes

Chapter 2

Installation

2-1 Static-Sensitive Devices

Electrostatic Discharge (ESD) can damage electronic components. To prevent damage to your system board, it is important to handle it very carefully. The following procedures are generally sufficient to protect your equipment from ESD.

Precautions

• Use a grounded wrist strap designed to prevent static discharge.
• Touch a grounded metal object before removing the board from the antistatic bag.
• Handle the board by its edges only; do not touch its components, peripheral chips, memory modules or gold contacts.
• When handling chips or modules, avoid touching their pins.
• Put the motherboard and peripherals back into their antistatic bags when not in use.
• For grounding purposes, make sure your computer chassis provides excellent conductivity between the power supply, the case, the mounting fasteners and the motherboard.
• Use only the correct type of onboard CMOS battery as specified by the manufacturer. Do not install the onboard battery upside down to avoid possible explosion.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage. When unpacking the board, make sure the person handling it is static protected.

2-2 Motherboard Installation

Note: Be sure to mount the motherboard into the chassis before you install the CPU onto the motherboard.

All motherboards have standard mounting holes to fit different types of chassis. Make sure that the locations of all the mounting holes for both motherboard and chassis match. Make sure that the metal standoffs click in or are screwed in tightly. Then, use a screwdriver to secure the motherboard onto the motherboard tray.

Note: some components are very close to the mounting holes. Please take precautionary measures to prevent damage to these components when installing the motherboard to the chassis.

2-3 Processor and Heatsink Installation

When handling the processor package, avoid placing direct pressure on the label area of the fan.

Notes:

Always connect the power cord last and always remove it before adding, 1. removing or changing any hardware components. Make sure that you install the processor into the CPU socket before you install the CPU heatsink.

Intel's boxed Xeon CPU package contains the CPU fan and heatsink assem-2. bly. If you buy a CPU separately, make sure that you use only Intel-certified multi-directional heatsink and fan.

When purchasing an LGA 771 CPU or when receiving a motherboard with an 3. LGA 771 CPU pre-installed, make sure that the CPU plastic cap is in place and none of the CPU pins are bent; otherwise, contact the retailer immediately.

Refer to the MB Features Section for more details on CPU support.4.

CPU Package Configuration

soni1 duration Heatsink CPU

CPU Socket Motherboard

CPU Retention Bracket (Pre-installed on the Back of the MB)

Installing the LGA771 Processor

Press the load lever to release 1. the load plate, which covers the CPU socket, from its locking position.

Load Lever PnP Cap or top of the Load Plate

Close-up of a green circuit board with a black integrated chip and surrounding components (no visible text or symbols)

Close-up of a hand pressing down on a green printed circuit board with electronic components (no visible text or symbols)

Close-up of a hand inserting a component into a green circuit board (no visible text or symbols)

Gently lift the load lever to open 2. the load plate.

Load Plate(w/PnP Cap attached)

Close-up of a green circuit board with an open microchip and surrounding components (no visible text or symbols)

Use your thumb and your index 3. finger to hold the CPU at the North Center Edge and the South Center Edge of the CPU.

North Center Edge

South Center Edge

Loading the CPU into the Socket

Align CPU Pin1 (the CPU corner 1. marked with a triangle) against the socket corner that is marked with a triangle cutout.

Align the CPU key that is the 2. semi-circle cutout below a gold dot against the socket key, the notch on the same side of the triangle cutout on the socket.

Once aligned, carefully lower the 3. CPU straight down to the socket. (Do not drop the CPU on the socket. Do not move the CPU horizontally or vertically. Do not rub the CPU against the surface or any pins of the socket.)

With the CPU inside the socket, 4. inspect the four corners of the CPU and make sure it is properly installed.

Use your thumb to gently push 5. the load lever down to the lever lock.

If the CPU is properly installed 6. into the socket, the plastic PnP cap will be automatically released from the load plate when the load lever is pushed in the lever lock. Remove the PnP cap from the motherboard.

Warning: Please save the plastic PnP cap. The motherboard must be shipped with the cap properly installed to protect the CPU socket pins. Shipment without the PnP cap properly installed will cause damage to the socket pins.

Socket Key (Socket Notch)

CPU Key (semi-circle cutout) below the circle.

Corner with a triangle cutout

gold dot

Close-up of a green CPU socket with visible traces and soldering (no text or symbols)

CPU Pin1

Close-up of a green printed circuit board with a central processor and surrounding components (no visible text or symbols)

CPU in the CPU socket

Load Lever

Close-up of a hand holding a microchip on a green circuit board (no visible text or symbols)

Plastic cap is released from the load plate if CPU properly installed.

Close-up of a green printed circuit board with visible components and connectors (no text or symbols)

Installation and Removal of the Heatsink

Do not apply any thermal grease to the 1. heatsink or the CPU die-the required amount has already been applied.

Place the heatsink on top of the CPU 2. so that the four mounting holes are aligned with those on the retention mechanism.

Screw in two diagonal screws (ie the 3. #1 and the #2 screws) until just snug (- do not over tighten the screws to avoid possible damage to the CPU.)

Finish the installation by fully tighten-4. ing all four screws.

CEK Passive Heatsink

Close-up of a metallic electronic component with internal structure (no visible text or symbols)

Screw#1 Screw#2

Illustration of a hand holding a rack with a curved handle (no text or symbols visible)

Screw#1

Pure barcode pattern with vertical stripes and corner markers (no text or symbols)

Screw#2

To Remove the Heatsink

Warning: We do not recommend that the CPU or the heatsink be removed. However, if you do need to uninstall the heatsink, please follow the instructions below to uninstall the heatsink to prevent damage done to the CPU or the CPU socket.

Unscrew and remove the heatsink screws 1. from the motherboard in the sequence as show in the picture on the right.

Hold the heatsink as shown in the pic-2.
ture on the right and gently wriggle the heatsink to loosen it from the CPU. (Do not use excessive force when wriggling the heatsink!!)

Once the CPU is loosened, remove the 3. heatsink from the CPU socket.

Clean the surface of the CPU and the 4. heatsink to get rid of the old thermal grease. Reapply the proper amount of thermal grease on the surface before you re-install the CPU and the heatsink.

NO.1 SCREW NO.4 SCREW NO.3 SCREW NO.2 SCREW

Illustration of a hand holding a rack-mounted cooling unit (no text or symbols visible)

2-4 Installing DIMMs

Note: Check the Supermicro web site for recommended memory modules.

CAUTION

Exercise extreme care when installing or removing DIMM modules to prevent any possible damage. Also Note that the memory is interleaved to improve performance (see step 1).

DIMM Installation (See Figure 2-2)

1. Insert the desired number of DIMMs into the memory slots, starting with Bank 1. (Refer to the Memory Configuration Table below for more details.)
2. Insert each DIMM module vertically into its slot. Pay attention to the notch along the bottom of the module to prevent inserting the DIMM module incorrectly.
3. Gently press down on the DIMM module until it snaps into place in the slot. Repeat for all modules (see step 1 above).

Memory Support

The X7DWA-N supports up to 64 GB fully buffered (FBD) ECC DDR2 800/667/533 in 8 DIMMs. Populating DIMM modules with a pair (or pairs) of memory modules of the same type and same size will result in interleaved memory. For best performance, please install (a) pair(s) of DIMM modules of the same type in both Branch 0 and Branch 1.

Memory Configuration Table
	Branch0 Branch1
Number of DIMMs	Bank 1 (Channel 0)		Bank 2 (Channel 1)		Bank 3 (Channel 2)		Bank 4 (Channel 3)
2 DIMMs 1A	---- 2A	----	----	----
4 DIMMs 1A	---- 2A	---- 3A	---- 4A	----
6 DIMMs 1A	1B 2A 2B	3A ---- 4A	----
8 DIMMs 1A	1B 2A 2B	3A 3B 4A	4B
(*Notes: i. DIMM slot# specified: DIMM slot to be populated; “---”: DIMM slot not to be populated. ii. FBD 533 MHz, 667MHz and 800 MHz DIMMs are supported; however, we recommend that you use the memory modules of the same speed and of the same type on a motherboard. iii. For memory to work properly, you need to follow the restrictions listed above.)

Note 1: Different types of memory modules are supported by processors with different front side bus speeds. Refer to the Memory Support Table below.

DIMM Modules Supported by CPUs
CPU DIMM	FSB: 1600 MHz	FSB: 1333 MHz	FSB: 1066 MHz
800 MHz	Supported	Supported (Note2)	Supported (Note2)
667 MHz	Supported	Supported	Supported
533 MHz	Not Supported	Supported	Supported

Note 2: DDR2 FBD 800 MHz memory is supported by the processors with FSB 1333 MHz and 1066 MHz; however, it will run @667 MHz.

Note 3: Due to the OS limitations, some operating systems may not show more than 4 GB of memory.

Note 4: Due to memory allocation to system devices, memory remaining available for operational use will be reduced when 4 GB of RAM is used. The reduction in memory availability is disproportional. Refer to the Memory Availability Table below for details.

Possible System Memory Allocation & Availability
System Device Size Physical Memory		Remaining (-Available)(4 GB Total System Memory)
Firmware Hub i ash memory (System BIOS) 1 MB 3.99
Local APIC 4 KB 3.99
Area Reserved for the chipset 2 MB 3.99
I/O APIC (4 Kbytes) 4 KB 3.99
PCI Enumeration Area 1 256 MB 3.76
PCI Express (256 MB) 256 MB 3.51
PCI Enumeration Area 2 (if needed) -Aligned on 256-MB boundary-	512 MB 3.01
VGA Memory 16 MB 2.85
TSEG	1 MB 2.84
Memory available to OS and other applications		2.84

Installing and Removing DIMMs

graph TD
    A["SuperX70WA-N"] --> B["DDR2 FBD DIMM"]
    B --> C["Release Tab"]
    C --> D["Note: Notch should align with the receptive point on the slot"]
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#fcc,stroke:#333

To Install: Insert module vertically and press down until it snaps into place. Pay attention to the alignment notch at the bottom.

To Remove:

Use your thumbs to gently push the release tabs near both ends of the module. This should release it from the slot.

Top View of DDR2 FBD Slot Release Tab Release Tab

2-5 Control Panel Connectors/IO Ports

The I/O ports are color coded in conformance with the PC 99 specification. See Figure 2-3 below for the colors and locations of the various I/O ports.

Back Panel Connectors/IO Ports

SUPER® X7DWA-N ① ② ③ ④ ⑤ ⑥ ⑦ ⑧ ⑨ ⑩ ⑪ ⑫ ⑬ ⑭ ⑮ ⑯ ⑰ ⑱ ⑲ ⑳ ㉑ ㉒ ㉓ ㉔ ㉕ ㉖ ㉗ ㉘ ㉙ ㉚ ㉛ ㉜ ㉝ ㉞ ㉟ ㉳ ㉴ ㉵ ㉶ ㉇ ㉈ ㉒ ㉓ ㉔ ㉕ ㉖ ㉗ ㉘ ㉙ ㉚ ㉛ ㉜ ㉝ ㉞ ㉟ ㉟a ㊱

Back Panel I/O Port Locations and Definitions

Back Panel Connectors

1. Keyboard (Purple)
2. PS/2 Mouse (Green)
3. Back Panel USB Port 0
4. Back Panel USB Port 1
5. Back Panel USB Port 2
6. Back Panel USB Port 3
7. COM Port 1 (Turquoise)
8. Parallel Port (Printer)
9. Gigabit LAN 2
10. Gigabit LAN 1
11. Side_Surround (Grey)
12. Back_Surround (Black)
13. CEN/LFE (Orange)
14. Microphone-In (Pink)
15. Front (Green)
16. Line-In (Blue)
    (See Section 2-5 for details.)

Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally located on a control panel at the front of the chassis. These connectors are designed specifically for use with Supermicro server chassis. See Figure 2-4 for the descriptions of the various control panel buttons and LED indicators. Refer to the following section for descriptions and pin definitions.

JF1 Header Pins

SUPER•X7DWA-N Ground X Power LED HDD LED NIC1 LED NIC2 LED OH/Fan Fail LED PWR Fail LED Ground Ground 20 19 NMI X Vcc Vcc Vcc Vcc Vcc Vcc Reset Reset Button PWR Power Button 2 1

Front Control Panel Pin Definitions

NMI Button

The non-maskable interrupt button header is located on pins 19 and 20 of JF1. Refer to the table on the right for pin definitions.

NMI ButtonPin Definitions (JF1)
Pin#	Definition
19	Control
20	Ground

Power LED

The Power LED connection is located on pins 15 and 16 of JF1. Refer to the table on the right for pin definitions.

Power LEDPin Definitions (JF1)
Pin#	Definition
15	+3.3V
16	Ground

A. NMI B. PWR LED KBU Mouse USB 6:1/23 COMI Parallel Port LAN12 HD Audio SUPERO X7DWA-N GLAN CTLR PCI-1 PCI-3MHz PCI-Exp x18 PCI-32 MHz PCI-X 130-100 MHz JWDO PCI-X 130-100 MHz FP Audio SINO C5-U IPNR 1394.1 1394.2 USB4.5 MHz CPU1 CPU2 CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU CPU Power LED HDD LED NIC1 LED NIC2 LED OH/Fan Fail LED PWR Fail LED Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground

HDD LED

The HDD LED connection is located on pins 13 and 14 of JF1. Attach the hard drive LED cable here to display disk activity (for any hard drives on the system, including Serial ATA and IDE). See the table on the right for pin definitions.

HDD LEDPin Defi nitions (JF1)
Pin#	Defi nition
13 +5V
14 HD	Active

NIC1/NIC2 LED Indicators

The NIC (Network Interface Controller) LED connection for GLAN port1 is located on pins 11 and 12 of JF1 and the LED connection for GLAN Port2 is on Pins 9 and 10. Attach the NIC LED cables to display network activity. Refer to the table on the right for pin definitions.

GLAN1/2 LEDPin Defi nitions (JF1)
Pin#	Defi nition
9/11 Voc
10/12 Ground

A. HDD LED B. NIC1 LED C. NIC2 LED USB 0: 1/2/3 COM1 Parallel Port LAM1/2 HD Audio SUPER X7DWA-N SIu7 IFM GLAM CTLR SDD8 PCI-Exp x16 SCL1 PCI-39MHz SDD8 PCI-Exp x16 JUD0 PCI 33 MHz SDD2 PCI-X 133-100 MHz JUD0E SIC1 PCI-X 133-100 MHz FP Audio SUI0 PCI-U IPNR 190A-1139A-2 USGAS HOD CPU1 CPU2 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 CPU12 CPU13 CPU14 CPU15 CPU16 CPU17 CPU18 CPU19 CPU20 CPU21 CPU22 CPU23 CPU24 CPU25 CPU26 CPU27 CPU28 CPU29 CPU30 CPU31 CPU32 CPU33 CPU34 CPU35 CPU36 CPU37 CPU38 CPU39 CPU40 CPU41 CPU42 CPU43 CPU44 CPU45 CPU46 CPU47 CPU48 CPU49 CPU50 CPU51 CPU52 CPU53 CPU54 CPU55 CPU56 CPU57 CPU58 CPU59 CPU60 CPU61 CPU62 CPU63 CPU64 CPU65 CPU66 CPU67 CPU68 CPU69 CPU70 CPU71 CPU72 CPU73 CPU74 CPU75 CPU76 CPU77 CPU78 CPU79 CPU80 CPU81 CPU82 CPU83 CPU84 CPU85 CPU86 CPU87 CPU88 CPU89 CPU90 CPU91 CPU92 CPU93 CPU94 CPU95 CPU96 CPU97 CPU98 CPU99 CPU100 Ground 20 19 NMI Power LED A HDD LED B NIC1 LED C NIC2 LED OH/Fan Fail LED PWR Fail LED Ground Reset Power Button Ground 2 1 PWR

Overheat/Fan Fail LED (OH)

Connect an LED to the OH/Fan Fail connection on pins 7 and 8 of JF1 to provide advanced warnings of chassis overheating or fan failure. Refer to the table on the right for pin definitions.

OH/Fan Fail LEDPin Defi nitions (JF1)
Pin#	Defi nition
7 Vcc
8 Ground

OH/Fan Fail Indicator Status
State	Definition
Off Normal
On Overheat
Flashing	Fan Fail

Power Fail LED

The Power Fail LED connection is located on pins 5 and 6 of JF1. Refer to the table on the right for pin definitions.

PWR Fail LEDPin Definitions (JF1)
Pin#	Definition
5 Vcc
6 Ground

A. OH/Fan Fail LED

B. PWR Supply Fail

CPU1 CPU2 SIP SIP Power LED HDD LED NIC1 LED NIC2 LED OH/Fan Fail LED PWR Fail LED Ground Ground Ground 20 19 NMI X Vcc Vcc Vcc Vcc Vcc Reset Reset Button PWR Power Button 2 1 Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground GND1 1304-1 1304-2 USB/4 ExoQI SATA1 SATA3 SATA5 DATA4 DATA7 DATA8 JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCOM JCONJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOjAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOJAMOjAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIAAIBMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMOMMCMo jamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjummcmo jamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamon jamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjamomjummcmo jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon njuo mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio mio miao jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawnjiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiawn jiowmcmo jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon jhamon iunmcmo jhamon iunmcmo jhamon iunmcmo jhamon iunmcmo jhamosmco o f t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e g t h e f o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o l o r o n i a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u a s u c i n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a n i a t i v i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i n i ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ini ink 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

Reset Button

The Reset Button connection is located on pins 3 and 4 of JF1. Attach it to the hardware reset switch on the computer case. Refer to the table on the right for pin definitions.

Reset ButtonPin Defi nitions (JF1)
Pin#	Defi nition
3 Reset
4 Ground

Power Button

The Power Button connection is located on pins 1 and 2 of JF1. Momentarily contacting both pins will power on/off the system. This button can also be configured to function as a suspend button (with a setting in the BIOS - see Chapter 4). To turn off the power when set to suspend mode, press the button for at least seconds or longer. Refer to the table on the right for pin definitions.

Power ButtonPin Defi nitions (JF1)
Pin#	Defi nition
1 Signal
2 +3V	Standby

A. Reset Button B. PWR Button 20 19 Ground X Power LED HDD LED NIC1 LED NIC2 LED OH/Fan Fail LED PWR Fail LED Ground Ground Reset Reset Button Power Button 2 1 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7 CPU8 CPU9 CPU10 CPU11 CPU12 CPU13 CPU14 CPU15 CPU16 CPU17 CPU18 CPU19 CPU20 CPU21 CPU22 CPU23 CPU24 CPU25 CPU26 CPU27 CPU28 CPU29 CPU30 CPU31 CPU32 CPU33 CPU34 CPU35 CPU36 CPU37 CPU38 CPU39 CPU40 CPU41 CPU42 CPU43 CPU44 CPU45 CPU46 CPU47 CPU48 CPU49 CPU50 CPU51 CPU52 CPU53 CPU54 CPU55 CPU56 CPU57 CPU58 CPU59 CPU60 CPU61 CPU62 CPU63 CPU64 CPU65 CPU66 CPU67 CPU68 CPU69 CPU70 CPU71 CPU72 CPU73 CPU74 CPU75 CPU76 CPU77 CPU78 CPU79 CPU80 CPU81 CPU82 CPU83 CPU84 CPU85 CPU86 CPU87 CPU88 CPU89 CPU90 CPU91 CPU92 CPU93 CPU94 CPU95 CPU96 CPU97 CPU98 CPU99 CPU100

2-6 Connecting Cables

ATX Main PWR & CPU PWR Connectors

The 24-pin main power connector (JPW1) is used to provide power to the motherboard. The 8-pin CPU PWR connector (JPW3) is also required for the processors. These power connectors meet the SSI EPS 12V specification. See the table on the right for pin definitions of these connectors.

4-Pin Power Connectors

In addition to the ATX main power and the CPU PWR connectors, the 4-pin 12V PWR connector, located at JPW2, is also required to provide power to the South Bridge, North Bridge and all VRMs. Use the 4-pin 12V/5V PWR connector at JPW4 to provide additional power to the add-on cards installed on the PCI-E slots when needed. See the table on the right for pin definitions.

ATX Power 24-pin Connector Pin Definitions (JPW1)
Pin#	Definition	Pin #	Definition
13	+3.3V	1	+3.3V
14	-12V	2	+3.3V
15	COM	3	COM
16	PS_ON	4	+5V
17	COM	5	COM
18	COM	6	+5V
19	COM	7	COM
20	Res (NC)	8	PWR_OK
21	+5V	9	5VSB
22	+5V	10	+12V
23	+5V	11	+12V
24	COM	12	+3.3V

(Required)

12V 8-pin Power Connector Pin Defi nitions (JPW3)
Pins	Defi nition
1 through 4	Ground
5 through 8	+12V

(Required)

12V 4-pin Power Connector Pin Definitions (JPW2)
Pins	Definitions
1 and 2	Ground
3 and 4	+12V

(Required)
(Used when needed)

DCA KB Mouse USB 0/1:23 COM1 Parallel Port LAN1/2 HD Audio SUPERO® X7DWA-N CD1 CPU1 CPU2 SI05 PCI-Exp x16 SI15 PCI-33MHz SI04 PCI-Exp x16 JWD SI03 PCI-33 MHz SI02 PCI-X 133/100 MHz JWOR SI01 PCI-X 133/100 MHz FP Audio SI00 PCI-U IPME 24-Pin ATX PWR CPU Fan1 PIN 4 Pin PWR VP DDB IAS CPU1 CPU2 CPU JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOR JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWAKI 4B (Bank 4) DIMM 4A (Bank 4) DIMM 3B (Bank 3) DIMM 3A (Bank 3) DIMM 2B (Bank 2) DIMM 2A (Bank 2) DIMM 1B (Bank 1) DIMM 1A (Bank 1) North Bridge CPU1 CPU2 CPU JWOR JWOR JWOR JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK JWOK

A. 24-pin ATX PWR

B. 8-pin Processor PWR

C.4-pin12V PWR (JPW2)

D. 4-pin PWR (JPW4)

Universal Serial Bus (USB)

There are six USB 2.0 (Universal Serial Bus) ports/headers on the motherboard. Four Back Panel USB ports (USB #0, #1, #2 & #3) are located at JUSB1, and the other two are Front Panel Accessible USB headers (USB #4 & #5). These two FP USB headers are located at JUSB2. See the tables on the right for pin definitions.

Back Panel USB(USB0/1/2/3)
Pin#	Definitions
1	+5V
2	PO-
3	PO+
4	Ground
5	N/A

Chassis Intrusion

A Chassis Intrusion header is located at JL1 on the motherboard. Attach the appropriate cable from the chassis to inform you of a chassis intrusion when the chassis is opened.

Front Panel USBPin Definitions (USB4/5)
USB4		USB5
Pin #	Definition	Pin #	Definition
1	+5V	1	+5V
2	PO-	2	PO-
3	PO+	3	PO+
4	Ground	4	Ground
5	Key	5	No connection

Chassis Intrusion Pin Definitions (JL1)
Pin#	Definition
1	Intrusion Input
2	Ground

graph TD
    subgraph CPU
        CPU1["CPU1"] -->|SPIA PS| SIO["1394 CTLR"]
        CPU1 -->|JCOM2| Buzzer["Buzzer"]
        CPU1 -->|JCPFIE| BIOS["BIOS"]
        CPU1 -->|JWIF1| ESB2["ESB2"]
        CPU1 -->|JWF1| JCPFIE
        CPU1 -->|JCPFIE| SIO
    end
    subgraph Memory
        CPU2["CPU2"] -->|SPIA PS| SIO
        CPU2 -->|JCOM2| Buzzer
        CPU2 -->|JCPFIE| BIOS
        CPU2 -->|JWIF1| ESB2
        CPU2 -->|JCPFIE| SIO
    end
    subgraph Audio
        CPU3["CPU3"] -->|SPIA PS| SIO
        CPU3 -->|JCOM2| Buzzer
        CPU3 -->|JCPFIE| BIOS
        CPU3 -->|JWIF1| ESB2
        CPU3 -->|JCPFIE| SIO
    end
    subgraph Control
        CPU4["CPU4"] -->|SPIA PS| SIO
        CPU4 -->|JCOM2| Buzzer
        CPU4 -->|JCPFIE| BIOS
        CPU4 -->|JWIF1| ESB2
        CPU4 -->|JCPFIE| SIO
    end
    subgraph Audio_Port
        COM1["COM1"] -->|USB 0/1/2/3| A["A"]
        Parallel_Port["Parallel Port"] --> A
        LAN1/2["LAN1/2"] --> CD1-1["CD1-1"]
        HD_Audio["HD Audio"] --> CD1-1
    end
    subgraph Power_PWR
        USB_0["USB 0/1/2/3"] --> A
        COM1 --> A
    end
    subgraph Control_Power
        CPU1 -->|SPIA PS| SIO
        CPU1 -->|JCOM2| Buzzer
        CPU1 -->|JCPFIE| BIOS
        CPU1 -->|JWIF1| ESB2
        CPU1 -->|JCPFIE| SIO
    end

A. Back panel USB Ports #0, #1, #2, #3

B. Front Panel USB #4,# 5

C. Chassis Intrusion

Fan Headers

The X7DWA-N has eight chassis/system fan headers (Fan1 to Fan8), including two CPU Fans (Fans 7/8). See the table on the right for pin defi nitions. The onboard fans are controlled by Thermal Management via BIOS Hardware Monitor in the Advanced Setting. (Default: Disabled)

Note: When using Thermal Management setting, please use all 3-pin fans or all 4-pin fans on the motherboard.

Fan HeaderPin Definitions (Fan1-8)
Pin#	Definition
1	Ground
2	+12V
3	Tachometer
4	PWR Modulation

F B KB/ Mouse USB 6/ 1:2:3 COM1 Parallel Port LAN1:2 HD Audio SUPERO® X7DWA-N Slot7 IPMI GLAN CTLR Slot6 PCI-Exp x16 JPL1 Slot5 PCI-33MHz Slot4 PCI-Exp x16 JWD Slot3 PCI 33 MHz Slot2 PCI-X 133:100 MHz JWOR Slot1 PCI-X 133:100 MHz FP Audio Sio80 PCI-U IPMB 1394-1 1394-2 USB4.5 JWD SATA1 SATA3 SATA5 JBT Clear CMOS Cha Inru. SATA0 SATA2 SATA4 JCOM CPU1 CPU2 HC JWF1 JCP BIOS Compact Flash IDE1 Buzzer Battery SIO 1394 CTLR LEI 8-pin PWR B A B C D

A. Fan 1

B. Fan 2

C. Fan 3

D. Fan 4

E. Fan 5

F. Fan 6

G. Fan 7 (CPU Fan 1)

H. Fan 8 (CPU Fan 2)

ATX PS/2 Keyboard and PS/2 Mouse Ports

The ATX PS/2 keyboard and the PS/2 mouse are located at JKM1. See the table on the right for pin definitions. (The mouse port is above the keyboard port. See the table on the right for pin definitions.)

PS/2 Keyboard and Mouse Port Pin Definitions
Pin#	Definition
1	Data
2	NC
3	Ground
4	VCC
5	Clock
6	NC

Serial Ports

COM1 is a connector located on the IO Backpanel, and COM2 is a header located at JCOM2. JCOM2 can be accessed from the front panel by using the optional cable kit. See the table on the right for pin definitions.

Serial Port Pin Definitions (COM1/COM2)
Pin #	Definition	Pin #	Definition
1	CD	6	DSR
2	RD	7	RTS
3	TD	8	CTS
4	DTR	9	RI
5	Ground	10	NC

(Pin 10 is available on COM2 only. NC: No Connection.)

KB Mouse USB 0/ 1:2/3 COM1 Parallel Port LAN1/2 HD Audio SUPER® X7DWA-N Slot7 IPMI OLAN CTLR Slot6 PCI-Exp x16 JPL1 Slot5 PCI-33MHz Slot4 PCI-Exp x16 JWD Slot3 PCI 33 MHz Slot2 PCI-X 133/100 MHz JWOR Slot1 PCI-X 133/100 MHz FP Audio Slot0 IPMI 4-Pin PWR 24-Pin ATX PWR CPU Fan7 Fan1 USB PS PF DIMM 4B (Bank 4) DIMM 4A (Bank 4) DIMM 3B (Bank 3) DIMM 3A (Bank 3) DIMM 2B (Bank 2) DIMM 2A (Bank 2) DIMM 1B (Bank 1) DIMM 1A (Bank 1) CPU1 CPU2 CPU Fan2 Fan1 Fan2 Fan3 CPU JWF1 JCF1E IIC ESB2 South Bridge BIOS Buzzer SIO 1394 CTLR Battery SATA1 SATA3 SATA5 SATA0 SATA2 SATA4 JCOM4 8-pin PWR FP Control Fan P/WLDGay fan2 LEI JOH1 SGP01 SGPC02 Compact Flash IDE1 JIDE1 Buzzer Clear CMOS Cha Intru. Fand

A. Keyboard/Mouse
B.COM1
C.COM2

Wake-On-Ring

The Wake-On-Ring header is designated JWOR. This function allows your computer to receive and be "awakened" by an incoming call to the modem when the system is in the suspend state. See the table on the right for pin definitions. You must have a Wake-On-Ring card and cable to use this feature.

Wake-On-Ring Pin Dei nitions (JWOR)
Pin#	Dei nition
1 Ground
2 Wake-up

Wake-On-LAN

The Wake-On-LAN header is located at JWOL on the motherboard. See the table on the right for pin defi nitions. (You must also have a LAN card with a Wake-On-LAN connector and cable to use this feature.)

Wake-On-LANPin Defi nitions(JWOL)
Pin#	Defi nition
1 +5V	Standby
2 Ground
3 Wake-up

KB Mouse USB 6/ 1/2/3 COM1 Parallel Port LAN1/2 HD Audio SUPERO® X7DWA-N Slot7 IPMI GLAN CTLR Slot5 PCI-Exp x16 IPL1 Slot5 PCI-33MHz Slot4 PCI-Exp x16 JWD Slot3 PCI 33 MHz Slot1 PCI-X 133/100 MHz JWOR Slot1 PCI-X 133/100 MHz FP Audio Slot0 PCI-U IPMB 1394-1 1394-2 USB4/5 JU CPU Fan Fan SUB RS PSF DIMM 4B (Bank 4) DIMM 4A (Bank 4) DIMM 3B (Bank 3) DIMM 3A (Bank 3) DIMM 2B (Bank 2) DIMM 2A (Bank 2) DIMM 1B (Bank 1) DIMM 1A (Bank 1) CPU1 CPU2 CPU Fan Fan Sub RS PSF JWF1 JCFE BIOS SATA5 SATA4 JCOM2 JBT Clear CMOS Cha.Intn. Pack LE1 JOH1 SPGPO1 SGPO2 JIDE2 IDE1 Buzzer Battery SIO 1394 CTLR

A. WOR

B. WOL

GLAN 1/2 (Giga-bit Ethernet Ports)

Two G-bit Ethernet ports are located at JLAN1 on the IO backplane. This port accepts RJ45 type cables.

GLAN1

GLAN2

Power LED/Speaker

On the JD1 header, pins 1-3 are for a power LED and pins 4-7 are for the speaker. See the table on the right for speaker pin definitions.

Note: The speaker connector pins are for use with an external speaker. If you wish to use the onboard speaker, you should close pins 6-7 with a jumper.

Speaker ConnectorPin Defi nitions
Pin Setting	Defi nition
Pins 6-7	Internal Speaker
Pins 4-7	External Speaker

KB Mouse USB 0/ 1/2/3 CO#1 Parallel Port A LAN1/2 HD Audio Super® X7DWA-N Slot7 IPM GLAN CTLR Slot6 PCI-Exp x18 JPL1 Slot5 PCI-33MHz Slot4 PCI-Exp x16 JWD Slot3 PCI 33 MHz Slot2 PCI-X 133:100 MHz JWOR Slot1 PCI-X 133:100 MHz FP Audio IPMD SIO PCI-U 1394-1 1394-2 USB4-X/PIOU SATA1 SATA3 SATA5 JBT1 Clear CMOS Chu Imu Fan1 4-Pin PWR PWR CPU Fan1 SMR PS PGF MAR NAR CPU1 CPU2 North Bridge CPU1 BIOS SIO 1394 CTLR LEI JOH1 SGPO1 SGPO2 Compact Flash IIDE JIDE B Buzzer

A. GLAN1/2
B. PWR LED/Speaker

Power Supply Failure

Connect a cable from your power supply to the PSF(Power Supply Failure) header at JP3 to provide warning of power supply failure. This warning signal is passed through the PWR_LED pin to indicate of a power failure on the chassis. See the table on the right for pin definitions.

PWR Supply Fail LED Pin Definitions
Pin#	Definition
1	PWR 1: Fail
2	PWR 2: Fail
3	PWR 3: Fail
4	Signal: Alarm Reset

Note: This feature is only available when using Supermicro redundant power supplies.

Overheat LED/Fan Fail (JOH1)

The JOH1 header is used to connect an LED to provide warnings of chassis overheat. This LED will blink to indicate a fan failure. Refer to the table on right for pin definitions.

Overheat LEDPin Definitions
Pin#	Definition
1	5vDC
2	OH Active

OH/Fan Fail LED Pin Definitions
State	Message
Solid	Overheat
Blinking	Fan Fail

KB Mouse USB 6i 1:2:3 COM1 Parallel Port LAN1:2 HD Audio SUPERO® X7DWA-N CD1 Slot7 IPMN GLAN CTLR Slot6 PCI-Exp x16 JPL1 Slot5 PCI-33MHz Slot4 PCI-Exp x16 JWD Slot3 PCI 33 MHz Slot2 PCI-X 133-100 MHz JWOR Slot1 PCI-X 133-100 MHz FP Audio SIO PCI-U IPMB 1394.5 1394.2 USB4.5 NWO CPU Fan7 Fan1 SWS BAR CPU1 CPU2 CPU JWF1 JCF1E JF BIOS Battery SI/O 1394 CTLR JBT1 Clear CMOS Cha.Intru. JCOM2 LE1 SPPO1 SPPO2 JIDE1 IDE1 BUZZER Compact Flash JIDE2

A. Power Fault
B. Overheat LED

Alarm Reset

If three power supplies are installed and Alarm Reset (JAR) is enabled, the system will notify you when any of the three power modules fails. Connect JAR to a micro-switch to enable you to turn off the alarm that is activated when a power module fails. See the table on the right for pin definitions.

Alarm ResetPin Defi nitions
Pin Setting	Defi nition
Pin 1 Ground
Pin 2 +5V

Power SMB (I²C) Connector

Power SMB (I ^2 C) Connector (J17) monitors power supply, fan and system temperatures. See the table on the right for pin definitions.

PWR SMBPin Defi nitions
Pin#	Defi nition
1 Clock
2 Data
3 PWR Fail
4 Ground
5 +3.3V

graph TD
    subgraph Central Components
        A["KB Mouse"] --> B["USB 0' 1/2/3"]
        C["COM1"] --> D["Parallel port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["CD1"] --> H["North Bridge"]
        I["SIPMI"] --> J["PCI-Exp x16"]
        K["PCI-33MHz"] --> L["PCI-Exp x16"]
        M["JWD"] --> N["PCI 33 MHz"]
        O["PCI-X 133/100 MHz"] --> P["PCI-X 133/100 MHz"]
        Q["IPM8"] --> R["PCI-U"]
        S["FP Audio"] --> T["PCI0"]
    end

    subgraph External Components
        U["CPU1"] --> V["CPU2"]
        W["CPU2"] --> X["CPU"]
        Y["CPU2"] --> Z["CPU"]
        AA["CPU2"] --> AB["CPU"]
        AC["CPU2"] --> AD["CPU"]
        AE["CPU2"] --> AF["CPU"]
        AG["CPU2"] --> AH["CPU"]
        AI["CPU2"] --> AJ["CPU"]
        AK["CPU2"] --> AL["CPU"]
        AM["CPU2"] --> AN["CPU"]
        AO["CPU2"] --> AP["CPU"]
        AQ["CPU2"] --> AR["CPU"]
        AS["CPU2"] --> AT["CPU"]
        AU["CPU2"] --> AV["CPU"]
        AW["CPU2"] --> AX["CPU"]
        AY["BIOS"] --> AZ["BIIZER"]

    style Central Components fill:#f9f,stroke:#333
    style External Components fill:#ccf,stroke:#333

A. Alarm Reset B. PWR SMB

Compact Flash Card PWR Connector

A Compact Flash Card Power Connector is located at JWF1. For the Compact Flash Card to work properly, you will also need to configure JCF1 properly and connect the Compact Flash Card power cable to JWF1 first. Refer to the board layout below for the location.

Compact Flash Card PWR Connector
Jumper Definition
On	Compact Flash Power On
Off	Compact Flash Power Off

SGPIO Headers

There are two SGPIO (Serial General Purpose Input/Output) headers (J29, J30) located on the motherboard. These headers support serial link interfaces for the onboard serial link (SATA or SAS) connectors. See the table on the right for pin definitions. Refer to the board layout below for the location.

SGPIOPin Definitions
Pin#	Definition	Pin	Definition
1	NC	2	NC
3	Ground	4	DATA Out
5	Load	6	Ground
7	Clock	8	NC

Note: NC= No Connections

graph TD
    subgraph CPU
        CPU1["CPU1"] -->|DINAM 4B (Bank 4)| DIMM_4A["DIMM 4A (Bank 4)"]
        CPU1 -->|DINAM 3B (Bank 3)| DIMM_3A["DIMM 3A (Bank 3)"]
        CPU1 -->|DINAM 2B (Bank 2)| DIMM_2A["DIMM 2A (Bank 2)"]
        CPU1 -->|DINAM 1B (Bank 1)| DIMM_1A["DIMM 1A (Bank 1)"]
        CPU1 -->|DINAM 1A (Bank 1)| LAN1_2["LAN1/2"]
        CPU -->|DINAM 1B (Bank 1)| CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD1-CD2
    end
    subgraph Memory
        CPU2["CPU2"] -->|DINAM 4B (Bank 4)| DISH_4_B["DIMM 4B (Bank 4)"]
        CPU2 -->|DINAM 3B (Bank 3)| DISH_3_A["DIMM 3A (Bank 3)"]
        CPU2 -->|DINAM 2B (Bank 2)| DISH_2_A["DIMM 2A (Bank 2)"]
        CPU2 -->|DINAM 1B (Bank 1)| DISH_1_A["DIMM 1A (Bank 1)"]
        CPU2 -->|DINAM 1A (Bank 1)| LAN1_2
    end
    subgraph Control
        CPU_Pack["CPU Pamp"] -->|JCP_0.05| CompactFlash["Compact Flash"]
        CPU_Pack -->|JCP_0.05| IIDE["IDE"]
        CPU_Pack -->|JCP_0.05| Buzzer["Buzzer"]
    end
    subgraph Audio
        CPU_A["CPU A"] -->|JCP_0.05| CompactFlash
        CPU_A -->|JCP_0.05| IIDE
        CPU_A -->|JCP_0.05| Buzzer
    end
    subgraph Media
        CPU_Pack -->|JCP_0.05| CompactFlash
        CPU_Pack -->|JCP_0.05| IIDE
        CPU_Pack -->|JCP_0.05| Buzzer
    end
    subgraph Display
        CPU_Pack -->|JCP_0.05| CompactFlash
        CPU_Pack -->|JCP_0.05| IIDE
        CPU_Pack -->|JCP_0.05| Buzzer
    end
    subgraph Display
        CPU_Pack -->|JCP_0.05| CompactFlash
        CPU_Pack -->|JCP_0.05| IIDE
        CPU_Pack --> JBT_Clear["CBT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Pack -->|JBT_Clear["CMT"]
        CPU_Land["LED"] -->|JCP_0.05| CompactFlash
    end

A. Compact Flash PWR

B. SGPIO 1

C. SGPIO 2

High Definition Audio (HD Audio)

The X7DWA-N features a 7.1+2 Channel High Definition Audio (HDA) (JC1) codecs that provides 10DAC channels, simultaneously supporting 7.1 sound playback with 2 channels of independent stereo sound output (multiple streaming) through the front panel stereo out (for front L&R, rear L&R), center and subwoofer speakers. Use the advanced software included in the CD-ROM with your motherboard to enable this function. Sound is then output through the Line-In, Line-Out and MIC jacks (see the graphics at right). Enable this feature in the BIOS to use this feature.

Orange: CEN/LFE Blue: Line-In Black: Back Surround Green:Front Grey: Side Surround Pink: Mic-In

CD Header

A 4-pin CD header is located at CD1 and a Front Pane Accessible Audio header is located at JC2 on the motherboard. This headers allow you to use the onboard sound for audio CD playback. Connect an audio cable from your CD drive to the CD header that fits your cable's connector. Only one CD header can be used at any time. See the tables at right for pin definitions. (Refer to the next page for the FP Audio.)

CD1 Pin Defi nition
Pin#	Defi nition
1 Left
2 Ground
3 Ground
4 Right

graph TD
    subgraph Top_Layer
        A["KB Mouse"] --> B["USB 0/1/2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["HD Audio"] --> F["SUPER® X7DWA-N"]
        G["CDI"] --> H["Slot7 IPMI"]
        I["GLAN CTLR"] --> J["Slot6 PCI-Exp x16"]
        K["PCI5 PCI-33MHz"] --> L["JPL1"]
        M["Slot4 PCI-Exp x16"] --> N["JWD"]
        O["Slot3 PCI 33 MHz"] --> P["PCI"]
        Q["Slot2 PCI-X 133/100 MHz"] --> R["JWOR"]
        S["Slot1 PCI-X 133/100 MHz"] --> T["IPMD"]
    end

    subgraph Middle_Layer
        U["CPU1"] --> V["CPU2"]
        W["CPU2"] --> X["CPU"]
        Y["CPU2"] --> Z["CPU"]
        AA["CPU2"] --> AB["CPU"]
        AC["CPU2"] --> AD["CPU"]
        AE["CPU2"] --> AF["CPU"]
        AG["CPU2"] --> AH["CPU"]
        AI["CPU2"] --> AJ["CPU"]
        AK["CPU2"] --> AL["CPU"]
        AM["CPU2"] --> AN["CPU"]
        AO["CPU2"] --> AP["CPU"]
        AQ["CPU2"] --> AR["CPU"]
        AS["CPU2"] --> AT["CPU"]
        AU["CPU2"] --> AV["CPU"]
        AW["CPU2"] --> AX["CPU"]
        AY["BIOS"] --> AZ["JCFIE"]
        BA["BIOS"] --> BB["JWIF1"]
        BC["Puppy"] --> BD["Fuppy"]
        BE["Compact Flash"] --> BF["JIDEC"]
        BG["IIDE1"] --> BH["JIDE4"]
        BI["Buzzer"] --> BJ["Buzzer"]
    end

    subgraph Bottom_Layer
        BK["USB 0/1/2/3"]
        BL["COM1"] --> BM["Parallel Port"]
        BN["LAN1/2"] --> BO["HDD Audio"]
        BP["SUPER® X7DWA-N"] --> BQ["SIPOL"]
    end

    style Top_Layer fill:#f9f,stroke:#333
    style Middle_Layer fill:#ccf,stroke:#333
    style Bottom_Layer fill:#cfc,stroke:#333

A. BP HD Audio
B. FP Accessible Audio
C. CD1

Front Panel Audio Control

When front panel headphones are plugged in, the back panel audio output is disabled. This is done through the FP Audio header (JC2). If the front panel interface card is not connected to the front panel audio header, jumpers should be installed on the header (JC2) pin pairs: 1-2, 5-6, and 9-10. If these jumpers are not installed, the back panel line out connector will be disabled and microphone input Pin 1 will be left floating, which can lead to excessive back panel microphone noise and cross talk. See the table below for pin definitions.

FP AudioPin Den nitions
Pin#	Den n.
1 MIC_L
2 AUD_GND
3 MIC_R
4 FP Audio-Detect
5 Line_2_R
6 Ground
7 FP Jack-Detect
8 Key
9 Line_2_L
10 Ground

KB Mouse USB 6/ 1/2/3 COM1 Parallel Port LAN1/2 HD Audio SUPERO® X7DWA-N Slot7 IPMI GLAN CTLR Slot5 PCI-Exp x16 IPL1 Slot5 PCI-33MHz Slot4 PCI-Exp x16 JWD Slot3 PCI 33 MHz Slot2 PCI-X 133:100 MHz JWOR Slot1 PCI-X 133:100 MHz FP Audio Slot0 PCI-U IPMB 1394-1 1394-2 USB4/5 JWOL SATA1 SATA3 SATA5 JBT Clear CMOS Cha.Intu Pack CPU Fan Fan SUB RS PSF DIMM 4B (Bank 4) DIMM 4A (Bank 4) DIMM 3B (Bank 3) DIMM 3A (Bank 3) DIMM 2B (Bank 2) DIMM 2A (Bank 2) DIMM 1B (Bank 1) DIMM 1A (Bank 1) CPU1 CPU2 CPU Fan Fan Fan JWFJ JCF E JCI PQQY CompactFlash IDE2 IDE1 Buzzer BIOS SIO 1394 CTLR Battery

A. FP Accessible Audio

1394-1/1394-2 Connections

1394-1 and 1394-2 provide the IEEE 1394 Fire-Wire connections on the motherboard. See the tables on the right for pin definitions.

1394-1Pin Definitions
Pin#	Defin.	Pin#	Defin
1	PTPA0+ 2	PTPA0-
3	GND 4	GND
5	PTPB0+ 6	PTPB0-
7	PWR 1394	8 PWR 1394
		10 ZX

1394-2Pin Definitions
Pin#	Defin.	Pin#	Defin
1	PTPA1+ 2	PTPA1-
3	GND 4	GND
5	PTPB1+ 6	PTPB1-
7	PWR 1394 8	PWR	1394
		10 ZY

graph TD
    subgraph Top_Layer
        A["KB Mouse"] --> B["USB 0/1/2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["SUPER• X7DWA-N"] --> H["Slot7 IPMI"]
        I["GLAN CTLR"] --> J["Slot6 PCI-Exp x16"]
        K["IPL1"] --> L["Slot5 PCI-33MHz"]
        M["Slot4"] --> N["PCI-Exp x16"]
        O["JWD"] --> P["Slot3 PCI 33 MHz"]
        Q["Slot2"] --> R["PCI-X 133/100 MHz"]
        S["JWOR"] --> T["Slot1 PCI-X 133/100 MHz"]
        U["FP Audio"] --> V["Slot0 PCI-U"]
    end

    subgraph Bottom_Layer
        W["CPU1"] --> X["CPU2"]
        Y["CPU2"] --> Z["CPU"]
        AA["CPU2"] --> AB["CPU Fan2"]
        AC["CPU2"] --> AD["FSB"]
        AE["CPU2"] --> AF["Fan3"]
        AG["CPU2"] --> AH["JWF1"]
        AI["CPU2"] --> AJ["JCPF1E"]
        AK["CPU2"] --> AL["BIOS"]
        AM["CPU2"] --> AN["Propify"]
        AO["CPU2"] --> AP["CompactFlash"]
        AQ["CPU2"] --> AR["IDE1"]
        AS["CPU2"] --> AT["Buzzer"]
    end

    style Top_Layer fill:#f9f,stroke:#333
    style Bottom_Layer fill:#ccf,stroke:#333

A. 1394-1 Fire-Wire

B. 1394-2 Fire-Wire

2-7 Jumper Settings

Explanation of Jumpers

To modify the operation of the motherboard, jumpers can be used to choose between optional settings. Jumpers create shorts between two pins to change the function of connector. Pin 1 is identified with a square solder pad on the printed circuit board. See the motherboard layout pages for jumper locations.

Note: On two pin jumpers, "Closed" means the jumper is on and "Open" means the jumper is off the pins.

Connector Pins Jumper Cap the Setting

3 2 1 Pin 1-2 short

GLAN Enable/Disable

JPL1 enables or disables GLAN Port1 and GLAN Port2 on the motherboard. See the table on the right for jumper settings. The default setting is enabled.

GLAN EnableJumper Settings
Pin#	Definition
1-2	Enabled (default)
2-3	Disabled

graph TD
    subgraph Top_Layer
        A["KB: Mouse"] --> B["USB 0/1/2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["SUPER® X7DWA-N"] --> H["Slot7 IPMI"]
        I["GLAN CTLR"] --> J["Slot5 PCI-Exp x16"]
        K["Slot3 PCI-33MHz"] --> L["Slot5 PCI-Exp x16"]
        M["Slot3 PCI 33 MHz"] --> N["Slot3 PCI-33 MHz"]
        O["Slot2 PCI-X 133/100 MHz"] --> P["JWORF"]
        Q["Slot1 PCI-X 132/100 MHz"] --> R["IPMB"]
    end

    subgraph Bottom_Layer
        S["CPU1"] --> T["CPU2"]
        U["CPU2"] --> V["CPU"]
        W["CPU2"] --> X["CPU"]
        Y["CPU2"] --> Z["CPU"]
        AA["CPU2"] --> AB["CPU"]
        AC["CPU2"] --> AD["CPU"]
        AE["CPU2"] --> AF["CPU"]
        AG["CPU2"] --> AH["CPU"]
        AI["CPU2"] --> AJ["CPU"]
        AK["CPU2"] --> AL["CPU"]
        AM["CPU2"] --> AN["CPU"]
        AO["CPU2"] --> AP["CPU"]
        AQ["CPU2"] --> AR["CPU"]
        AS["CPU2"] --> AT["CPU"]
        AU["CPU2"] --> AV["CPU"]
        AW["CPU2"] --> AX["CPU"]
        AY["8-pin PWR"] --> AZ["FP Control"]
        BA["SGPO1"] --> BB["JIDE2"]
        BC["SGP02"] --> BD["IIDE1"]
        BE["Buzzer"] --> BF["BIO5"]
        BG["SIO"] --> BH["1394 CTLR"]
        BI["JBT"] --> BJ["CNOs"]
        BK["JBT"] --> BL["CNOs"]
        BM["JBT"] --> BN["CNOs"]
    end

    style Top_Layer fill:#f9f,stroke:#333
    style Bottom_Layer fill:#bbf,stroke:#333
    style Bottom_Layer fill:#dfd,stroke:#333

A. GLAN Ports1/2 Enable

CMOS Clear

JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads to prevent accidental clearing of CMOS. To clear CMOS, use a metal object such as a small screwdriver to touch both pads at the same time to short the connection. Always remove the AC power cord from the system before clearing CMOS.

Note: For an ATX power supply, you must completely shut down the system, remove

the AC power cord and then short JBT1 to clear CMOS.

Watch Dog Enable/Disable

Watch Dog is a system monitor that can reboot the system when a software application hangs. Close pins 1-2 to reset the system if an application hangs. Close pins 2-3 to generate a non-maskable interrupt signal for the application that hangs. See the table on the right for jumper settings. Watch Dog must also be enabled in the BIOS.

Watch DogJumper Settings (JWD)
Jumper Setting	Definition
Pins 1-2 Reset	(default)
Pins 2-3 NMI
Open Disabled

graph TD
    subgraph Central Components
        A["KB/Mouse"] --> B["USB 0/1:2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["CD1"] --> H["SUPER® X7DWA-N"]
        I["CPU1"] --> J["CPU2"]
        K["CPU2"] --> L["CPU"]
        M["CPU2"] --> N["CPU"]
        O["CPU2"] --> P["CPU"]
        Q["CPU2"] --> R["CPU"]
        S["CPU2"] --> T["CPU"]
        U["CPU2"] --> V["CPU"]
        W["CPU2"] --> X["CPU"]
        Y["CPU2"] --> Z["CPU"]
        AA["CPU2"] --> AB["CPU"]
        AC["CPU2"] --> AD["CPU"]
        AE["CPU2"] --> AF["CPU"]
        AG["CPU2"] --> AH["CPU"]
        AI["CPU2"] --> AJ["CPU"]
        AK["CPU2"] --> AL["CPU"]
        AM["CPU2"] --> AN["CPU"]
        AO["CPU2"] --> AP["CPU"]
        AQ["CPU2"] --> AR["CPU"]
        AS["CPU2"] --> AT["CPU"]
        AU["CPU2"] --> AV["CPU"]
        AW["CPU2"] --> AX["CPU"]
        AY["SI0"] --> AZ["SIO"]
        BA["SIO"] --> BB["SIO"]
        BC["SIO"] --> BD["SIO"]
        BE["SIO"] --> BF["SIO"]
        BG["SIO"] --> BH["SIO"]
        BI["SIO"] --> BJ["SIO"]
        BK["SIO"] --> BL["SIO"]
    end
    subgraph External Components
        AM --> BM["SIO"]
        AN --> BN["SIO"]
        AO --> BO["SIO"]
        AP --> BP["SIO"]
        AQ --> BQ["SIO"]
        AR --> BR["SIO"]
        AS --> BS["SIO"]
        AT --> BT["SIO"]
        AU --> BU["SIO"]
        AV --> BV["SIO"]
        AW --> BW["SIO"]
        AX --> BX["SIO"]
        AY --> BY["SIO"]
        AZ --> BZ["SIO"]
        BA --> CA["SIO"]
        BB --> CB["SIO"]
        BC --> CC["SIO"]
        AD --> CD["SIO"]
        AE --> CE["SIO"]
        AF --> CF["SIO"]
        AG --> CG["SIO"]
        AH --> CH["SIO"]
        AI --> CI["SIO"]
        AJ --> CJ["SIO"]
        AK --> CK["SIO"]
    end
    style Central Components fill:#f9f,stroke:#333
    style External Components fill:#ccf,stroke:#333

A. Clear CMOS

B. Watch Dog Enable

3rd PWR Supply PWR Fault Detect (J3P)

The system can notify you in the event of a power supply failure. This feature is available when three power supply units are installed in the chassis with one acting as a backup. If you only have one or two power supply units installed, you should disable this (the default setting) with J3P to prevent false alarms.

3rd PWR Supply PWR Fault Jumper Settings
Jumper Setting	Definition
Closed	Enabled
Open	Disabled (Default)

SMB to PCI-X/PCI-E Slots Speeds

Jumpers JI ^2 C1/JI ^2 C2 allow you to connect PCI-X slots to the System Management Bus, and Jumpers JI ^2 C3/JI ^2 C4 allow you to connect PCI-Exp. Slots to the System Management Bus for enhanced power management. The default setting is to close pins 2-3 to disable the connection. See the table on the right for jumper settings.

SMBus to PCI-X/PCI-Exp Slots Jumper Settings
Jumper Setting	Definition
Pins 1-2	Enabled
Pins 2-3	Disabled (Default)

graph TD
    subgraph Top
        A["KB/Mouse"] --> B["USB 0/1:2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["SUPER® X7DWA-N"] --> H["Slot7 IPMI"]
        I["GLAN CTLR"] --> J["Slot5 PCI-Exp x16"]
        K["PCI-33MHz"] --> L["Slot3 PCI-Exp x16"]
        M["PCI-33 MHz"] --> N["Slot4 PCI-Exp x16"]
        O["PCI-X 133/100 MHz"] --> P["JWD"]
        Q["JWOR"] --> R["Slot1 PCI-X 133/100 MHz"]
        S["FP Audio"] --> T["Slot8 PCI-U"]
        U["IPMB"] --> V["1394-1 1394-2 USB4/5 JW0"]
        W["SATA1 SATA3 SATA5 JBT Clear CMOS Che Intu. Fan4"] --> X["SATA0 SATA2 SATA4 JCOM2"]
    end
    subgraph Bottom
        Y["CPU1"] --> Z["CPU2"]
        AA["CPU2"] --> AB["CPU"]
        AC["CPU2"] --> AD["CPU"]
        AE["CPU2"] --> AF["CPU"]
        AG["CPU2"] --> AH["CPU"]
        AI["CPU2"] --> AJ["CPU"]
        AK["CPU2"] --> AL["CPU"]
        AM["CPU2"] --> AN["CPU"]
        AO["CPU2"] --> AP["CPU"]
        AQ["CPU2"] --> AR["CPU"]
        AS["CPU2"] --> AT["CPU"]
        AU["CPU2"] --> AV["CPU"]
        AW["CPU2"] --> AX["CPU"]
        AY["8-pin PWR"] --> AZ["FP Control Fan1"]
        BA["SGPO1"] --> BB["JIDE2 IDE1"]
        BC["SGPO2"] --> BD["BIOS"]
        BE["Compact/Flash"] --> BF["JUP"]
        BG["Buzzer"] --> BH["JINT"]
    end
    style Top fill:#f9f,stroke:#333
    style Bottom fill:#ccf,stroke:#333

A. 3rd PWR Fail

B. SMB to PCI-X slots

C. SMB to PCI-E slots

Compact Flash Master/Slave Select

A Compact Flash Master/Slave Select Jumper is located at JCF1. Close this jumper to enable Compact Flash Card. For the Compact Flash Card or the Compact Flash Jumper (JCF1) to work properly, you will need to connect the Compact Flash Card power cable to JWF1 first. Refer to the board layout below for the location.

Compact Flash Card Master/Slave Select
Jumper	Definition
Open	Slave
Closed	Master

graph TD
    A["KB/Mouse"] --> B["USB 0/1/2/3"]
    B --> C["COM1"]
    C --> D["Parallel Port"]
    D --> E["LAN1/2"]
    E --> F["HD Audio"]
    F --> G["SUPERO® X7DWA-N"]
    G --> H["Slot7 IFM"]
    H --> I["GLAN CTLR"]
    I --> J["Slot5 PCI-Exp x16"]
    J --> K["JWD"]
    K --> L["Slot3 PCI 33 MHz"]
    L --> M["Slot2 PCI-X 133/100 MHz"]
    M --> N["JWORF"]
    N --> O["Slot1 PCI-X 133/100 MHz"]
    O --> P["FP Audio"]
    P --> Q["Slot0 PCI-U"]
    Q --> R["IPMB"]
    R --> S["1394-1 1394-2 USB4/5 JWOL"]
    S --> T["SATA1 SATA3 SATA5"]
    T --> U["SATA0 SATA2 SATA4 JCOMB"]
    U --> V["Battery"]
    V --> W["SIO"]
    W --> X["1394 CTLR"]
    X --> Y["JBT1 Clear CMOS Chs. Intru Fan4"]

A. Compact Flash Master/Slave Select

2-8 Onboard Indicators

GLAN LEDs

There are two GLAN ports on the motherboard. Each Gigabit Ethernet LAN port has two LEDs. The green LED indicates activity, while the Link LED may be green, amber or off to indicate the speed of the connection. See the tables at right for more information.

Activity LED Link LED Activity LED Link LED

Rear View

GLAN Activity Indicator
Color	Status	Definition
Green	Flashing Active

GLAN Link Indicator
LED Color	Definition
Off No Connection or 10 Mbps
Green (On)	100 Mbps
Amber (On)	1 Gbps

KB: Mouse USB 6/1/2/3 COM1 Parallel Port LAN1:2 HD Audio Super® X7DWA-N CD1- Slot7 IPMI GLAN CTLR Slot6 PCI-Exp x16 JPL1 Slot5 PCI-33MHz Slot4 PCI-Exp x16 JWD Slot3 PCI 33 MHz Slot2 PCI-X 133:100 MHz JWOR Slot1 PCI-X 133:100 MHz FP Audio Slot9 PCI-U IPMB 1394-1 1394-2 USB4/5 JWOL SATA1 SATA3 SATA5 JBT Clear CMOS CHA.Intn Fand CPU Fan Fan SSB R5 PSF DIMM 4B (Bank 4) DIMM 4A (Bank 4) DIMM 3B (Bank 3) DIMM 3A (Bank 3) DIMM 2B (Bank 2) DIMM 2A (Bank 2) DIMM 1B (Bank 1) DIMM 1A (Bank 1) CPU1 CPU2 CPU Fan Fan Fan JWF1 JCI E K BIOS JWF1 Puppy CompactFlash IDE2 IDE1 IOE1 Buzzer SIO 1394 CTLR Battery

A. GLAN Ports1/2 LEDs

Overheat LED (JOH1)

The JOH1 header is used to connel LED to provide warnings in the event of chassis overheating. Refer to the layout below for the location. Also See the table on the right for pin definitions.

ct an Overheat LEDPin Defi nitions
Pin#	Defi nition
1 5vDC
2 OH Active

Onboard Power LED (LE1)

There is an Onboard Power LED (LE1) located on the motherboard. When LE1 is off, the system is off. When the green light is on, the system is on. When the LED is on, the power is on. Unplug the power cable before removing or installing components. See the layout below for the LED location.

Onboard PWR LED Indicator (LE1) Pin Definitions
LED Color	Definition
Off System	Off
Blinking Standby
On System	On

graph TD
    subgraph Top_Layer
        A["KB/Mouse"] --> B["USB 0/1/2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["SUPER® X7DWA-N"] --> H["Slot7 IPMI"]
        I["GLAN CTLR"] --> J["Slot5 PCI-Exp x16"]
        K["Slot5"] --> L["PCI-33MHz"]
        M["Slot4"] --> N["PCI-Exp x16"]
        O["Slot3"] --> P["PCI 33 MHz"]
        Q["Slot2"] --> R["PCI-X 133/100 MHz"]
        S["JW/OPE"] --> T["PCI-X 133/100 MHz"]
        U["FP Audio"] --> V["Slot0 PCI-U"]
        W["Fan/Fan+"] --> X["4-Pin PWR PWR"]
        Y["I-Pin 24-PinATX PWR"] --> Z["CPU Fan1"]
        AA["CPU1"] --> AB["DIMM 4B (Bank 4)"]
        AC["DIMM 4A (Bank 4)"] --> AD["DIMM 3B (Bank 3)"]
        AE["DIMM 3A (Bank 3)"] --> AF["DIMM 2B (Bank 2)"]
        AG["DIMM 2A (Bank 2)"] --> AH["DIMM 1B (Bank 1)"]
        AI["DIMM 1A (Bank 1)"] --> AJ["DIMM 1A (Bank 1)"]
    end
    subgraph Bottom_Layer
        AK["CPU2"] --> AL["SI/O"]
        AM["CPU"] --> AN["JWF1"]
        AO["BIOS"] --> AP["Compact Flash"]
        AQ["Buzzer"] --> AR["IDE1"]
        AS["SIO"] --> AT["1394 CTLR"]
        AU["SATA1"] --> AV["SATA3"]
        AW["SATA0"] --> AX["SATA2"]
        AY["SATA5"] --> AZ["JCOM2"]
        BA["SATA4"] --> BB["JDT1"]
        BC["SATA4"] --> BD["Clear CMOS Chs.Intn"]
        BE["SATA4"] --> BF["JCOM2"]
    end
    subgraph Bottom_Layer
        BG["SATA1"] --> BH["SATA3"]
        BI["SATA0"] --> BJ["SATA2"]
        BK["SATA5"] --> BL["SATA4"]
        BM["SATA4"] --> BN["JCOM2"]
    end
    subgraph Bottom_Layer
        BO["SATA4"] --> BP["JDT1"]
        BQ["SATA4"] --> BR["JDT1"]
    end

A. Overheat LED
B. Onboard PWR LED

2-9 Parallel Port, Floppy Drive, Hard Disk Drive, PCI-U Slot and IPMI Connections

Note the following when connecting the floppy and hard disk drive cables:

• The floppy disk drive cable has seven twisted wires.
• A red mark on a wire typically designates the location of pin 1.
• A single floppy disk drive ribbon cable has 34 wires and two connectors to provide for two floppy disk drives. The connector with twisted wires always connects to drive A, and the connector that does not have twisted wires always connects to drive B.

Parallel (Printer) Port Connector

The parallel (printer) port is located at J21. See the table on the right for pin definitions.

Parallel (Printer) Port Connector Pin Definitions
Pin#	Definition	Pin #	Definition
1	Strobe-	2	Auto Feed-
3	Data Bit 0	4	Error-
5	Data Bit 1	6	Init-
7	Data Bit 2	8	SLCT IN-
9	Data Bit 3	10	GND
11	Data Bit 4		12 GND
13	Data Bit 5		14 GND
15	Data Bit 6		16 GND
17	Data Bit 7		18 GND
19	ACK		20 GND
21	BUSY		22 Write Data
23	PE		24 Write Gate
25	SLCT		26 NC

graph TD
    A["KB: Mouse"] --> B["USB 6/1/2/3"]
    B --> C["CDM1"]
    C --> D["Pertallet Port"]
    D --> E["LAN1/2"]
    E --> F["HD Audio"]
    F --> G["SUPERO® X7DWA-N"]
    G --> H["Slot7 IPMI"]
    H --> I["GLAN CTLR"]
    I --> J["Slot5 PCI-Exp x16"]
    J --> K["JPL1"]
    K --> L["Slot5 PCI-33MHz"]
    L --> M["Slot4 PCI-Exp x16"]
    M --> N["JWD"]
    N --> O["Slot3 PCI 33 MHz"]
    O --> P["Slot2 PCI-X 133/100 MHz"]
    P --> Q["JWOR"]
    Q --> R["Slot1 PCI-X 133/100 MHz"]
    R --> S["IPMB"]
    S --> T["FP Audio"]
    T --> U["Slot8 PCI-U"]
    U --> V["1394-1 1394-2 USB4/5 JW01 SATA1 SATA3 SATA5 JBT1 Clear CMOS Chc.Intu."]
    V --> W["SATA0 SATA2 SATA4 JCOM"]
    W --> X["Battery"]
    X --> Y["SIO"]
    Y --> Z["1394 CTLR"]
    Z --> AA["Buzzer"]
    AA --> AB["CPU1"]
    AB --> AC["CPU2"]
    AC --> AD["SGPO1"]
    AD --> AE["SGPO2"]
    AE --> AF["LE1"]
    AF --> AG["JOH"]
    AG --> AH["Compact Flash"]
    AH --> AI["JIDE2"]
    AI --> AJ["IIDE1"]
    AJ --> AK["Buzzer"]

A. Parallel Port

Floppy Connector

The fl oppy connector is located at J22. See the table below for pin definitions.

Floppy Drive Connector Pin Definitions (Floppy)
Pin#	Definition	Pin #	Definition
1	Ground	2	FDHDIN
3	Ground	4	Reserved
5	Key	6	FDEDIN
7	Ground	8	Index
9	Ground	10	Motor Enable
11	Ground	12	Drive Select B
13	Ground	14	Drive Select B
15	Ground	16	Motor Enable
17	Ground	18	DIR
19	Ground	20	STEP
21	Ground	22	Write Data
23	Ground	24	Write Gate
25	Ground	26	Track 00
27	Ground	28	Write Protect
29	Ground	30	Read Data
31	Ground	32	Side 1 Select
33	Ground	34	Diskette

graph TD
    subgraph Top_Layer
        A["KB Mouse"] --> B["USB 0/1/2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["SUPER® X7DWA-N"] --> H["Slot7 IPM"]
        I["PCI-33MHz"] --> J["Slot5 PCH-Exp x16"]
        K["JWD"] --> L["Slot3 PCI 33 MHz"]
        M["PCI-X 133/100 MHz"] --> N["Slot2 PCI-X 133/100 MHz"]
        O["JWOR"] --> P["Slot1 PCI-X 133/100 MHz"]
        Q["FP Audio"] --> R["Slot0 PCI-U"]
    end

    subgraph Middle_Layer
        S["CPU1"] --> T["CPU2"]
        U["CPU2"] --> V["CPU"]
        W["CPU2"] --> X["CPU"]
        Y["CPU2"] --> Z["CPU"]
        AA["CPU2"] --> AB["CPU"]
        AC["CPU2"] --> AD["CPU"]
        AE["CPU2"] --> AF["CPU"]
        AG["CPU2"] --> AH["CPU"]
        AI["CPU2"] --> AJ["CPU"]
        AK["CPU2"] --> AL["CPU"]
        AM["CPU2"] --> AN["CPU"]
        AO["CPU2"] --> AP["CPU"]
        AQ["CPU2"] --> AR["CPU"]
        AS["CPU2"] --> AT["CPU"]
        AU["CPU2"] --> AV["CPU"]
        AW["CPU2"] --> AX["CPU"]
        AY["BUCK"] --> AZ["BUCK"]
        BA["Buzzer"] --> BB["Buzzer"]
    end

    style Top_Layer fill:#f9f,stroke:#333
    style Middle_Layer fill:#ccf,stroke:#333
    style Middle_Layer fill:#cfc,stroke:#333
    style Middle_Layer fill:#fcc,stroke:#333
    style Middle_Layer fill:#cff,stroke:#333
    style Middle_Layer fill:#ffc,stroke:#333
    style Middle_Layer fill:#cfc,stroke:#333
    style Middle_Layer fill:#fcc,stroke:#333
    style Middle_Layer fill:#ffc,stroke:#333
    style Middle_Layer fill:#cfc,stroke:#333
    style Middle_Layer fill:#fcc,stroke:#333
    style Middle_Layer fill:#ffc,stroke:#333
    style Middle_Layer fill:#cfc,stroke:#333
    style Middle_Layer fill:#fcc,stroke:#333

</details>

A. Floppy

<h1 id="ipmi-slot">IPMI Slot</h1>

There is a IPMI Slot located at Slot 7 (J16) on the motherboard. Refer to the layout below for the SIMLP IPMI Slot location.

<h1 id="pci-u-universal-slot">PCI-U Universal Slot</h1>

PCI-U Slot, located on PCI-Slot 0 (J31), is a PCI-E x8 connector specially designed for Supermicro's storage devices to add SATA/SAS and LAN connections to the motherboard. This slot can also support other compatible PCI-E devices. Refer to the layout below for the location.

![](images/434242c8147c5516ee5f6fb716320db9cf382a3e9e52fee07558be6c8f391a0e.jpg)

<details>
<summary>text_image</summary>

KB/Mouse
USB 0/1/2/3
COM1
Parallel Port
LAN1/2
HD Audio
HD Audio
Super® X7DWA-N
Slot7 PIM
GLAN
CTLR
Slot6 PCI-Exp x16
JPL1
Slot5 PCI-33MHz
Slot4 PCI-Exp x16
JWD
Slot3 PCI 33 MHz
Slot2 PCI-X 133/100 MHz
JWOR
Slot1 PCI-X 133/100 MHz
FP Audio
PCI-U
IPM8
24-Pin ATX PWR
Fan5 Fan3
4-Pin PWR PWR
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
DIMM 3B (Bank 3)
DIMM 3A (Bank 3)
DIMM 2B (Bank 2)
DIMM 2A (Bank 2)
DIMM 1B (Bank 1)
DIMM 1A (Bank 1)
CPU1
SIMP PS PSF LAB
CPU2
North Bridge
SGPO1
SGPO2
LEI1
JOH1
SRS/PWR Control
FP Control
JFWLEDesk Fan2
SCGPO1
SGPO2
JIDE1
IDE1
BUOER
CPU Fan2 Fan3 Fan4
JWF1 JCFE IP
BIOS
SVO
1394 CTLR
Battery SIVO
JBT1 Clear CMOS
Chg. Intn.
File
</details>

A. IPMI Slot B. PCI-U Slot

<h1 id="ide-connectors">IDE Connectors</h1>

There are two IDE Connectors (JIDE1: Blue, JIDE2: White) on the motherboard. The blue IDE connector (JIDE1) is designated the Primary IDE Drive. The white IDE connector (JIDE2) is designated the Secondary IDE Drive, reserved for Compact Flash Card use only. (See the Note below.) See the table on the right for pin definitions.

Note: JIDE2 (the white slot) is reserved for Compact Flash Card only. Do not use it for other devices. If JIDE2 is populated with a Compact Flash Card, JIDE1 (the blue slot) will be available for one device only. For the Compact Flash Card to work properly, you will need to connect a power cable to JWF1 first.

<table><tr><td colspan="4">IDE Drive ConnectorsPin Definitions</td></tr><tr><td>Pin#</td><td>Definition</td><td>Pin #</td><td>Definition</td></tr><tr><td>1</td><td>Reset IDE</td><td>2</td><td>Ground</td></tr><tr><td>3</td><td>Host Data 7</td><td>4</td><td>Host Data 8</td></tr><tr><td>5</td><td>Host Data 6</td><td>6</td><td>Host Data 9</td></tr><tr><td>7</td><td>Host Data 5</td><td>8</td><td>Host Data 10</td></tr><tr><td>9</td><td>Host Data 4</td><td>10</td><td>Host Data 11</td></tr><tr><td>11</td><td>Host Data 3</td><td>12</td><td>Host Data 12</td></tr><tr><td>13</td><td>Host Data 2</td><td>14</td><td>Host Data 13</td></tr><tr><td>15</td><td>Host Data 1</td><td>16</td><td>Host Data 14</td></tr><tr><td>17</td><td>Host Data 0</td><td>18</td><td>Host Data 15</td></tr><tr><td>19</td><td>Ground</td><td>20</td><td>Key</td></tr><tr><td>21</td><td>DRQ3</td><td>22</td><td>Ground</td></tr><tr><td>23</td><td>I/O Write</td><td>24</td><td>Ground</td></tr><tr><td>25</td><td>I/O Read</td><td>26</td><td>Ground</td></tr><tr><td>27</td><td>IOCHRDY</td><td>28</td><td>BALE</td></tr><tr><td>29</td><td>DACK3</td><td>30</td><td>Ground</td></tr><tr><td>31</td><td>IRQ14</td><td>32</td><td>IOCS16</td></tr><tr><td>33</td><td>Addr1</td><td>34</td><td>Ground</td></tr><tr><td>35</td><td>Addr0</td><td>36</td><td>Addr2</td></tr><tr><td>37</td><td>Chip Select 0</td><td>38</td><td>Chip Select 1</td></tr><tr><td>39</td><td>Activity</td><td>40</td><td>Ground</td></tr></table>

![](images/7e1f876775b30fc3b48ff0d7073443945f7fc7ab2060de0599a92d7261a074f4.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph TD
    subgraph Top_Layer
        A["KB Mouse"] --> B["USB 0/1/2/3"]
        C["COM1"] --> D["Parallel Port"]
        E["LAN1/2"] --> F["HD Audio"]
        G["SUPER• X7DWA-N"] --> H["Slot7 IPM"]
        I["GLAN CTLR"] --> J["Slot5 PCI-Exp x16"]
        K["IPL1"] --> L["Slot5 PCI-33MHz"]
        M["Slot4"] --> N["PCI-Exp x16"]
        O["JWD"] --> P["Slot3 PCI 33 MHz"]
        Q["Slot2"] --> R["PCI-X 133/100 MHz"]
        S["JWORF"] --> T["Slot1 PCI-X 132/100 MHz"]
        U["IPME"] --> V["Slot0 PCI-U"]
    end

    subgraph Bottom_Layer
        W["CPU1"] --> X["CPU2"]
        Y["CPU2"] --> Z["CPU"]
        AA["CPU2"] --> AB["CPU"]
        AC["CPU2"] --> AD["CPU"]
        AE["CPU2"] --> AF["CPU"]
        AG["CPU2"] --> AH["CPU"]
        AI["CPU2"] --> AJ["CPU"]
        AK["CPU2"] --> AL["CPU"]
        AM["CPU2"] --> AN["CPU"]
        AO["CPU2"] --> AP["CPU"]
        AQ["CPU2"] --> AR["CPU"]
        AS["CPU2"] --> AT["CPU"]
        AU["CPU2"] --> AV["CPU"]
        AW["CPU2"] --> AX["CPU"]
        AY["8-pin PWR"] --> AZ["FP Control"]
        BA["SGPOI"] --> BB["Buzzer"]
        BC["BIOIS"] --> BD["Puppy"]
        BE["Battery"] --> BF["SIO"]
        BG["SATO"] --> BH["SATA1"]
        BI["SATA2"] --> BJ["SATA3"]
        BK["SATA4"] --> BL["SATA5"]
        BM["JCOM2"] --> BN["JBT1"]
        BO["CLEAR CMOS Che Intu."] --> BP["JBT1"]
    end

    style Top_Layer fill:#f9f,stroke:#333
    style Bottom_Layer fill:#ccf,stroke:#333

A. IDE#1 B. IDE#2 (Compact Flash)

Notes

Chapter 3 Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the 'Technical Support Procedures' and/or 'Returning Merchandise for Service' section(s) in this chapter.

Note: Always disconnect the power cord before adding, changing or installing any hardware components.

Before Power On

1. Make sure that there are no short circuits between the motherboard and chassis.
2. Disconnect all ribbon/wire cables from the motherboard, including those for the keyboard and mouse.
3. Remove all add-on cards.
4. Install one CPU (making sure it is fully seated) and connect the chassis speaker and the power LED to the motherboard. (Check all jumper settings as well.)

No Power

1. Make sure that there are no short circuits between the motherboard and chassis..
2. Make sure that all jumpers are set to their default positions.
3. Check that the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your motherboard may be old. Check to make sure that it still supplies \~3VDC. If it does not, replace it with a new one.

No Video

1. If the power is on but you have no video, remove all the add-on cards and cables.
2. Use the speaker to determine if any beep codes exist. Refer to Appendix B for details on beep codes.
3. Remove all memory modules and turn on the system. (If the alarm is on, check the specs of the memory, reset the memory or try a different one.)

Losing the System's Setup Configuration

1. Make that you are using a high quality power supply. A poor quality power supply may cause the system to lose the CMOS setup information. Refer to Section 1-6 for details on recommended power supplies.
2. The battery on your motherboard may be old. Check to verify that it still supplies \~3VDC. If it does not, replace it with a new one.
3. If the above steps do not fix the Setup Configuration problem, contact your vendor for repairs.

Note

If you are a system integrator, VAR or OEM, a POST diagnostics card is recommended. For I/O port 80h codes, refer to App. B.

Memory Errors

1. Make sure the DIMM modules are properly and fully installed.
2. Check if different speeds of DIMMs have been installed, and make sure that the BIOS setup is configured for the fastest speed of RAM used. It is recommended to use the same RAM speed for all DIMMs in the system.
3. Make sure you are using the correct type of DDR2 FBD (Fully Buffered) ECC 800/667/533 SDRAM (recommended by the manufacturer). Also make sure that the type of memory used is supported by the CPU installed on the motherboard. Refer to Page 2-6 for more information.
4. Check for bad DIMM modules or slots by swapping a single module between four slots and noting the results.
5. Make sure all memory modules are fully seated in their slots. As an interleaved memory scheme is used, you must install two modules at a time, beginning with 1A, then 1B, and so on (see Page 2-6).
6. Check the position of the 115V/230V switch on the power supply.

3-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, Note that as a motherboard manufacturer, Super Micro does not sell directly to end-users, so it is best to first check with your distributor or reseller for troubleshooting services. They should know of any possible problem(s) with the specific system configuration that was sold to you.

1. Please go through the 'Troubleshooting Procedures' and 'Frequently Asked Question' (FAQ) sections in this chapter or see the FAQs on our web site (http://www.supermicro.com/support/faqs/) before contacting Technical Support.

2. BIOS upgrades can be downloaded from our web site at (http://www.supermicro.com/support/bios/)

Note: Not all BIOS can be flashed; it depends on the modifications to the boot block code.

1. If you still cannot resolve the problem, include the following information when contacting Super Micro for technical support:

2. Motherboard model and PCB revision number

3. BIOS release date/version (this can be seen on the initial display when your system fi rst boots up)

- System configuration

An example of a Technical Support form is on our web site at (http://www.supermicro.com/support/contact.cfm).

1. Distributors: For immediate assistance, please have your account number ready when placing a call to our technical support department. We can be reached by e-mail at [e-mail] or by fax at: [phone], option 2.

3-3 Frequently Asked Questions

Question: What are the various types of memory that my motherboard can support?

Answer: The X7DWA-N has eight 240-pin DIMM slots that support DDR2 FBD ECC 800/667/533 SDRAM modules. It is strongly recommended that you do not mix memory modules of different speeds and sizes.

Question: How do I update my BIOS?

Answer: It is recommended that you do not upgrade your BIOS if you are not experiencing any problems with your system. Updated BIOS files are located on our web site at http://www.supermicro.com/support/bios/. Please check our BIOS warning message and the information on how to update your BIOS on our web site. Select your motherboard model and download the BIOS file to your computer. Also, check the current BIOS revision and make sure that it is newer than your BIOS before downloading. You can choose from the zip file and the .exe file. If you choose the zip BIOS file, please unzip the BIOS file onto a bootable USB device. Run the batch file using the format flash.bat filename.rom from your bootable USB device to flash the BIOS. Then, your system will automatically reboot. If you choose the .exe file, please run the .exe file under Windows to create the BIOS flash floppy disk. Insert the floppy disk into the system you wish to flash the BIOS. Then, bootup the system to the floppy disk. The BIOS utility will automatically flash the BIOS without

any prompts. Please note that this process may take a few minutes to complete. Do not be concerned if the screen is paused for a few minutes.

Warning: Do not shut down or reset the system while updating BIOS to prevent possible system boot failure!

Question: What's on the CD that came with my motherboard?

Answer: The supplied compact disc has quite a few drivers and programs that will greatly enhance your system. We recommend that you review the CD and install the applications you need. Applications on the CD include chipset drivers for the Windows OS, security and audio drivers.

3-4 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your vendor for a Returned Merchandise Authorization (RMA) number. When returning to the manufacturer, the RMA number should be prominently displayed on the outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and handling charges will be applied for all orders that must be mailed when service is complete.

For faster service, you can also request a RMA authorization online (http://www.supermicro.com/support/rma/).

This warranty only covers normal consumer use and does not cover damage incurred in shipping or from failure due to the alternation, misuse, abuse or improper maintenance of products.

During the warranty period, contact your distributor first for any product problems.

Chapter 4

BIOS

4-1 Introduction

This chapter describes the Phoenix BIOS™ Setup utility for the X7DWA-N. The Phoenix ROM BIOS is stored in a flash chip and can be easily upgraded using a fi oppy disk-based program.

Note: Due to periodic changes to the BIOS, some settings may have been added or deleted and might not yet be recorded in this manual. Please refer to the Manual Download area of the Supermicro web site http://www.supermicro.com for any changes to the BIOS that may not be reflected in this manual.

System BIOS

BIOS is the Basic Input Output System used in all IBM ^ PC, XT ^TM , AT ^ , and PS/2 ^ compatible computers. The Phoenix BIOS utility stores the system parameters, types of disk drives, video displays, etc. in the CMOS. CMOS memory requires very little electrical power. When the computer is turned off, a backup batt provides power to the CMOS Logic, enabling it to retain system parameters. When the computer is powered on, the computer is configured with the values stored in the CMOS Logic by the system BIOS, which gains control at boot up.

How To Change the Configuration Data

CMOS information that determines the system parameters may be changed by entering the BIOS Setup utility. This Setup utility can be accessed by pressing the key at the appropriate time during system boot.

Starting the Setup Utility

Normally, the only visible POST (Power On Self Test) routine is the memory test. As the memory is being tested, press the key to enter the main menu of the BIOS Setup utility. From the main menu, you can access the other setup screens, such as the Security and Power menus. Beginning with Section 4-3, detailed descriptions are given for each parameter setting in the Setup utility.

Warning: Do not shut down or reset the system while updating BIOS

ent possible boot failure.

4-2 Running Setup

Default settings are in bold text unless otherwise Noted.

The BIOS setup options described in this section are selected by choosing the appropriate text from the main BIOS Setup screen. All displayed text is described in this section although the screen display is often all you need to understand how to set the options as shown on the following page.

When you first power on the computer, the Phoenix BIOS ^™ is immediately activated.

While the BIOS is in control, the Setup program can be activated in one of two ways:

1. By pressing immediately after turning the system on, or
2. When the message shown below appears briefly at the bottom of the screen during the POST (Power On Self-Test), press the key to activate the main Setup menu:

Press the key to enter Setup

4-3 Main BIOS Setup

All main Setup options are described in this section. The main BIOS Setup screen is displayed below.

Use the Up/Down arrow keys to move among the different settings in each menu. Use the Left/Right arrow keys to change the options for each setting.

Press the key to exit the CMOS Setup Menu. The next section describes in detail how to navigate through the menus.

Items that use submenus are indicated with the ▶icon. With the item highlighted, press the key to access the submenu.

Main BIOS Setup Menu

PhoenixBIOS Setup Utility Main Advanced Security Boot Exit System Time: [14:34:03] System Date: [07/27/2009] BIOS Date 05/29/09 Legacy Diskette A: [1.44/1.25 MB ] IDE Channel 0 Master [None] IDE Channel 0 Slave [None] SATA Port 0 [None] SATA Port 1 [None] SATA Port 2 [None] SATA Port 3 [None] Parallel ATA: [Enabled] Serial ATA: [Enabled] SATA Controller Mode Option: [Enhanced] SATA RAID Enable [Disabled] Item Specific Help , , or selects field.

Main Setup Features

System Time

To set the system date and time, key in the correct information in the appropriate fields. Then press the key to save the data.

System Date

Using the arrow keys, highlight the month, day and year fields, and enter the correct data. Press the key to save the data.

BIOS Date

This field displays the date when this version of BIOS was built.

Legacy Diskette A

This setting allows the user to set the type of floppy disk drive installed as diskette A. The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb 3.5 in, 1.44/1.25MB, 3.5 in and 2.88MB 3.5 in.

▶IDE Channel 0 Master/Slave, SATA Port 1, SATA Port 2, SATA Port 3 and SATA Port 4

These settings allow the user to set the parameters for the slots indicated above. Press to activate the following submenu screen for options of these items. Set the correct configurations accordingly. The items included in the submenu are:

Type

This option allows the user to select the type of the HDD drive. Select Auto for the BIOS to automatically configure the parameters of the HDD installed at the connection. Enter a number between 1 to 39 to select a predetermined HDD type. Select User to allow the user to enter the parameters of the HDD installed. Select CDROM if a CDROM drive is installed. Select ATAPI if a removable disk drive is installed.

Multi-Sector Transfers

This item allows the user to specify the number of sectors per block to be used in multi-sector transfer. The options are Disabled, 4 Sectors, 8 Sectors, and 16 Sectors.

LBA Mode Control

This item determines whether the Phoenix BIOS will access the IDE Channel 0 Master Device via the LBA mode. The options are Enabled and Disabled.

32 Bit I/O

This option allows the user to enable or disable the function of 32-bit data transfer. The options are Enabled and Disabled.

Transfer Mode

This option allows the user to set the transfer mode. The options are Standard, Fast PIO1, Fast PIO2, Fast PIO3, Fast PIO4, FPIO3/DMA1 and FPIO4/DMA2.

Ultra DMA Mode

This option allows the user to select Ultra DMA Mode. The options are Disabled, Mode 0, Mode 1, Mode 2, Mode 3, Mode 4, and Mode 5.

Parallel ATA

This setting allows the user to enable the function of Parallel ATA. The options are Disabled, and Enable.

Serial ATA

Select Enabled to enable Serial ATA support. The options are Disabled and Enabled.

Native Mode Operation (Available when the SATA Controller Mode Option is set to Compatible.)

This option allows the user to select the native mode for ATA. The options are Serial ATA and Auto. Note: Some operating systems might not be supported by Native Mode.

SATA Controller Mode Option

Select Compatible for the BIOS to automatically detect the SATA and PATA drives and place them in the Legacy Mode. Select Enhanced (non-AHCI) for the BIOS to automatically detect the SATA and PATA drives and place them in the Native IDE Mode. (Note: The Enhanced mode is supported by the Windows 2000 or a later version of OS.)

When the SATA Controller Mode is set to Enhanced, the following items will display:

Serial ATA (SATA) RAID Enable

Select Enable to enable Serial ATA RAID Functions. (For the Windows OS environment, use the RAID driver if this feature is set to Enabled. When this item is set to Enabled, the following option "ICH RAID Code Base" will become available, so you can use Intel or Adaptec Host RAID firmware to configure your RAID settings. If SATA RAID is set to Disabled, the item-SATA AHCI Enable will be available.) The options are Enabled and Disabled.

ICH RAID Code Base

Select Intel to enable Intel's SATA RAID firmware. Select Adaptec to use Adaptec's HostRAID firmware. The options are Intel and Adaptec.

SATA AHCI Enable

Select Enable to enable Serial ATA Advanced Host Interface support. (Take caution when using this function. It is for advanced programmers only. The options are Enabled and Disabled.)

System Memory

This display informs you how much system memory is detected by the BIOS in the system.

Extended Memory

This display informs you how much extended memory is detected by the BIOS in the system.

4-4 Advanced Setup

Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. The items with a triangle beside them have sub menus that can be accessed by highlighting the item and pressing .

Main Advanced Security Boot Exit
▶ Boot Features ▶ Memory Cache ▶ PCI Configuration ▶ Advanced Chipset Control ▶ Advanced Processor Options ▶ I/O Device Configuration ▶ DMI Event Logging ▶ Console Redirection ▶ Hardware Monitor ▶ IPMI	Item Specific Help
	Select Boot features

▶Boot Features

Access the submenu to make changes to the following settings.

QuickBoot Mode

If enabled, this feature will speed up the POST (Power On Self Test) routine by skipping certain tests after the computer is turned on. The settings are Enabled and Disabled. If Disabled, the POST routine will run at normal speed.

QuietBoot Mode

This setting allows you to Enable or Disable the graphic logo screen during boot-up.

POST Errors

Set to Enabled to display POST Error Messages if an error occurs during bootup. If set to Disabled, the system will continue to boot without displaying any error message even when a boot error occurs.

ACPI Mode

Use the setting to determine if you want to employ ACPI (Advanced Configuration and Power Interface) power management on your system. The options are Yes and No.

Power Button Behavior

If set to Instant-Off, the system will power off immediately as soon as the user hits the power button. If set to 4-sec., the system will power off when the user

presses the power button for 4 seconds or longer. The options are instant-off and 4-sec override.

Resume On Modem Ring

Select On to "wake your system up" when an incoming call is received by your modem. The options are On and Off.

EFI OS Boot

If enabled, this feature provides support for EFI OS booting. The options are Enabled and Disabled.

Power Loss Control

This setting allows you to choose how the system will react when power returns after an unexpected loss of power. The options are Stay Off, Power On, and Last State.

Watch Dog

If enabled, this option will automatically reset the system if the system is not active for more than a predefined time period. The options are Enabled and Disabled.

Summary Screen

This setting allows you to Enable or Disable the summary screen which displays the system configuration during bootup.

▶ Memory Cache

Cache System BIOS Area

This setting allows you to designate a reserve area in the system memory to be used as a System BIOS buffer to allow the BIOS to write (cache) data into this reserved memory area. Select Write Protect to enable the function and reserve this area for the Video BIOS ROM access only. Select Uncached to disable this function and make this area available for other devices.

Cache Video BIOS Area

This setting allows you to designate a reserve area in the system memory to be used as a Video BIOS buffer to allow the BIOS to write (cache) data into this reserved memory area. Select Write Protect to enable the function and reserve this area for the Video BIOS ROM access only. Select Uncached to disable this function and make this area available for other devices.

Cache Base 0-512K

If enabled, this feature will allow the data stored in the base memory area: block 0-512K to be cached (written) into a buffer, a storage area in the Static DROM (SDROM) or to be written into L1, L2 cache inside the CPU to speed up CPU operations. Select Uncached to disable this function. Select Write Through to allow data to be cached into the buffer and written into the system memory at the same time. Select Write Protect to prevent data from being written into the base memory area of Block 0-512K. Select Write Back to allow the CPU to write data back directly from the buffer without writing data to the System Memory for fast CPU data processing and operation. The options are Uncached, Write Through, Write Protect, and Write Back.

Cache Base 512K-640K

If enabled, this feature will allow the data stored in the memory area: 512K-640K to be cached (written) into a buffer, a storage area in the Static DROM (SDROM) or written into L1, L2 or L3 cache inside the CPU to speed up CPU operations. Select Uncached to disable this function. Select Write Through to allow data to be cached into the buffer and written into the system memory at the same time. Select Write Protect to prevent data from being written into the base memory area of Block 512-640K. Select Write Back to allow the CPU to write data back directly from the buffer without writing data to the system memory to speed up CPU's operation. The options are Uncached, Write Through, Write Protect, and Write Back.

Cache Extended Memory

If enabled, this feature will allow the data stored in the extended memory area to be cached (written) into a buffer, a storage area in the Static DROM (SDROM) or written into L1, L2, L3 cache inside the CPU to speed up CPU operations. Select Uncached to disable this function. Select Write Through to allow data to be cached into the buffer and written into the system memory at the same time. Select Write Protect to prevent data from being written into the extended memory area above 1 MB. Select Write Back to allow the CPU to write data back directly from the buffer without writing data to the System Memory for fast CPU data processing and operation. The options are Uncached, Write Through, Write Protect, and Write Back.

Discrete MTRR Allocation

If enabled, MTRRs (-Memory Type Range Registers) are configured as distinct, separate units and cannot be overlapped. If enabled, the user can achieve better graphic effects when using a Linux graphic driver that requires the write-combining configuration with 4GB or more memory. The options are Enabled and Disabled.

▶PCI Configuration

Access the submenu to make changes to the following settings for PCI devices.

Onboard GLAN1/Onboard GLAN2 (Gigabit-LAN) OPROM Configure

Select Enabled to allow the system to boot from the GLAN1 connection or the GLAN 2 connection. The options are Disabled and Enabled.

IPMI 3rd-LAN OPROM Configure (Available only for the IPMI with Data LAN)

Select Enabled to allow the system to boot from the IPMI 3rd-LAN connection. The options are Disabled and Enabled.

Option ROM Replacement

Set to Enabled to use the Option ROM Replacement feature. If this feature is enabled, and the system hangs, please reboot the system and change the setting. The options are Enabled and Disabled.

ROM Scan Ordering

This feature allows the user to decide which Option ROM to be activated first. The options are Onboard first and Add-On first.

PCI Parity Error Forwarding

The feature allows SERR and PERR errors detected in PCI slots to be sent (forwarded) to the BIOS DMI Event Log for the user to review. The options are Enabled and Disabled.

PCI Fast Delayed Transaction

Enable this function to improve the DMA data transfer rate for a PCI 32-bit multimedia card. The options are Enable and Disabled.

Reset Configuration Data

If set to Yes, this setting clears the Extended System Configuration Data- (ESCD) area. The options are Yes and No.

Frequency for PCI-X#1\~PCI-X#2

This option allows the user to change the bus frequency for the devices installed in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66 MHz, PCI-X 100 MHz, and PCI-X 133 MHz.

▶Slot0 PCI-U. x8, Slot1 PCI-X 133 MHz, Slot2 PCI-X 133 MHz, Slot3 PCI-Exp. x8, Slot4 PCI-Exp x4, Slot5 PCI-Exp. x8, and Slot6 PCI-Exp x8

Access the submenu for each of the settings above to make changes to the following:

Option ROM Scan

When enabled, this setting will initialize the device expansion ROM. The options are Enabled and Disabled.

Enable Master

This setting allows you to enable the selected device as the PCI bus master. The options are Enabled and Disabled.

Latency Timer

This setting allows you to set the clock rate for Bus Master. A high-priority, high-throughput device may benefit from a greater clock rate. The options are Default, 0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novell and other Operating Systems, please select the option: other. If a drive fails after the installation of a new software, you might want to change this setting and try again. A different OS requires a different Bus Master clock rate.

Large Disk Access Mode

This setting determines the size of the hard drive to be accessed the OS. The options are DOS or Other (for Unix, Novelle NetWare and other operating systems).

▶Advanced Chipset Control

Access the submenu to make changes to the following settings.

Warning: Take caution when changing the Advanced settings. An Incorrect value, a very high DRAM frequency or an incorrect DRAM timing may cause system to become unstable. When this occurs, reset the setting to the default setting.

SERR Signal Condition

This setting specifies the ECC Error conditions that an SERR# is to be asserted. The options are None, Single Bit, Multiple Bit, and Both.

Clock Spectrum Feature

If Enabled, the BIOS will enable the Clock Spectrum feature in the Clock Generator. It aims at reducing the level of Electromagnetic Interference caused by the components whenever is needed. The options are Enabled and Disabled.

Intel VT for Directed I/O

Select Enabled to bring up the following Intel VT for Directed I/O (VT-d) Configuration submenu. The options are Enabled and Disabled.

VT-d for Direct I/O

Select Enabled to enable VT-d support for DRHD Structure support in the ACPI Tables during POST. The options are Disabled and Enabled.

4GB PCI Hole Granularity

This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs are not enough, this option may be used to reduce MTRR occupation. The options are: 256 MB, 512 MB, 1GB and 2GB.

Memory Voltage

This feature allows the user to set the memory voltage for the onboard memory modules. Select Auto to allow the BIOS to automatically detect the onboard memory voltage according to the SPD (Serial Presence Detect.) Select 1.5V to force the memory modules to run at 1.5V in order to accommodate lower power fully buffered DIMM modules. Select 1.8V to force memory modules to run on 1.8V for testing. When set to 1.8V, damage may occur to memory modules that only support 1.5V. The options are: Auto, 1.5V and 1.8V.

Memory Branch Mode

This option determines how the two memory branches operate. System address space can either be interleaved between the two branches or Sequential from one branch to another. Mirror mode allows data correction by maintaining two copies of data in two branches. Single Channel 0 allows a single DIMM population during system manufacturing. The options are Interleave, Sequential, Mirroring, and Single Channel 0.

Branch 0 Rank Sparing/Branch 1 Rank Sparing

Select Enable to enable the function of memory sparing for Memory Branch 0 or Branch 1. The options are Enabled and Disabled.

Branch 0 Rank Interleaving/Branch 1 Rank Interleaving

Select enable to enable Interleaved Memory for Memory Branch 0 Rank or Branch 1 Rank. The options for Memory Interleaving are 1:1, 2:1 and 4:1.

Enhanced x8 Detection

Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options are Disabled and Enabled.

Demand Scrubbing

Scrubbing is a process that allows the North Bridge to correct correctable memory errors found on an FBD memory module. When the CPU or I/O issues a demand-read command, and the read data from memory turns out to be a correctable ECC, it is corrected and sent to the original source. Memory is updated as well. Select Enabled to use Demand Scrubbing for ECC memory correction. The options are Enabled and Disabled.

High Temperature DRAM Operation

When set to Enabled, the BIOS will refer to the SPD table to set the maximum DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature based on a predefined value. The options are Enabled and Disabled.

AMB Thermal Sensor

Select Enabled to enable the thermal sensor embedded in the Advanced Memory Buffer on a fully buffered memory module for thermal monitoring. The options are Disabled and Enabled.

Thermal Throttle

Select Enabled to enable closed-loop thermal throttling on a fully buffered (FBD) memory module. In the closed-loop thermal environment, thermal throttling will be activated when the temperature of the FBD DIMM module exceeds a predefined threshold. The options are Enabled and Disabled.

Global Activation Throttle

Select Enabled to enable the function of open-loop global thermal throttling on the fully buffered (FBD) memory modules and allow global thermal throttling to become active when the number of activate control exceeds a predefined number. The options are Enabled and Disabled.

Force ITK Configuration Clocking

Select Enabled to configure FBD clock settings to support ITK testing. The options are Disabled and Enabled.

Snoop Filter

Select Enabled to eliminate snoop traffic to the graphics port to greatly improve system performance when running graphics intensive applications. The options are Enabled and Disabled.

I/OAT2

Select Enabled to use the Intel I/O AT (Acceleration Technology) to accelerate the performance of TOE devices. (Note: A TOE device is a specialized, dedicated processor that is installed on an add-on card or a network card to handle some or all packet processing of this add-on card. For this motherboard, the TOE device is built inside the ESB 2 South Bridge chip.) The options are Enabled and Disabled.

Max Payload Size

Some add-on cards perform faster with the coalesce feature, which limits the payload size to 128 MB; while others, with a payload size of 256 MB which inhibits the coalesce feature. Please refer to your add-on card user guide for the desired setting. The options are 256 MB, 128MB, and Auto.

PCI-Exp. Speed

When this item is set to Auto, BIOS will configure PCI-Exp slots to run at the highest speed possible. When this item is set to "Force Gen1", BIOS will configure PCI-Exp slots to run at the speed of Gen1. When this item is set to "By H/W Default", BIOS will configure PCI-Exp slots to run at the hardware default speeds. (ie: A PCI-Exp. Gen2 device will run at Gen2 speed.) The options are Auto, Force Gen1, and By H/W Default.

Route Port 80h Cycles to

This feature allows the user to decide which bus to send debug information to. The options are Disabled, PCI and LPC.

High Precision Event Time

Select Yes to activate the High Precision Event Timer (HPET) to produce periodic interrupts at a higher frequency than a Real-time Clock (RTC) can in synchronizing multimedia streams, providing smooth playback and reducing the dependency on other timestamp calculation devices, such as an x86 RDTSC Instruction embedded in a CPU. The High Precision Event Timer is used to replace the 8254 Programmable Interval Timer. The options are Yes and No.

USB Function

Select Enabled to enable the function of USB devices specified. The settings are Enabled and Disabled.

Legacy USB Support

This setting allows you to enable support for Legacy USB devices. The settings are Enabled and Disabled.

▶Advanced Processor Options

Access the submenu to make changes to the following settings.

CPU Speed

This is a display that indicates the speed of the installed processor.

Frequency Ratio (Available if supported by the CPU.)

The feature allows the user to set the internal frequency multiplier for the CPU. The options are: Default, x12, x13, x14, x15, x16, x17 and x18.

Set to Enabled to use a processor's Second Core and beyond. (Please refer to Intel's web site for more information.) The options are Disabled and Enabled.

Machine Checking (Available if supported by the CPU)

Set to Enabled to enable Machine Checking support and allow the CPU to detect and report hardware (machine) errors via a set of model-specific registers (MSRs). The options are Disabled and Enabled.

Fast String Operations (Available if supported by the CPU)

Set to Enabled to enable the fast string operations for special CPU instructions. The options are Disabled and Enabled.

Thermal Management 2 (Available if supported by the CPU)

Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage and frequency when the CPU temperature reaches a predefined overheat threshold. Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be regulated via CPU Internal Clock modulation when the CPU temperature reaches the overheat threshold.

C1/C2 Enhanced Mode (Available if supported by the CPU)

Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to prevent overheat. The options are Enabled and Disabled. (Note: please refer to Intel's web site for detailed information.)

Execute Disable Bit (Available if supported by the CPU and the OS)

Set to Enabled to enable Execute Disable Bit and allow the processor to classify areas in memory where an application code can execute and where it cannot, and thus preventing a worm or a virus from inserting and creating a flood of codes to overwhelm the processor or damage the system during an attack. Note: this feature is available when your OS and your CPU support the function of Execute Disable Bit. The options are Disabled and Enabled. For more information, please refer to Intel's and Microsoft's web sites.

Adjacent Cache Line Prefetch (Available if supported by the CPU.)

The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The CPU fetches both cache lines for 128 bytes as comprised if Enabled. The options are Disabled and Enabled.

Hardware Prefetch (Available if supported by the CPU.)

Set to this option to Enabled to enable the hardware components that are used in conjunction with software programs to prefetch data in order to speed up data processing. The options are Disabled and Enabled.

Set Maximum Ext. CPUID=3

When set to Enabled, the Maximum Extended CPUID will be set to 3. The options are Disabled and Enabled.

Direct Cache Access (Available when supported by the CPU)

Set to Enable to route inbound network IO traffic directly into processor caches to reduce memory latency and improve network performance. The options are Disabled and Enabled.

DCA Delay Clocks (Available if supported by the CPU)

This feature allows the user to set the clock delay setting from snoop to prefetch for Direct Cache Access. Select a setting from 8 (bus cycles) to 120 (bus cycles) (in 8-cycle increment). The default setting is 32 (bus cycles).

Intel Virtualization Technology (Available if supported by the CPU)

Select Enabled to use the feature of Virtualization Technology to allow one platform to run multiple operating systems and applications in independent partitions, creating multiple "virtual" systems in one physical computer. The options are Enabled and Disabled. (Note: If there is any change to this setting, you will need to power off and restart the system for the change to take effect.) Please refer to Intel's web site for detailed information.

SMRR Control (Available if supported by the CPU)

Select Enabled to use the feature of System Management Mode Address Register which will make the memory region specified in the register uncacheable while not executing in SMM (System Management Mode). This feature will protect your system by preventing an external program (including a virus) from using SMM. The options are Enabled and Disabled. Please refer to Intel's web site for detailed information.

Intel EIST Support (Available if supported by the CPU)

Select Enabled to use the Enhanced Intel SpeedStep Technology and allows the system to automatically adjust processor voltage and core frequency in an effort to reduce power consumption and heat dissipation. The options are Enabled and Disabled. Please refer to Intel's web site for detailed information.

▶ I/O Device Configuration

Access the submenu to make changes to the following settings.

KBC Clock Input

This setting allows you to select clock frequency for the keyboard controller. The options are 6MHz, 8MHz, 12MHz, and 16MHz.

Serial Port A

This setting allows you to determine how Serial Port A is controlled. The options

are Enabled (user defined), Disabled, and Auto (BIOS- or OS- controlled).

Base I/O Address

This setting allows you to select the base I/O address for Serial Port A. The options are 3F8, 2F8, 3E8, and 2E8.

Interrupt

This setting allows you to select the IRQ (interrupt request) for Serial Port A. The options are IRQ3 and IRQ4.

Serial Port B

This setting allows you to determine how Serial Port B is controlled. The options are Enabled (user defined), Disabled, Auto (BIOS- and OS-Controlled).

Mode

This setting allows you to set the type of device that will be connected to Serial Port B. The options are Normal and IR (for an infrared device).

Base I/O Address

This setting allows you to select the base I/O address for Serial Port B. The options are 3F8, 2F8, 3E8 and 2E8.

Interrupt

This setting allows you to select the IRQ (interrupt request) for Serial Port B. The options are IRQ3 and IRQ4.

Floppy Disk Controller

This setting allows you to decide how the floppy disk drive is controlled in the system. The options are Enabled (user defined), Disabled, and Auto (BIOS and OS controlled).

Base I/O Address

This setting allows you to select the base I/O address for the floppy disk drive. The options are Primary and Secondary.

▶DMI Event Logging

Access the submenu to make changes to the following settings.

Event Log Validity

This is a display to inform you of the event log validity. It is not a setting.

Event Log Capacity

This is a display to inform you of the event log capacity. It is not a setting.

View DMI Event Log

Highlight this item and press to view the contents of the event log.

Event Logging

This setting allows you to Enable or Disable event logging.

ECC Event Logging

This setting allows you to Enable or Disable ECC event logging.

Mark DMI Events as Read

Highlight this item and press to mark the DMI events as read.

Clear All DMI Event Logs

Select Yes and press to clear all DMI event logs. The options are Yes and No.

▶Console Redirection

Access the submenu to make changes to the following settings.

COM Port Address

This item allows you to specify which COM port to direct the remote console to: Onboard COM A or Onboard COM B. This setting can also be Disabled.

BAUD Rate

This item allows you to set the BAUD rate for console redirection. The options are 300, 1200, 2400, 9600, 19.2K, 38.4K, 57.6K, and 115.2K.

Console Type

This item allows you to set console redirection type. The options are VT100, VT100,8bit, PC-ANSI, 7bit, PC ANSI, VT100+, VT-UTF8 and ASCII.

Flow Control

This item allows you to select the flow control option for the console. The options are: None, XON/XOFF, and CTS/RTS.

Console Connection

This item allows you to decide how console redirection is to be connected: either Direct or Via Modem.

Continue CR after POST

Select on to continue with console redirection after the POST routine. The options are On and Off.

▶Hardware Monitor

This feature allows the user to monitor system health and review the status of each item as displayed.

Overheat Alarm

This option allows the user to select the CPU Overheat Alarm setting which determines when the CPU OH alarm will be activated to provide warning of possible CPU overheat.

Warning! 1. Any temperature that exceeds the CPU threshold temperature predefined by the CPU manufacturer may result in CPU overheat or system instability. When the CPU temperature reaches this predefined threshold, the CPU and system cooling fans will run at full speed.

1. To avoid possible system overheating, please be sure to provide adequate airflow to your system.

The options are:

- Early Trigger: Select this setting if you want the CPU overheat alarm (including the LED and the buzzer) to be triggered as soon as the CPU temperature reaches the CPU overheat threshold as predefined by the CPU manufacturer.

- Normal trigger setting if you want the CPU overheat alarm (including the LED and the buzzer) to be triggered when the CPU temperature reaches about 5°C above the threshold temperature as predefined by the CPU manufacturer to give the CPU and system fans additional time needed for CPU and system cooling. In both the alarms above, please take immediate action as shown below.

CPU Temperature/System Temperature

Note: The following item display current temperature readings for the CPU and the system. These items are displayed for your reference only.

CPU1 Temperature/CPU2 Temperature

The CPU Temperature feature will display the CPU temperature status as detected by the BIOS:

Low - This level is considered as the 'normal' operating state. The CPU temperature is well below the CPU 'Temperature Tolerance'. The motherboard fans and CPU will run normally as configured in the BIOS (Fan Speed Control).

Medium – The processor is running warmer. This is a ‘precautionary’ level and generally means that there may be factors contributing to this condition, but

the CPU is still within its normal operating state and below the CPU 'Temperature Tolerance'. The motherboard fans and CPU will run normally as configured in the BIOS. The fans may adjust to a faster speed depending on the Fan Speed Control settings.

High – The processor is running hot. This is a ‘caution’ level since the CPU’s ‘Temperature Tolerance’ has been reached (or has been exceeded) and may activate an overheat alarm. The system may shut down if it continues for a long period to prevent damage to the CPU.

User intervention: If the system buzzer and Overheat LED has activated, take action immediately by checking the system fans, chassis ventilation and room temperature to correct any problems.

System Temperature

Fan1-Fan8 Speeds: If the feature of Auto Fan Control is enabled, the BIOS will automatically display the status of the fans indicated in this item.

Fan Speed Control Modes

This feature allows the user to decide how the system controls the speeds of the onboard fans. The CPU temperature and the fan speed are correlative. When the CPU on-die temperature increases, the fan speed will also increase, and vice versa. Select Workstation if your system is used as a Workstation. Select Server if your system is used as a Server. Select 3-pin if your chassis uses 3-pin fans. Select 4-pin if your chassis uses 4-pin fans. Select "Disable" to disable the fan speed control function and allow the onboard fans to constantly run at full speed (12V). The Options are: 1. Disable (Full Speed), 2. 3-pin (Server), and 3. 3-pin (Workstation).

Voltage Monitoring

The following items will be monitored and displayed:

VcoreA/VcoreB

+12V/-12V

+5Vsb/+5VDD

+3.3V

P1V5/CPU_VTT/Vbat

Note: In the Windows OS environment, the Supero Doctor III settings take precedence over the BIOS settings. When first installed, Supero Doctor III adopts the temperature threshold settings previously set in the BIOS. Any subsequent changes to these thresholds must be made within Supero Doctor, since the SD III settings override the BIOS settings. For the Windows OS to adopt the BIOS temperature threshold settings, please change the SDIII settings to be the same as those set in the BIOS.

▶IPMI (The option is available only when an IPMI card is installed in the system.)

PhoenixBIOS Setup Utility Advanced
IPMI	Item Specific Help
IPMI Specification Version 2.0 Firmware Version 2.1 System Event Logging [Enabled] Clear System Event Log [Disabled] Existing Event Log number 282 Event Log Control SYS Firmware Progress [Disabled] BIOS POST Errors [Enabled]	Enable/Disable IPMI event logging. Disabling will still log events received via the system interface.
BIOS POST Watchdog [Disabled] OS boot Watchdog [Disabled] Timer for loading OS (min) [10] Time out action [No Action]

IPMI Specification Version: This item displays the current IPMI Version.

Firmware Version: This item displays the current Firmware Version.

System Event Logging

Select Enabled to enable IPMI Event Logging. When this function is set to Disabled, the system will continue to log events received via system interface. The options are Enabled and Disabled.

Clear System Event Logging

Enabling this function to force the BIOS to clear the system event logs during the next cold boot. The options are Enabled and Disabled.

Existing Event Log Number

This item displays the number of the existing event log.

Event Log Control

System Firmware Progress

Enabling this function to log POST progress. The options are Enabled and Disabled.

BIOS POST Errors

Enabling this function to log POST errors. The options are Enabled and Disabled.

BIOS POST Watch Dog

Set to Enabled to enable POST Watch Dog. The options are Enabled and Disabled.

OS Boot Watch Dog

Set to Enabled to enable OS Boot Watch Dog. The options are Enabled and Disabled.

Timer for Loading OS (Minutes)

This feature allows the user to set the time value (in minutes) for the previous item: OS Boot Watch Dog by keying-in a desired number in the blank. The default setting is 10 (minutes.) (Please ignore this option when OS Boot Watch Dog is set to "Disabled".)

Time Out Option

This feature allows the user to determine what action to take in an event of a system boot failure. The options are No Action, Reset, Power Off and Power Cycles.

▶System Event Log/System Event Log (List Mode)

These options display the System Event (SEL) Log and System Event (SEL) Log in List Mode. Items include: SEL (System Event Log) Entry Number, SEL Record ID, SEL Record Type, Time Stamp, Generator ID, SEL Message Revision, Sensor Type, Sensor Number, SEL Event Type, Event Description, and SEL Event Data.

System Event Log SEL Entry Number = 1 SEL Record ID = 0001 SEL Record Type = 02 - System Event Record Timestamp = 02.10.2006 17:11:23 Generator Id = 20 00 SEL Message Rev = 04 Sensor Type = 02 - Voltage Sensor Number = 0A --12V SEL Event Type = 01 - Threshold Event Description = Lower Non-critical Going Low, Assertion SEL Event Data = 50 06 0E F1 Help 11 Select Item -/* Change Values F9 Setup Defaults Esc Exit Select Menu Enter Select ▶ Sub-Menu F10 Save and Exit

▶Realtime Sensor Data

This feature displays information from motherboard sensors, such as temperatures, fan speeds and voltages of various components.

PhoenixBIOS Setup Utility
Advanced
Realtime Sensor Data
Sensor Type	Sensor Name	Sensor Data	Sensor Units	Lower Limit	Upper Limit
Temp Voltage	Sys Temp	33.00	degrees C	0.00	75.00
	CPU1 Ucore	1.00	Volts	0.91	1.61
	CPU2 Ucore	0.00	Volts	0.91	1.61
	3.3U	3.29	Volts	2.96	3.63
	5U	4.94	Volts	4.48	5.49
	12U	12.00	Volts	10.75	13.24
	-12U	-12.30	Volts	-13.19	-10.00
	1.5U	1.55	Volts	1.34	1.64

▶IPMI LAN Configuration

The following features allow the user to configure and monitor IPMI LAN settings.

PhoenixBIOS Setup Utility Advanced IPMI Lan Configuration Item Specific Help ULAN Tagging [Disabled] ULAN ID [1h] IP Address Source [DHCP] IP Address [192.168.001.096] IP Subnet Mask [255.255.255.000] Default Gateway [192.168.001.001] MAC Address [00h:30h:48h:98h:78h:58h] Update Lan Settings [No] F1 Help 11 Select Item -/- Change Values F9 Setup Defaults Esc Exit Select Menu Enter Select ▶ Sub-Menu F10 Save and Exit

VLAN Tagging

Select Enabled to enable Virtual LAN(s) for IPMI connections and allow the user to configure VLAN settings. The options are Enabled and Disabled.

VLAN ID

If VLAN Tagging above is set to Enabled, this item allows the user to change the VLAN ID. If VLAN Tagging is disabled, this item will be ignored by the firmware.

IP Address Source

Select the source of this machine's IP address. If Static is selected, you will need to know and enter manually the IP address of this machine below. If DHCP is selected, the BIOS will search for a DHCP (Dynamic Host Configuration Protocol) server in the network it is attached to, and request the next available IP address.

The options are DHCP and Static.

IP Address

This item displays the IP address for the IPMI connection detected.

IP Subnet Mask

This item displays the IP Subnet Mask for the IPMI connection detected.

Default Gateway

This item displays the Default Gateway for the IPMI connection detected.

MAC Address

This item displays the MAC Address for the IPMI connection detected.

Update LAN Settings

This item saves the IPMI Lan Configuration settings into memory. If you wish to change any of the settings, select Yes and press F10 to save your settings. Otherwise, leave this setting to its default setting of No.

4-5 Security

Choose Security from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. Security setting options are displayed by highlighting the setting using the arrow keys and pressing . All Security BIOS settings are described in this section.

PhoenixBIOS Setup Utility
Main Advanced Security Boot Exit
Supervisor Password Is: Clear User Password Is: Clear Set Supervisor Password [Enter] Set User Password [Enter] Password on boot: [Disabled]	Item Specific Help
	Supervisor Password controls access to the setup utility.
F1 Help 11 Select Item -/- Change Values F9 Setup Defaults Esc Exit Select Menu Enter Select ▶ Sub-Menu F10 Save and Exit

Supervisor Password Is:

This feature indicates if a supervisor password has been entered to the system. Clear means such a password has not been used, and Set means a supervisor password has been entered.

User Password Is:

This feature indicates if a user password has been entered to the system. Clear means such a password has not been used, and Set means a user password has been entered.

Set Supervisor Password

When the item Set "Supervisor Password" is highlighted, hit the key. When prompted, enter the Supervisor's password in the dialogue box to set or to change supervisor's password, which allows access to the BIOS.

Set User Password

When the item "Set User Password" is highlighted, hit the key. When prompted, enter the user's password in the dialogue box to set or to change the user's password, which allows access to the system at bootup.

Password on Boot

This setting allows you to determine if a password is required for a user to enter the system at system boot. The options are Enabled (password required) and Disabled (password not required).

4-6 Boot

Choose Boot from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. See details on how to change the order and specs of boot devices in the Item Specific Help window. All Boot BIOS settings are described in this section.

PhoenixBIOS Setup Utility Main Advanced Security Boot Exit Boot List Boot priority order: 1: USB FDC; 2: Legacy Floppy Drives 3: USB KEY; 4: IDE CD; 5: IDE 0; 6: IDE 2; 7: PCI SCSI; 8: PCI HEV; Candidate List Excluded from boot order: : IDE 1; : IDE 3; : IDE 4; : IDE 5; : USB HDD; : USB CDRUM; : USB ZIP; Item Specific Help Keys used to view or configure devices: Up and Down arrows select a device. <-> and <-> moves the device up or down. <-> and <-> specifies the device fixed or removable. <-> exclude or include the device to boot. enables or disables a device. <1 - 4> Loads default boot sequence. F1 Help 11 Select Item -/• Change Values F9 Setup Defaults Esc Exit Select Menu Enter Select ▶ Sub-Menu F10 Save and Exit

Boot Priority Order/Excluded from Boot Orders

The devices included in the boot list section (above) are bootable devices listed in the sequence of boot order as specified. The boot functions for the devices included in the candidate list (above) are currently disabled. Use a <+> key or a <-> key to move the device up or down. Use the key or the key to specify the type of an USB device, either fixed or removable. You can select one item from the boot list and hit the key to remove it from the list of bootable devices (to make its resource available for other bootable devices). Subsequently, you can select an item from the candidate list and hit the key to remove it from the candidate list and put it in the boot list. This item will then become a bootable device. See details on how to change the priority of boot order of devices in the "Item Specific Help" window.

4-7 Exit

Choose Exit from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. All Exit BIOS settings are described in this section.

PhoenixBIOS Setup Utility
Main Advanced Security Boot Exit
Exit Saving Changes Exit Discarding Changes Load Setup Defaults Discard Changes Save Changes	Item Specific Help
	Exit System Setup and save your changes to CMOS.

Exit Saving Changes

Highlight this item and hit to save any changes you have made and to exit the BIOS Setup utility.

Exit Discarding Changes

Highlight this item and hit to exit the BIOS Setup utility without saving any changes you may have made.

Load Setup Defaults

Highlight this item and hit to load the default settings for all items in the BIOS Setup. These are the safest settings to use.

Discard Changes

Highlight this item and hit to discard (cancel) any changes you have made. You will remain in the Setup utility.

Save Changes

Highlight this item and hit to save any changes you have made. You will remain in the Setup utility.

Appendix A POST Error Beep Codes

This section lists POST (Power On Self Test) error beep codes for the Phoenix BIOS. POST error beep codes are divided into two categories: recoverable and terminal. This section lists Beep Codes for recoverable POST errors.

Recoverable POST Error Beep Codes

When a recoverable type of error occurs during POST, BIOS will display a POST code that describes the problem. BIOS may also issue one of the following beep codes:

1 long and two short beeps - video configuration error
1 repetitive long beep - no memory detected
1 continuous beep with Front Panel Overheat LED on - system overheat

Notes

Appendix B Installing the Windows OS

After all hardware components have been installed, you must first configure Intel South Bridge RAID Settings before you install the Windows OS and other software drivers. To configure RAID settings, please refer to RAID Configuration User Guides posted on our website at www.supermicro.com/support/manuals.

Note: The following OS installation instructions are written for the Windows XP/2003 OS only. If you have the Windows 2008 or Windows Vista OS, please follow the instructions displayed on your screen to install the OS.

B-1 Installing the Windows XP/2000/2003 OS to a RAID System

Insert Microsoft's Windows XP/2000/2003 Setup CD in the CD Drive, and the 1. system will start booting up from CD.

Press the key when the message-" Press F6 if you need to install a 2. third party SCSI or RAID driver" displays.

When the Windows XP/2000/2003 Setup screen appears, press "S" to specify 3. additional device(s).

Insert the driver diskette-"Intel AA RAID XP/2000/2003 Driver for ESB2" into 4. Drive A: and press the key.

1. Choose the Intel(R) ESB2 SATA RAID Controller from the list indicated in the XP/2000/2003 Setup Screen, and press the key.

Press the key to continue the installation process. (If you need to 6. specify any additional devices to be installed, do it at this time.) Once all devices are specified, press the key to continue with the installation.

From the Windows XP/2000/2003 Setup screen, press the key. The 7. XP/2000/2003 Setup will automatically load all device files and then, continue the Windows XP/2000/2003 installation.

After the Windows XP/2000/2003 OS Installation is completed, the system will 8. automatically reboot.

B-2 Installing the Windows XP/2000/2003 OS to a Non-RAID System

Insert Microsoft's Windows XP/2000/2003 Setup CD in the CD Drive, and the 1. system will start booting up from CD.

Continue with the OS installation. The Windows OS Setup screen will display.2.

From the Windows XP/2000/2003 Setup screen, press the key. The 3. XP/2000/2003 Setup will automatically load all device files and then continue with the Windows XP/2000/2003 installation.

After the Windows XP/2000/2003 OS Installation is completed, the system will 4. automatically reboot.

Insert the Supermicro Setup CD that came with your motherboard into the 5. CD Drive during system boot, and the main screen as shown on Page C-1 will display. Follow the instructions given in Appendix C to complete other driver/software installation.

Appendix C Installing Other Software Programs and Drivers

C-1 Installing other Software Programs and Drivers

After you've installed the Windows Operating System, a screen as shown below will appear. You are ready to install software programs and drivers that have not yet been installed. To install these software programs and drivers, click the icons to the right of these items.

SUPERMICRO X7DWA-N Motherboard Drivers & Tools (WinXP) SUPERMICRO® Drivers & Tools Intel 5400 Chipset X7DWA-N SUPERMICRO Computer Inc. Intel Seaburg Chipset INF files Microsoft DirectX 9.0 ATI Graphics Driver Universal Audio Architecture Driver Realtek High Definition Audio Driver Intel Matrix Storage Manager Adaptec Storage Manager Intel PRO Network Connections Drivers SUPERMICRO Supero Doctor III Build driver diskettes and manuals Browse CD □ Auto Start Up Next Time For more information, please visit SUPERMICRO's web site.

Driver/Tool Installation Display Screen

Note: Click the icons showing a hand writing on the paper to view the readme files for each item. Click a computer icon to the right of an item to install an item (from top to the bottom) one at a time. After installing each item, you must re-boot the system before proceeding with the next item on the list. The bottom icon with a CD on it allows you to view the entire contents of the CD.

C-2 Configuring Supero Doctor III

The Supero Doctor III program is a Web-based management tool that supports remote management capability. It includes Remote and Local Management tools. The local management is called the SD III Client. The Supero Doctor III program included on the CDROM that came with your motherboard allows you to monitor the environment and operations of your system. Supero Doctor III displays crucial system information such as CPU temperature, system voltages and fan status. See the Figure below for a display of the Supero Doctor III interface.

Note 1: The default user name and password are ADMIN.

Note 2: In the Windows OS environment, the Supero Doctor III settings take precedence over the BIOS settings. When first installed, Supero Doctor III adopts the temperature threshold settings previously set in the BIOS. Any subsequent changes to these thresholds must be made within Supero Doctor, since the SD III settings override the BIOS settings. For the Windows OS to adopt the BIOS temperature threshold settings, please change the SDIII settings to be the same as those set in the BIOS.

Supero Doctor III Interface Display Screen-I (Health Information)

Super Doctor III Remote Management Sapiere Info: Health Info | Performances Warning Control | Configuration | Administration | Systems Management Report Help ■ Health Information Fan Status CPU1 Chassis CPU2 Chassis Voltage +1.2V +5V +3.1V 3.1Vsp- SUPERMICRC INTUATION

Supero Doctor III Interface Display Screen-II (Remote Control)

Super Doctor III Remote Management System Info Health Info Performance Remote Control Configuration Administration Systems Management Report Help ■ Remote Control graceful Power control Open Console Power Control ↓ Enter Graceful power control Supero Doctor III allows a user to inform the OS to reboot or shut down within a specified time (the default is 30 seconds) Before the system reboots or shuts down, it's allowed to cancel the action. Requirements Keep Supero SD/Service Daemon running at all times on this system. Provide TCP/IP connectivity. Power control

Note: The SD III Software program can be downloaded from our web site at: ftp://ftp.supermicro.com/utility/Supero_Doctor_III/. You can also download the SDIII User's Guide at: http://www.supermicro.com/PRODUCT/Manuals/SDIII/User-Guide.pdf. For Linux, we will still recommend that you use Supero Doctor II.

Notes

(Disclaimer continued)

The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment, nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency communication devices or other critical systems whose failure to perform be reasonably expected to result in significant injury or loss of life or catastrophic property damage. Accordingly, Supermicro disclaims any and all liability, and should buyer use or sell such products for use in such ultra-hazardous applications, it does so entirely at its own risk. Furthermore, buyer agrees to fully indemnity, defend and hold Supermicro harmless for and against any and all claims, demands, actions, litigation, and proceedings of any kind arising out of or related to such ultra-hazardous use or sale.