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USER MANUAL PD81101 Microchip

PD81101 and PD81000 User Guide Implementing Reverse Power Feed (RPF) Power Source Equipment (PSE) using Microsemi PD81101 and PD81000 Devices

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Contents

1 Revision History .... 1

1.1 Revision 2.0 1
1.2 Revision 1.0 1

2 Overview 2

2.1 Main Features 2

3 General Circuit Description 3

3.1 Isolation Domains 3
3.2 Interface Description 4
3.3 Isolated DC/DC 5
3.4 VAUX5/VAUX3P3 6
3.5 PSE Manager/PSE Controller 8
3.6 Communication 8
3.7 IRQ/RESET 8
3.8 Power Good Signal 8
3.9 3.3 V Supply 8
3.10 Off-Hook Detection 8
3.11 Power Splitters 8
3.12 Overvoltage Protection 9
3.12.1 Option 1—SIDACTOR 'TRS1' 65 V at U-R2P 9 3.12.2 Option 2—GDT 75V at U-R 10
3.13 Non-Ideal Signaling Pulse 10
3.14 Status LEDs 11
3.15 Thermal Design 11

4 Layout Guidelines 12

4.1 Ground and Power Planes 12
4.2 PD81101 Peripheral Components 12
4.3 Conductors Routing 12
4.4 Thermal Pad Definition and Design 12
4.4.1 Requirements 13
4.5 Thermal Pad Design 13

5 Schematic Reference 14

6 Bill of Materials (BOM) 17

Figures

Figure 1 Block Diagram RPF Module 3
Figure 2 Internal Regulation with External NPN from VMAIN 6
Figure 3 Internal Regulation with External NPN from Auxiliary Voltage 7
Figure 4 External DC/DC 7
Figure 5 Immunity Option 1: SIDACTOR TRS1 at U-R2P 9
Figure 6 Immunity Option 2: GDT2 at U-R 10
Figure 7 Non-Ideal Signaling Pulse 10
Figure 8 Heat Dissipation in PCB 13
Figure 9 PSE Interfaces and Surge Protection 14
Figure 10 PSE Manager PD81101 and PSE Controller PD81000 15
Figure 11 Isolated DC/DC Module 16

Tables

Table 1 PSE-CPE Interface 4

Table 2 DC/DC Module Specification 5

Table 3 VAUX5/VAUX3P3 Options 6

Table 4 LED Indications 11

Table 5 BOM PSE Module 17

Table 6 BOM DC/DC 20

Table 7 BOM Immunity 23

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

1.1 Revision 2.0

Revision 2.0 was published in May 2018. The following is a summary of changes in revision 2.0 of this document.

• The main features section was updated. For more information about the main features, see Main Features, page 2.
• PSE-CPE interface descriptions were updated. For more information, see Table 1, page 4.
• DC/DC module specification was updated. For more information, see Table 2, page 5
• The VAUX5/VAUX3P3 section was updated. For more information about the VAUX5/VAUX3P3, see VAUX5/VAUX3P3, page 6.
- The immunity section was updated. For more information about immunity, see Overvoltage Protection, page 9.
• The PSE-DPU signaling section was updated. For more information, see Non-Ideal Signaling Pulse, page 10.
• The error registers section was updated. For more information, see Status LEDs, page 11.
• LED indications were updated. For more information, see Table 4, page 11.
• The schematic reference was updated. For more information, see Schematic Reference, page 14.
• The bill of materials was updated. For more information, see Bill of Materials (BOM), page 17.

1.2 Revision 1.0

Revision 1.0 was published in January 2017. It was the first publication of this document.

2 Overview

This document provides guidelines for designing a RPF system PSE, integrated in the customer premises equipment (CPE) using Microsemi's PD81101 (RPF PSE manager) and PD81000 (RPF PSE controller) chipset.

The PD81101/PD81000 chipset is designed to comply with the European Telecommunications Standards Institute (ETSI) TS 101 548 metallic detection startup (MDSU) protocol, and supports both detection and classification prior to power-up, disabling a disconnected port, and provides continuous protection (prior to power up and after) from error line conditions (ELC) in accordance with the standard. The chipset allows the CPE host to receive telemetry data through I2C communication. The same communication can be used for software download and field upgrades.

Microsemi offers the PD81101EVB-xxWx evaluation system to provide designers with the needed environment to evaluate the performance and implementation of the PD81101/PD81000 chipset in an integrated RPF CPE module. Microsemi offers complementary products for RPF applications (for both CPE and DPU), including the LX7309 PWM controller, PD82000 DPU RPF controller, and PD70101/PD70201 PD front-end controllers with PWM. Contact Microsemi for additional information.

For more information, see the following documents.

• ETSI DTS 101 548 V2.2.1 (2017-12) Technical Specification
- Microsemi RPF PD81101 Datasheet
- Microsemi RPF PD81000 Datasheet
- Microsemi RPF PD81000 PD81101 Firmware Datasheet
- Microsemi PD81101EVB-xxWx User Guide CPE RPF Card
- Microsemi RPF PD81000 Firmware Release Notes

2.1 Main Features

• Provides RPF for VDSL and G.FAST networks
  • RPF MDSU detection and classification in presence of metallic line testing (MELT) signature
  • Foreign DC voltage detection
• Off-hook phone detection and line disconnection
• Error line conditions support
  • I2C communication with CPE host
• Programmable I2C address.
  • Over-temperature thermal protection and monitoring
• Surge protection
• Includes optional reset/IRQ command pin
  • Continuous port monitoring and system data
• Configurable short range power classes, current settings
  • Voltage monitoring/protection (OVP)
• LED indications
• On-board software download
• Interrupt out pin for system and port events
  • Power splitter (PS) voltage droop compensation
  • UDL/OVL indication and line-disconnection
  • Supports signaling indication to DPU by RPF voltage modulation (DGL/ACM/BAT)
  • Battery backup support
  • Supports DPU micro-interruption

3 General Circuit Description

The following illustration shows the functional blocks of the RPF module.

Figure 1 • Block Diagram RPF Module

graph TD
    A["CPE HOST INTERFACE"] --> B["Isolated DC/DC (Based on LX7309 PWM controller)"]
    B --> C["LDO 5 V"]
    C --> D["VALX5 57 V PSE Manager PD81101"]
    D --> E["VOAUX3P3"]
    E --> F["VDD (3.3 V) PSE Controller PD81000"]
    F --> G["Opto-Isolator"]
    G --> H["Secondary GND ISO_DC"]
    H --> I["Primary GND ISO+DC"]
    I --> J["IO"]
    J --> K["IO"]
    K --> L["IO"]
    L --> M["IO"]
    M --> N["IO"]
    N --> O["IO"]
    O --> P["IO"]
    P --> Q["IO"]
    Q --> R["IO"]
    R --> S["IO"]
    S --> T["IO"]
    T --> U["IO"]
    U --> V["IO"]
    V --> W["IO"]
    W --> X["IO"]
    X --> Y["IO"]
    Y --> Z["IO"]
    Z --> AA["IO"]
    AA --> AB["IO"]
    AB --> AC["IO"]
    AC --> AD["IO"]
    AD --> AE["IO"]
    AE --> AF["IO"]
    AF --> AG["IO"]
    AG --> AH["IO"]
    AH --> AI["IO"]
    AI --> AJ["IO"]
    AJ --> AK["IO"]
    AK --> AL["IO"]
    AL --> AM["IO"]
    AM --> AN["IO"]
    AN --> AO["IO"]
    AO --> AP["IO"]
    AP --> AQ["IO"]
    AQ --> AR["IO"]
    AR --> AS["IO"]
    AS --> AT["IO"]
    AT --> AU["IO"]
    AU --> AV["IO"]
    AV --> AW["IO"]
    AW --> AX["IO"]
    AX --> AY["IO"]
    AY --> AZ["IO"]
    AZ --> BA["IO"]
    BA --> BB["IO"]
    BB --> BC["IO"]
    BC --> BD["IO"]
    BD --> BE["IO"]
    BE --> BF["IO"]
    BF --> BG["IO"]
    BG --> BH["IO"]
    BH --> BI["IO"]
    BI --> BJ["IO"]
    BJ --> BK["IO"]
    BK --> BL["IO"]
    BL --> BM["IO"]
    BM --> BN["IO"]
    BN --> BO["IO"]
    BO --> BP["IO"]
    BP --> BQ["IO"]
    BQ --> BR["IO"]
    BR --> BS["IO"]
    BS --> BT["IO"]
    BT --> BU["IO"]
    BU --> BV["IO"]
    BV --> BW["IO"]
    BW --> BX["IO"]
    BX --> BY["IO"]
    BY --> BZ["IO"]
    BZ --> CA["IO"]
    CA --> CB["IO"]
    CB --> CC["IO"]
    CC --> CD["IO"]
    CD --> CE["IO"]
    CE --> CF["IO"]
    CF --> CG["IO"]
    CG --> CH["IO"]
    CH --> CI["IO"]
    CI --> CJ["IO"]
    CJ --> CK["IO"]
    CK --> CL["IO"]
    CL --> CM["IO"]
    CM --> CN["IO"]
    CN --> CO["IO"]
    CO --> CP["IO"]
    CP --> CQ["IO"]
    CQ --> CR["IO"]
    CR --> CS["IO"]
    CS --> CT["IO"]
    CT --> CU["IO"]
    CU --> CV["IO"]
    CV --> CW["IO"]
    CW --> CX["IO"]
    CX --> CY["IO"]
    CY --> CZ["IO"]
    CZ --> DA["IO"]
    DA --> DB["IO"]
    DB --> DC["IO"]
    DC --> DV["IO"]
    DV --> DW["IO"]
    DW --> DX["IO"]
    DX --> DXB["IO"]
    DXB --> DXC["IO"]

3.1 Isolation Domains

The application contains the following two isolation domains.

- ISO1_DC-RPF module primary ground, referenced to CPE's host local ground.

Participating grounds: GND_C = PRI_GND, ISO1_DC_SGNL_GND = ISO1_DC_GND

- ISO_DC-RPF module secondary ground, reference ground for 57 V main RPF output voltage rail to VMAIN RPF output voltage rail, which is fed to the copper pair cable between the CPE and the DPU.

Participating grounds: ISO_AGND = MCU_GND, SEC_GND

3.2 Interface Description

The following table lists the PSE-CPE interface descriptions.

Table 1 • PSE-CPE Interface

Name Direction Schematic Reference			Isolation Domain Description
12 V	CPE to PSE	ISO1_DC_12_V	ISO1	12 V input to isolated DC/DC block. The 12 V is converted to 59.2 V RPF output rail, managed and controlled by the PSE. The DC/DC output power is limited by ETSI standard to classes SR1 (10 W), SR2 (15 W), and SR3 (21 W).
12 V GND CPE to PSE	ISO1_DC_GND	ISO1
3.3 V	CPE to PSE	ISO1_DC_3_3_V	ISO1	3.3 V supply to primary side of PSE module isolators used for communication between host CPU and PSE controller. The host's signals interface is referenced to 3.3 V ground.
3.3 V GND	CPE to PSE	ISO1_DC_SGNL_GND	ISO1
Power-good	CPE to PSE	ISO1_DC_PG	ISO1	Power-good IRQ to PD81000 from AC supply.
IRQ to PSE	CPE to PSE	ISO1_DC_INT_N	ISO1	IRQ signal can be an alternative to I2C in non-embedded solution such as PSE injectors.
RESET to PSE	CPE to PSE	ISO1_DC_RESET_N	ISO1	PSE reset.
I2C bus	CPE to PSE	ISO1_DC_I2C0_SDA	ISO1 I2C communication. Supports register access (PSE status, ELC indications, PSE measurements, PSE commands, program parameters, and so on), GUI, and software upgrades.
	PSE to CPE	ISO1_DC_I2C0_SCL
IRQ to CPE	PSE to CPE	INT_OUT	ISO	PSE supports IRQ to host under detection of error conditions or system reset. Isolation is required.
ELC2 IRQ	PSE to CPE	xFORGEIGN_V	ISO	Direct ELC2 interrupt from PSE to host. Isolation is required.
PSE module positive port output	PSE to CPE	ISO_DC_57_V	ISO	The PSE module port is connected to the CPE system port through surge-protection and a power-splitter. The PSE port is controlled by PD81000/PD81101.
PSE module negative port output	PSE to CPE	ISO_DC_PORT_NEG0	ISO

3.3 Isolated DC/DC

The DC/DC should be designed to conform with ETSI TS 101 548 PSE output electrical requirements. This application note includes a reference design for high-efficiency step-up DC/DC module that supports the maximum power level in PSE side (class SR-3). The proposed DC/DC module is based on the LX7309 current-mode PWM controller. The DC/DC module receives 12 V from the CPE host and has the following two outputs.

• Up to 60 V main output rail (ISO_VMAIN). The DC/DC 60 V output voltage used as main high voltage supply (VMAIN) to PSE manager PD81101.
• Auxiliary output 11.6 V (ISO_AUX). The auxiliary output used as external supply to PD81101/PD81000 for enhanced efficiency solution.

Both outputs share the same reference ground: ISO_AGND.

If the PSE is not embedded in the CPE (as in a RPF injector application), then the DC/DC module is replaced by a AC/DC module, 60 V output. In this case, I2C communication with the host may not be available, and the communication between the PSE and CPE host is limited to mutual IRQ signals. In non-embedded solutions, the I2C interface should be prepared for future software upgrades.

The following table lists the DC/DC module specifications.

Table 2 • DC/DC Module Specification

Parameter Symbol Conditions Min Typ Max Units
Input voltage V	IN	DC input voltage 11 12	13.2 V
Input voltage turn on	V_IN\_TURNON	Load 0–100%				10.6 V
Inrush current	I_INRUSH	Full load, cold start, V_IN =13.2 V.No tripping of fuse/breaker AC/DC PSU			3		A
Input power	P_IN\_DC	Required power from CPE AC/DC PSU(for reference).		26			W
Output voltage	V_OUT\_DC	Initial accuracy. No PS droop compensation.DC/DC output (VMAIN).		58.6	59.2	59.65	V
Output power	P_OUT\_DC	DC/DC module designed to meet output powerminimum requirement.		22			W
Efficiency	Eff	At full load and V_IN\_MIN =≤ V_IN ≤ V_IN\_MAX conditions.		90			%
Total output voltage regulation(line/load/temperature)		At V_IN =12V.			±0.5		%
Auxiliary output		Extra winding.		71	11	12	V
Auxiliary output current	I_AUX	25 °C			29		mA
Output voltage rise time	T_RISE	Any load and line conditions.				100	msec
Transient response		Overshoot/undershoot with dl/dt =3 A/μs.				±2	%

1. No load condition.

3.4 VAUX5/VAUX3P3

The PD81101 regulates ISO_AUX to 5 V (VAUX5) and 3.3 V (VAUX3P3), both used for internal and external consumption. There are three options to supply these sources, and the designer can choose the best option for their design.

The following table lists the VAUX5/VAUX3P3 options.

Table 3 · VAUX5/VAUX3P3 Options

Parameter Option 1 Option 2 Option 3
Input voltage ISO_VMAIN ISO_VAUX ISO_VAUX
Input range 55.75 V V_AUX5 + V_CE(sat) + I_AUX * R_LIM ISO_VAUX = 5 V (regulated)	V_AUX5 + V_CE(sat) + I_AUX * R_LIM	V_AUX5 + V_CE(sat) + I_AUX * R_LIM	ISO_VAUX = 5 V (regulated)
Estimated power loss 1.6 W	0.15W · 1 - + (ISO_VAUX - 5V) · I_AUX	0.15W · 1 -
5 V output regulator Internal regulator, external NPN	Internal regulator, external NPN	External DC/DC
Description and comments Power dissipation imposed on external NPN. Thermal design can be improved by locating NPN away from PD81101.	Utilize VMAIN regulation to generate unregulated ISO_VAUX from extra winding on the SMPS transformer. ISO_VAUX should be higher than VAUX5 (5 V), to allow linear regulation by PD81101 internal 5 V regulator and external NPN.Efficiency and thermal stress improved significantly with AUX to secondary turns ratio of 20%-30%. In cases where ISO_AUX is regulated, use option 3.	Low-power dissipation similar to option 2. Power provided from external high-efficiency 5 V regulator. This option does not utilize the PD81101 internal regulator.

Note: When using an external supply for the 5 V, the following power sequence is required: VMAIN, VAUX5, VAUX3P3= TRIM, DVDD.

The following illustration shows option one's internal regulation with external NPN from VMAIN.

Figure 2 • Internal Regulation with External NPN from VMAIN

Iaux Rlim Pin 19 (DRV VAUX5) Pin 20 (VAUX5) 5 V Regulator 5 V Internal Load Pin 23 (VAUX3P3_INT) Pin 22 (VAUX3P3) 3.3 V Regulator To PD81000 Vmain PD81101 3.3 V Internal Load

The following illustration shows option two's internal regulation with external NPN from auxiliary voltage.

Figure 3 • Internal Regulation with External NPN from Auxiliary Voltage

Primary Secondary: 60 V Auxiliary 12 V Iaux Rlim ISO1 ISO PD81101 Pin 19 (DRV VAUX5) Pin 20 (VAUX5) 5 V Regulator 5 V Internal Load To PD81000 Pin 23 (VAUX3P3 INT) Pin 22 (VAUX3P3) 3.3 V Regulator VMAIN 3.3 V Internal Load

The following illustration shows option three's external DC/DC.

Figure 4 • External DC/DC

graph TD
    A["SMPS DC/DC"] -->|Iaux| B["PD81101"]
    B --> C["5 V Regulator"]
    C --> D["3.3 V Regulator"]
    D --> E["3.3 V Internal Load"]
    B --> F["Pin 19 (DRV VAUX5)"]
    B --> G["Pin 20 (VAUX5)"]
    B --> H["5 V Internal Load"]
    B --> I["Pin 23 (VAUX3P3_INT)"]
    B --> J["Pin 22 (VAUX3P3)"]
    B --> K["To PD81000"]
    L["VMAIN"] --> M["Ground"]

3.5 PSE Manager/PSE Controller

The PD81101 (PSE manager), PD81000 (PSE controller), and system firmware make up the PSE system. The PD81101 uses a SPI bus in order to communicate with PD81000. For more information, see the firmware and device datasheets.

3.6 Communication

The CPE host CPU communicates with the PSE controller through the I2C bus. For more information about MCU's register map, software download, and communication protocol, see the Microsemi RPF PD81000/PD81101 Firmware Datasheet.

Isolation is required. The recommended I2C isolators are ISO1540DR or ADUM1250.

Using the I2C interface, the host can do the following:

• Read port/ICs status.
• Read port measurements (VMAIN, VPORT, IPORT).
• Read error line conditions (ELC) and fault indication (open tip-to-ring, short tip-to-ring, foreign DC voltage, off-hook phone, detection/class error, overload and underload).
  • Perform software downloads.
• Send shutdown/wake-up commands to the PSE manager, and perform temporary port shutdown for MELT (40 s).
• Set CPE's operation mode: AC-mains mode or battery mode. The PSE communicates the CPE operation mode to the DPU RPF controller (PD82000) by signaling, according to ETSI TS 101 548 requirements.

3.7 IRQ/RESET

The PD81000 supports IRQ to the host (schematic reference INT_OUT, pin 27) and IRQ from the host (schematic reference INT_N, pin 28), according to customer request. The host can enable/disable IRQ triggers using nIRQ_Mask register.

The host is able to send direct reset commands to the PSE controller (schematic reference xRESET, pin 3).

Isolation is required. Optional Opto isolator: MOCD217.

3.8 Power Good Signal

Power good signal input (PD81000, pin 10) should be connected to PSE AC/DC power supply's power-good indication through isolation. The power-good signal is used by the PSE controller to indicate CPE dying gasp to the DPU by sending immediate signaling patterns over the RPF line. If PD81000 detects falling edge (high-to-low transition) of the power-good signal, it sends dying gasp signaling to the DPU. The PD82000 (DPU RPF controller) communicates the received CPE dying gasp signaling to the DPU's host. The time between power-good falling-edge to dying gasp signaling generation is about 1 msec (schematic reference IRQ_IN_PG, pin 10).

3.9 3.3 V Supply

The primary side of the isolators is supplied by the CPE host (3.3 V). The host should connect ISO1_DC_3_3V to 3.3 V supply, which is referenced to ground: ISO1_DC_SGNL_GND. The typical current consumption from 3.3 V is 2 mA (photo-couplers normally off). The isolator's maximum current requirement (total) is 6 mA.

3.10 Off-Hook Detection

The ETSI TS 101 548 requires the PD81000 and PD81101 chipset to support off-hook phone detection and line disconnection before and after DPU power-up.

3.11 Power Splitters

Power splitters are a very important part of the RPF circuitry that influence G.FAST and RPF performance. Configuration instructions, schematics, and component value of power splitters are

provided by G.FAST SoC manufactures in their reference designs. For successful operation of this EVB, customers should use power splitters from G.FAST SoC reference designs.

3.12 Overvoltage Protection

Microsemi's reference design includes two protection options for surges, power induction, AC contact, and ringing voltage. The following standards are supported.

• I T U - T K 2 1
- GR-1089-CORE
• EN61000 4-5

3.12.1 Option 1—SIDACTOR 'TRS1' 65 V at U-R2P

This option can be considered if the power splitter inductors can withstand AC-contact current for the time duration before fuse F1 or F2 opens (about 5 seconds), because AC-positive current goes through TRS1, and AC-contact negative current goes through D14. Placing the differential protection at U-R2P instead of U-R is recommended if there is a concern of triggering the protection device during DPU micro-interruptions or any cable contact bouncing, as a result of filter inductors discharge.

The following illustration shows the immunity option 1: SIDACTOR TRS1 at U-R2P.

Figure 5 • Immunity Option 1: SIDACTOR TRS1 at U-R2P

VMAIN PD81101 PORT_NEGO ISO_VMAIN D2 BAR46FILM C100 47 nf/100 V R110 2.43 Ω L10 6.8 uH DIFF D31 STPS LH100A C103 +300 nF R131 100 KΩ D31 STPS1H100A D14 TRS1 P0720SDLRP U-R2P Power Splitter G.Fast/ VDSL LPF C36 C37 U-R2 (Data) Surge Protection 2 GDT1 BOURNS-2036-SM F1 04611.25ER U-R Power + Data F2 04611.25ER

Note: *Optional component: may be required for proper micro interrupt performance, depending on G.Fast/VDSL LPF characteristics. Please consult Microsemi for a recommendation.

3.12.2 Option 2—GDT 75V at U-R

In this option, the power splitter needs to withstand about half of the AC current seen in option 1 because the AC positive current goes through GDT2. However, GDT2 may be triggered during micro-interruption or cable bouncing, if the power-splitter inductors has insufficient damping.

The following illustration shows the immunity option 2: GDT2 at U-R.

Figure 6 • Immunity Option 2: GDT2 at U-R

VMAIN PD81101 PORT_NEG0 ISO_VMAIN D2 BAR46FILM C100 47 nF/100 V R110 2.43 Ω L10 6.8 uH DIFF D31 STPS1H100A C103 *300 nF R131 100 KΩ D14 Surge Protection1 G.Fast/VDSL LPF U-R2P Power Power-Splitter C36 CS7 U-R2 (Data) Surge Protection 2 GDT1 BOURNS-2036- SM GDT2 CG75MS F2 04611.25ER U-R Power + Data

Note: *Optional component: may be required for proper micro interrupt performance, depending on G.Fast/VDSL LPF characteristics. Please consult Microsemi for a recommendation.

3.13 Non-Ideal Signaling Pulse

A practical signaling pulse waveform may be non-ideal, as it is affected by line characteristics, instantaneous DPU load, power splitters, and so on.

The V_o2p is the voltage at reference point U-O2P. The V_o2p0 is the steady-state (DC) voltage of V_o2p. The pulse width w1 is implied from the distance between two consecutive crossing of V_o2p-5V: the first cross point is during pulse falling-edge, and the second during pulse rising-edge.

V_o2p , the pulse amplitude, shall be higher than 10 V. V_r2p should be high enough to meet this constraint. V_r2p set-point in the PD81101/PD81000 reference design is 51 V to support wide operating conditions.

Microsemi's reference design is tolerant to pulse noise and ringing. There is no limitation on the minimum pulse voltage, Nvalley. Ringing peak is allowed, as long as Npk is below V_o2p0-5V trip point.

The following illustration shows the non-ideal signaling pulse behavior.

Figure 7 • Non-Ideal Signaling Pulse

3.14 Status LEDs

LED0_OD-LED3_OD are open-drain PSE manager outputs for LED indication. Connect the LED in serial with a current limit pull-up resistor.

The following table describes the LED functions.

Table 4 • LED Indications

Pin Name	Pin Type	LEDNumber	LED On LED Blink 1 Hz
LED0_OD	Open-drain	LED0 Port on (pwrOn)	Overload (ERR8)
LED1_OD	Open-drain	LED1 Line open (ERR0)	Foreign DC voltage (ERR2)
LED2_OD	Open-drain	LED2	Off-hook-phone (ERR3|ERR4)	Short-circuit (ERR1)
LED3_OD	Open-drain	LED3	Classification fail (ERR6)	Resistor detection fail (ERR5)

3.15 Thermal Design

The design should take into account the power dissipation of PD81101 and associated circuitry, and the maximum ambient operating temperature of the CPE. Adequate ventilation and airflow should be part of the design to avoid thermal over-stress. The power dissipation over the RPF manager can be calculated as follows:

$$ I _ {\text { port }} ^ {2} \times R _ {\text { CH_ON }} = P _ {\text { RPF_manager }} $$

where, I_port = the port maximum output current, R_CH_ON = the total PSE manager internal channel resistance.

The temperature is monitored at all times. If the die exceeds 150 °C, the system port will be disconnected to protect PD81101. The temperature can be read and monitored by the host as well through I2C if required.

4 Layout Guidelines

Microsemi's PD81101 PSE manager is designed to simplify the integration of PSE circuitry. The pin-out arrangement has been configured for optimal PCB routing.

4.1 Ground and Power Planes

Because the RPF-PSE solution is a mixed-signal (analog and digital) circuitry, special care must be taken when routing the ground and power signal lines.

The reference design assumes a four layer board—top, mid1, mid2, and bottom. The main planes are VMAIN/analog ground (AGND) and digital ground (DGND). Ground planes are crucial for proper operation and should be designed in accordance with the following guidelines.

• Separate analog and digital grounds, with a gap of at least 40 mils.
• AGND plane utilized to transfer the heat generated by PD81101. For more information, see Thermal Design, page 11.
  • AGND should be located on an external layer
  • To prevent ground loop currents, use only a single connection point between the digital and analog grounds.
• A focal interconnection point for the digital and analog grounds should be located at the middle of the overlapping section.
• The power and return (ground) planes for the VMAIN supply must be designed to carry the system's maximum continuous current, based on the design capacity.

Note: Minimize DC power losses on these planes by using wide copper lands. When implementing the PSE circuitry on a daughter board, the high current does not have to be routed through the daughter board but only the return path.

4.2 PD81101 Peripheral Components

The layout should ensure that the PD81101 maximum operating junction temperature is not exceeded under worst case conditions. Heat dissipating components, such as npn transistor Q1, should be placed away from PD81101. The side of the PSE manager that includes pins 41–56 should face the DGND plane. The pins function as communication and control pins.

Locate the bypass capacitors for the PSE manager supply input close to the relevant pin. In cases where two bypass capacitors are placed on the same line, locate the lower value capacitor closer to the pin on the same layer and place the higher value capacitor at a more distant location.

Place VAUX5 and VAUX3P3 0.1 F and 4.7 F filtering capacitors as close as possible to the PSE manager pins 20 and 22, respectively.

4.3 Conductors Routing

Conductor (or printed lands) routing is to be performed as practiced in general layout guidelines. Specifically, conductors that deliver a digital signal should be routed between the analog and the digital ground planes. Avoid routing analog signals above the digital ground.

The IREF resistor (connected to pin 24), is used for current reference, and should be directly connected to AGND and pin 24 using the shortest path (clock sensitivity).

4.4 Thermal Pad Definition and Design

The PD81101 utilizes a thermal dissipation exposed pad in a 56-pin 8mm× 8mm QFN package. The package is molded in such a way that the lead frame is exposed at the bottom surface of the package.

Direct soldering of the exposed pad to a copper land provides an efficient thermal path. In multilayer board designs, a matrix of 6 × 6 vias thermally connects the exposed pad to the AGND copper planes.

4.4.1 Requirements

The PCB design should consider the exposed pad of the PD81101. This pad is used for thermal cooling of the package. The PD81101 pad is soldered to a dedicated area on the PCB. This contact area is composed of a 49-vias array, each penetrating and thermally connecting to large ground areas in the PCB at various planes, providing efficient heat dissipation.

4.5 Thermal Pad Design

The PD81101 exposed pad is a metal substrate on the bottom of the package. The attachment process for the exposed pad package is equivalent to standard surface mount packages.

The following illustration shows the heat dissipation in PCB.

Figure 8 • Heat Dissipation in PCB

Signal trace Die Pad-to-Board Soldering Cu Planes Metal Land Thermal Via region

For proper heat dissipation, the following footprint and layout guidelines should be followed.

• All thermal vias are to be connected to the AGND area under PD81101.
- For a nominal package standoff of 2.5 mils, a solder mask stencil thickness of 5 mils should be considered.

5 Schematic Reference

The following illustrations show the various schematic references for the PD81101 and PD81000 device.

Figure 9 • PSE Interfaces and Surge Protection

TSO1_DC DSO_DC DC DC DC DC DATA INPUT DATA-PUMBER OUTPUT PLACHOLDER TOR XDSL/G.FAST FILTER PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 DATA-PUMBER OUTPUT PLACHOLDER TOR XDSL/G.FAST FILTER PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT PLL-OUT

Figure 10 • PSE Manager PD81101 and PSE Controller PD81000

Electrical schematic diagram with labeled components and connections, including transistors, diodes, capacitors, and control elements.

Note: *Optional component: may be required for proper micro interrupt performance, depending on G.Fast/VDSL LPF characteristics. Please consult Microsemi for a recommendation.

Figure 11 · Isolated DC/DC Module

Electrical schematic diagram with labeled components and connections, including ISO_DC and ISO_DC blocks

6 Bill of Materials (BOM)

The following tables list the BOMs for the PD81101 and PD81000 device.

Table 5 • BOM PSE Module

Quantity Ref Part Description Mfr Part Number/Notes
1 C10 Ceramic capacitor 1 nF 100 V X7R ±10% 0603
5 C16 Ceramic capacitor 1 nF 16 V X7R ±10% 0402
C28 Ceramic capacitor 1 nF 16 V X7R ±10% 0402
C94 Ceramic capacitor 1 nF 16 V X7R ±10% 0402
C95 Ceramic capacitor 1 nF 16 V X7R ±10% 0402
C101 Ceramic capacitor 1 nF 16 V X7R ±10% 0402
1 C102 Ceramic capacitor 100 pF 10 V NPO ±5% 0402
5 C24 Ceramic capacitor 4.7 μF 10 V X7R ±20% 0805
C62 Ceramic capacitor 4.7 μF 10 V X7R ±20% 0805
C63 Ceramic capacitor 4.7 μF 10 V X7R ±20% 0805
C92 Ceramic capacitor 4.7 μF 10 V X7R ±20% 0805
C99 Ceramic capacitor 4.7 μF 10 V X7R ±20% 0805
9 C61 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C64 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C75 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C76 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C77 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C78 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C79 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C80 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
C82 Ceramic capacitor 0.1 μF 10 V X7R ±10% 0402
1 C65 Ceramic capacitor 1 μF 100 V X7R ±10% 1210
1 C74 Ceramic capacitor 1 μF 6.3 V X7R ±10% 0402
1 C81 Ceramic capacitor 10 nF 6.3 V X7R ±10% 0402
1 C86 Ceramic capacitor 4.7 nF 100 V X7R ±10% 0603
1 C98 Ceramic capacitor 47 pF 10 V NPO ±5% 0402
1 C100 Ceramic capacitor 47 nF 100 V X7R ±10% 0805
5 D1 Chip LED bi-color green/red 5 V Everlight 19-21-
	SYGCS530E3TR8 or equivalent
D3 Chip LED bi-color green/red 5 V Everlight 19-21-
	SYGCS530E3TR8 or equivalent

Table 5 • BOM PSE Module (continued)

Quantity	Ref	Part Description	Mfr Part Number/Notes
D7 Chip LED bi-color green/red 5 V Everlight 19-21-			SYGCS530E3TR8 or equivalent
D8 Chip LED bi-color green/red 5 V Everlight 19-21-			SYGCS530E3TR8 or equivalent
D9 Chip LED bi-color green/red 5 V Everlight 19-21-			SYGCS530E3TR8 or equivalent
1 D2 Diode Schottky 100 V 150 mA SOT23 BAR46FILM or equivalent
1 D32 Diode Schottky 20 V 150 mA SOT23
1 D6 Diode Zener 51 V ±5% 500 mW SOD123 MMSZ5262BT1G or equivalent
1 D14 Diode Schottky 100 V 1 A surface mount SMA STPS1H100A or equivalent
1 D25 Diode array GP 100 V 200 mA SOT23 MMBD7000LT1G or equivalent
1 D26 Diode GP 100 V 300 mA SOD123 1N4148W-7-F or equivalent
1 L10 Inductor 6.8 μH ±10% 600 mA 472 mΩ max 1812 API Delevan P1812R-682K or equivalent
1	Q1	Transistor NPN 100 V 1 A 1.56 W TO-252-3	KSH29CTF, MJD47TF, or equivalent
2 Q5	MOSFET P-CH 200 V 0.035 A SOT23-3		ZVP1320FTA or equivalent
Q8	MOSFET P-CH 200 V 0.035 A SOT23-3		ZVP1320FTA or equivalent
2	Q6	MOSFET N-CH 100 V 170 mA SOT-23 Rdson=6 Ω max	BSS123LT1G or equivalent
	Q9	MOSFET N-CH 100 V 170 mA SOT-23 Rdson=6 Ω max	BSS123LT1G or equivalent
1 R5 Resistor 28.7 kΩ 0.1% 1/16 W 0402
1 R6 Resistor 5.1 kΩ ±5% 0.1 W, 1/10 W 0603
1 R139	Resistor 100 kΩ ±1% 1/16 W 0402
11	R14 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R45 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R50 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R84 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R85 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R86 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R87 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R97 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R98 Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R124	Resistor 10 kΩ ±1% 0.063 W, 1/16 W 0402
R132	Resistor 10 kΩ ±1% 1/16 W 0402
1 R137	Resistor 0 Ω jumper 0603
4 R15 Resistor 49.9K kΩ ±1% 1/16 W 0402
R16 Resistor 49.9K kΩ ±1% 1/16 W 0402

Table 5 • BOM PSE Module (continued)

Quantity Ref Part Description	Mfr Part Number/Notes
R17 Resistor 49.9K kΩ ±1% 1/16 W 0402
R18 Resistor 49.9K kΩ ±1% 1/16 W 0402
1 R101 Resistor 1 kΩ ±1% 1/10 W 0603
1 R46 Resistor 49.9 Ω ±1% 1/16 W 0402
1 R55 Resistor 10 Ω ±1% 1/10 W 0603
4 R70 Resistor 2 kΩ ±1% 1/16 W 0402
R72 Resistor 2 kΩ ±1% 1/16 W 0402
R73 Resistor 2 kΩ ±1% 1/16 W 0402
R78 Resistor 2 kΩ ±1% 1/16 W 0402
1 R71 Resistor 20 Ω ±5% 1/8 W 0805
1 R88 Resistor 68.1 kΩ ±0.1% 1/16 W 0402
1 R91 Resistor 2 kΩ ±0.1% 1/16 W 0402
1 R92 Resistor 2.21 kΩ ±1% 1/16 W 0402
1 R94 Resistor 8.87 kΩ ±1% 1/16 W 0402
1 R95 Resistor 10 kΩ ±1% 1/16 W 0402
2 R99 Resistor 3.3 kΩ ±5% 1/16 W 0402
R100 Resistor 3.3 kΩ ±5% 1/16 W 0402
1 R102 Resistor 5.1 kΩ ±1% 1/10 W 0805
3 R103 Resistor 1 kΩ ±5% 1/16 W 0402
R115 Resistor 1 kΩ ±5% 1/16 W 0402
R47 Resistor 1 kΩ ±5% 1/16 W 0402
2 R104 Resistor 200 ±5% 1/4 W 1206
R107 Resistor 200 ±5% 1/4 W 1206
1 R110 Resistor 2.43 ±1% 1/4 W 1206
1 R118 Resistor 150 kΩ ±5% 1/16 W 0402
1 R119 Resistor 1 MΩ ±5% 1/10 W 0603
2 R120 Resistor 1 MΩ ±0.1% 1/16 W 0805
R121 Resistor 1 MΩ ±0.1% 1/16 W 0805
2 R122 Resistor 49.9 kΩ ±0.1% 1/16 W 0402
R123 Resistor 49.9 kΩ ±0.1% 1/16 W 0402
1 R136 Resistor 0 Ω jumper 0402
1 U1 RPF PSE manager Microsemi PD81101ILQ-TR
1 U4 Dual bi-directional I2C isolator 1 MHz 3.0 V–5.5 V	ISO1540DR, ADUM1250ARZ-RL, or equivalent
1 U6 Optoisolator transistor output 1 channel CTR 20% min 4-SO Broadcom ACPL-217-500E
1 U8 RPF PSE controller PD81000 Microsemi PD81000
1 U9 Optoisolator transistor output 2 channels CTR 100% min SOIC-8 Fairchild MOCD217R2-M or equivalent

Table 6 · BOM DC/DC

Quantity Ref Part Description Mfr Part Number/Notes
1 C98 Ceramic capacitor 47 pF 10 V NPO ±5% 0402
1 C99 Ceramic capacitor 4.7 μF 10 V X5R ±20% 0402
2 C1 Ceramic capacitor 100 nF 100 V X7R ±10% 0805
C73 Ceramic capacitor 100 nF 100 V X7R ±10% 0805
8 C2 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
C3 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
C49 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
C50 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
C51 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
C52 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
C53 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
C54 Ceramic capacitor 2.2 μF 100 V X7R ±10% 1210
1 C4 Ceramic capacitor 47 nF 100 V X7R ±10% 0805
2 C6 Ceramic capacitor 1 nF 100 V X7R ±10% 0603
C55 Ceramic capacitor 1 nF 100 V X7R ±10% 0603
3 C7 Ceramic capacitor 10 μF ±20% 25 V X7R 1210
C8 Ceramic capacitor 10 μF ±20% 25 V X7R 1210
C58 Ceramic capacitor 10 μF ±20% 25 V X7R 1210
2 C11 Ceramic capacitor 10 nF 25 V X7R ±10% 0402
C69 Ceramic capacitor 10 nF 25 V X7R ±10% 0402
1 C14 Ceramic AL 47 μF 16 V ±20% 6.3 mm × 5.8 mm UCL1C470MCL1GS or equivalent
1 C15 Ceramic AL 47 μF 16 V ±20% 6.3 mm × 5.8 mm UUX2A470MNL1GS or equivalent
3 C19 Ceramic capacitor 100 nF 25 V X7R ±10% 0402
C20 Ceramic capacitor 100 nF 25 V X7R ±10% 0402
C90 Ceramic capacitor 100 nF 25 V X7R ±10% 0402
1 C21 Ceramic capacitor 470 pF 6.3 V X7R ±10% 0402
1 C22 Ceramic capacitor 100 pF 10 V X7R ±10% 0402
1 C23 Ceramic capacitor 82 nF 10 V X7R ±10% 0402
1 C26 Ceramic capacitor 2.2 μF 10 V X7R ±20% 0805
1 C27 Ceramic capacitor 10 μF 10 V X7R ±10% 0805
1 C29 Ceramic capacitor 10 nF 16 V X7R ±10% 0402
4 C48 Ceramic capacitor 1 nF 2000 V X7R ±10% 1206 Kemet	C1206C102KGRAC or equivalent

Table 6 • BOM DC/DC (continued)

Quantity	Ref	Part Description	Mfr Part Number/Notes
C83	Ceramic capacitor 1 nF 2000 V X7R ±10% 1206	Kemet	C1206C102KGRAC or equivalent
C88	Ceramic capacitor 1 nF 2000 V X7R ±10% 1206	Kemet	C1206C102KGRAC or equivalent
C89	Ceramic capacitor 1 nF 2000 V X7R ±10% 1206	Kemet	C1206C102KGRAC or equivalent
2	C59 Ceramic capacitor 100 nF 25 V X7R ±10% 0603
C68	Ceramic capacitor 100 nF 25 V X7R ±10% 0603
1	C60 Ceramic capacitor 1 nF 100 V X7R ±10% 0603
1	C70 Ceramic capacitor 1 nF 25 V X7R ±10% 0805
1	C84 Ceramic capacitor 1 μF 6.3 V X7R ±10% 0402
1	C91 Ceramic capacitor 10 μF ±20% 25 V X7R 1206
2	C93 Ceramic capacitor 2.2 μF ±10% 25 V X7R 0603
C97	Ceramic capacitor 2.2 μF ±10% 25 V X7R 0603
1	C96 Ceramic capacitor 220 nF 16 V X7R ±10% 0603
1	C103 Ceramic capacitor 300 nF ±20% 100 V X7R 1206
1	D4 Diode ultrafast 2 A 400 V 35 ns SMB ES2G-E3/52T or equivalent
1	D10 IC shunt voltage reference 1.24 V ±0.5% SOT-23-5 TLV431BIDBVR
1	D20 Diode standard 50 V 1 A SMA ES1A-LTP or equivalent
1	D27 Diode Schottky 100 V 75 mA SOD-123 BAT46W-TP or equivalent
1	D29 Zener diode 30 V 225 mW ±7% surface mount SOT-23-3 BZX84C30LT1G or equivalent
1	D30 Zener diode 33 V 300 mW ±5% SOT-23-3 BZX84C33-E3-08 or equivalent
1	L1 Inductor 10 μH ±20% shielded wirewound 4.1 A 32.5 mΩ Taiyo Yuden NR10050T100M or equivalent
1	L3 Inductor 10 μH ±20% shielded wirewound 1.2 A 160 mΩ Wurth 7445510 or equivalent
2	L8 Ferrite bead 600 Ω at 100 MHz 0603	Wurth 742792651 or equivalent
L9	Ferrite bead 600 Ω at 100 MHz 0603	Wurth 742792651 or equivalent
1	Q2 MOSFET N-CH 100 V 7 A POWER56	FDMS86104 or equivalent
1	Q7 MOSFET N-CH 100 V 170 mA SOT-23 Rdson=6 Ω max	BSS123 or equivalent
2	R12 Resistor 36 mΩ ±1% 0.5 W 1206	RL1632S-R036-F or equivalent
R13 Resistor 36 mΩ ±1% 0.5 W 1206 RL1632S-R036-F or equivalent
3 R21 Resistor 0 Ω jumper 0402
R37 Resistor 0 Ω jumper 0402
R127 Resistor 0 Ω jumper 0402
1 R24 Resistor 19.1 kΩ ±1% 0.1 W, 0603
1 R25 Resistor 2.67 kΩ ±1% 1/16 W 0402
1 R26 Resistor 64.9 kΩ ±1% 1/16 W 0402
2 R27 Resistor 100 Ω ±1% 1/16 W 0402
R40 Resistor 100 Ω ±1% 1/16 W 0402
1 R28 Resistor 2.7 Ω ±5% 0.1 W, 0603
2 R29 Resistor 100 kΩ ±1% 1/16 W 0402
R36 Resistor 100 kΩ ±1% 1/16 W 0402
1 R30 Resistor 100 kΩ ±1% 1/16 W 0402
1 R31 Resistor 13.3 kΩ ±1% 1/8 W 0805
2 R38 Resistor 20 kΩ ±1% 1/16 W 0402
R39 Resistor 20 kΩ ±1% 1/16 W 0402
1 R42 Resistor 10 kΩ ±1% 1/16 W 0402
1 R43 Resistor 4.99 kΩ ±0.1% 1/16 W 0402
1 R44 Resistor 220 kΩ ±0.1% 1/8 W 0805
1 R51 Resistor 0 Ω jumper 0603
1 R52 Resistor 1.2 kΩ ±1% 1/16 W 0402
1 R53 Resistor 1.65 kΩ ±1% 1/16 W 0402
1 R69 Resistor 1.5 kΩ ±5% 1/2 W 1210
1 R74 Resistor 47 Ω ±5% 1/8 W 0805 RC0805FR-0747RL
1 R77 Resistor 0 Ω jumper 1206 RC1206JRG070R
1 R79 Resistor 1 kΩ ±1% 1/16 W 0402 ERJ3EKF1001V
1 R80 Resistor 680 Ω ±1% 1/10 W 0603
1 R114 Resistor 5.1 Ω ±5% 1/8 W 0805
1 R117 Resistor 100 kΩ ±1% 1/16 W 0402
1 R128 Resistor 10 Ω ±1% 1/10 W 0603
1 R129 Resistor 10 kΩ ±1% 1/16 W 0402 CR0402-FX-1002GLF
1 T2 Transformer flyback 57 V custom 4.1 μH TMP DG-EFD2011-0005 GP
1	T3	Choke common mode 320 μH	Wurth 744290321
1	U2	Optoisolator 3 kV transistor 4SMD	FOD817ASD
1 U5	PWM controller		Microsemi LX7309ILQ

Table 7 • BOM Immunity

Quantity Ref Part Mfr Part Number

2 D14 Diode Schottky 100 V 1 A surface mount DO-214AC (SMA)

D31 Diode Schottky 100 V 1 A surface mount DO-214AC (SMA)

2 F1 Fuse SMT 1.25 A 600 VAC/80 VDC 04611.25ER

F2 Fuse SMT 1.25 A 600 VAC/80 VDC 04611.25ER

1 GDT1 Gas discharge tube 600 V ±20% 10K A 3-pole surface mount Bourns 2036-60

1 GDT2 Gas discharge tube 75 V 20000 A (20K A) 2-pole surface mount Littelfuse CG75MS

1 R131 Resistor 100 kΩ 1% 1/8 W 0805