PIC16F13124 - Electronic component Microchip - Free user manual and instructions

USER MANUAL PIC16F13124 Microchip

The PIC16F13145 family of microcontrollers introduce a new peripheral, the Configurable Logic Block (CLB).

The CLB peripheral, comprised of 32 Basic Logic Elements (BLE), allows the users to incorporate hardware-based custom logic into their applications. Each logic element's Look-up Table (LUT) based design offers vast customization options, and the CPU-independent operation improves the response time and power consumption.

The user must configure elements as matrix multiplexers, LUTs, and flip-flops to achieve a given logic function, which is similar to the Configurable Logic Cell (CLC) on PIC ^ MCUs or the Configurable Custom Logic (CCL) on the AVR ^ MCUs. However, the matrix is much larger and is interconnected to a higher degree - which enables users to make more complex logic functions. To help users focus on the intended functionality of their logic design without having to understand the inner workings of the peripheral, Microchip provides a GUI (CLB Synthesizer) used for Configurable Logic Block configuration.

Tool Versions: MCC-Integrated and Stand-Alone-Online

The available configuration tool has two versions: One integrated into MCC Melody and one online, stand-alone version.

CLB Synthesizer - MCC Melody: The version of the tool integrated into MPLAB® Code Configurator (MCC) Melody allows one to create a logic design from scratch or to import a logic design from the online version of the tool. It enables the user to develop a complete application using the CLB in MCC Melody and offers a high level of integration with other peripherals also configured using MCC Melody.

CLB Synthesizer - Online: The tool's online version allows one to create a logic design, synthesize it, and download it as a file (bitstream). In addition to the bitstream, a template source code is provided for configuring the CLB, but integrating it into the embedded project is left up to the user.

The logic configuration experience is common to both versions of the tool, so the tool's online version can be used to start a logic design using the CLB before moving to MCC Melody for further development.

Table of Contents

CLB Synthesizer....1

Tool Versions: MCC-Integrated and Stand-Alone-Online ....1

1. Getting Started....4

2. Drawing a Schematic....5

2.1. Components in CLB Synthesizer....5

2.2. Drawing a Basic Schematic.... 11

1. Status of the Synthesis Process....13

2. Tips and Tricks....14

4.1. How to Make use of Limited Display Resources.... 14

4.2. Tidying up a Design.... 15

1. Interacting with Peripherals and the CPU....17

5.1. Interacting with Peripherals.... 17

5.2. Interacting with the CPU....18

1. Storing and Retrieving Logic Designs....20

2. Using Hierarchical Modules......21

7.1. Using Verilog to Describe a Logic Design....22

1. Libraries and Modules....24

8.1. The Built-In PIC16F131 Device Library....24

8.2. Using the Hardware Counter 24

8.3. Using Modules from the Microchip Library....25

8.4. Using Modules from a Custom Library.... 25

8.5. Creating a Library with Modules....26

1. Advanced Topics....30

9.1. Clocking the Configurable Logic Block....30

9.2. Preferences....30

9.3. Making Use of the Output ZIP....31

9.4. Description of Output Files....31

9.5. Synthesis and Place-and-Route Process.... 32

1. Known Issues and Change Log....34

2. Revision History....35

Microchip Information.... 36

The Microchip Website....36

Product Change Notification Service.... 36

Customer Support....36

Microchip Devices Code Protection Feature....36

Legal Notice....36

Trademarks....37

Quality Management System....38

Worldwide Sales and Service....39

1. Getting Started

Use Cases to hit the ground running with the CLB.

The CLB Synthesizer start page provides:

• A way to start a new design, load a previous design, or continue with the current design
• Quick-start examples for users to browse and see how the tool works
• Documentation links

CLB Synthesizer

Start

Blank design

Load...

Continue last project

CUB Synthesis • Instruments • D:\Users\* • Components • Components (1) • Complexity (2) • Complexity (3) • Complexity (4) • Complexity (5) • Complexity (6) • Complexity (7) • Complexity (8) • Complexity (9) • Complexity (10) • Complexity (11) • Complexity (12) • Complexity (13) • Complexity (14) • Complexity (15) • Complexity (16) • Complexity (17) • Complexity (18) • Complexity (19) • Complexity (20) • Complexity (21) • Complexity (22) • Complexity (23) • Complexity (24) • Complexity (25) • Complexity (26) • Complexity (27) • Complexity (28) • Complexity (29) • Complexity (30) • Complexity (31) • Complexity (32) • Complexity (33) • Complexity (34) • Complexity (35) • Complexity (36) • Complexity (37) • Complexity (38) • Complexity (39) • Complexity (40) • Complexity (41) • Complexity (42) • Complexity (43) • Complexity (44) • Complexity (45) • Complexity (46) • Complexity (47) • Complexity (48) • Complexity (49) • Complexity (50)

Quick-start examples

Example 1: inverting a signal

Example 2: software driven multiplexer

Example 3: clock divider to a timer

Example 4: PSK encoders

Documentation

CLB Synthesizer User Guide

PIC16F13145 Family Product Brief

2. Drawing a Schematic

Getting started with logic design.

This section contains an introduction to the components in CLB Synthesizer and getting started with a logic design.

2.1 Components in CLB Synthesizer

Following are the components available in CLB Synthesizer.

2.1.1 Ports

Port components represent the interface between a hierarchical layer and the layer above and are strictly input or output.

An input port is an input to the CLB: unconfigured An output port is an output from the CLB: unconfigured

There are two main categories of ports:

• I/O ports (Global)
- Off-sheet ports (hierarchical)

Global Input Ports

Global I/O ports represent the interface to other peripherals on the MCU. To place an input port, drag and drop the input port symbol onto the canvas and select the I/O option in the Properties panel.

PROPERTIES I/O Port Off-Sheet Port Input Ports Filter search CLBIN0PPS CLBIN1PPS CLBIN2PPS CLBIN3PPS FOSC HFINTOSC

The selection box specifies to which signal the input is mapped.

Note: Selecting a signal to be used as an input does not configure the actual source of that signal. Make sure to configure the peripheral or clock source to produce the signal.

Input ports from other peripherals have one of four synchronizer options selected in the Input Synchronizer options box. For more information, see 5.1.1. Input Synchronizers.

Input ports from the CPU do not have synchronizer options. For more information, see 5.2.1. Using CLBSWIN.

Usually, the global ports are used only at the top level (main), but there are cases in which it makes sense to use global input ports on sub-sheets. It is also possible to use the same input signal with an alternative synchronizer option - in which case a second input port symbol must be used, and the alternative synchronizer option applied to that input.

Global output ports

To place an output port, drag and drop the output port symbol onto the canvas and select the I/O option in the Properties panel.

PROPERTIES I/O Port Off-Sheet Port Output Ports Filter search PPS_OUT0 PPS_OUT1 PPS_OUT2 PPS_OUT3 PPS_OUT4 PPS_OUT5

The selection box specifies to which signal the output is mapped.

Note: Selecting a signal to be used as an output does not configure the actual destination of that signal. Make sure to configure the peripheral to use the signal as its input.

For more information on output signals, see 5.1.2. CLB Outputs to other Peripherals.

Off-Sheet I/O Ports

Off-sheet ports represent the interface from the module defined on that particular sheet to the sheets in which the module is used. To place an off-sheet port, drag and drop the input or output symbol onto the canvas, select the Off-Sheet Port option in the Properties panel, and give the signal an appropriate name.

Note: Verilog keywords and other reserved words cannot be used as sheet or signal names.

PROPERTIES ○ I/O Port ● Off-Sheet Port Off-Sheet Port Name in

For more information on hierarchical design, see 7. Using Hierarchical Modules.

2.1.2 Logic Gates

The building blocks of a configurable logic design.

The CLB Synthesizer provides a palette of common logic gates in the left hand panel.

Diagram showing various logic gate symbols including NAND, OR, and NOT gates with corresponding labels.

To use a logic gate, drag and drop the symbol from the palette onto the canvas and connect it as required.

Note: Input and output ports of logic gates must not be left unconnected.

2.1.3 Flip-Flops

Building blocks for synchronous logic designs.

The CLB Synthesizer provides four basic flop-flops to use in synchronous designs.

D Q EN D Q EN R J Q K

Notes:

• The CLB architecture has only one type of flip-flop, identical to its BLEs.

- It is not possible to provide an input clock to any flip-flops. For more information, refer to 9.1. Clocking the Configurable Logic Block.

2.1.4 Multiplexers

Switching between signals.

The CLB Synthesizer provides two multiplexers (muxes) for use in logic designs - one with a single-bit select input and one with a two-bit select input.

3 2 1 0 S0 S1 1 0

Note: The CLB architecture does not contain actual MUXes - these are implemented in the CLB by LUTs.

2.1.5 Look-up Tables

Manually configured logic functions.

The CLB Synthesizer provides a four-bit LUT implementation.

A B C D LUT Q 2482

To use the LUT, drag and drop the LUT symbol onto the canvas and set the output (Q) states in the properties panel according to the required logic function.

PROPERTIES

DCBA	Q
0000	0
0001	1
0010	0
0011	0
0100	0
0101	0
0110	0
0111	1
1000	0
1001	0
1010	1
1011	0
1100	0
1101	1
1110	0
1111	0

Note: Although the CLB architecture consists of four input LUTs, it is no guarantee that a manually entered LUT will be implemented entirely in one BLE LUT in the same way it was drawn. The synthesis process will always produce the logic equivalent to this LUT, which may be simplified or distributed over several actual BLEs.

2.1.6 Constants

A source of a fixed signal.

The CLB Synthesizer provides several ways to give a fixed signal to an input:

- Individual constant output bits can be connected to inputs

- Multi-signal constants

0:1 1:0 2:1 3:0 0x5

- Configure the number of bits and their values in the properties panel

0 1 1 0 2 1 3 0 + - 05

- A Zero port can also be used to provide a constant by using an input MUX position

ZERO

Note: Although constants can be useful in many cases, they can also be a source of problems. The input logic is optimized into a logical equivalent during the synthesis process. When using constants, this has a major impact. The "zero port" is an exception since it is treated as any other input signal with an unknown value. For more information, see 9.5. Synthesis and Place-and-Route Process.

2.1.7 Net Labels

Using the same signal in many places in a design.

A netlabel component dispenses a signal to be used in several places in a logic design, which can increase the readability of a schematic by reducing the number of crossing lines.

For example, then inverted CLBIN1PPS signal is used immediately (connection not shown) and routed to a netlabel SWITCH.

CLBIN1PPS SWITCH

The SWITCH signal can then be used elsewhere in the design as a source.

graph TD
    A["CCP1_OUT"] --> B["1"]
    C["SWITCH"] --> B
    B --> D["Output"]

2.2 Drawing a Basic Schematic

How to get started with a logic design.

The CLB Synthesizer GUI simplifies the process of creating a logic design.

Step 1: Add and configure logic input sources

- Drag-and-drop an input port from the left side panel onto the canvas

- Select the input port and configure its source properties in the right-hand panel

PROPERTIES I/O Port Off-Sheet Port Input Ports Filter search CLBIN0PPS CLBIN1PPS CLBIN2PPS CLBIN3PPS FOSC HFINTOSC

- Repeat as needed

Step 2: Add and configure logic outputs

- Drag and drop an output port from the left side panel onto the canvas

- Select the output port and configure its destination properties in the right-hand panel

PROPERTIES I/O Port Off-Sheet Port Output Ports Filter search PPS_OUT0 PPS_OUT1 PPS_OUT2 PPS_OUT3 PPS_OUT4 PPS_OUT5

- Repeat as needed

Step 3: Add logic content

- Drag and drop logic gates, flip-flops, multiplexers, LUTs and constants from the palette on the left side panel onto the canvas

CLBIN2PPS PPS_OUT1

- Connect them up by dragging connections from outputs to inputs, or vice versa

graph LR
    A["CLBIN2PPS"] --> B["Square"]
    B --> C["Square"]
    C --> D["Inverter"]
    D --> E["Circle"]
    F["PPS_OUT1"] --> G["Square"]
    G --> H["Arrow to C"]
    style A fill:#FFD700,stroke:#333
    style F fill:#FF6347,stroke:#333

- Add comments for future understanding

graph LR
    A["CLBIN2PPS"] --> B((NOT gate))
    B --> C["PPS_OUT1"]

Step 4: Synthesize

- Click the Synthesize button, and the logic design is converted into a bitstream using a Microchip online service

3. Status of the Synthesis Process

Understanding the synthesis status indicator

A synthesis process converts a logic design into bitstream form which can be loaded into the CLB. This is triggered by clicking the Synthesize button.

The outcome of the synthesis process is indicated by the status indicator and the resource view.

Successful Synthesis

A green indicator will show when the synthesis succeeds and the resource view is updated.

SYNTHESIZE STATUS Synthesize LUTs: 14 of 32 used

The resource view indicates how much of the CLBs resources have been used, and hovering the mouse over it gives additional information.

Failed Synthesis

A red indicator will show when synthesis has failed.

SYNTHESIZE STATUS Synthesize

The nature of the failure can be determined by:

• Checking the problems/notifications panels for warnings about unconnected pins
• Downloading the ZIP and checking the backend log output. This must also be included when consulting Microchip support channels.

Tip: Selecting the entry in the Problems panel highlights the component or port that is causing the problem.

Resource Usage Debugging

Resource allocation when using the CLB Synthesizer is done by the place and route algorithm in the backend synthesis process. Determining the reason for failure can be complicated, since there are some resources which are locked to individual BLE outputs or a range of BLE outputs. Therefore, a small logic design cannot be synthesized if these resources are in conflict (technically this is a failure to complete place-and-route). In cases where synthesis fails, these actions can be taken to try to alleviate the conflict and reach a solution:

• Try to use alternative outputs (eg: change IRQ0 to IRQ1)
• Try to remove some logic functionality
• Check that there are no unused modules included in the documents
• Check that there are no logic functions with pre-determined outputs (eg: a constant zero as an input to an AND gate)

When contacting Microchip support, include the ZIP file which was returned from the failing synthesis process.

4. Tips and Tricks

Productivity tips and tricks for the CLB Synthesizer.

4.1 How to Make use of Limited Display Resources

Tips for using small displays.

When using the CLB Synthesizer inside MCC the amount of display real-estate available for logic drawings becomes constrained. It is possible to float the logic editor view to mitigate this.

Right click on the CLB1 tab and select Float from the menu.

CLB1 Close Ctrl+W Close All Ctrl+Shift+W Close Other Maximize Shift+Escape Float Float Group Dock Alt+Shift+D Dock Group Shift Left Shift Right Clone New Document Tab Group Collapse Document Tab Group

The CLB1 tab can then be moved onto an additional display or maximized on the current display by clicking one of the maximize buttons at the top of the window.

CLB1 Easy View Reg ▼ Software Set Custom Name PROPERTIES

To restore the layout right-click on the CLB1 tab and select Dock from the menu.

CLB1 - Editor

CLB1 Close Ctrl+W Close All Ctrl+Shift+W Close Other Maximize Shift+Escape Float Float Group Dock Alt+Shift+D Dock Group Shift Left Shift Right Clone New Document Tab Group Collapse Document Tab Group

It is also possible to toggle the side and lower panels on and off using the control on the upper right side of the editor window:

• The left control toggles on and off the component palette to the left of the editor window
• The middle control toggles on and off the problems panel at the bottom of the editor window
• The right control toggles on and off the properties panel to the right of the editor window

4.2 Tidying up a Design

Making a logic design orderly and readable.

Making connections between components on the canvas is a simple process of connecting a source to a sink. The signal drawn on the schematic usually follows the shortest route by default, but can be manually edited to make a schematic design more readable. This process may require some practice and follows these main concepts:

- Selecting a signal will show what nodes are available for altering the path it takes. Elbow nodes are shown as squares and are used to move the node itself, while and mid-point nodes are diamond-shaped, and are used to split a line into additional segments.

Pure geometric line diagram with no text, numbers, or symbols

- Hovering over a elbow node indicates which axes are available for altering the location of that node. Dragging this node in one of the indicated directions will move the location of that node.

Pure geometric lines forming an angle on grid paper (no text or symbols)

• Hovering over a mid-point always shows that is can be moved (split) in any direction

Pure decorative symbol with a central cross-like motif and horizontal blue line on grid background (no text or symbols)

- Dragging a mid-point node splits the section into two segments and moves the location of the split-point accordingly

Pure geometric line diagram with no text, numbers, or symbols on grid paper (no text or symbols)

- Split segments can be joined by manually aligning the two segments by dragging the elbow node - dragging the mid-point will create an additional split

The following methods can also be used to create a more orderly schematic design:

- Modules: by extracting functional parts of a design into separate documents, a logic design can be divided into several hierarchical layers. This not only makes the top-level (main) schematic more tidy and readable, but allows the modules to be used multiple times in the same design without duplication. For more information, see 7. Using Hierarchical Modules.

- Net labels: if the same signal needs to be used on opposite sides of a schematic a net label can be used instead of drawing a wire across the schematic. For more information, see 2.1.7. Net Labels.

- Input ports can be duplicated in cases where the same input signal is required in multiple places. This may help to reduce congestion of signals, but may reduce maintainability.

Note: It is possible to use the same input more than once with a different input synchronizer setting on each instance.

- Rotate and flip: all components can be rotated and flipped so that they can be aligned to suit the signals they are connected to. Right-click a component or port on the canvas and select the function from the context menu, or select the item and use shortcut keys 'R' (rotate), 'X' (horizontal flip) or 'Y' (vertical flip).

- Comments: adding comments to a schematic improves readability and can be used to add context to the design itself.

5. Interacting with Peripherals and the CPU

How to make connections between the CLB, CPU and other peripheral modules.

5.1 Interacting with Peripherals

Interaction with other peripherals is done by using the input ports from other peripherals and output ports to other peripherals in a logic design. Consult the device datasheet for information on how these signals are used by the corresponding peripheral.

5.1.1 Input Synchronizers

Making use synchronizers on input signals

The CLB peripheral includes 16 input sources, which connects the CLB to external signals, in addition to the 32 CLBSWIN signals for interacting with the CPU. The 16 input sources include modifiers which can be used to condition the incoming signal before it enters the BLE matrix.

Input synchronizer options are selected on the right side properties panel below the input port source selection box.

Input Synchronizer options

Synchronized input (default)

Direct input

Positive edge detector

Negative edge detector

The available input synchronizer options are shown in the following table:

Table 5-1. Input Synchronizer Options

Option Description
Synchronized input The input signal will be synchronized to the CLB clock. This is the default, and the safest option when unsure.
Direct input Synchronization is bypassed, and the input signal is connected directly to the BLE input.This must be used with caution as it can cause metastability in sequential logic designs.
Positive edge detector A rising edge on the input signal will generate a pulse synchronized to the CLB clock
Negative edge detector A falling edge on the input signal will generate a pulse synchronized to the CLB clock

Notes:

• The CLBSWIN signals cannot pass through the input synchronizers
• The input synchronizer is selected in hardware with three configuration bits, but not all eight possible permutations are made available in the CLB Synthesizer

5.1.2 CLB Outputs to other Peripherals

How to route signals from the CLB to other peripheral modules

The CLB BLE outputs can be connected to various other peripherals. This is a two-stage process:

Step 1: Configure an output from the CLB

In the CLB Synthesizer GUI, configure an output port by selecting the peripheral signal to route to in the port properties panel.

graph LR
    A["CLBIN0PPS"] --> B["NOT"]
    B --> C["CLB_TMR1_GATE"]
    style B fill:#f9f,stroke:#333
    style C fill:#ccf,stroke:#333

Synthesize the logic design.

Step 2: Configure the peripheral to accept the signal from the CLB

The peripheral to which the CLB is connecting must be configured to accept the CLB input signal. This is Peripheral-dependent, consult the datasheet for more information.

The peripheral input selector usually specified a range of BLEs which can be used as inputs from the CLB. It is not up to the user to specify this - the place and route algorithm must hit one of these BLEs to satisfy the criteria to use the peripheral. The actual BLE which was realized during synthesis receives the synthesis output.

MCC Users

MCC will automatically unpack the output from the synthesis process and notify the user on how to configure the peripherals being connected to. Check the Notifications window after synthesis.

Web/Bare-Metal Users

Users of the web version need to download the ZIP output from the synthesis process and examine (or use directly) the contents of clb1_output_mappings.h file, which provides values for use in the peripheral configuration register.

5.2 Interacting with the CPU

Interaction between the CPU (running code) and the CLB using the CLBSWIN register.

5.2.1 Using CLBSWIN

How to use CLBSWIN from the MCU

The CLB Software Input register (CLBSWIN) enables the MCU to communicate directly with the logic design in the CLB. So for example, this can be used to load a 'value' into the CLB at run time.

To make use of the CLBSWIN register within a logic design, simply use the individual CLBSWINn bits as input ports.

If a logic design needs to trigger an action when a new value is written to CLBSWIN, then the CLBSWIN_SFR_WR_HOLD input signal can be used. This signal is asserted when the CPU writes a new value to CLBSWIN and that value have been latched into the CLB.

CLB Synthesizer

Interacting with Peripherals and the

CPU

graph TD
    A["Nibble from CPU"] --> B["CLBSWIN0"]
    A --> C["CLBSWIN1"]
    A --> D["CLBSWIN2"]
    A --> E["CLBSWIN3"]
    F["Latch signal"] --> G["CLBSWIN_SFR_WR_HOLD"]

Notes:

• The CLBSWIN register cannot be used via the input synchronizers
• The CLBSWIN_SFR_WR_HOLD signal is asserted only when the lower eight bits of CLBSWIN are written (CLBSWINL), so the byte must be written after writing the upper bytes in CLBSWIN

6. Storing and Retrieving Logic Designs

The circuit drawings and verilog content of your logic design can be saved to a file in json format

D main × New design Load design... Save design... Save design as module... Preferences... Show start page About...

Load and save functionality is accessed from the left panel, in the main drawer-menu.

The entire content of a logic design can be stored to disk for later use by clicking the Save design button. When using the web version, this is a file download from the browser, and the file will be stored in the default download location for that browser. When using MCC, this file can be stored in a custom location.

To continue working with a previously saved logic design, the Load design button will open a file browser where the stored file can be selected and loaded.

The file extension is .clb, and its content is a json string including all content in the design.

7. Using Hierarchical Modules

Complex logic designs can increase their readability, and be reused by placing logic functions in modules, and then using that module elsewhere in the design.

Modules are defined as schematics or Verilog descriptions, which are managed in the documents section of the left panel.

≡ D New schematic V New Verilog

Step 1. Create a new module

• In the documents drawer-menu, select New schematic or New Verilog
- Give the module a suitable name

The module is added to the document list, and a new tab appears for its definition.

DOCUMENTS D better_inverter D main V verilog_inverter

The icon indicates which of the documents is the top-level document in the hierarchy.

Step 2a. Schematic module

• Draw the required logic for the module
• Add input and output ports accordingly using the Off-Sheet Port in the properties pane and giving them suitable names for the function of the module

PROPERTIES I/O Port Off-Sheet Port Off-Sheet Port Name in

graph LR
    A["in"] --> B((△))
    B --> C["O"]
    C --> D["out"]

Step 2b. Verilog module

• Describe the module in Verilog
  • The Verilog module must have the same name as the document

• Take care to define the module inputs and outputs

V verilog_inverter ✗
1 module verilog_inverter (in, out);
2    input in;
3    output out;
4    logic net2;
5    not U1 (net2, in);
6    assign out = net2;
7 endmodule
8 

Step 3. Use the module

• When the module is complete and has no problems, switching back to the main/top-level document will update the modules list on the left side-bar
• Drag the new module onto the canvas
• Connect it up and use it

MODULES better_inverter verilog_inverter

graph TD
    A["CLBIN0PPS"] --> B["better_inverter"]
    A --> C["verilog_inverter"]
    B --> D["PPS_OUT1"]
    C --> E["PPS_OUT2"]

Tip: You can double-click a module to descend into its contents.

7.1 Using Verilog to Describe a Logic Design

Advanced users can make use of Verilog to describe their logic rather than drawing a logic circuit.

Step 1. Create a new Verilog document

• Click on the 'New Verilog' with 'V' symbol
• Name it as you like

CLB Synthesizer DOCUMENTS main COMPONENTS ≡ ≡ D main × D New schematic V New Verilog

Step 2. Add your Verilog module

• Delete the long line with random numbers and letters (used for internal debugging)
• Give your module the same name as the document (step 1)
• Define inputs and outputs at the module level
• Add the 'code'

CLB Synthesizer DOCUMENTS main myverilog COMPONENTS D main × V myverilog × module myverilog(IN1,IN2,IN3,OUT); input IN1, IN2, IN3; output OUT; or U1 (OUT, IN1, IN2, IN3) endmodule

Step 3. Click on the main document tab, and select the Design side bar on the left

• Your Verilog module will appear under "modules"
• Drag it in and connect it up as any other logic symbol

graph LR
    A["CLBIN0PPS"] --> B["myverilog"]
    C["IN1"] --> B
    D["IN2"] --> B
    E["IN3"] --> B
    B --> F["OUT"]

8. Libraries and Modules

Making a library of modules that can be easily re-used.

The CLB Synthesizer supports hierarchical designs which includes sub-sheets as either schematics or verilog. It is also possible to store these sub-sheets in a way that they can be reused in multiple designs or projects. A single functional item, which may itself be implemented across multiple sheets, is referred to as a module, and a collection of modules is referred to as a library.

8.1 The Built-In PIC16F131 Device Library

The hardware counter in the CLB is accessed by using a counter module in the built-in PIC16F131 Device Library.

Working with the built-in counter module is no different to working with a custom module from a custom library.

8.2 Using the Hardware Counter

How to work with the built-in hardware counter.

The CLB peripheral contains a dedicated 3-bit hardware counter. This is a convenient building block to use when, for example, implementing state machines. The counter has STOP and RESET inputs, which must be connected, and 8 one-hot outputs which can be used according to needs.

The counter is always available in the PIC16F131 Device Library in the Library section of the left side-bar.

LIBRARY PIC16F131 Device Library pic16f131_counter

Click the + icon nect to the pic13f131_counter to add the counter to a design.

LIBRARY PIC16F131 Device Library pic16f131_counter + Copy into design

Once added to a design, it will appear as a module in the modules section of the left side-bar.

MODULES pic16f131_counter

The counter can now be placed onto the schematic canvas and connected up as required.

pic16f131_counter STOP COUNT_IS_0 RESET COUNT_IS_1 COUNT_IS_2 COUNT_IS_3 COUNT_IS_4 COUNT_IS_5 COUNT_IS_6 COUNT_IS_7

8.3 Using Modules from the Microchip Library

Microchip publishes a library of modules for the CLB Synthesizer on GitHub in the Microchip PIC&AVR Tools pages. This library includes counters, shifters and other utility functions that can be used in a logic design in the CLB Synthesizer.

Download the library from GitHub before it can be used in a logic design. To save the library to local storage, use the Download ZIP menu option in the Code drop-down menu.

Go to file t Add file Code Local Codespaces Clone HTTPS SSH GitHub CLI https://github.com/microchip-pic-avr-tools/pic Clone using the web URL. Open with GitHub Desktop Download ZIP

Follow the procedure outlined in 8.4. Using Modules from a Custom Library to use a module from the library.

8.4 Using Modules from a Custom Library

Load a library into the CLB Synthesizer before its modules can be used in a design.

Note: The CLB Synthesizer currently supports only loading libraries from locally stored archives. First, download the library as a zip archive and store it locally to use the stored libraries in version control systems like GitHub.

To load a library to be used in a design:

1. Use the Load Library from file option on the drawer menu on the library section of the left-side panel.

2. Browse and select the library zip archive.

3. The newly loaded library will appear as a new entry in the library section of the left-side panel. The individual modules included in that library are listed below the library.
4. Click the + next to a module to include that module in the current design. It appears in the modules section, and the associated sheets and Verilog files appear in the documents section.
5. Use the module by dragging the module representation from the modules section onto the canvas and connecting it as required in the design.

Note: A module included in a design is a copy of the module from the Library section, meaning that if the library source is changed, it has to be re-imported into the design. This also means that it is possible to use a module from a library and make changes to it after importing it without affecting the original library source.

8.5 Creating a Library with Modules

The re-used logic functionality designs can be saved as modules, which can be included in a library archive.

Step 1: Create the module using sub-sheets

Start with a new design in the CLB Synthesizer. Create at least one document in addition to main and sketch logic content or write Verilog to perform the function of the module. During this process the main schematic page (top-level) functions as a test bench. The entire module (all sub-sheets) and the test bench (main) must synthesize successfully before continuing.

This example:

• Creates a document called "myinverter"
• Uses off-sheet ports to invert signal 'a' to signal 'b'
• Uses the "myinverter" module in main and connects it to PPS ports as a test bench
  • Synthesizes successfully

CLB Synthesizer DOCUMENTS main myinverter COMPONENTS unconfigured unconfigured D main × D myinverter × a b

graph LR
    A["CLBIN0PPS"] --> B["myinverter"]
    B --> C["PPS_OUT1"]

Step 2: Remove the testbench

Before exporting a module, the test bench must be removed since it is not part of the module.

Click the trash can icon next to main in the documents section and remove it.

CLB Synthesizer ≡ DOCUMENTS ≡ main myinverter Delete this file

Note: The design will no longer synthesize successfully since it no longer has an entry point. This is the correct behaviour for creating a module.

Step 3: Save the module

In the main drawer-menu in the CLB Synthesizer, select Save design as module

CLB Synthesizer DOCUMENTS myinverter COMPONENTS unconfigured unconfigured New design Load design... Save design... Save design as module... Preferences... Show start page About...

Give the module an appropriate name.

This example saves the module as "myinverter.zip"

Save the module in a convenient place.

Step 4: Create a library structure

Create a new folder in a convenient place. This will be known as the "library folder".

Tip: The working folder can be in a git version control system if the library is to be distributed by browsing in the git repository. This is optional.

Important: When adding a new module to an existing library, skip this step.

Inside the library folder, create a new folder/directory with the same name as the module in a convenient place and copy the entire contents of the archive from 8.5. Step 3: Save the module into this folder. This includes a manifest, readme and one or more sheets.

Step 5: Document the library

In the library folder, create a new text file called manifest.json and add a manifest in this form, using a suitable name in the "name" field and a new GUID in the "id" field.

{
    "type": "CLB Synthesizer Library",
} 

"formatversion": "1.0",
"name": "DemoLib",
"id": "xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx",
"version": "1.0.0"
} 

Attention: When adding a new module to an existing library, skip this step.

Important: A new library required a new GUID. Use an online tool to generate a globally unique ID.

Add a readme.md file and describe the library using markdown format.

Step 6: Document the module (optional)

Edit the readme.md to describe the module

Step 7: Create and test the library archive

Add all the content of the library folder to a new zip archive. Any name can be used here, but take care not to include the library folder itself inside the archive.

The resulting zip archive is now the library which contains the module.

To test it, start a new design in the CLB synthesizer and use the Load library from file option in the drawer-menu in the library section of the left-pane. The newly created library should appear, with the module inside it, ready to be used.

Step 8: Deployment of libraries

A library can be deployed in the simplest of ways by storing the archive zip file and distributing it.

Alternatively, the library folder from step 4 can be placed inside a version control system such as git. Note: The library zip archive itself should not be checked into version control, but rather the contents.

Once under version control, new modules can be added and module versions managed accordingly.

Users can download library archives using the web interface to the version control system as supported by most modern version control system interfaces. For example this is done in GitHub using the Download ZIP menu on the repository.

Go to file Add file Code Local Codespaces Clone HTTPS SSH GitHub CLI [e-mail]:mraardvark/clblib.git Use a password-protected SSH key. Open with GitHub Desktop Download ZIP

9. Advanced Topics

Additional reading for advanced users.

9.1 Clocking the Configurable Logic Block

How the CLB relates to clocks

The CLB peripheral receives its clock input from the source specified in the CLK field in the CLBCLK register which is written from the CPU. Consult the datasheet for available clock sources.

The CLB also includes a clock divider which must be configured along with the logic design, and is incorporated into the bitstream. The clock source can be divided by 1, 2, 4, 8, 16, 32, 64 or 128.

Note: The CLB clock divider is configured in the Easy View window inside MCC and the Global Settings panel in the Web version.

The CLB clock is distributed to all BLE flip-flops, so the entire logic design runs off the same clock. So although logic design schematics can include various flip-flop types, it is not possible to connect or configure an individual clock source.

Pure electrical circuit symbol for a D flip-flop without any text or labels

9.2 Preferences

The preferences panel is accessed via the main drawer-menu.

Preferences Synthesis backend URL https://logic.microchip.com/api/v2/synthesize Reset Localhost Synthesis settings Always allow synthesis View Show model Show HDL Show output OK Cancel

Option Description
Synthesis backend URL	URL for the synthesis server. This should not be changed unless instructed to by Microchip support engineers.
Show model	The right-hand pane will show the "GUI model" of the current design - this is for internal debugging of the GUI.
Show HDL The right-hand pane will show the intermediate HDL of the current design. This content will be sent to the backend for synthesis - it is for internal debugging of the interface between GUI and backend.
Show output The right-hand pane will show output from the synthesis engine - this is for internal debugging of the backend logic-synthesis engine.

9.3 Making Use of the Output ZIP

How to use the output

The synthesis process should always return a ZIP file with outputs.

Note: MCC users do not need to relate to the ZIP file contents.

The ZIP file is intended for the CLB Synthesizer Web version's users who want to convert a logic design into a bitstream.

The ZIP file contains a readme file which provides details about:

• The resultant bitstream
• A basic CLB driver for configuring the peripheral
- Build artefacts

For further details, read the readme inside the ZIP.

9.4 Description of Output Files

After synthesis, a ZIP file containing many build artifacts can be downloaded. The filename prefix (XXX) is determined by the server in some cases.

The files in the zip are intended for bare-metal users and/or for debugging purposes:

• Root folder: outputs for use in bare-metal projects
  • Build folder: debug artifacts from the build process
• Build/input folder: inputs passed into the server for processing

Filename Description
readme.txt Instructions for bare-metal users
clb1.c; clb1.h Driver for configuring and enabling the CLB
clb1_output_mappings.h	Header file defining output mappings from eh CLB to peripherals
bitstream.s Bitstream in assembler format for embedding into a bare-metal project
input/*.v Verilog representation of input design
input/*.xdc Mappings to physical pins
input/project.json Top level description of the design
input/stats.json	Statistical summary of the design
input/*.clb	Save-file for the design
XXX.inputs.json	List of design Inputs in json format
XXX.outputs.json	List of design outputs in json format
XXX.bitstream.output Declarations.json	Peripheral output mappings in json format
XXX.bitstream	Raw bitstream words
XXX.bitstream.json	Bitstream words in json format
XXX.result.json	Entire operation output summary as json
......continued
Filename Description
XXX.json json formatted netlist output from Yosys
XXX.v Verilog netlist output from Yosys (before place and route)
XXX.netlist Binary form of netlist
XXX.phys Binary form of physical netlist
XXX.net Packed netlist in XML format
XXX.net.post_routing Post-routing packed netlist in XML format
XXX.place Placer output report
XXX.route Router output report
packaging_pin_util.rpt Packing pin usage report
XXX.fasm Output from FASM stage
XXX.svg Diagramatic representation output from Yosys (generic)
XXX-2.svg Alternative diagramatic representation output from Yosys (generic)
XXX.dot Input to svg above
vpr_stdout.log Place and route output
XXX.yosys.log	Log from Yosys synthesis stage
XXX.stderr.txt	Stderr output

9.5 Synthesis and Place-and-Route Process

What goes on behind the scenes

Once an application has been captured in the CLB Synthesizer GUI, it needs to be converted into a configuration bitstream which can be loaded into the CLB module itself. This process is known as "synthesis", although it also includes place and route steps, and is done by Microchip's online web-service.

It is not necessary for a user to understand how this process works - a brief summary is given here for advanced or curious users.

How it works

1. The schematic drawings of the CLB application are converted to equivalent Verilog descriptions which are then passed to the backend for processing.
2. The first stage in the backend process is logic synthesis. Logic synthesis is a process of converting the Verilog textual representation of a logic design into a netlist which describes the hardware in equivalent logic gates and wires. Logic synthesis is done using Yosys Open SYNthesis Suite which is equipped with a plug-in that describes the actual structure of the logic elements in the CLB module. The output of the synthesis stage is a Verilog netlist.
3. The next stage is place-and-route (PNR). During this stage the netlist elements are mapped into physical locations in the CLB array (placement), and interconnects are made between them (routing). This is a complex and iterative process, and is not guaranteed to achieve an outcome (eg: if space or routing constraints are exceeded). Place-and-route is done using the VPR provided by Verilog to Routing (VTR) which is equipped with a plug-in that describes the actual available interconnects within the CLB module. The output of the PNR stage is a FASM file, which specifies the CLB configuration content in a generic, plain-text format.
4. The final stage is bitstream generation. The bitstream generator parses the FASM file and converts configuration of generic configurable logic resources into bit patterns in a bitstream according to the actual CLB bitstream implementation. The bitstream generator is a script which is specific to the Microchip CLB implementation. The output of the bitstream generator is a sequence of bits which are to be loaded into the CLB during configuration. This is embedded as

a sequence of data words (DW) which are stored as constants in flash by the compiler during building of the application.

10. Known Issues and Change Log

If you experience unexpected behavior, read the known issues list here.

The CLB Synthesizer toolchain comprises of:

• The synthesis engine (backend), hosted in the cloud
• CLB Synthesizer GUI hosted in the cloud at logic.microchip.com/clbsynthesizer/
• CLB Synthesizer GUI integrated into MCC, deployed via Content Manager

Find the latest changes for all of these components here.

11. Revision History

Doc. Rev. Date Comments
A 04/2024 Initial document release

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