MCP33111-05 - Convertisseur analogique-numérique Microchip - Free user manual and instructions

USER MANUAL MCP33111-05 Microchip

1 Msps/500 kSPS 16/14/12-Bit Single-Ended Input SAR ADC

Features

• Sample Rate (Throughput):

- MCP33131/21/11-10: 1 Msps

- MCP33131/21/11-05: 500 kSPS

• 16/14/12-Bit Resolution with No Missing Codes

- No Latency Output

- Wide Operating Voltage Range:

- Analog Supply Voltage (AV _DD ): 1.8V

- Digital Input/Output Interface Voltage (DV _IO ): 1.7V - 5.5V

- External Reference (V _REF ): 2.5V - 5.1V

- Pseudo-Differential Input Operation with Single-Ended Configuration:

- Input Full-Scale Range: 0V to +V _REF

- Ultra Low Current Consumption (typical):

- During Input Acquisition (Standby): \~ 0.8 μA

- During Conversion:

MCP331x1-10: \~1.6 mA

MCP331x1-05: \~1.4 mA

• SPI-Compatible Serial Communication:

- SCLK Clock Rate: up to 100 MHz

- ADC Self-Calibration for Offset, Gain, and Linearity Errors:

- During Power-Up (automatic)

- On-Demand via user's command during normal operation

• AEC-Q100 Qualified:

- Temperature Grade 1: -40°C to +125°C

• Package Options: MSOP-10 and TDFN-10

Typical Applications

• High-Precision Data Acquisition
• Medical Instruments
- Test Equipment
• Electric Vehicle Battery Management Systems
• Motor Control Applications
- Switch-Mode Power Supply Applications
- Battery-Powered Equipment

System Design Supports

The MCP331x1-XX Evaluation Kit demonstrates the performance of the MCP331x1-XX SAR ADC family devices. The evaluation kit includes: (a) MCP331x1-XX Evaluation Board, (b) PIC32MZ EF Curiosity Board for data collection, and (c) SAR ADC Utility PC GUI.

Contact Microchip Technology Inc. for the evaluation tools and the PIC32 MCU firmware example codes.

Package Types

MSOP-10 VREF 1 AV_DD 2 AIN+ 3 AIN- 4 GND 5 Top View 10 DVIO 9 SDI 8 SCLK 7 SDO 6 CNVST TDFN-10 VREF 1 AV_DD 2 AIN+ 3 AIN- 4 GND 5 Top View 10 DVIO 9 SDI 8 SCLK 7 SDO 6 CNVST

MCP331x1-XX Device Offering (Note 1):

Part Number	Resolution	Sample Rate	Input Type	Input Range	Performance (Typical)
					SNR (dBFS)	SFDR (dB)	THD (dB)	INL (LSB)	DNL (LSB)
MCP33131-10	16-bit	1 Msps	Single-Ended	0V to 5.1V	86.7	98.9	-97.4	±2.2	±0.9
MCP33121-10	14-bit	1 Msps	Single-Ended	0V to 5.1V	83.5	98.8	-97.2	±0.55	±0.25
MCP33111-10	12-bit	1 Msps	Single-Ended	0V to 5.1V	73.8	95.9	-93.7	±0.12	±0.06
MCP33131-05	16-bit	500 kSPS	Single-Ended	0V to 5.1V	86.7	98.9	-97.4	±2.2	±0.9
MCP33121-05	14-bit	500 kSPS	Single-Ended	0V to 5.1V	83.5	98.8	-97.2	±0.55	±0.25
MCP33111-05	12-bit	500 kSPS	Single-Ended	0V to 5.1V	73.8	95.9	-93.7	±0.12	±0.06

Note 1: SNR, SFDR, and THD are measured with f_IN = 10 kHz, V_IN = -1 dBFS, V_REF = 5.1V .

Application Diagram

Analog Input (0V to VREF) Ground Reference of Analog Input 22Ω 1.7 nF AIN+ VREF AVDD DVIO MCP331x1-XX SDI CNVST SCLK SDO GND Host Device (PIC32MZ)

Description

The MCP33131/MCP33121/MCP33111-10 and MCP33131/MCP33121/MCP33111-05 are single-ended 16, 14, and 12-bit, single-channel 1 Msps and 500 kSPS ADC family devices, respectively, featuring low power consumption and high performance, using a successive approximation register (SAR) architecture.

The device operates with a 2.5V to 5.1V external reference ( V_REF ), which supports a wide range of input full-scale range from 0V to V_REF . The reference voltage setting is independent of the analog supply voltage ( AV_DD ) and is higher than AV_DD . The conversion output is available through an easy-to-use simple SPI-compatible 3-wire interface.

The device requires a 1.8V analog supply voltage (AV DD ) and a 1.7V to 5.5V digital I/O interface supply voltage (DV IO ). The wide digital I/O interface supply (DV _IO ) range (1.7V - 5.5V) allows the device to interface with most host devices (Master) available in the current industry such as the PIC32 microcontrollers, without using external voltage level shifters.

When the device is first powered-up, it performs a self-calibration to minimize offset, gain and linearity errors. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage was not fully settled during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration to restore optimum performance.

When the initial power-up sequence is completed, the device enters a low-current input acquisition mode, where sampling capacitors are connected to the input pins. This mode is called Standby.

During Standby, most of the internal analog circuitry is shutdown in order to reduce current consumption. Typically, the device consumes less than 1 A during Standby. A new conversion is started on the rising edge of CNVST. When the conversion is complete and the host lowers CNVST, the output data is presented on SDO, and the device enters Standby to begin acquiring the next input sample. The user can clock out the ADC output data using the SPI-compatible serial clock during Standby.

The ADC system clock is generated by an internal on-chip clock, therefore the conversion is performed independent of the SPI serial clock (SCLK).

This device can be used for various high-speed and high-accuracy analog-to-digital data conversion applications, where design simplicity, low power, and no output latency are needed.

The device is AEC-Q100 qualified for automotive applications and operates over the extended temperature range of -40^ to +125^ . The available package options are Pb-free TDFN-10 and MSOP-10.

1.0 KEY ELECTRICAL CHARACTERISTICS

1.1 Absolute Maximum Ratings†

External Analog Supply Voltage (AVDD) -0.3V to 2.0V
External Digital Supply Voltage (DV IO ) ...... -0.3V to 5.8V
External Reference Voltage ( VREF ) -0.3V to 5.8V
Analog Inputs w.r.t GND -0.3V to V_REF +0.3V
Current at Input Pins ....±2 mA
Current at Output and Supply Pins ....±250 mA
Storage Temperature ....-65°C to +150°C
Maximum Junction Temperature ( T_J ) ..... +150°C
ESD protection on all pins .... ≤ 2kV HBM, ≤ 2kV CDM, ≤ 200V MM

†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

1.2 Electrical Specifications

TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, all parameters apply for T_A = -40°C to +125°C, AV_DD = 1.8V, DV_IO = 3.3V, V_REF = 5 V, GND = 0V, Analog Input ( V_IN ) = -1 dBFS sine wave, f_IN = 10 kHz, I_LOAD\_SDO = 20 pF.• MCP331x1-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.• MCP331x1-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
Power Supply Requirements
Analog Supply Voltage Range	AV_DD	1.7	1.8	1.9	V	(Note 3)
Digital Input/Output Interface Voltage Range	DV_IO	1.7	—	5.5	V	(Note 3)
Analog Supply Current at AV_DD pin:During Conversion	I_DDAN	—	1.6	2.4	mA	f_s = 1 Msps (MCP331x1-10) f_s = 500 kSPS (MCP331x1-05)During input acquisition ( t_ACQ )
		—	1.4	2.0	mA
During Standby	I_DDAN\_STBY	—	0.8	—	μA
Digital Supply Current At DV_DD pin:During Output Data Reading	I_IO\_DATA	—	290	—	μA	f_s = 1 Msps (MCP331x1-10) f_s = 500 kSPS (MCP331x1-05)During input acquisition ( t_ACQ )
		—	200	—	μA
During Standby	I_IO\_STBY	—	30	—	nA
External Reference Voltage Input
Reference Voltage (Note 2), (Note 3)	V_REF	2.5		5.1	V	-40°C ≤ A ≤ 85°C85°C < T_A ≤ 125°C
		2.7		5.1
Reference Load Current at V_REF pin:During Conversion	I_REF	—	450	600	μA	f_s = 1 Msps (MCP331x1-10) f_s = 500 kSPS (MCP331x1-05)During input acquisition ( t_ACQ )
		—	220	360	μA
During Standby	I_REF\_STBY		240	—	nA
Total Power Consumption (Including AV_DD , DV_IO , V_REF pins)
MCP331x1-10
at 1 Msps	P_DISS\_TOTAL	—	6.2	—	mW	Averaged power for t_ACQ + t_CNV
at 500 ksps		—	3.1	—	mW
at 100 ksps		—	0.6	—	mW
During Standby	P_DISS\_STBY	—	2.6	—	μW	During input acquisition ( t_ACQ )
MCP331x1-05
at 500 ksps	P_DISS\_TOTAL	—	4.2	—	mW	Averaged power for t_ACQ + t_CNV
at 100 ksps		—	0.8	—	mW
During Standby	P_DISS\_STBY	—	2.6	—	μW	During input acquisition ( t_ACQ )

Note
1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV_DD pin: 1 F ceramic capacitor, (b) DV_IO pin: 0.1 F ceramic capacitor, (c) V_REF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (D VOUT /AV DD ), where D _VOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02

TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF.MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
Analog Inputs
Input Voltage Range V	IN+	-0.1 — V		REF+0.1 V	(Note 2)
Input Full-Scale Voltage Range FSR 0	— +V			REF	Vpp	(Note 2)
Input Sampling Capacitance C	S	—	3	1	—	p F (Note 1)
-3dB Input Bandwidth	BW-3dB	—	2	5	—	(NMe 1) H z
Aperture Delay (Note 1)		—	2.5	—	ns	Time delay between CNVST rising edge and when input is sampled
Leakage Current at Analog Input Pin	ILEAK_AN_INPUT	—	±2	±200	nA	During input acquisition (IACQ)
System Performance
Sample Rate (Throughput rate)	fs	—	—	1 Msps	MCP331x1-10
		—	—	500	kSPS	MCP331x1-05
Resolution (No Missing Codes)		16	—	—	Bits	MCP33131-10 and MCP33131-05
		14	—	—	Bits	MCP33121-10 and MCP33121-05
		12	—	—	Bits	MCP33111-10 and MCP33111-05
Integral Nonlinearity	INL	-6	±2.2	+6	LSB	MCP33131-10 and MCP33131-05
		-1.5	±0.55	+1.5	LSB	MCP33121-10 and MCP33121-05
			±0.12		LSB	MCP33111-10 and MCP33111-05
Differential Nonlinearity	DNL	-0.98	±0.9	+1.8	LSB	MCP33131-10 and MCP33131-05
		-0.8	±0.25	+0.8	LSB	MCP33121-10 and MCP33121-05
		-0.3	±0.06	+0.3	LSB	MCP33111-10 and MCP33111-05
Offset Error			±0.1	±2.3	mV	MCP33131-10 and MCP33131-05
		—	±0.125	±3	mV	MCP33121-10 and MCP33121-05
		—	±0.8	±3.66	mV	MCP33111-10 and MCP33111-05
Offset Error Drift with Temperature		—	±0.8	—	μV/°C
Gain Error	GER	—	±4	—	LSB	MCP33131-10 and MCP33131-05
		—	±1	—	LSB	MCP33121-10 and MCP33121-05
		—	±0.2	—	LSB	MCP33111-10 and MCP33111-05
Gain Error Drift with temperature		—	±0.35	—	μV/°C
Input Common-Mode Rejection Ratio	CMRR	—	84	—	dB
Power Supply Rejection Ratio	PSRR	—	60	—	dB	(Note 4)

Note 1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: Decoupling capacitor is recommended on the following pins:

(a) AV_DD pin: 1 F ceramic capacitor, (b) DV_IO pin: 0.1 F ceramic capacitor, (c) V_REF pin: 10 F tantalum capacitor.

4: PSRR (dB) = -20 log (D VOUT /AV DD ), where D _VOUT = change in conversion result.

5: ENOB = (SINAD - 1.76)/6.02

TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V, GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF.MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
Dynamic Performance
Signal-to-Noise Ratio SNR		MCP33131-10 and MCP33131-05: 16-bit ADC
		—	8	6		8 REF = 5V, fIN = 1 kHz— d
		—	8	0		9 REF = 2.5V, fIN = 1 kHz-
		83.5 86.7	—V			REF = 5V, fIN = 10 kHz
		—	8	0		9 REF = 2.5V, fIN = 10 kHz
		MCP33121-10 and MCP33121-05: 14-bit ADC
		—	8	3		6 REF = 5V, fIN = 1 kHz— d
		—	7	9		8 REF = 2.5V, fIN = 1 kHz-
		81.5 83.5	—V			REF = 5V, fIN = 10 kHz
		—	7	9		8 REF = 2.5V, fIN = 10 kHz
		MCP33111-10 and MCP33111-05: 12-bit ADC
		—	7	3		8 REF = 5V, fIN = 1 kHz— d
		—	7	3		2 REF = 2.5V, fIN = 1 kHz-
		71.1 73.8	—V			REF = 5V, fIN = 10 kHz
		—	7	3		2 REF = 2.5V, fIN = 10 kHz
Signal-to-Noise and Distortion Ratio (Note 5)	SINAD	MCP33131-10 and MCP33131-05: 16-bit ADC
		—	8	6		9 REF = 5V, fIN = 1 kHz— d
		—	8	0		9 REF = 2.5V, fIN = 1 kHz-
		—	8	6		6 REF = 5V, fIN = 10 kHz-
		—	8	0		REF = 2.5W fIN = 10 kHz
		MCP33121-10 and MCP33121-05: 14-bit ADC
		—	8	3		6 REF = 5V, fIN = 1 kHz— d
		—	7	9		8 REF = 2.5V, fIN = 1 kHz-
		—	8	3		4 REF = 5V, fIN = 10 kHz-
		—	7	9		1 REF = 2.5V, fIN = 10 kHz
		MCP33111-10 and MCP33111-05: 12-bit ADC
		—	7	3		8 REF = 5V, fIN = 1 kHz— d
		—	7	3		2 REF = 2.5V, f IN = 1 kHz-
		—	7	3		8 REF = 5V, fIN = 10 kHz-
		—	7	3		REF = 2.5W fIN = 10 kHz

Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV_DD pin: 1 F ceramic capacitor, (b) DV_IO pin: 0.1 F ceramic capacitor, (c) V_REF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (D VOUT /AV DD ), where D _VOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02

TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for T_A = -40°C to +125°C, AV_DD = 1.8V, DV_IO = 3.3V, V_REF = 5V, GND = 0V, Analog Input ( V_IN ) = -1 dBFS sine wave, f_IN = 10 kHz, C_LOAD\_SDO = 20 pF.MCP331x1-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.MCP331x1-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
Spurious Free Dynamic Range SFDR MCP33131-10 and MCP33131-05: 16-bit ADC

Note
1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV_DD pin: 1 F ceramic capacitor, (b) DV_IO pin: 0.1 F ceramic capacitor, (c) V_REF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log D_VOUT/AV_DD , where D_VOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02

TABLE 1-1: KEY ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for T_A = -40°C to +125°C, AV_DD = 1.8V, DV_IO = 3.3V, V_REF = 5V, GND = 0V, Analog Input ( V_IN ) = -1 dBFS sine wave, f_IN = 10 kHz, C_LOAD\_SDO = 20 pF.MCP331x1-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.MCP331x1-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
System Self-Calibration
Self-Calibration Time t	CAL	—	5	0	0	6 5 0
Number of SCLK Clocks for Recalibrate Command	ReCalNSCLK	— 1024	— clocks includes clocks for data bits
Serial Interface Timing Information: See Table 1-2
Digital Inputs/Outputs
High-level Input voltage V	IH	0.7 * DV _IO	—	DV _IO + 0.3	V	DV _IO ≥ 2.3V
		0.9 * DV _IO	—	DV _IO + 0.3	V	DV _IO < 2.3V
Low-level input voltage	V_IL	-0.3	—	0.3 * DV _IO	V	DV _IO ≥ 2.3V
		-0.3	—	0.2 * DV _IO	V	DV _IO < 2.3V
Hysteresis of Schmitt Trigger Inputs	V_HYST	—	0.2 * DV _IO	—	V	All digital inputs
Low-level output voltage	V_OL	—	—	0.2 * DV _IO	V	I_OL = 500 μA (sink)
High-level output voltage	V_OH	0.8 * DV _IO	—	—	V	I_OL = - 500 μA (source)
Input leakage current	I_LI	—	—	±1	μA	CNVST/SDI/SCLK = GND or DV _IO
Output leakage current	I_LO	—	—	±1	μA	Output is high-Z, SDO = GND or DV _IO
Internal capacitance (all digital inputs and outputs)	C_INT	—	7	—	pF	T_A = 25°C (Note 1)

Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AV_DD pin: 1 F ceramic capacitor, (b) DV_IO pin: 0.1 F ceramic capacitor, (c) V_REF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log D_VOUT/AV_DD , where D_VOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02

TABLE 1-2: SERIAL INTERFACE TIMING SPECIFICATIONS

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVO = 3.3V, GND = 0V, Analog Input (AIN) = -1 dBFS sine wave, Resolution = 16-bit (MCP33131-10), fIN = 10 kHz, CLOAD_SDO = 20 pF, +25°C is applied for typical value. All timings are measured at 50%. See Figure 1-1 for timing diagram.· MCP331x1-10: Sample Rate (f s) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.· MCP331x1-05: Sample Rate (f s) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters Symbol Min. Typ. Max.	Units Conditions
Serial Clock frequency f	SCLK	—	—	100	MHz	See tSCLK specification
SCLK Period	tSCLK	10	—	—	ns	DVIO ≥ 3.3V, fSCLK = 100 MHz (Max)
		12	—	—	ns	DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max)
		16	—	—	ns	DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max)
SCLK Low Time	tSCLK_L	3	—	—	ns	DVIO ≥ 2.3V
		4.5	—	—	ns	DVIO ≥ 1.7V
SCLK High Time	tSCLK_H	3	—	—	ns	DVIO ≥ 2.3V
		4.5	—	—	ns	DVIO ≥ 1.7V
Output Valid from SCLK Low	tDO	—	—	9.5	ns	DVIO ≥ 3.3V
		—	—	12	ns	DVIO ≥ 2.3V
		—	—	16	ns	DVIO ≥ 1.7V
Quiet time	tQUIET	10	—	—	ns	(Note 2)
3-Wire Operation:
SDI Valid Setup time	tsU_SDIH_CNV	5	—	—	ns	SDI High to CNVST Rising Edge
CNVST Pulse Width High Time	tCNVH	10	—	—	ns
Output Enable Time	tEN	—	—	10	ns	DVIO ≥ 2.3V
		—	—	15	ns	DVIO ≥ 1.7V
Output Disable Time	tDIS	—	—	15	ns	(Note 2)
MCP331x1-10
Sample Rate	fs	—	—	1	Msps	Throughput rate
Input Acquisition Time (Note 2)	tACQ	290	300	—	ns	-40°C ≤ TA ≤ 85°C85°C < TA ≤ 125°C
		250		—
Data Conversion Time	tCNV	—	700	710	ns	-40°C ≤ TA ≤ 85°C85°C < TA ≤ 125°C
		—		750
Time between Conversions	tCYC	1	—	—	μs	tCYC = tACQ + tCNV, fs = 1 Msps
MCP331x1-05
Sample Rate	fs	—	—	500	kSPS	Throughput rate
Input Acquisition Time (Note 2)	tACQ	700	800	—	ns	-40°C ≤ TA ≤ 125°C
Data Conversion Time	tCNV	—	1200	1300	ns	-40°C ≤ TA ≤ 125°C
Time between Conversions	tCYC	2	—	—	μs	tCYC = tACQ + tCNV, fs = 500 kSPS

Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.

TABLE 1-3: TEMPERATURE CHARACTERISTICS

Parameters	Symbol	Min.	Typ.	Max.	Units	Conditions
Temperature Ranges
Operating Temperature Range	T_A	-40	—	+125	°C	(Note 1)
Storage Temperature Range	T_A	-65	—	+150	°C	(Note 1)
Thermal Package Resistance
Thermal Resistance, MSOP-10	0_JA	—	202	—	°C/W
Thermal Resistance, TDFN-10	0_JA	—	68	—	°C/W

Note 1: The internal junction temperature ( T_j ) must not exceed the absolute maximum specification of +150 °C.

FIGURE 1-1: Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for More Details.

NOTES:

2.0 TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131-XX)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise specified, all parameters apply for T A = +25^ , AVDD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD SDO = 20 pF.

MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33131-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 2-1: INL vs. Output Code.

FIGURE 2-4: INL vs. Output Code.

FIGURE 2-2: DNL vs. Output Code.

FIGURE 2-5: DNL vs. Output Code.

FIGURE 2-3: INL vs. Temperature.

FIGURE 2-6: DNL vs. Temperature.

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33131-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP33131-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 2-7: INL vs. Reference Voltage.

FIGURE 2-10: DNL vs. Reference Voltage.

FIGURE 2-8: FFT for 10 kHz Input Signal: f_S = 1 Msps, V_IN = -1 dBFS, V_REF = 5V .

FIGURE 2-11: FFT for 10 kHz Input Signal: f_S = 1 Msps, V_IN = -1 dBFS, V_REF = 2.5V .

FIGURE 2-9: FFT for 10 kHz Input Signal: f_S = 500 kSPS, V_IN = -1 dBFS, V_REF = 5V .

FIGURE 2-12: FFT for 10 kHz Input Signal: f_S = 500 kSPS, V_IN = -1 dBFS, V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AVDD = 1.8V , DVIO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33131-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 2-13: SNR/SINAD/ENOB vs. V REF

FIGURE 2-16: SFDR/THD vs. V REF

FIGURE 2-14: SNR/SINAD vs. Temperature: V_REF = 5V .

FIGURE 2-17: SNR/SINAD vs. Temperature: V_REF = 2.5V .

FIGURE 2-15: SNR/SINAD vs. Input Amplitude: F_IN = 10kHz .

FIGURE 2-18: SNR/SINAD vs. Input Amplitude: F_IN = 10kHz .

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33131-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP33131-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 2-19: SNR/SINAD vs.Input Frequency: V_IN = -1 dBFS.

FIGURE 2-22: SNR/SINAD vs.Input Frequency: V_IN = -1 dBFS.

FIGURE 2-20: THD/SFDR vs. Temperature: V_REF = 5V .

FIGURE 2-23: THD/SFDR vs. Temperature: V_REF = 2.5V .

FIGURE 2-21: THD/SFDR vs. Input Frequency: V_REF = 5V .

FIGURE 2-24: THD/SFDR vs. Input Frequency: V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 2-25: THD/SFDR vs. Input Amplitude: V_REF = 5V .

FIGURE 2-28: THD/SFDR vs. Input Amplitude: V_REF = 2.5V .

FIGURE 2-26: Shorted Input Histogram: V_REF = 5V .

FIGURE 2-29: Shorted Input Histogram: V_REF = 2.5V .

FIGURE 2-27: Offset and Gain Error vs. Temperature: V_REF = 5V .

FIGURE 2-30: Offset and Gain Error vs. Temperature: V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33131-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP33131-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 2-31: CMRR vs. Input Frequency: V_REF = 5V .

FIGURE 2-34: Power Consumption vs. Temperature During Shutdown.

FIGURE 2-32: Power Consumption vs. Sample Rate: C_LOAD_SDO = 20pF .

FIGURE 2-35: Power Consumption vs. Sample Rate: C_LOAD_SDO = 20 pF.

FIGURE 2-33: Power Consumption vs. Temperature: C_LOAD_SDO = 20pF .

FIGURE 2-36: Power Consumption vs. Temperature: C_LOAD_SDO = 20pF .

3.0 TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33121-XX)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise specified, all parameters apply for T A = +25^ , AVDD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD SDO = 20 pF.

MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33121-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 3-1: INL vs. Output Code.

FIGURE 3-4: INL vs. Output Code.

FIGURE 3-2: DNL vs. Output Code.

FIGURE 3-5: DNL vs. Output Code.

FIGURE 3-3: INL vs. Temperature.

FIGURE 3-6: DNL vs. Temperature.

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33121-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP33121-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 3-7: INL vs. Reference Voltage.

FIGURE 3-10: DNL vs. Reference Voltage.

FIGURE 3-8: FFT for 10 kHz Input Signal: f_S = 1 Msps, V_IN = -1 dBFS, V_REF = 5V .

FIGURE 3-11: FFT for 10 kHz Input Signal: f_S = 1 Msps, V_IN = -1 dBFS, V_REF = 2.5V .

FIGURE 3-9: FFT for 10 kHz Input Signal: f_S = 500 kSPS, V_IN = -1 dBFS, V_REF = 5V .

FIGURE 3-12: FFT for 10 kHz Input Signal: f_S = 500 kSPS, V_IN = -1 dBFS, V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T A = +25°C, AV DD = 1.8V, DV _IO = 3.3V,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD SDO = 20 pF.

MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33121-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 3-13: SNR/SINAD/ENOB vs. V REF.

FIGURE 3-16: SFDR/THD vs. V REF.

FIGURE 3-14: SNR/SINAD vs.
Temperature: V_REF = 5V .

FIGURE 3-17: SNR/SINAD vs.
Temperature: V_REF = 2.5V .

FIGURE 3-15: SNR/SINAD vs. Input
Amplitude: F_IN = 10 kHz.

FIGURE 3-18: SNR/SINAD vs. Input
Amplitude: F_IN = 10 kHz.

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33121-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP33121-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 3-19: SNR/SINAD vs.Input Frequency: V_IN = -1 dBFS.

FIGURE 3-22: SNR/SINAD vs.Input Frequency: V_IN = -1 dBFS.

FIGURE 3-20: THD/SFDR vs. Temperature: V_REF = 5V .

FIGURE 3-23: THD/SFDR vs. Temperature: V_REF = 2.5V .

FIGURE 3-21: THD/SFDR vs. Input Frequency: V_REF = 5V .

FIGURE 3-24: THD/SFDR vs. Input Frequency: V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T A = +25°C, AV DD = 1.8V, DV _IO = 3.3V,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD SDO = 20 pF.

MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33121-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 3-25: THD/SFDR vs. Input Amplitude: V_REF = 5V .

FIGURE 3-28: THD/SFDR vs. Input Amplitude: V_REF = 2.5V .

FIGURE 3-26: Shorted Input Histogram: V_REF = 5V .

FIGURE 3-29: Shorted Input Histogram: V_REF = 2.5V .

FIGURE 3-27: Offset and Gain Error vs. Temperature: V_REF = 5V .

FIGURE 3-30: Offset and Gain Error vs. Temperature: V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33121-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

MCP33121-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 3-31: CMRR vs. Input Frequency: V_REF = 5V .

FIGURE 3-34: Power Consumption vs. Temperature During Shutdown.

FIGURE 3-32: Power Consumption vs. Sample Rate: C_LOAD_SDO = 20 pF .

FIGURE 3-35: Power Consumption vs. Sample Rate: C_LOAD_SDO = 20 pF.

FIGURE 3-33: Power Consumption vs. Temperature: C_LOAD_SDO = 20 pF .

FIGURE 3-36: Power Consumption vs.

4.0 TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33111-XX)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise specified, all parameters apply for T A = +25^ , AVDD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD SDO = 20 pF.

MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33111-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 4-1: INL vs. Output Code.

FIGURE 4-4: INL vs. Output Code.

FIGURE 4-2: DNL vs. Output Code.

FIGURE 4-5: DNL vs. Output Code.

FIGURE 4-3: INL vs. Temperature.

FIGURE 4-6: DNL vs. Temperature.

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33111-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33111-05: Sample Rate ( f_s ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 4-7: INL vs. Reference Voltage.

FIGURE 4-10: DNL vs. Reference Voltage.

FIGURE 4-8: FFT for 10 kHz Input Signal: f_S = 1 Msps, V_IN = -1 dBFS, V_REF = 5V .

FIGURE 4-11: FFT for 10 kHz Input Signal: f_S = 1 Msps, V_IN = -1 dBFS, V_REF = 2.5V .

FIGURE 4-9: FFT for 10 kHz Input Signal: f_S = 500 kSPS, V_IN = -1 dBFS, V_REF = 5V .

FIGURE 4-12: FFT for 10 kHz Input Signal: f_S = 500 kSPS, V_IN = -1 dBFS, V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T A = +25°C, AV DD = 1.8V, DV _IO = 3.3V,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD SDO = 20 pF.

MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33111-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 4-13: SNR/SINAD/ENOB vs. V REF

FIGURE 4-16: SFDR/THD vs. V REF

FIGURE 4-14: SNR/SINAD vs.
Temperature: V_REF = 5V .

FIGURE 4-17: SNR/SINAD vs.
Temperature: V_REF = 2.5V .

FIGURE 4-15: SNR/SINAD vs. Input
Amplitude: F_IN = 10 kHz.

FIGURE 4-18: SNR/SINAD vs. Input
Amplitude: F_IN = 10 kHz.

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33111-10: Sample Rate (f _S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33111-05: Sample Rate ( f_s ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 4-19: SNR/SINAD vs. Input Frequency: V_IN = -1 dBFS.

FIGURE 4-22: SNR/SINAD vs. Input Frequency: V_IN = -1 dBFS.

FIGURE 4-20: THD/SFDR vs. Temperature: V_REF = 5V .

FIGURE 4-23: THD/SFDR vs. Temperature: V_REF = 2.5V .

FIGURE 4-21: THD/SFDR vs. Input Frequency: V_REF = 5V .

FIGURE 4-24: THD/SFDR vs. Input Frequency: V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD SDO = 20 pF.

MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33111-05: Sample Rate ( f_S ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 4-25: THD/SFDR vs. Input Amplitude: V_REF = 5V .

FIGURE 4-28: THD/SFDR vs. Input Amplitude: V_REF = 2.5V .

FIGURE 4-26: Shorted Input Histogram: V_REF = 5V .

FIGURE 4-29: Shorted Input Histogram: V_REF = 2.5V .

FIGURE 4-27: Offset and Gain Error vs. Temperature: V_REF = 5V .

FIGURE 4-30: Offset and Gain Error vs. Temperature: V_REF = 2.5V .

Note: Unless otherwise specified, all parameters apply for T_A = +25^ , AV_DD = 1.8V , DV_IO = 3.3V ,

V_REF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, f_IN = 10 kHz, C_LOAD, SDO = 20 pF.

MCP33111-10: Sample Rate ( f_S ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz

MCP33111-05: Sample Rate ( f_s ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

FIGURE 4-31: CMRR vs. Input Frequency: V_REF = 5V .

FIGURE 4-34: Power Consumption vs. Temperature During Shutdown.

FIGURE 4-32: Power Consumption vs. Sample Rate: C_LOAD_SDO = 20pF .

FIGURE 4-35: Power Consumption vs. Sample Rate: C_LOAD_SDO = 20 pF.

FIGURE 4-33: Power Consumption vs. Temperature: C_LOAD_SDO = 20pF .

FIGURE 4-36: Power Consumption vs. Temperature: C_LOAD_SDO = 20pF .

5.0 PIN FUNCTION DESCRIPTIONS

TABLE 5-1: PIN FUNCTION TABLE

Pin Number	Pin Name Function
1	V_REF	Reference voltage input (2.5V - 5.1V).This pin should be decoupled with a 10 μF tantalum capacitor.
2	AV_DD	DC supply voltage input for analog section (1.8V).This pin should be decoupled with a 1 μF ceramic capacitor.
3	A_IN^+ Analog input.
4	A_IN^-	Ground reference pin for analog input. Connect this pin to the ground reference of the analog input.
5	GND	Power supply ground reference. This pin is a common ground for both the analog power supply ( AV_DD ) and digital I/O supply ( DV_IO ).
6	CNVST	Conversion-start control and active-low SPI chip-select digital input.A new conversion is started on the rising edge of CNVST.When the conversion is complete, output data is available at SDO by lowering CNVST.
7	SDO	SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK clock, with MSB first.
8	SCLK	SPI-compatible serial data clock digital input.The ADC output is synchronously shifted out by this clock.
9	SDI	SPI-compatible serial data digital input. Tie to DV_IO for normal operation.
10	DV_IO	DC supply voltage for digital input/output interface (1.7V - 5.5V).This pin should be decoupled with a 0.1 μF ceramic capacitor.

5.1 Supply Voltages (AV DD, DVIO)

The device has two power supply pins:

(a) Analog power supply (AV DD ): 1.8V
(b) Digital input/output interface power supply (DV IO ): 1.7V to 5.5V.

The large supply voltage range of DV_IO allows the device to interface with various host devices that are operating with different supply voltages. See Table 1-2 for timing specifications for I/O interface signal parameters depending on DV_IO voltage.

Note: Proper decoupling capacitors (1 F to AV DD , 0.1 F to DV IO ) should be mounted as close as possible to the respective pins. See Figure 6-1 for example circuit.

5.2 Reference Voltage (V REF)

The device requires a single-ended external reference voltage ( V_REF ). The external input reference range is from 2.5V to 5.1V. This reference voltage sets the input full-scale range from 0V to V_REF . See Figure 6-1 to Figure 6-2 for example application circuit and reference voltage settings.

Note: The reference pin needs a tantalum decoupling capacitor (10 F, 10V rating). Additional multiple ceramic capacitors can be added in parallel to decouple high-frequency noises.

Note: During the initial power-up sequence, the reference voltage ( V_REF ) must be provided prior to supplying AV_DD or within about 64 ms after supplying AV_DD . Otherwise, it is strongly recommended to send a recalibrate command. See Section 7.1 “Recalibrate Command” for more details.

5.2.1 VOLTAGE REFERENCE SELECTION

The performance of the voltage reference has a large impact on the accuracy of high-precision data acquisition systems. The voltage reference should have high-accuracy, low-noise, and low-temperature drift. A ±0.1% output accuracy of the reference directly corresponds to ±0.1% absolute accuracy of the ADC output. The RMS output noise voltage of the reference should be less than 1/2 LSB of the ADC.

6.0 DEVICE OVERVIEW

The device converts unipolar single-ended analog input into unipolar straight binary codes.

When the MCP33131/MCP33121/MCP33111-XX is first powered-up, it performs a self-calibration and enters a low current input acquisition mode (Standby) by itself.

The external reference voltage ( V_REF ) ranging from 2.5V to 5.1V sets the input full-scale range (FSR) from 0V to +V_REF

During input acquisition (Standby), the internal input sampling capacitors are connected to the input signal, while most of the internal analog circuits are shutdown to save power. During this input acquisition time ( t_ACQ ), the device consumes less than 1 A.

The user can operate the device with an easy-to-use SPI-compatible 3-wire interface.

The device initiates data conversion on the rising edge of the conversion-start control (CNVST). The data conversion time ( t_CNV ) is set by the internal clock. Once the conversion is complete, the device starts the next input acquisition. During this input acquisition time ( t_ACQ ), the user can clock out the output data by providing the external SPI serial clock (SCLK).

The device provides conversion data with no missing codes. This ADC device family has a large input full-scale range, high precision, high throughput with no output latency, and is an ideal choice for various ADC applications.

6.1 Analog Input

Figure shows a simplified equivalent circuit of the input architecture with a switched capacitor input stage. The input sampling capacitor ( C_S^+ ) is about 31 pF. The back-to-back diodes ( D_1 - D_2 ) at each input pin are ESD protection diodes. Note that these ESD diodes are tied to V_REF , so that each input signal can swing from 0V to V_REF .

The input sampling and hold circuit in A_IN+ path is also repeated in A_IN- path. This allows the device to perform a pseudo-differential conversion of the input signal. Therefore, the common mode signal presented at both input pins is rejected. In applications, A_IN+ pin is for the input signal and A_IN- pin is for the ground reference of the input signal. The user must connect the A_IN- pin to a clean ground plane of the input signal externally.

During input acquisition phase (Standby), the sampling switches are closed and each input sees the sampling capacitor ( ≈ 31 pF) in series with the on-resistance of the sampling switch, R_SON(≈ 200) .

For high-precision data conversion applications, the input voltage needs to be fully settled within 1/2 LSB during the input acquisition period ( t_ACQ ). The settling time is directly related to the source impedance: A lower impedance source results in faster input settling

time. Although the device can be driven directly with a low impedance source, using a low noise input driver is highly recommended.

MCP331x1-XX VREF D1 VT=0.6V AIN+ CIN D2 LEAKAGE (~ ±1 nA) Sample VIN+ SW1+ RSON CS+ SW2+ (200 Ω) (31 pF) AIN- CIN D1 VT=0.6V I LEAKAGE (~ ±1 nA) Sample VIN- SW1+ RSON CS+ SW2- (200 Ω) (31 pF) AIN+ AIN- ground reference of analog input. where: CS+, CS- = Input sample and hold capacitor = 31 pF. RSON = On-resistance of the sampling switch = 200 Ω. CPN = Package pin + ESD capacitor = 2 pF. AIN+ = Analog input. AIN- = Ground reference of analog input.

Simplified Equivalent Analog Input Circuit.

Note: The ESD diodes at the analog input pins are biased from V_REF . Any input voltage outside the absolute maximum range can turn on the input ESD protection diodes and results in input leakage current which may cause conversion errors and permanent damage to the device. Care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range.

6.1.1 INPUT VOLTAGE RANGE

The device has two analog input pins: A_IN+ and A_IN- pins. The analog input signal is applied to the A_IN+ pin, and the ground reference of the input signal is tied to the A_IN- pin.

The voltage difference between A_IN+ and A_IN- is the ADC input ( V_IN ) and needs to be between 0V and +V_REF to produce unsaturated output codes. Equation 6-4 shows the input full-scale range (FSR) and input range.

The device will output unipolar straight binary codes for the analog input. If the input ( V_IN ) is greater than the reference voltage ( V_REF ), the output code will be saturated. If the input ( V_IN ) is less than or equals to 0V, the output will be all 0's.

EQUATION 6-1: FSR AND INPUT RANGE

Input Full-Scale Range (FSR) = V_REF

Input Range: 0V V_IN V_REF ILSB-(

where V_IN = AIN^+ - AIN^-

6.2 Analog Input Conditioning Circuit

The MCP33131/MCP33121/MCP33111-XX can be driven directly when the source impedance of the input driver is low.

Large source impedance of the input signal may affect the ADC's performance. In general, the source impedance is less sensitive to the ADC's DC performances such as INL and DNL. However, it affects significantly to the dynamic performances such as THD, SFDR and SNR.

Therefore, it is a good design practice to isolate the ADC input from the high impedance source using a low noise input driver amplifier. Figure 6-1 shows an input configuration example using a low-noise OP amplifier such as MCP6286 and Figure 6-2 shows the transfer function of the MCP33131/MCP33121/MCP33111-XX.

VDC Voltage Reference MCP1501 (Note 2) CR 2.5V to 5.1V 10 µF (Tantalum) 1.8V 1.7V to 5.5V 0.1 µF 0.1 µF Analog Input VREF R1 fC = 1 / (2πRC1) (22Ω ±0.1%) (1.7nF, NPO) C1 -0V VREF -0V AIN+ VREF AVDD DVIO VOUT VIN MCP331x1-XX 0V AIN- GND SDI CNVST SCLK SDO Host Device (PIC32MZ) Ground Reference of Analog Input

Note 1: Contact Microchip Technology Inc. for more selections of the low-noise input driver amplifiers.
2: Contact Microchip Technology Inc. for the MCP1501 application circuit.

FIGURE 6-1: Unipolar-Input Application Example

FIGURE 6-2: Transfer Function for Figure 6-1.

6.3 ADC Input Driver Selection

The noise and distortion of the ADC input driver can degrade the dynamic performance (SNR, SFDR, and THD) of the overall ADC application system. Therefore, the ADC input driver needs better performance specifications than the ADC itself. The data sheet of the driver typically shows the output noise voltage and harmonic distortion parameters.

Figure 6-3 shows a simplified system noise presentation block diagram for the front-end driver and ADC.

graph LR
    A["ADC Input Driver"] --> B["+"]
    B --> C["R"]
    C --> D["+"]
    D --> E["ADC"]
    F["V_N_RMS_Driver Noise"] --> B
    G["V_N_ADC Input-Referred Noise"] --> D
    H["C"] --> D

FIGURE 6-3: Simplified System Noise Representation.

• Unity-Gain Bandwidth:

An input driver with higher bandwidth usually results in better overall linearity performance. Typically, the driver should have the unity-gain bandwidth greater than 5 times the -3 dB cutoff frequency of the anti-aliasing filter:

EQUATION 6-2: BANDWIDTH

REQUIREMENT FOR ADC INPUT DRIVER

$$ \mathrm{BW} _ {\text { Input Driver }} \geq 5 \times f _ {\mathrm{B}} \tag {Hz} $$

$$ \frac {5}{2 \pi R C} \geq \text { for a single - pole RC filter } $$

where, f_B = -3 dB bandwidth of RC anti-aliasing filter as shown in Figure 6-3.

- Distortion:

The nonlinearity characteristics of the input driver cause distortions in the ADC output. Therefore, the input driver should have less distortion than the ADC itself. The recommended total harmonic distortion (THD) of the driver is at least 10 dB less than that of the ADC:

EQUATION 6-3: RECOMMENDED THD FOR ADC INPUT DRIVER

$$ T H D _ {\text { Input Buffer }} \leq T H D _ {A D C} - 1 0 \quad (\mathrm{dB}) $$

• ADC Input-Referred Noise:

When the ADC is operating with a full-scale input range, the ADC input-referred RMS noise for a single-ended input configuration is approximated as shown in Equation 6-4.

EQUATION 6-4: ADC INPUT-REFERRED NOISE

$$ \begin{array}{c c} \hline V _ {N _ A D C I n p u t - R e f e r r e d N o i s e} & \frac {V _ {R E F}}{2 \sqrt {2}} \quad \frac {\text { SNR }}{2 0} \ \hline \end{array} _ {1 0} (\mathrm{V}) $$

- Noise Contribution from the Front-End Driver:

The noise from the input driver can degrade the ADC's SNR performance. Therefore, the selected input driver should have the lowest possible broadband noise density and 1/f noise. When an anti-aliasing filter is used after the input driver, the output noise density of the input driver is integrated over the -3 dB bandwidth of the filter.

Equation 6-5 shows the RMS output noise voltage calculation using the RC filter's bandwidth and noise density ( e_N ) of the input driver. G_N in Equation 6-5 is the noise gain of the driver amplifier and becomes 1 for a unity gain buffer driver.

EQUATION 6-5: NOISE FROM FRONT-END DRIVER AMPLIFIER

$$ V _ {N _ R M S _ D r i v e r N o i s e} \approx G _ {N} \frac {e _ {N}}{\sqrt {2}} \sqrt {\pi f _ {B}} \tag {V} $$

where e_N is the broadband noise density (V/√Hz) of the front-end driver amplifier and is typically given in its data sheet. In Equation 6-5, 1/f noise ( e_NFlicker ) is ignored assuming it is very small compared to the broadband noise ( e_N ).

For high precision ADC applications, the noise contribution from the front-end input driver amplifier is typically constrained to be less than about 20% (or 1/5 times) of the ADC input-referred noise as shown in Equation 6-6:

EQUATION 6-6: RECOMMENDED ADC INPUT DRIVER NOISE

$$ V _ {N _ R M S _ D r i v e r N o i s e} \leq \frac {1}{5} V _ {N _ A D C I n p u t - R e f e r r e d N o i s e} $$

Using Equation 6-4 to Equation 6-6, the recommended noise voltage density ( e_N ) limit of the ADC input driver is expressed in Equation 6-7:

EQUATION 6-7: NOISE DENSITY FOR ADC INPUT DRIVER

$$ \begin{array}{l} G _ {N} \frac {e _ {N}}{\sqrt {2}} \sqrt {\pi f _ {B}} \leq \frac {1}{5} V _ {N _ A D C I n p u t - R e f e r r e d N o i s e} \ e _ {N} \leq \frac {1}{1 0} \frac {1}{G _ {N} \sqrt {\pi f _ {B}}} V _ {R E F} 1 0 ^ {- \frac {S N R}{2 0}} \left(\frac {V}{\sqrt {H z}}\right) \ \end{array} $$

Using Equation 6-7, the recommended maximum noise voltage density limit for unity gain input driver for single-ended input ADC can be estimated. Table 6-1 to Table 6-3 show a few example results with G_N = 1 . The user may use these tables as a reference when selecting the ADC input driver amplifier.

TABLE 6-1: Noise Voltage Density (e _N ) of Input Driver for MCP33131-XX

ADC (Note 1)			RC Filter	ADC Input Driver Amplifier ( G_N = 1 )
V_REF	SNR (dBFS)	ADC Input-Referred Noise	f_B (Table 2)	Noise Voltage Density ( e_N )
2.5V 81	78.8	μV	3 MHz 7	3 nV/√Hz
			4 MHz 6	3 nV/√Hz
			5 MHz 5	6 nV/√Hz
3.3V	83	82.6 μV	3 MHz	7.6 nV/√Hz
			4 MHz 6	6 nV/√Hz
			5 MHz	5.9 nV/√Hz
5V	87	79 μV	3 MHz 7	3 nV/√Hz
			4 MHz 6	3 nV/√Hz
			5 MHz 5	6 nV/√Hz

Note 1: See Equation 6-4 for the ADC input-referred noise calculation for single-ended input.
2: f_B is -3dB bandwidth of the RC anti-aliasing filter.

TABLE 6-2: Noise Voltage Density (e _N ) of Input Driver for MCP33121-XX

ADC (Note 1)			RC Filter	ADC Input Driver Amplifier ( G_N = 1 )
V_REF	SNR (dBFS)	ADC Input-Referred Noise	f_B (Note 2)	Noise Voltage Density ( e_N )
2.5V	80	88.4 μV	3 MHz	8.1 nV/√Hz
			4 MHz	7.1 nV/√Hz
			5 MHz	6.3 nV/√Hz
3.3V	81.5	98.2 μV	3 MHz	9.0 nV/√Hz
			4 MHz	7.8 nV/√Hz
			5 MHz	7.0 nV/√Hz
5V	83.5	118.1 μV	3 MHz	10.9 nV/√Hz
			4 MHz	9.4 nV/√Hz
			5 MHz	8.4 nV/√Hz

Note 1: See Equation 6-4 for the ADC input-referred noise calculation for single-ended input.
2: f_B is -3dB bandwidth of the RC anti-aliasing filter.

TABLE 6-3: Noise Voltage Density (e _N ) of Input Driver for MCP33111-XX

ADC (Note 1)			RC Filter	ADC Input Driver Amplifier ( G_N=1 )
V_REF	SNR (dBFS)	ADC Input-Referred Noise	f_B (Note 2)	Noise Voltage Density ( e_N )
2.5V	73.2	193.3 μV	3 MHz	17.8 nV/√Hz
			4 MHz	15.4 nV/√Hz
			5 MHz	13.8 nV/√Hz
3.3V	73.5	246.6 μV	3 MHz	22.7 nV/√Hz
			4 MHz	19.7 nV/√Hz
			5 MHz	17.6 nV/√Hz
5V 7	3.8	360.9 μV	3 MHz	33.3 nV/√Hz
			4 MHz	28.8 nV/√Hz
			5 MHz	25.8 nV/√Hz

Note 1: See Equation 6-4 for the ADC input-referred noise calculation for single-ended input.
2: f_B is -3dB bandwidth of the RC anti-aliasing filter.

6.4 Device Operation

When the MCP33131/MCP33121/MCP33111-XX is first powered-up, it self-calibrates internal systems and enters input acquisition mode by itself. The device operates in two phases: (a) Input Acquisition (Standby) and (b) Data Conversion. Figure 6-4 shows the ADC operating sequence.

6.4.1 INPUT ACQUISITION PHASE (STANDBY)

During the input acquisition phase ( t_ACQ ), also called Standby, the two input sampling capacitors, C_S^+ and C_S^- , are connected to the A_IN^+ and A_IN^- pins, respectively. The input voltage is sampled until a rising edge on CNVST is detected. The input voltage should be fully settled within 1/2 LSB during t_ACQ .

During this input acquisition time ( t_ACQ ), the ADC consumes less than 1 A. The acquisition time ( t_ACQ ) is user-controllable. This acquisition time ( t_ACQ ) can be increased as long as needed for additional power savings.

6.4.2 DATA CONVERSION PHASE

The start of the conversion is controlled by CNVST. On the rising edge of CNVST, the sampled charge is locked (sample switches are opened) and the ADC performs the conversion. Once a conversion is started, it will not stop until the current conversion is complete. The data conversion time ( t_CNV ) is not user-controllable. After the conversion is complete and the host lowers CNVST, the output data is presented on SDO.

Any noise injection during the conversion phase may affect the accuracy of the conversion. To reduce environment noise, minimize I/O events and running clocks during the conversion time.

The output data is clocked out MSB first. While the output data is being transferred, the device enters the next input acquisition phase.

Note: Transferring output data during the acquisition phase can disturb the next input sample. It is highly recommended to allow at least t_QUIET (10 ns, typical) between the last edge on the SPI interface and the rising edge on CNVST. See Figure 1-1 for t_QUIET .

FIGURE 6-4: Device Operating Sequence.

6.4.3 SAMPLE (THROUGHPUT) RATE

The device completes data conversion within the maximum specification of the data conversion time ( t_CNV ). The continuous input sample rate is the inverse of the sum of input acquisition time ( t_ACQ ) and data conversion time ( t_CNV ). Equation 6-8 shows the continuous sample rate calculation using the minimum and maximum specifications of the input acquisition time ( t_ACQ ) and data conversion time ( t_CNV ).

EQUATION 6-8: SAMPLE RATE

$$ \text { Sample Rate } = \frac {1}{t _ {A C Q} + (t _ {C N V})} $$

$$ \text { (a) MCP331x1 - 10: } \text { Sample Rate } = \frac {1}{(2 9 0 n s + 7 1 0 n s)} = 1 M s p s $$

$$ \text { Sample Rate } = \frac {1}{(7 0 0 n s + 1 3 0 0 n s)} = 5 0 0 k S P S \tag {b} $$

6.4.4 SERIAL SPI CLOCK FREQUENCY REQUIREMENT

The ADC output is collected during the input acquisition time ( t_ACQ ). For continuous input sampling and data conversion sequence, the SPI clock frequency should be fast enough to clock out all output data bits during the input acquisition time ( t_ACQ ). For the continuous sampling rate ( f_S ), the minimum SPI clock frequency requirement is determined by the following equation:

EQUATION 6-9: SPI CLOCK FREQUENCY REQUIREMENT

$$ t _ {A C Q} = N \times T _ {S C L K} + t _ {Q U I E T} + t _ {E N} $$

$$ f _ {S C L K} = \frac {1}{T _ {S C L K}} = \frac {N}{t _ {A C Q} - (t _ {Q U I E T} + t _ {E N})} $$

where N is the number of output data bits, given by

$$ N = 1 6 - \text { bit for MCP33131 - XX } $$

$$ = 1 4 - \text { bit for MCP33121 - XX } $$

$$ = 1 2 - \text { bit for MCP33111 - XX } $$

$$ T _ {S C L K} = \text { Period of SPI clock } $$

$$ N \times T _ {S C L K} = \text { Output data window } $$

$$ \begin{array}{r l} {t _ {Q U I E T}} & {= \quad \text { Quiet time between the last output bit }} \ & {\text { and beginning of the next }} \ & {\text { conversion start. }} \end{array} $$

$$ = 1 0 \mathrm{ns} (\min) $$

$$ \begin{array}{r l r} {t _ {E N}} & = & {\mathrm{Output~enable~time=10~ns~(max),with}} \ & & {\mathrm {DV_ {IO} \geq 2.3V}} \end{array} $$

Note: See Figure 1-1 for digital interface timing diagram.

where f_SCLK is the minimum SPI serial clock frequency required to transfer all N-bits of output data during input acquisition time ( t_ACQ ).

Table 6-4 and Table 6-5 show the examples of calculated minimum SPI clock ( t_SCLK ) requirements for various input acquisition times for 1 Msps and 500 kSPS family devices, respectively.

TABLE 6-4: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME ( T_ACQ ) FOR MCP331X1-10

Input Acquisition Time: t_ACQ (nS) (Note 4)	Data Conversion Time: t_CNV (nS) (Note 5)	SPI Clock ( f_SCLK ) Speed Requirement (Note 1), (Note 2)			Sample Rate: f_S (Msps)	Conditions
		MCP33131-10 (16-bit)	MCP33121-10 (14-bit)	MCP33111-10 (12-bit)
250	750	69.57 MHz	60.87 MHz	52.17 MHz	1	85°C < T_A ≤ 125°C (Note 3)
270		64 MHz	56 MHz	48 MHz	0.98
280		61.54 MHz	53.85 MHz	46.15 MHz	0.97
290	710	59.26 MHz	51.85 MHz	44.44 MHz	1	-40°C ≤ T_A ≤ 85°C
300		57.15 MHz	50 MHz	42.86 MHz	0.99
320		53.33 MHz	46.67 MHz	40 MHz	0.97
400		42.11 MHz	36.84 MHz	30 MHz	0.9
540		30.77 MHz	26.92 MHz	23.08 MHz	0.8
720		22.86 MHz	20 MHz	17.14 MHz	0.7
720		17.2 MHz	15.05 MHz	12.9 MHz	0.6
1290		12.6 MHz	11.02 MHz	9.45 MHz	0.5
1750		9.04 MHz	7.91 MHz	6.78 MHz	0.4
2620		6.15 MHz	5.39 MHz	4.62 MHz	0.3
4290		3.75 MHz	3.28 MHz	2.81 MHz	0.2
9290		1.73 MHz	1.51 MHz	1.3 MHz	0.1
Note 1: This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time ( t_ACQ ), when the ADC is operating in continuous input sampling mode.2: See Equation 6-9 for the calculation of the SPI clock speed requirement.3: In extended temperature range, the device takes longer data conversion time ( t_CNV : 750 nS, max). Using a shorter input acquisition time is recommended ( t_ACQ : 250 nS) for 1 Msps throughput rate.4: Input acquisition time ( t_ACQ ) is user-controllable.5: Data conversion time ( t_CNV ) is not user-controllable.

TABLE 6-5: SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (T _ACQ ) FOR MCP331X1-05

Input Acquisition Time: t_ACQ (nS) (Note 3)	Data Conversion Time: t_CNV (nS) (Note 4)	SPI Clock ( f_SCLK ) Speed Requirement (Note 1), (Note 2)			Sample Rate: f_S (kSPS)	Conditions
		MCP33131-05 (16-bit)	MCP33121-05 (14-bit)	MCP33111-05 (12-bit)
700	1300	23.53MHz 20.59 MHz 17.65 MHz			500	-40°C ≤ A_T ≤ 125°C
740		22.22 MHz	19.44 MHz	16.67 MHz	490
790		20.78 MHz	18.18 MHz	15.58 MHz	480
930		17.58 MHz	15.39 MHz	13.19 MHz	450
1200		13.56 MHz	11.86 MHz 10.17 MHz		400
1560		10.39 MHz	9.09 MHz	7.79 MHz	350
2030		7.96 MHz	6.97 MHz	5.97 MHz	300
2700		5.97 MHz	5.22MHz	4.48 MHz	250
3700		4.35 MHz	3.8 MHz	3.26 MHz	200
5370		2.99 MHz	2.62 MHz	2.25 MHz	150
8700		1.84 MHz	1.61 MHz	1.38 MHz	100
Note 1: This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time ( t_ACQ ), when the ADC is operating in continuous input sampling mode.2: See Equation 6-9 for the calculation of the SPI clock speed requirement.3: Input acquisition time ( t_ACQ ) is user-controllable.4: Data conversion time ( t_CNV ) is not user-controllable.

6.5 Transfer Function

The pseudo-differential analog input is:

$$ V _ {I N} = \left(V _ {I N} +\right) - \left(V _ {I N ^ {-}}\right) $$

where V_IN^+ is the analog input voltage at A_IN^+ pin with respect to the ground reference (GND), and Vin- is the voltage at A_IN^- pin, which is 0V when tied to the analog input ground reference (GND).

The LSB size is given by Equation 6-10. and an example of LSB size vs. reference voltage is summarized in Table6-6.

EQUATION 6-10: LSB SIZE - EXAMPLE

LSB = _REF2^N

where N is the resolution of the ADC in bits.

TABLE 6-6: LSB SIZE VS. REFERENCE

Reference Voltage (VREF)	LSB Size
	MCP33131-XX (16-bit)	MCP33121-XX (14-bit)	MCP33111-XX (12-bit)
2.5V	38.2μV	152.6 μV	0.6104 mV
2.7V	41.2 μV	164.8 μV	0.6592 mV
3V	45.8 μV	183.1 μV	0.7324 mV
3.3V	50.4 μV	201.4 μV	0.8057 mV
3.5V	53.4 μV	213.6 μV	0.8545 mV
4V	61.0 μV	244.1 μV	0.9766 mV
4.5V	68.7 μV	274.7 μV	1.0986 mV
5V	76.3 μV	305.2 μV	1.2207 mV

5.1

77.8 μV

311.3 μV

1.2451 mV

Figure 6-5 shows the ideal transfer function and Table 6-7 shows the digital output codes for the MCP33131/MCP33121/MCP33111-XX.

FIGURE 6-5: Ideal Transfer Function.

6.6 Digital Output Code

The digital output code is proportional to the input voltage. The output data is in unipolar straight binary format. The following is an example of the output code:

(a) for a zero or negative input:

Analog Input: V_IN ≤ 0 (V)

Output Code: 0000...0000

(b) for a mid-scale input:

Analog Input: V_IN = +V_REF/2(V)

Output Code: 1000...0000

(c) for a positive full-scale input:

Analog Input: V_IN = +V_REF(V)

Output Code: 1111...1111

The code will be locked at 1111...11 for all voltages greater than (V _REF - 1 LSB) and 0000...00 for voltages less than 0V. Table6-7 shows an example of output codes of various input levels.

TABLE 6-7: DIGITAL OUTPUT CODE

Input Voltage (V)	Digital Output Codes
	MCP33131-XX(16-bit)	MCP33121-XX(14-bit)	MCP33111-XX(12-bit)
V_REF	1111-1111-1111-111111	-1111-1111-11111111-1111	1-1111
V_REF - 1 LSB 1111	-1111-1111-111111-1111	-1111-11111111-1111-1111
:	:	:	:
.	.	.	.
V_REF/2 1000-0	000-0000-000010-0000-00	00-00001000-0000-0000
:	:	:	:
.	.	.	.
2 LSB 0000	0000-0000-001000-0000	0000-00100000-0000-0010
1 LSB 0000	0000-0000-000100-0000	0000-00010000-0000-0001
≤ 0V	0000-0000-0000-0000	00-0000-0000-0000	0000-0000-0000

7.0 DIGITAL SERIAL INTERFACE

The device has a SPI-compatible serial digital interface using four digital pins: CNVST, SDI, SDO and SCLK.

Figure 7-1 shows the connection diagram with the host device and Figure 7-2 shows the SPI-compatible serial interface timing diagram.

The SDI pin can be tied to the digital I/O interface supply voltage (DV _IO ) or just maintain logic "High" level by the host. The CNVST pin is used for both chip select (CS) and conversion-start control.

A rising edge on CNVST initiates the conversion process. Once the conversion is initiated, the device will complete the conversion regardless of the state of CNVST. This means the CNVST pin can be used for other purposes during t_CNV .

When the conversion is complete, the output is available at SDO by lowering CNVST. Data is sent MSB-first and changes on the falling edge of SCLK.

Output data can be sampled on either edge of SCLK. However, a digital host capturing data on the falling edge of SCLK can achieve a faster read out rate.

SDO returns to high-Z state after the last data bit is clocked out or when CNVST goes high, whichever occurs first.

(a) MCP33131/21/11-XX (b) Host Device (Master) Note 1: Adding this pull-up is needed when monitoring status of Recalibrate. DV_IO CNVST SDI SDO SCLK 10 kΩ (Note 1) CS SDI SCLK

FIGURE 7-1: Digital Interface Connection Diagram.

SDI = DVIO tCYC = 1/fS (Note 1) CNVST tCNVH tSU_SDIH_CNV (Note 2) SCLK (SNote 5) tDO tSCLK_L tSCLK_H tQUIET tDIS sCLK sD15 (MSB) D14 D13 D12 D2 D1 D0 Hi-Z Hi-Z tCNV (MAX) tEN (Note 3) tEN (Note 4) ADC State Input Acquisition (tACQ) Conversion (tCNV) Input Acquisition (tACQ)

Note 1: SDI must maintain "High" during the entire t_CYC .

2: Any SCLK toggling events (dummy clocks) before CNVST is changed to "Low" are ignored.

3: t_EN when CNVST is lowered after t_CNV (Max).

4: t_EN when CNVST is lowered before t_CNV (Max).

5: Recommended data detection: Detect SDO on the falling edge of SCLK.

FIGURE 7-2: SPI Compatible Serial Interface Timing Diagram (16-bit device).

7.1 Recalibrate Command

The user may use the recalibrate command in the following cases:

• When the reference voltage was not fully settled during the first-power sequence.
• During operation, to ensure optimum performance across varying environment conditions, such as reference voltage and temperature.

A self-calibration is initiated by sending the recalibrate command. The host device sends a recalibrate command by transmitting 1024 SCLK pulses (including the clocks for data bits) while the device is in the acquisition phase (Standby).

The device drives SDO low during the recalibration procedure, and returns to high-Z once completed. The status of the recalibration procedure can be monitored by placing a pull-up on SDO, so that SDO goes high when the recalibration is complete.

Figure 7-3 shows the recalibrate command timing diagram. The calibration takes approximately 500 ms ( t_CAL ).

SDI = DVIO (Note 1) CNVST Complete data reading Start recalibration Finish recalibration Device Recalibration 1 2 3 ... 15 16 ... 1024 clocks (SPI™Recalibrate command) 1024 tCAL SCLK "High" with Pull-up ADC Output Data Stream (Hi-Z) SDO "Low" (Hi-Z) ADC State tCNV (Note 2) (High" with Pull-up) (Note 3) (Hi-Z) (Note 4) Note 1: SDI must remain "High" during the entire recalibration cycle. 2: The 1024 clocks include the clocks for data bits. 3: SDO outputs "Low" during calibration, and Hi-Z when exiting the calibration. 4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately.

FIGURE 7-3: Recalibrate Command Timing Diagram.

Note: When the device performs a self-calibration, it is important to note that both AV_DD and the reference voltage ( V_REF ) must be stabilized for a correct calibration. This is also true when the device is first powered-up, the reference voltage ( V_REF ) must be stabilized before self-calibration begins. This means the V_REF must be provided prior to supplying AV_DD or within about 64 ms after supplying AV_DD .

NOTES:

8.0 TERMINOLOGY

Analog Input Bandwidth (Full-Power Bandwidth)

The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

Aperture Delay or Sampling Delay

This is the time delay between the rising edge of the CNVST input and when the input signal is held for a conversion.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. No missing codes to 16-bit resolution indicates that all 65,536 codes (16,384 codes for 14-bit, 4096 codes for 12-bit) must be present over all the operating conditions.

Integral Nonlinearity (INL)

INL is the maximum deviation of each individual code from an ideal straight line drawn from negative full scale through positive full scale.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the power of the fundamental ( P_S ) to the noise floor power ( P_N ), below the Nyquist frequency and excluding the power at DC and the first nine harmonics.

EQUATION 8-1:

$$ S N R 1 0 \quad \log \left(\frac {P _ {S}}{P _ {N}}\right) $$

SNR is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range.

Signal-to-Noise and Distortion (SINAD)

SINAD is the ratio of the power of the fundamental ( P_S ) to the power of all the other spectral components including noise ( P_N ) and distortion ( P_D ) below the Nyquist frequency, but excluding DC:

EQUATION 8-2:

$$ \begin{array}{r l} S I N A D 1 0 & \log \left(\frac {P _ {S}}{P _ {D} + P _ {N}}\right) \ & 1 0 = \left[ \frac {\frac {S N R}{1 0}}{- 1 0 Q} ^ {- \frac {T H D}{1 0}} \right] 0 \end{array} $$

SINAD is either given in units of dBc (dB to carrier), when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale), when the power of the fundamental is extrapolated to the converter full-scale range.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula:

EQUATION 8-3:

$$ E N O B = \frac {S I N A D 1 . 7 6 -}{6 . 0 2} $$

Gain Error

Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain error is given as a percentage of the ideal input full-scale range. Gain error is usually expressed in LSB or as a percentage of full-scale range (%FSR).

Offset Error

Offset error is the difference between the ideal voltage (0V + 0.5 LSB) that produces the first code transition ("000...000" to "000...001") and the actual voltage producing that code.

Temperature Drift

The temperature drift for offset error and gain error specifies the maximum change from the initial (+25°C) value to the value at across the T_MIN to T_MAX range. The value is normalized by the reference voltage and expressed in V/^ or ppm/°C.

Maximum Conversion Rate

The maximum clock rate at which parametric testing is performed.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier) or dBFS.

Total Harmonic Distortion (THD)

THD is the ratio of the power of the fundamental (P_S) to the summed power of the first 13 harmonics (P_D) .

EQUATION 8-4:

$$ T H D 1 0 \quad l o g \left(\frac {P _ {S}}{P _ {D}}\right) $$

THD is typically given in units of dBc (dB to carrier). THD is also shown by:

EQUATION 8-5:

$$ T H D 2 \text {②} - \log \frac {\sqrt {V _ {2} ^ {2} + V _ {3} ^ {2} + V _ {4} ^ {2} + \dots + V _ {n} ^ {2}}}{V _ {1} ^ {2}} $$

Where:

$$ V _ {1} = \text { RMS amplitude of the } $$

fundamental frequency

$$ V _ {1} \text { through } V _ {n} = \text { Amplitudes of the second } $$

through n^th harmonics

Common-Mode Rejection Ratio (CMRR)

Common-mode rejection is the ability of a device to reject a signal that is common to both sides of a differential or pseudo-differential input pair. The common-mode signal can be an AC or DC signal or a combination of the two. CMRR is measured using the ratio of the differential signal gain to the common-mode signal gain and expressed in dB with the following equation:

EQUATION 8-6:

$$ C M R R 2 0 \quad \log \left(\frac {A _ {D I F F}}{A _ {C M}}\right) $$

Where:

$$ A _ {D I F F} = \Delta \text { Output Code } / \Delta \text { Differential Voltage } $$

$$ A _ {D I F F} = \Delta \text { Output Code } / \Delta \text { Common - Mode Voltage } $$

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

10-Lead MSOP (3x3 mm)

XXXXXX YWWNNN

Corresponding Part Number:

31-10	= MCP33131-10
31-05	= MCP33131-05
21-10	= MCP33121-10
21-05	= MCP33121-05
11-10	= MCP33111-10
11-05	= MCP33111-05

Example

31-10 839256

10-Lead TDFN (3x3x0.9 mm) Example

XXXX YYWW NNN PIN 1

Corresponding Part Number:

311	= MCP33131-10
310	= MCP33131-05
211	= MCP33121-10
210	= MCP33121-05
111	= MCP33111-10
110	= MCP33111-05

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

eBb-free JEDEC ^® designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

10-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

0.20 H D D/2 A N E1/2 E1 E/2 E 0.25 C 0.20 H 1 2 e B 8X b Ø 0.13 M A B

TOP VIEW

SEATING PLANE A A1 8X 0.10 C A2

H SEE DETAIL A

SIDE VIEW END VIEW

Microchip Technology Drawing C04-021D Sheet 1 of 2

10-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

4X Θ1 SEATING PLANE C L (L1) 4X Θ1 DETAIL A c Θ

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N	10
Pitch	e	0.50 BSC
Overall Height	A	-	-	1.10
Molded Package Thickness	A2	0.75	0.85	0.95
Standoff	A1	0.00	-	0.15
Overall Width	E	4.90 BSC
Molded Package Width	E1	3.00 BSC
Overall Length	D	3.00 BSC
Foot Length	L	0.40	0.60	0.80
	L1F	0.95 REF
Mold Draft Angle		0°	-	8°
Foot Angle - 15°5°	1
Lead Thickness	c	0.08	-	0.23
Lead Width	b	0.15	-	0.33

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-021D Sheet 2 of 2

10-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

G Z C SILK SCREEN G1 Y1 X1 E

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.50 BSC
	CContact Pad Spacing40
Overall Width	Z			5.80
Contact Pad Width (X10)	X1			0.30
Contact Pad Length (X10)	Y1			1.40
Distance Between Pads (X5) G1 3.0
	GDistance Between Pads (X6) 0.20

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2021B

10-Lead Thin Plastic Dual Flat, No Lead Package (MN) - 3x3x0.8mm Body [TDFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Microchip Technology Drawing C04-185A Sheet 1 of 2

10-Lead Thin Plastic Dual Flat, No Lead Package (MN) - 3x3x0.8mm Body [TDFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

NOTE 2

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N	10
Pitch	e	0.50 BSC
Overall Height	A	0.70	0.75	0.80
Standoff	A1	0.00	0.02	0.05
Contact Thickness	A3	0.20 REF
Overall Length	D	3.00 BSC
Exposed Pad Length	D2	2.20	2.30	2.35
Overall Width	E	3.00 BSC
Exposed Pad Width	E2	1.55	1.65	1.70
Contact Width	b	0.18	0.25	0.30
Contact Length	L	0.30	0.40	0.50
Contact-to-Exposed Pad	K	0.20	-	-

Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04-0185A Sheet 2 of 2

APPENDIX A: REVISION HISTORY

Revision A (November 2018)

• Original release of this document.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. Device Input Type -X Sample Rate -Tape and Reel Package Temperature Range -X /XXX

Device: MCP33131-10: 1 Msps 16-Bit Single-Ended Input SAR ADC

MCP33121-10: 1 Msps 14-Bit Single-Ended Input SAR ADC MCP33111-10: 1 Msps 12-Bit Single-Ended Input SAR ADC

MCP33131-05: 500 kSPS 16-Bit Single-Ended Input SAR ADC
MCP33121-05: 500 kSPS 14-Bit Single-Ended Input SAR ADC
MCP33111-05: 500 kSPS 12-Bit Single-Ended Input SAR ADC

Input Type Blank = Single-Ended Input

Sample Rate: 10 = 1 Msps 05 = 500 kSPS

Tape and Blank = Standard packaging (tube or tray) Reel Option: T = Tape and Reel

Temperature E = -40°C to +125°C (Extended) Range: I = -40°C to +85°C (Industrial)

Package: MS = Plastic Micro Small Outline Package (MSOP), 10-Lead MN = Thin Plastic Dual Flat No Lead Package (TDFN), 10-Lead

Note 1: Tape and Reel identifier appears only in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

Examples:

a)	MCP33131-10-I/MS: 1 Msps, 10LD MSOP, 16-bit device
b)	MCP33131-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 16-bit device
c)	MCP33131-10-I/MN: 1 Msps, 10LD TDFN, 16-bit device
d)	MCP33131-10T-I/MN: 1 Msps, 10LD TDFN, Tape and Reel, 16-bit device
e)	MCP33121-10-I/MS: 1 Msps, 10LD MSOP, 14-bit device
f)	MCP33121-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 14-bit device
g)	MCP33121-10-I/MN: 1 Msps, 10LD TDFN, 14-bit device
h)	MCP33121-10T-I/MN: 1 Msps, 10LD TDFN, Tape and Reel, 14-bit device
i)	MCP33111-10-I/MS: 1 Msps, 10LD MSOP, 12-bit device
j)	MCP33111-10T-I/MS: 1 Msps, 10LD MSOP, Tape and Reel, 12-bit device
k)	MCP33111-10-I/MN: 1 Msps, 10LD TDFN, 12-bit device
l)	MCP33111-10T-I/MN: 1 Msps, 10LD TDFN, Tape and Reel, 12-bit device
m)	MCP33131-05-I/MS: 500 kSPS, 10LD MSOP, 16-bit device
n)	MCP33131-05T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 16-bit device
o)	MCP33131-05-I/MN: 500 kSPS, 10LD TDFN, 16-bit device
p)	MCP33131-05T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 16-bit device
q)	MCP33121-05-I/MS: 500 kSPS, 10LD MSOP, 14-bit device
r)	MCP33121-05T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 14-bit device
s)	MCP33121-05-I/MN: 500 kSPS, 10LD TDFN, 14-bit device
t)	MCP33121-05T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 14-bit device
u)	MCP33111-05-I/MS: 500 kSPS, 10LD MSOP, 12-bit device
v)	MCP33111-05T-I/MS: 500 kSPS, 10LD MSOP, Tape and Reel, 12-bit device
w)	MCP33111-05-I/MN: 500 kSPS, 10LD TDFN, 12-bit device
x)	MCP33111-05T-I/MN: 500 kSPS, 10LD TDFN, Tape and Reel, 12-bit device

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
- Microchip is willing to work with the customer who is concerned about the integrity of their code.

- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

= ISO/TS 16949=

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELoQ, KEELoQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, InterChip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQL, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3911-0

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