MIC4742 - Electronic component Microchip - Free user manual and instructions

USER MANUAL MIC4742 Microchip

2 MHz Dual 2A Integrated Switch Buck Regulator

General Description

The Micrel MIC4742 is a high efficiency dual PWM buck (step-down) regulator that provides dual 2A current output. The MIC4742 operates at 2MHz. A proprietary internal compensation technique allows a closed loop bandwidth of over 200kHz.

The low on-resistance internal P-Channel MOSFET of the MIC4742 allows efficiencies over 92%, reduces external components count and eliminates the need for an expensive current sense resistor.

The MIC4742 operates from 2.9V to 5.5V input and the output can be adjusted down to 0.6V. The device can operate with a maximum duty cycle of 100% for use in low-dropout conditions.

The MIC4742 is available in the exposed pad 16-pin 3mm x 3mm MLF® and EPAD TSSOP-16 packages with a junction operating range from -40^ to +125^ .

All support documentation can be found on Micrel's web site at: www.micrel.com.

Features

• 2.9 to 5.5V supply voltage
• 2MHz PWM mode
- 2A Dual output
• Greater than 92% efficiency
• 100% maximum duty cycle
- Adjustable output voltage option down to 0.6V
• Ultra-fast transient response
- Ultra-small external components Stable with a 1μH inductor and a 4.7μF output capacitor
• Fully integrated 2A MOSFET switches
- Micro-power shutdown
• Thermal shutdown and current limit protection
• Available in a 3mm x 3mm 16-pin MLF ^® and 16-pin TSSOP
- -40°C to +125°C junction temperature range

Applications

• Broadband: xDSL modems
  • Automotive satellite radios
  • HD STB, DVD/TV recorder
  • Computer peripherals: printers and graphic cards
• FPGA/ASIC
• General point of load

Typical Application

MIC4742 VIN=2.9V to 5.5V VOUT2 L2 6 15 VIN2 VIN2 SW2 SW2 FB2 EN2 PGND2 PGND1 SGND 8 13 6 15 4 3 1 2 5 8 16 7 14 9 10 12 11 EP D1 SW1 SW1 FB1 EN1 CIN1 L1 1.0μH COUT1 4.7μF VOUT1

2A 2MHz Dual Buck Regulator

MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information

Part Number Voltage	Junction Temp.	Range Package Lead Finish
MIC4742YML Adj. -40° to +125°C	16-Pin 3mm x 3mm MLF		^®	Pb-Free
MIC4742YTSE Adj. -40° to +125°C		16-Pin EPAD TSSOP Pb-Free

Note:
MLF ^® is a GREEN RoHS-compliant package. Lead finish is NiPdAu. Mold compound is Halogen Free.

Pin Configuration

EN1 1 FB1 2 SGND 3 VIN1 4 VIN2 5 BIAS 6 FB2 7 EN2 8 EPAD 16 SW1 15 SW1 14 PGND1 13 VIN1 12 VIN2 11 PGND2 10 SW2 9 SW2

16-Pin EPAD-TSSOP (YTSE)

Pin Description

Pin Number (MLF®)	Pin Number (EPAD-TSSOP)	Pin Name Pin Function
1	7	FB2	Feedback for output 2 (Input). Input to the error amplifier, connect to the external resistor divider network to set the output voltage.
2^(1)	8^(1)	EN2	Enable for output 2 (Input). Logic level low, will shutdown the device, reducing the current draw to less than 5μA (both EN1 and EN2 are low).
3,4	9,10	SW2	Switch for output 2 (Output): Internal power P-Channel MOSFET output switch
5	11	PGND2	Power Ground for output 2. Provides the ground return path for the high-side drive current.PGND1 pin and PGND2 pin are internally connected by anti-parallel diodes.
6,15	5,12	VIN2	Supply Voltage for output 2 (Input): Supply voltage for the source of the internal P-channel MOSFET and driver. Requires bypass capacitor to GND.VIN1 pins and VIN2 pins are internally connected by anti-parallel diodes.
7,14	4,13	VIN1	Supply Voltage for output 1 (Input): Supply voltage for the source of the internal P-channel MOSFET and driver. Requires bypass capacitor to GND.VIN1 pins and VIN2 pins are internally connected by anti-parallel diodes.
8	14	PGND1	Power Ground for output 1. Provides the ground return path for the high-side drive current.PGND1 pin and PGND2 pin are internally connected by anti-parallel diodes.
9,10	15,16	SW1	Switch for output 1 (Output): Internal power P-Channel MOSFET output switch
11^(1)	1^(1)	EN1	Enable for output 1 (Input). Logic level low, will shutdown the device, reducing the current draw to less than 5μA (both EN1 and EN2 are low).
12	2	FB1	Feedback for output 1 (Input). Input to the error amplifier, connect to the external resistor divider network to set the output voltage.
13	3	SGND	Signal (Analog) Ground. Provides return path for control circuitry and internal reference.
16	6	BIAS	Internal circuit bias supply. Must be bypassed with a 0.1μF ceramic capacitor to SGND. Biased through a 10Ω resistor to VIN.
EPAD EPAD GND Connect to ground.

Note:
1. Do not float Enable Input.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_IN )....-0.3V to +6V

Output Switch Voltage (V SW1 , V SW2 )......-0.3V to +6V

Output Switch Current ( I_SW1 , I_SW2 ).....Internally Limited

Input Voltage (VEN), (VFB), (VBIAS)....-0.3V to VIN

Storage Temperature (T _s )......-60°C to +150°C

Junction Temperature 150°C

Lead Temperature (soldering, 10sec.) 260°C

ESD Rating ^(3) 2KV

Operating Ratings ^(2)

Supply Voltage ( V_IN )....+2.9V to +5.5V

Logic Input Voltage ( V_EN ) 0V to V_IN

Junction Temperature (T _J )......-40°C to +125°C

Junction Thermal Resistance

3mm x 3mm MLF ^ (θJA)....60°C/W

EPAD TSSOP ( _JA )....35°C/W

Electrical Characteristics ^(4)

V_IN = V_EN = 3.6V; L = 1.0 H; C_OUT = 4.7 F; T_A = 25^, unless noted. Bold values indicate -40^ ≤ T_J ≤ +125^ .

Parameter	Condition	Min				Typ
Supply Voltage Range		2.9		5.5	V
Under-Voltage Lockout Threshold Turn-on		2.45	2.6	2.7	V
UVLO Hysteresis			100		mV
Quiescent Current	V_FB = 0.9 * V_NOM (not switching); V_IN = 5.5V		1.4	3.0	mA
	V_FB = 0.9 * V_NOM (not switching); V_IN = 3.6V		1.0		mA
Shutdown Current	V_EN = 0V		1.6	10	μA
[Adjustable] Feedback Voltage	±2% (over temperature) I_LOAD = 100μA	0.588	0.6	0.612	V
FB pin input current			1		nA
Current Limit	V_FB = 0.9 * V_NOM	2.5	4.3		A
Output Voltage Line Regulation	V_IN = 2.9V to 5.5V; I_LOAD = 100 μA		0.07		%
Output Voltage Load Regulation	20mA < I_LOAD < 2A		0.2		%
Maximum Duty Cycle	V_FB ≤ 0.9 * V_NOM	100			%
Switch ON-Resistance	I_SW = 50mA V_FB = GND		155			mΩ
Oscillator Frequency		1.5	2	2.3	MHz
Switching Phase			180		Deg
Enable Threshold		0.5	0.9	1.3	V
Enable Hysteresis			55		mV
Enable Input Current			0.1	2	μA
Over-Temperature Shutdown			153		°C
Over-Temperature Hysteresis			18		°C

Notes:

1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. Specification for packaged product only.

Typical Characteristics

Typical Characteristics (continue)

Functional Characteristics

Functional Diagram

graph TD
    subgraph Power Source
        A["VIN"] --> B["BIAS"]
        C["VIN"] --> D["Enable and Control Logic"]
        E["VIN"] --> F["Oscillator P1 P2"]
        G["VIN"] --> H["0.6V Voltage Reference"]
    end

    subgraph Power Supply
        I["PWM Control"] --> J["Predriver"]
        K["PWM Control"] --> L["Predriver"]
        M["PWM Control"] --> N["Predriver"]
        O["PWM Control"] --> P["Predriver"]
        Q["PWM Control"] --> R["Predriver"]
        S["PWM Control"] --> T["Predriver"]
        U["PWM Control"] --> V["Predriver"]
        W["PWM Control"] --> X["Predriver"]
        Y["PWM Control"] --> Z["Predriver"]
        AA["PWM Control"] --> AB["Predriver"]
        AC["PWM Control"] --> AD["Predriver"]
        AE["PWM Control"] --> AF["Predriver"]
        AG["PWM Control"] --> AH["Predriver"]
        AI["PWM Control"] --> AJ["Predriver"]
        AK["PWM Control"] --> AL["Predriver"]
        AM["PWM Control"] --> AN["Predriver"]
        AO["PWM Control"] --> AP["Predriver"]
        AQ["PWM Control"] --> AR["Predriver"]
        AS["PWM Control"] --> AT["Predriver"]
        AU["PWM Control"] --> AV["Predriver"]
        AW["PWM Control"] --> AX["Predriver"]
        AY["PWM Control"] --> AZ["Predriver"]
        BA["PWM Control"] --> BB["Predriver"]
        BC["PWM Control"] --> BD["Predriver"]
        BE["PWM Control"] --> BF["Predriver"]
        BG["PWM Control"] --> BH["Predriver"]
        BI["PWM Control"] --> BJ["Predriver"]
        BK["PWM Control"] --> BL["Predriver"]
        BM["PWM Control"] --> BN["Predriver"]
        BO["PWM Control"] --> BP["Predriver"]
        BQ["PWM Control"] --> BR["Predriver"]
        BS["PWM Control"] --> BT["Predriver"]
        BU["PWM Control"] --> BV["Predriver"]
        BW["PWM Control"] --> BX["Predriver"]
        BY["PWM Control"] --> BZ["Predriver"]
        CA["PWM Control"] --> CB["Predriver"]
        CC["PWM Control"] --> CD["Predriver"]
        DE["PWM Control"] --> DF["Predriver"]
        DG["PWM Control"] --> DH["Predriver"]
        DI["PWM Control"] --> DJ["Predriver"]
        DK["PWM Control"] --> DL["Predriver"]
        DM["PWM Control"] --> DN["Predriver"]
        DOP["SW1 SW1 FB1 PGND1 SW2 SW2 FB2 PGND2"] --> DC["Power Supply"]
    end

    subgraph Power Supply
        E
        F
        G
        H
        I
        J
        K
        L
        M
    end

    %% Note: The diagram shows a schematic of an electrical or control logic circuit with multiple input/output pins connected to the output lines.

MIC4742 Block Diagram

Pin Description

VIN1/VIN2

VIN pins (two pins for VIN1 and two pins for VIN2) provide power to the source of the internal P-channel MOSFET along with the current limiting sensing. VIN1 pins and VIN2 pins are internally connected by anti-parallel diodes. The VIN operating voltage range is from 2.9V to 5.5V. Due to the high switching speeds, a 10 F capacitor is recommended close to VIN and the power ground (PGND) for each pin for bypassing. Please refer to layout recommendations for more details.

BIAS

The bias (BIAS) provides power to the internal reference and control sections of the MIC4742. A 10Ω resistor from VIN to BIAS and a 0.1μF from BIAS to SGND are required for clean operation.

EN1/EN2

The enable pins (EN1 and EN2) provides a logic level control of the outputs 1 and 2. In the off state, supply current of the device is greatly reduced (typically <2 A ). Do not drive the enable pin above the supply voltage.

FB1/FB2

The feedback pins (FB1 and FB2) provides the control path to control the outputs 1 and 2. A resistor divider connecting the feedback to the output is used to adjust the desired output voltage. The output voltage is calculated as follows:

$$ V _ {R E F O U} \left(\frac {R 1}{R 2} + x = 1 \right. $$

where V_REF is equal to 0.6V.

A feed-forward capacitor is recommended for most designs. To reduce current draw, 10K feedback resistors are recommended from the outputs to the FB pins (R1 in the equation). Also, feed-forward capacitors should be connected between the outputs and feedback pins (across R1). The large resistor value and the parasitic capacitance of the FB pin can cause a high frequency pole that can reduce the overall system phase margin. By placing a feed-forward capacitor, these effects can be significantly reduced. Feed-forward capacitance ( C_FF ) can be calculated as follows:

$$ C _ {F F} = \frac {1}{\pi \times \quad \times 2 0 0 \mathrm{kHzR12}} $$

SW1/SW2

The switch pins (SW1 and SW2) connect directly to the inductor and provide the switching current necessary to operate in PWM mode. Due to the high speed switching on these pins, the switch nodes should be routed away from sensitive nodes. These pins also connect to the cathodes of the free-wheeling diodes.

PGND1/PGND2

Power ground pins (PGND1 and PGND2) are the ground paths for the MOSFET drive current. PGND1 pin and PGND2 pin are internally connected by anti-parallel diodes. The current loop for the power ground should be as small as possible and separate from the Signal ground (SGND) loop. Refer to the layout recommendation for more details.

SGND

Signal ground (SGND) is the ground path for the biasing and control circuitry. The current loop for the signal ground should be separate from the power ground (PGND) loop. Refer to the layout recommendation for more details.

EPAD

The exposed pad on the bottom of the part must be connected to ground.

Application Information

The MIC4742 is a dual 2A PWM non-synchronous buck regulator. By switching an input voltage supply, and filtering the switched voltage through an inductor and capacitor, a regulated DC voltage is obtained. Figure 1 shows a simplified example of a non-synchronous buck converter.

VIN Vsw VOUT VIN Vsw VOUT

Figure 1. Example of Non-synchronous Buck Converter

For a non-synchronous buck converter, there are two modes of operation; continuous and discontinuous. Continuous or discontinuous refer to the inductor current. If current is continuously flowing through the inductor throughout the switching cycle, it is in continuous operation. If the inductor current drops to zero during the off time, it is in discontinuous operation. Critically continuous is the point where any decrease in output current will cause it to enter discontinuous operation. The critically continuous load current can be calculated as follows;

$$ \mathrm{I} _ {\text { OUT }} = \frac {\left[ \mathrm{V} _ {\text { OUT }} - \frac {\mathrm{V} _ {\text { OUT }} ^ {2}}{\mathrm{V} _ {\text { IN }}} \right]}{\times \times \mathrm{L2fsw}} $$

Continuous or discontinuous operation determines how we calculate peak inductor current.

Continuous Operation

Figure 2 illustrates the switch voltage and inductor current during continuous operation.

Figure 2. Continuous Operation

The output voltage is regulated by pulse width modulating (PWM) the switch voltage to the average required output voltage. The switching can be broken up into two cycles; On and Off.

During the On-Time, Figure 3 illustrates the high side switch is turned on, current flows from the input supply through the inductor and to the output. The inductor current is charged at the rate;

(VIN - VOUT) L VIN VSW VOUT ICIN IL VSW 0V IL IOUT ICIN 0A ID 0A TON

Figure 3. On-Time

To determine the total on-time, or time at which the inductor charges, the duty cycle needs to be calculated. The duty cycle can be calculated as;

$$ D = \frac {V _ {\text { OUT }}}{V _ {\text { IN }}} $$

and the On time is;

$$ \mathrm{T} _ {\mathrm{ON}} = \frac {\mathrm{D}}{\mathrm{fsw}} $$

Therefore, peak to peak ripple current is;

$$ \mathrm{I} _ {\mathrm{pk} - \mathrm{pk}} = \frac {\left(\mathrm{V} _ {\mathrm{IN}} - \mathrm{V} _ {\mathrm{OUT}}\right) \times \frac {\mathrm{V} _ {\mathrm{OUT}}}{\mathrm{V} _ {\mathrm{IN}}}}{\mathrm{fsw} \times \mathrm{L}} $$

Since the average peak to peak current is equal to the load current. The actual peak (or highest current the inductor will see in a steady-state condition) is equal to the output current plus 12 the peak-to-peak current.

$$ I = I _ {\text {OUTp}} \frac {(V - V _ {\text {OUTIN}}) \times \frac {V _ {\text {OUT}}}{V _ {\text {IN}}}}{\times \times L f s w 2} $$

Figure 4 demonstrates the off-time. During the off-time, the high-side internal P-channel MOSFET turns off. Since the current in the inductor has to discharge, the current flows through the free-wheeling Schottky diode to the output. In this case, the inductor discharge rate is (where V_D is the diode forward voltage);

$$ - \frac {\left(\mathrm{V} _ {\text { OUT }} + \mathrm{V} _ {\mathrm{D}}\right)}{\mathrm{L}} $$

The total off time can be calculated as;

$$ \mathrm{T} _ {\mathrm{OFF}} = \frac {1 - \mathrm{D}}{\mathrm{fsw}} $$

VIN ICIN VSW IL VOUT VSW 0V IL IOUT ICIN 0A ID 0A TOFF

Figure 4. Off-Time

Discontinuous Operation

Discontinuous operation is when the inductor current discharges to zero during the off cycle. Figure 5 demonstrates the switch voltage and inductor currents during discontinuous operation.

VIN ICIN VSW IL VOUT VIN VOUT 0V VSW IL IOUT 0A Inductor Current is zero ICIN ID 0A

Figure 5. Discontinuous Operation

When the inductor current (IL) has completely discharged, the voltage on the switch node rings at the frequency determined by the parasitic capacitance and the inductor value. In Figure 5, it is drawn as a DC voltage, but to see actual operation (with ringing) refer to the functional characteristics.

Discontinuous mode of operation has the advantage over full PWM in that at light loads, the MIC4742 will skip pulses as necessary, reducing gate drive losses, drastically improving light load efficiency.

Efficiency Considerations

Calculating the efficiency is as simple as measuring power out and dividing it by the power in;

$$ \text { Efficiency } \quad \frac {P _ {\text { OUT }}}{P _ {\text { IN }}} \times 1 0 0 $$

Where input power ( P_IN ) is;

$$ P = V _ {I N I N} I _ {I N} $$

and output power ( P_OUT ) is calculated as;

$$ \text { OUT } = \text { VOUT } \times \text { IOUT } $$

The Efficiency of the MIC4742 is determined by several factors.

• Rdson (Internal P-channel Resistance)
• Diode conduction losses
• Inductor Conduction losses
- Switching losses

Rdson losses are caused by the current flowing through the high side P-channel MOSFET. The amount of power loss can be approximated by;

$$ P _ {S W} = R _ {D S O N} \times I _ {O U T} ^ {2} \times D $$

Where D is the duty cycle.

Since the MIC4742 uses an internal P-channel MOSFET, Rdson losses are inversely proportional to supply voltage. Higher supply voltage yields a higher gate to source voltage, reducing the Rdson, reducing the MOSFET conduction losses. A graph showing typical Rdson vs input supply voltage can be found in the typical characteristics section of this datasheet.

Diode conduction losses occur due to the forward voltage drop ( V_F ) and the output current. Diode power losses can be approximated as follows;

$$ \text { OUTFD } (- \text { D }) \text { HVP } $$

For this reason, the Schottky diode is the rectifier of choice. Using the lowest forward voltage drop will help reduce diode conduction losses, and improve efficiency.

Duty cycle, or the ratio of output voltage to input voltage, determines whether the dominant factor in conduction losses will be the internal MOSFET or the Schottky diode. Higher duty cycles place the power losses on the high side switch, and lower duty cycles place the power losses on the Schottky diode.

Inductor conduction losses ( P_L ) can be calculated by multiplying the DC resistance (DCR) times the square of the output current;

$$ P _ {L} = D C R \times I _ {O U T} ^ {2} $$

Also, be aware that there are additional core losses associated with switching current in an inductor. Since most inductor manufacturers do not give data on the type of material used, approximating core losses becomes very difficult, so verify inductor temperature rise.

Switching losses occur twice each cycle, when the switch turns on and when the switch turns off. This is caused by a non-ideal world where switching transitions are not instantaneous, and neither are currents. Figure 6 demonstrates how switching losses due to the transitions dissipate power in the switch.

Figure 6. Switching Transition Losses

Normally, when the switch is on, the voltage across the switch is low (virtually zero) and the current through the switch is high. This equates to low power dissipation. When the switch is off, voltage across the switch is high and the current is zero, again with power dissipation being low. During the transitions, the voltage across the switch ( V_S-D ) and the current through the switch ( I_S-D ) are at middle, causing the transition to be the highest instantaneous power point. During continuous mode, these losses are the highest. Also, with higher load currents, these losses are higher. For discontinuous operation, the transition losses only occur during the “off” transition since the “on” transitions there is no current flow through the inductor.

Component Selection

Input Capacitor

A 10 F ceramic is recommended on each VIN pin for bypassing. X5R or X7R dielectrics are recommended for the input capacitor. Y5V dielectrics lose most of their capacitance over temperature and are therefore, not recommended. Also, tantalum and electrolytic capacitors alone are not recommended due to their reduced RMS current handling, reliability, and ESR increases.

An additional 0.1 F is recommended close to the VIN and PGND pins for high frequency filtering. Smaller case size capacitors are recommended due to their lower ESR and ESL. Please refer to layout recommendation for proper layout of the input capacitor.

Output Capacitor

The MIC4742 is designed for a 4.7 F output capacitor. X5R or X7R dielectrics are recommended for the output capacitor. Y5V dielectrics lose most of their capacitance over temperature and are therefore not recommended.

In addition to a 4.7 F , a small 0.1 F is recommended close to the load for high frequency filtering. Smaller case size capacitors are recommended due to there lower equivalent series ESR and ESL.

The MIC4742 utilizes type III voltage mode internal compensation and utilizes an internal zero to compensate for the double pole roll off of the LC filter. For this reason, larger output capacitors can create instabilities. In cases where a 4.7 F output capacitor is not sufficient, other values of capacitance can be used but the original LC filter pole frequency determined by C_OUT = 4.7 F and L = 1 H (which is approximately 73.4KHz) must remain fixed. Increasing C_OUT forces L to decrease and vice versa.

Inductor Selection

The MIC4742 is designed for use with a 1μH inductor. Proper selection should ensure the inductor can handle the maximum average and peak currents required by the load. Maximum current ratings of the inductor are generally given in two methods; permissible DC current and saturation current. Permissible DC current can be rated either for a 40°C temperature rise or a 10% to 20% loss in inductance. Ensure the inductor selected can handle the maximum operating current. When saturation current is specified, make sure that there is enough margin that the peak current will not saturate the inductor.

Diode Selection

Since the MIC4742 is non-synchronous, a free-wheeling diode is required for proper operation. A Schottky diode is recommended due to the low forward voltage drop and their fast reverse recovery time. The diode should be rated to be able to handle the average output current. Also, the reverse voltage rating of the diode should exceed the maximum input voltage. The lower the forward voltage drop of the diode the better the efficiency. Please refer to the layout recommendation to minimize switching noise.

Feedback Resistors

The feedback resistor set the output voltage by dividing down the output and sending it to the feedback pin. The feedback voltage is 0.6V. Calculating the set output voltage is as follows;

$$ V _ {F B O U T} \left(\frac {R 1}{R 2} + =\right) 1 $$

Where R1 is the resistor from V_OUT to FB and R2 is the resistor from FB to GND. The recommended feedback resistor values for common output voltages are available in the bill of materials on page 17. Although the range of resistance for the FB resistors is very wide, R1 is recommended to be 10K. This minimizes the effect the parasitic capacitance of the FB node.

Feedforward Capacitor ( C_FF )

A capacitor across the resistor from the output to the feedback pin (R1) is recommended for most designs. This capacitor can give a boost to phase margin and increase the bandwidth for transient response. Also, large values of feedforward capacitance can slow down the turn-on characteristics, reducing inrush current. For maximum phase boost, C_FF can be calculated as follows;

$$ C _ {F F} = \frac {1}{\pi \times \quad \times R 1 2 0 0 k H z 2} $$

Large values of feedforward capacitance may introduce negative FB pin voltage during load shorting, which will cause latch-off. In that case, a Schottky diode from FB pin to the ground is recommended.

Bias Filter

A small 10Ω resistor is recommended from the input supply to the bias pin along with a small 0.1μF ceramic capacitor from bias to ground. This will bypass the high frequency noise generated by the violent switching of high currents from reaching the internal reference and control circuitry. Tantalum and electrolytic capacitors are not recommended for the bias, these types of capacitors lose their ability to filter at high frequencies.

Loop Stability and Bode Analysis

Bode analysis is an excellent way to measure small signal stability and loop response in power supply designs. Bode analysis monitors gain and phase of a control loop. This is done by breaking the feedback loop and injecting a signal into the feedback node and comparing the injected signal to the output signal of the control loop. This will require a network analyzer to sweep the frequency and compare the injected signal to the output signal. The most common method of injection is the use of transformer. Figure 7 demonstrates how a transformer is used to inject a signal into the feedback network.

Output 50Ω Feedback Network Analyzer "A" Input Network Analyzer Source Network Analyzer "R" Input

Figure 7. Transformer Injection

A 50Ω resistor allows impedance matching from the network analyzer source. This method allows the DC loop to maintain regulation and allow the network analyzer to insert an AC signal on top of the DC voltage. The network analyzer will then sweep the source while monitoring A and R for an A/R measurement.

The following Bode analysis show the small signal loop stability of the MIC4742, it utilizes type III compensation. This is a dominant low frequency pole, followed by 2 zeros and finally the double pole of the inductor capacitor filter, creating a final 20dB/decade roll off. Bode analysis gives us a few important data points; speed of response (Gain Bandwidth or GBW) and loop stability. Loop speed or GBW determines the response time to a load transient. Faster response times yield smaller voltage deviations to load steps.

Instability in a control loop occurs when there is gain and positive feedback. Phase margin is the measure of how stable the given system is. It is measured by determining how far the phase is from crossing zero when the gain is equal to 1 (0dB).

Typically for 3.6Vin and 1.8Vout at 2A;

• Phase Margin=77.8 Degrees
- GBW=229KHz

Being that the MIC4742 is non-synchronous; the regulator only has the ability to source current. This means that the regulator has to rely on the load to be able to sink current. This causes a non-linear response at light loads. The following plot shows the effects of the pole created by the nonlinearity of the output drive during light load (discontinuous) conditions.

3.6Vin, 1.8Vout lout=0.1A;

• Phase Margin=89.9 Degrees
- GBW= 43.7kHz

Feed Forward Capacitor

The feedback resistors are a gain reduction block in the overall system response of the regulator. By placing a capacitor from the output to the feedback pin, high frequency signal can bypass the resistor divider, causing a gain increase up to unity gain.

The graph above shows the effects on the gain and phase of the system caused by feedback resistors and a feedforward capacitor. The maximum amount of phase boost achievable with a feedforward capacitor is graphed below.

By looking at the graph, phase margin can be affected to a greater degree with higher output voltages.

Ripple Measurements

To properly measure ripple on either input or output of a switching regulator, a proper ring in tip measurement is required. Standard oscilloscope probes come with a grounding clip, or a long wire with an alligator clip. Unfortunately, for high frequency measurements, this ground clip can pick-up high frequency noise and erroneously inject it into the measured output ripple.

The standard evaluation board accommodates a home made version by providing probe points for both the input and output supplies and their respective grounds. This requires the removing of the oscilloscope probe sheath and ground clip from a standard oscilloscope probe and wrapping a non-shielded bus wire around the oscilloscope probe. If there does not happen to be any non-shielded bus wire immediately available, the leads from axial resistors will work. By maintaining the shortest possible ground lengths on the oscilloscope probe, true ripple measurements can be obtained.

Technical line drawing of a mechanical component with a coiled spring and base mount (no text or symbols)

Bill of Materials

U1 MIC4742YML VIN C11 C12 C18 EN1 R14 7 VIN1 14 VIN1 11 EN1 6 VIN2 15 VIN2 2 EN2 SGND PGND2 PGND1 BIAS SW1 9 SW1 10 FB1 12 SW2 4 SW2 3 FB2 1 EP R5 C7 L1 R13* D1 C15 C16 C14 R11 R12 VOUT1 VOUT2 L2 R23* D2 C25 C26 R21 C23* C24 R22 5 8

MIC4742YML Schematic for 2A Output

Item	Part Number		Manufacturer Description	Qty
C11,C12	GRM188R60J106M	Murata^(1)	10μF Ceramic Capacitor X5R 0603 6.3V 4
C21,C22	C1608X5R0J106M	TDK^(2)
	06036D106KMAT2A	AVX^(3)
C13*,C23*	VJ0603A681KXXCW	Vishay^(4) 680pF Ceramic Capacitor NPO 0603 6.3V 2
C14,C24	VJ0603A820KXXCW	Vishay^(4) 680pF Ceramic Capacitor NPO 0603 10V 2
C15,C25	GRM188R60J475K	Murata^(1)	4.7μF Ceramic Capacitor X5R 0603 6.3V 2
	C1608 X5R0J475M TDK	^(2)
	0603D475MAT	AVX^(3)
C16,C26,C7	VJ0603Y104KXXAT	Vishay^(4) 0.1μF Ceramic Capacitor X7R 0603 25V 5
C18,C28
D1,D2	SS2P3L	Vishay^(4)	2A Schottky 30V 2
	SSA23L	Vishay^(4)
	B230A	Diodes^(5)
L1,L2	IHLP2525AH-01 1R0 Vishay	^(4) 1μH	Inductor 17.5mΩ 6.86mm(L) x 6.47mm(W) x 1.8mm(H)	2
	RLF7030-1R0 N	TDK^(2)	1μH Inductor 8.8mΩ 7.3mm(L) x 6.8mm(W) x 3.2mm(H)
	HCP0703-1R0	COOPER^(6)	1μH Inductor 10mΩ 7.3mm(L) x 7.0mm(W) x 3.0mm(H)
R11,R12	CRCW060310K0FKXX	Vishay^(4)	10KΩ1% 0603 resistor	2
R12,R22	CRCW06033K16FKXX	Vishay^(4)	3.16kΩ 1% 0603 For 2.5 V_OUT	2
	CRCW06034K99FKXX		4.99kΩ 1% 0603 For 1.8 V_OUT
	CRCW06036K65FKXX		6.65kΩ 1% 0603 For 1.5 V_OUT
	CRCW060310K0FKXX		10kΩ 1% 0603 For 1.2 V_OUT
	CRCW060315K0FKXX		15kΩ 1% 0603 For 1.0 V_OUT

* only for ultra-low noise applications.

Item	Part Number		Manufacturer Description	Qty
R13*, R23* CRCW06032R70FKXX Vishay		(4)	2.7Ω1% 0603 resistor 2
R14, R24 CRCW060349K9FKXX Vishay		(4)	49.9kΩ1% 0603 resistor 2
R5	CRCW060310R0FKXX	Vishay	10Ω1% 0603 resistor 1
U1	MIC4742YML	Micrel, Inc.(7) Dual 2A 2MHz Integrated Switch Buck Regulator		1

Notes:

1. Murata: www.murata.com
2. TDK: www.tdk.com
3. AVX: www.avx.com
4. Vishay: www.vishay.com
5. Cooper: www.cooperbussmann.com
6. Diode: www.diodes.com
7. Micrel, Inc: www.micrel.com
   * only for ultra-low noise applications.

MIC4742YML Layout Recommendation: 2A Evaluation Board

graph TD
    A["EN2"] --> B["L2"]
    B --> C["SW2"]
    C --> D["Cin2"]
    C --> E["Cin1"]
    C --> F["D1"]
    F --> G["Snubber 1"]
    G --> H["PGND1"]
    H --> I["SNubber 2"]
    I --> J["PGND2"]
    J --> K["Cout2"]
    K --> L["SW1"]
    L --> M["Cin2"]
    L --> N["Cin1"]
    M --> O["SNubber 1"]
    N --> P["Cout1"]
    P --> Q["PGND1"]
    Q --> R["SNubber 2"]
    R --> S["PGND2"]
    S --> T["SNubber 2"]
    T --> U["PGND2"]
    U --> V["SNubber 2"]
    V --> W["PGND2"]
    W --> X["SNubber 2"]
    X --> Y["PGND2"]
    Y --> Z["SNubber 2"]
    Z --> AA["PGND2"]
    AA --> AB["SNubber 2"]
    AB --> AC["PGND2"]
    AC --> AD["SNubber 2"]
    AD --> AE["PGND2"]
    AE --> AF["SNubber 2"]
    AF --> AG["PGND2"]
    AG --> AH["SNubber 2"]
    AH --> AI["PGND2"]
    AI --> AJ["SNubber 2"]
    AJ --> AK["PGND2"]
    AK --> AL["SNubber 2"]
    AL --> AM["PGND2"]
    AM --> AN["SNubber 2"]
    AN --> AO["PGND2"]
    AO --> AP["SNubber 2"]
    AP --> AQ["PGND2"]
    AQ --> AR["SNubber 2"]
    AR --> AS["PGND2"]
    AS --> AT["SNubber 2"]
    AT --> AU["PGND2"]
    AU --> AV["SNubber 2"]
    AV --> AW["PGND2"]
    AW --> AX["SNubber 2"]
    AX --> AY["PGND2"]
    AY --> AZ["SNubber 2"]
    AZ --> BA["PGND2"]
    BA --> BB["SNubber 2"]
    BB --> BC["PGND2"]
    BC --> BD["SNubber 2"]
    BD --> BE["PGND2"]
    BE --> BF["SNubber 2"]

Recommended TOP Layout

graph TD
    A["FB1"] --> B["Rfb1_1"]
    B --> C["Rfb1_2"]
    C --> D["Rfb2_1"]
    D --> E["FB2"]
    style A fill:#f9f,stroke:#333
    style B fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style D fill:#f9f,stroke:#333
    style E fill:#f9f,stroke:#333
    note right of A: Route FB trace away from switching node

Recommended Bottom Layout

Abstract geometric pattern with scattered white circles and squares on a gray background (no text or symbols)

Recommended Mid-Layer 1 Layout

Abstract geometric pattern with white squares and circular elements on gray background (no text or symbols)

Recommended Mid-Layer 2 Layout

Package Information

PIN 1 DOT BY MARKING 3.000±0.050 1 2 3.000±0.050

TOP VIEW

PIN #1 IDENTIFICATION CHAMFER 0.300 x 45° 1.550±0.050 Exp.DAP 0.400±0.050 1 2 1.550±0.050 Exp.DAP 0.500 BSC 0.230±0.050 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.05 C SEATING PLANE 0.000-0.050 0.203±0.025

SIDE VIEW

NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS.

1. MAX. PACKAGE WARPAGE IS 0.05 mm.

2. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.

3. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

APPLIED ONLY FOR TERMINALS.

APPLIED FOR EXPOSED PAD AND TERMINALS.

16-Pin 3mm x 3mm MLF ^® (ML)

D N e E1 E E PIN 1 ID MARK 1 2 3

TOP VIEW

X Y

EXPOSED PAD

DETAIL 'A' B B

0.25 GAUGE PLANE R B1 SEATING PLANE B1 L L1 DETAIL 'A'

A2 A SEATING PLANE A1 b

END VIEW

BOTTOM VIEW

SYMBOL	14L TSSOPThermally Enhanced			16L TSSOPThermally Enhanced
	MIN	NOM.	MAX	MIN	NOM.	MAX
A	—	—	1.20	—	—	1.20
A1	0.025	—	0.100	0.025	—	0.100
A2	0.80	0.90	1.05	0.80	0.90	1.05
D	4.9	5.0	5.1	4.9	5.0	5.1
E1	4.3	4.4	4.5	4.3	4.4	4.5
E	6.2	6.4	6.6	6.2	6.4	6.6
L	0.45	0.60	0.75	0.45	0.60	0.75
R	0.09	—	—	0.09	—	—
R1	0.09	—	—	0.09	—	—
b	0.19	—	0.30	0.19	—	0.30
b1	0.19	0.22	0.25	0.19	0.22	0.25
c	0.09	—	0.20	0.09	—	0.20
c1	0.09	—	0.16	0.09	—	0.16
01	0°	—	8°	0°	—	8°
L1	1.0 REF			1.0 REF
e	0.65 BSC			0.65 BSC
N	14			16
Ref.	Jedec MO-153 Issue CVariation ABI-1			Jedec MO-153 Issue CVariation ABI
EP Area	Pad Size	X	Y	Pad Size	X	Y
	Up 1	2.997	3.200	Up 1	2.997	2.997

Notes

1. All DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1982.
   DIMENSION 'D' DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
   DIMENSION 'EI' DOES NOT INCLUDE INTERNAL FLASH OR PROTRUSION
   DIMENSION 'b' DOES NOT INCLUDE DAMBAR PROTRUSION.
   *N' IS THE MAXIMUM NUMBER OF LEAD TERMINAL POSITIONS FOR THE SPECIFIED PACKAGE LENGTH.
   △ CROSS SECTION B-B TO BE DETERMINED AT 0.10 TO 0.25MM FROM THE LEAD TIP.
3. EXPOSED PAD WILL BE DEPEND ON THE PAD SIZE OF THE L/F.

16-Pin ETSSOP

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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