SY55858U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY55858U Microchip

■ Guaranteed AC parameters over temperature:
- f_MAX > 3.0GHz (3Gbps)
• t_r/t_f < 120ps
- Within-device skew < 25ps
■ Non-blocking "switch architecture"
■ Configurable as dual 2:1 mux, dual 1:2 fanout buffer, 1:4 fanout buffer, quad buffer, or dual 2 x 2 switch
■ 50Ω compatible outputs
■ Unique input termination and V_T pin for DC-coupled and AC-coupled input signals—CML or PECL
■ Fully differential inputs/outputs
■ TTL/CMOS compatible control logic
■ Wide supply voltage range: 2.3V to 3.6V
■ Wide operating temperature range: -40^ to +85^
■ Available in 32-pin EPAD-TQFP package

SuperLite™

DESCRIPTION

The SY55858U is a low-voltage, high-speed dual 2 x 2 crosspoint switch with a flexible input that accepts CML or PECL, and a 50Ω compatible differential CML (current-mode logic) output. The non-blocking design allows any input to connect to any output. Varying the state of the select inputs allows SY55858U to be used in backup, fault tolerant, protection and backplane distribution applications.

The signal inputs (DA 0-1 and DB 0-1 ) have a unique internal termination design that allows access to the termination network through V _T pins. This feature allows the device to easily interface to other logic standards such as AC-coupled or DC-coupled PECL/LVPECL signals. For applications that require a single-channel 2 x 2 crosspoint, consider the SY55854.

APPLICATIONS

■ SONET/SDH optical transport
■ Backplane redundancy
■ Add-drop Multiplexers

PACKAGE/ORDERING INFORMATION

Top View EPAD-TQFP H32-1

32-Pin EPAD-TQFP (H321)

Ordering Information ^(1)

Part Number Type Range	Package Marking	Operating Package Finish	Package Lead
SY55858UHI H32-1	Industrial SY5	55858UHI Sn-Pb
SY55858UHITR(2)	H32-1	Industrial SY55	858UHI Sn-Pb
SY55858UHG(3)	H32-1	Industrial SY55	858UHG with Pb-FreePb-Free bar-line indicator	NiPdAu
SY55858UHGTR(2, 3)	H32-1	Industrial SY55	858UHG with Pb-FreePb-Free bar-line indicator	NiPdAu

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A=25^ , DC Electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.

TRUTH TABLES

SELA0	SELA1	QA0	QA1	Function
0	0	DA0	DA0	Fanout Buffer or Redundant Distribution
0	1	DA0	DA1	Dual Buffer or Crosspoint
1	0	DA1	DA0	Dual Buffer or Crosspoint
1	1	DA1	DA1	Fanout Buffer or Redundant Distribution

Table 1. Input to Output Connectivity Crosspoint A

SELB0	SELB1	QB0	QB1	Function
0	0	DB0	DB0	Fanout Buffer or Redundant Distribution
0	1	DB0	DB1	Dual Buffer or Crosspoint
1	0	DB1	DB0	Dual Buffer or Crosspoint
1	1	DB1	DB1	Fanout Buffer or Redundant Distribution

Table 2. Input to Output Connectivity Crosspoint B

PIN DESCRIPTION

Pin Number Pin Name Pin Function
1 DB1 Channel B1 positive signal input.
2 VTB1 Channel B1 termination center-tap.		For CML inputs, leave this pin floating.Otherwise, see Figures 5a–5d in “Input Interface Application” section.
3 /DB1 Channel B1 negative signal input.
4 SELB0 Channel B0 output select. TTL/CMOS input.
5 DB0 Channel B0 positive signal input.
6 VTB0 Channel B0 termination center-tap.		For CML inputs, leave this pin floating.Otherwise, see Figures 5a–5d in “Input Interface Application” section.
7 /DB0 Channel B0 negative signal input.
8 SELB1 Channel B1 output select. TTL/CMOS input.
9, 24 GND Supply Ground.
10, 13, 16, 17, 20, 23 VCC Positive supply normally bypass each pin with 0.1 × F//0.01 × F low ESR capacitors.		connect to 2.5V, 3.3V, or 5V nominal supply, and 0.1 × F//0.01 × F low ESR capacitors.
11 /QB0 Channel B0 negative signal output.		50 CML.
12 QB0 Channel B0 positive signal output.		50 CML.
14 /QB1 Channel B1 negative signal output.		50 CML.
15 QB1 Channel B1 positive signal output.		50 CML.
18 /QA1 Channel A1 negative signal output.		50 CML.
19 QA1 Channel A1 positive signal output.		50 CML.
21 /QA0 Channel A0 negative signal output.		50 CML.
22 QA0 Channel A0 positive signal output.		50 CML.
25 DA0 Channel A0 positive signal input.
26 VTA0 Channel A0 termination center-tap.		For CML inputs, leave this pin floating.Otherwise, see Figures 5a–5d in “Input Interface Application” section.
27 /DA0 Channel A0 negative signal input.
28	SELA1 Channel A1 output select. TTL/CMOS input.
29 DA1 Channel A1 positive signal input.
30 VTA1 Channel A1 termination center-tap.		For CML inputs, leave this pin floating.Otherwise, see Figures 5a–5d in “Input Interface Application” section.
31 /DA1 Channel A1 negative signal input.
32	SELA0 Channel A1 output select. TTL/CMOS input.

FUNCTIONAL BLOCK DIAGRAM

graph TD
    DA0["DA0"] --> A0["50Ω"]
    VTA0["VTA0"] --> A0
    /DA0["/DA0"] --> A0
    SELA0["SELA0"] --> A0
    DA1["DA1"] --> A1["50Ω"]
    VTA1["VTA1"] --> A1
    /DA1["/DA1"] --> A1
    SELA1["SELA1"] --> A1
    A0 --> 0A0["0A0\n1"]
    0A0 --> CML1["CML"]
    0A1 --> 0A1a["0A1\n1"]
    0A1a --> CML2["CML"]
    CML1 --> QA0["QA0"]
    CML2 --> QA1["QA1"]
    style 0A0 fill:#f9f,stroke:#333
    style 0A1a fill:#ccf,stroke:#333
    style 0A1b fill:#cfc,stroke:#333
    style 0A1c fill:#fcc,stroke:#333
    style 0A1d fill:#ffc,stroke:#333
    style 0A1e fill:#cfc,stroke:#333
    style 0A1f fill:#fcc,stroke:#333
    style 0A1g fill:#ffc,stroke:#333
    style 0A2a fill:#cfc,stroke:#333
    style 0A2b fill:#fcc,stroke:#333
    style 0A2c fill:#ffc,stroke:#333
    style 0A2d fill:#cfc,stroke:#333

graph TD
    A["DB0"] --> B["50Ω"]
    C["V_TB0"] --> B
    D["/DB0"] --> B
    E["SELB0"] --> F["0"]
    G["DB1"] --> H["50Ω"]
    I["V_TB1"] --> H
    J["/DB1"] --> H
    K["SELB1"] --> L["0"]
    M["0"] --> N["B0"]
    O["1"] --> P["B1"]
    Q["CML"] --> R["QB0"]
    S["CML"] --> T["QB1"]
    U["CML"] --> V["QB1"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style D fill:#f9f,stroke:#333
    style E fill:#f9f,stroke:#333
    style G fill:#f9f,stroke:#333
    style I fill:#f9f,stroke:#333
    style K fill:#f9f,stroke:#333
    style M fill:#f9f,stroke:#333
    style U fill:#f9f,stroke:#333
    style N fill:#ccf,stroke:#333
    style P fill:#ccf,stroke:#333
    style Q fill:#ccf,stroke:#333
    style S fill:#ccf,stroke:#333
    style U fill:#ccf,stroke:#333

INPUT AND OUTPUT STAGE

VCC D0 50Ω 1.2mA VT+ 50Ω /D0 1.2mA SY55858U

Figure 1. Input Stage

Vcc 50Ω 50Ω Q /Q 16mA SY55858U

Figure 2. Output Stage
Note 1. See "Input Interface Applications" section for proper input connection.

ABSOLUTE MAXIMUM RATINGS ^(1)

Symbol	Rating	Value	Unit
V_CC	Power Supply Voltage	-0.5 to +6.0	V
V_IN	Input Voltage	-0.5 to V_CC +0.5 V
V_OUT	CML Output Voltage	V_CC -1.0 to V_CC +0.5	V
T_A	Operating Temperature Range	-40 to +85	°C
T_LEAD	Lead Temperature (soldering, 20sec.)	260	°C
T_store	Storage Temperature Range	-65 to +150	°C
_JA	Package Thermal Resistance(Junction-to-Ambient)–Still-Air (multi-layer PCB)–500Ifpm (multi-layer PCB)	2820	°C/W°C/W
_JC	Package Thermal Resistance(Junction-to-Case)	4	°C/W

Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

Symbol	Parameter Min. Typ. Max. Unit Condition
V_CC	Power Supply Voltage 2.3 — 3.6 V
I_CC	Power Supply Current — 150 190 mA No load, over temp.

TTL CONTROL ELECTRICAL CHARACTERISTICS
V_CC = 2.3V to 3.6V ; GND = 0V; T_A = -40^ C to +85^ C^(2)

Symbol	Parameter Min. Typ. Max. Unit Condition
V_IH	Input HIGH Voltage 2.0 —	—	V
V_IL	Input LOW Voltage	—	—	0.8	V
I_IH	Input HIGH Current	—	—	+20	A	V_IN = 2.7V, V_CC = Max. V_IN = V_CC, V_CC = Max.
		—	—	+100	A
I_IL	Input LOW Current	-300	—	—	A	V_IN = 0.5V, V_CC = Max.

Note 2. Specifications are guaranteed after thermal equilibrium has been established.

CML DC ELECTRICAL CHARACTERISTICS
V_CC=2.3V to 3.6V; GND = 0V; T_A=-40^ to +85^^(3)

Symbol	Parameter	Min.	Typ.	Max.	Unit	Condition
V_ID	Differential Input Voltage	100	—	—	mV
R_IN	Differential Input Resistance D-to-/D	90	100	110	Ω
V_IH	Input HIGH Voltage	1.6	—	V_CC	V
V_IL	Input LOW Voltage	1.5	—	V_CC-0.1	V
V_OH	Output HIGH Voltage	V_CC-0.040	V_CC-0.010	V_CC	V	No Load
V_OL	Output LOW Voltage V	_CC-1.00	V_CC-0.800	V_CC-0.650	V	No Load
V_OUT(SWING)	Output Voltage Swing(4)	0.650—	0.8000.400	1.00—	V	No Load50Ω Environment
R_OUT	Output Source Impedance	40	50	60	Ω

Note 3. Device is guaranteed to meet the DC specifications, shown in the table above, after thermal equilibrium has been established. The device is tested in a socket such that traverse airflow ≥ 500lfpm is maintained.
Note 4. V_OUT(SWING) is defined as the swing on one output of a differential pair, that is |V_OH - V_OL| on one pin. The swing for common mode immunity purposes is 2 · V_OUT(SWING) . Actual voltage levels and differential swing will depend on customer termination scheme. Typically, a 400mV swing is available in the 50Ω environment. Refer to the "CML Output Termination Application" section, Figures 3 and 4, for more details.

AC ELECTRICAL CHARACTERISTICS
V_CC=2.3V to 3.6V; GND = 0V; T_A=-40^ to +85^^(5)

Symbol	Parameter Min. Typ. Max. Unit	Condition
f_MAX	Maximum FrequencyNRZ Data Rate 3	.0 —	—	Gbps
	Clock Frequency^(6)	3.0 —	—	GHz
t_PLH t_PHL	Differential Propagation Delay D-to-Q	220 350 450 ps
t_SWITCH	Select-to-Valid Output^(7)	— 0.50 1.0 ns
t_SKEW	Within-Device Skew^(8)	—	12	25	ps
	Within-Device Skew^(9)	—	25	50	ps
	Part-to-Part Skew (Diff.)	—	100	—
R_J	Random Jitter	—	2	5	ps_RMS
D_J	Deterministic Jitter	—	5	20	ps_PP
t_r, t_f	CML Output Rise/Fall Times (20% to 80%)	—	80	120	ps

Note 5. Tested using environment of Figure 3, 50 equivalent load. AC parameters are guaranteed by design and characterization.
Note 6. f_MAX clock is defined as the maximum toggle rate the device can operate while still achieving a 250mV minimum CML output swing, 50Ω equivalent load.
Note 7. Input TTL/CMOS edge rate of <1.5ns.
Note 8. Worst-case difference between QA0 and QA1 from either DA0 or DA1 (or between QB0 and QB1 from either DB0 or DB1 respectively), when both outputs come from the same input.
Note 9. Worst-case difference between QA and QB outputs, when DA or DB inputs are shorted.

CML OUTPUT TERMINATION APPLICATION

All CML inputs accept a CML output from any other member of this family. All CML outputs are source terminated

50Ω differential drivers as shown in Figure 3.

Vcc 50Ω 50Ω 16mA SY55858U 50Ω 100Ω 50Ω

Figure 3. 50Ω Output Termination

Figure 4. Output Levels

INPUT INTERFACE APPLICATIONS

VCC CML D /D NC □ VT SY55858 VCC

Figure 5a. CML-to-CML (DC-Coupled) Input Interface

Vcc CML D /D SY55858 VT Vcc - 1.3V

Figure 5b. CML-to-CML (AC-Coupled) Input Interface

VCC PECL D /D SY55858 VT VCC - 2.0V

Figure 5c. PECL-to-CML (DC-Coupled) Input Interface

Vcc PECL 220Ω220Ω D /D SY55858 VT Vcc - 1.3V Vcc

Figure 5d. PECL-to-CML (AC-Coupled) Input Interface

32 -PIN EPAD-TQFP (DIE UP) (H32-1)

1. DIMENSION DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS, EITHER OF WHICH SHALL NOT EXCEED 0.254 [0.010]
2. LEAD DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION.
3. MAXIMUM AND MINIMUM SPECIFICATIONS ARE INDICATED AS FOLLOWS: MAX/MIN.
   G. THESE DIMENSIONS TO BE DETERMINED AT DATUM PLANE -H-
4. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG BOTTOM OF PACKAGE.
5. EXPOSED PAD SHALL BE COPLANAR WITH PACKAGE BOTTOM WITHIN 0.05mm EXPOSED PAD Cu WITH Sn/Pb PLATING
   9 DIMENSION INCLUDES LEAD FINISH.

Rev. 01

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