SY56017R - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY56017R Microchip

Low Voltage 1.2V/1.8V/2.5V CML 2:1 MUX 6.4 Gbps with Equalization

Features

• 1.2V/1.8V/2.5V CML 2:1 MUX
• Equalizes 9, 18, 27 inches of FR4
- Guaranteed AC Performance over Temperature and Voltage:

• DC-to >6.4 Gbps Throughput
• DC-to >4.5 GHz Clock Throughput
• <280 ps Propagation Delay (IN-to-Q)
• <20 ps Input Skew
• <80 ps Rise/Fall Times

- Ultra-Low Jitter Design

- 1 ps RMS Cycle-to-Cycle Jitter

• High-Speed CML Outputs

- 2.5V ±5% V CC , 1.2/1.8V/2.5V ±5% V CCO Power Supply Operation

- Industrial Temperature Range: -40^ to +85^

• Available In 16-Lead (3 mm x 3 mm) QFN Package

Applications

• Data Distribution
  • SONET Clock and Data Distribution
  • Fibre Channel Clock and Data Distribution
  • Gigabit Ethernet Clock And Data Distribution

Markets

• Storage
• ATE
  • Test and Measurement
• Enterprise Networking Equipment
  • High-End Servers
  • Metro Area Network Equipment

General Description

The SY56017R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 2:1 MUX with input equalization. The SY56017R can process clock signals as fast as 4.5 GHz or data patterns up to 6.4 Gbps.

The differential input includes Microchip's unique, 3-pin input termination architecture that interfaces to CML differential signals, without any level-shifting or termination resistor networks in the signal path. The differential input can also accept AC-coupled LVPECL and LVDS signals. Input voltages as small as 200 mV (400 mV _PP ) are applied before the 9", 18", or 27" FR4 transmission line. For AC-coupled input interface applications, an internal voltage reference is provided to bias the VT pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 80 ps.

The SY56017R operates from a 2.5V ±5% core supply and a 1.2V, 1.8V, or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range ( -40^ to +85^ ). The SY56017R is part of Microchip's high-speed, Precision Edge ^® product line.

Package Type

SY56017R 3mm x 3 mm QFN-16 (M) (Top View) IN0 SEL GND VCCO /IN0 1 16 15 14 13 VT0 2 NC VT1 3 11 Q IN1 4 10 /Q /IN1 EQ VCC VCCO NC 9

Functional Block Diagram

graph TD
    A["IN0"] --> B["50Ω"]
    C["VT0"] --> D["50Ω"]
    E["/IN0"] --> F["EQUALIZATION"]
    G["IN1"] --> H["50Ω"]
    I["VT1"] --> J["50Ω"]
    K["/IN1"] --> L["EQUALIZATION"]
    M["EQ (3 level input)"] --> N["S"]
    O["SEL (TTL/CMOS)"] --> P["0"]
    Q["MUX"] --> R["1"]
    S["Q"] --> T["Output"]
    U["/Q"] --> V["Output"]

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltage ( V_CC )....-0.5V to +3.0V

Supply Voltage ( V_CCO )....-0.5V to +3.0V

V_CC-V_CCO <1.8V

V_CCO-V_CC <0.5V

Input Voltage ( V_IN ) -0.5V to V_CC

CML Output Voltage ( V_OUT )....+0.6V to +3.0V

Current (I_T)

Source or Sink on VT Pin....±100 mA

Input Current

Source or Sink Current on, IN, /IN....±50 mA

Operating Ratings ††

Supply Voltage ( V_CC )....+2.375V to +2.625V

Supply Voltage ( V_CCO )....+1.14V to +2.625V

† Notice: Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

†† Notice: The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: T_A = -40^ to +85^ , unless otherwise stated. Note 1

Parameters Sym.	Min. Typ. Max. Units Conditions
Power Supply Voltage Range	V_CC	2.375 2.5 2.625			V	V_CC
		1.14 1.2 1.26 V				cc0
		1.7 1.8 1.9 V				cc0
		2.375 2.5 2.625 V				cc0
Power Supply Current	I_CC	—	55	80	mA	Max. V_CC
Power Supply Current I	cc0	—	16	21	mA	No load, V_CCO
Input Resistance (IN-to-VT, /IN-to-VT)	R_IN	45	50	55	Ω	—
Differential Input Resistance (IN-to-/IN)	R_DIFF\_IN	90	100	110	Ω	—
Input HIGH Voltage (IN, /IN)	V_IH	1.42	— V	cc	V	IN, /IN
Input LOW Voltage (IN, /IN)	V_IL	1.22	—	V_IH-0.2	V	IN, /IN, 1.22V = 1.7 - 0.475
Input Voltage Swing (IN, /IN)	V_IN	0.2	—	1.0	V	See Figure 3-4, (Note 2) applied to input of transmission line.
Differential Input Voltage Swing (|IN - /IN|)	V_DIFF\_IN	0.4	—	2.0	V	See Figure 3-5, (Note 2) applied to input of transmission line.
Voltage from Input to VT	V_T-IN	—	—	1.28	V	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
2: V_IN(MAX) is specified when VT is floating.

CML OUTPUTS DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CCO = 1.14V to 1.26V R_L = 50 to V_CCO , V_CCO = 1.7V to 1.9V , 2.375V to 2.625V , R_L = 50 to V_CCO or 100 across the outputs, V_CC = 2.375V to 2.625V ; T_A = -40^ to +85^ , unless otherwise stated. (Note 1)

Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
Output High Voltage	V_OH	V_CC - 0.02	V_CC - 0.01	V_CC	V	R_L = 50 to V_CCO
Output Voltage Swing	V_OUT	300	390	475	mV	See Figure 3-4
Differential Output Voltage Swing	V_DIFF\_OUT	600	780	950	mV	See Figure 3-5
Output Source Impedance	R_OUT	45	50	55	Ω	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CC = 2.375V to 2.625V; T_A = -40^ to +85°C, unless otherwise stated. (Note 1)

Parameter Symbol	Min. Typ.	Max. Units	Condition
Input HIGH Voltage V	IH	2.0 — V		cc	V	—
Input LOW Voltage V	IL	— — 0	8 V —
Input HIGH Current I	IH	-125	—	30	μA	—
Input LOW Current	IIL	-300	—	— μA	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

THREE LEVEL EQ INPUT DC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CC = 2.375V to 2.625V; T_A = -40^ to +85°C, unless otherwise stated. (Note 1)

Parameter Symbol	Min.	Typ. Max.	Units	Condition
Input HIGH Voltage V	IH	V_CC - 0.3 — V		CC	V	—
Input LOW Voltage V	IL	0	—	V_EE + 0.3	V —
Input HIGH Current I	IH	—	—	400	μA	V_IH = V_CC
Input LOW Current	I_IL	-480	—	—	μA	V_IL = GND

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_CCO = 1.14V to 1.26V R_L = 50 to V_CCO , V_CCO = 1.7V to 1.9V , 2.375V to 2.625V , R_L = 50 to V_CCO or 100 across the outputs, V_CC = 2.375V to 2.625V ; T_A = -40^ to +85^ , unless otherwise stated.

Parameter	Symbol Min.		Typ.	Max. Units		Condition
Maximum Frequency	f_MAX	6.4	—	—	Gbps	NRZ (Data)
		4.5	—	—	GHz	V_OUT ≥ 200 mV (Clock)
Propagation Delay IN-to-Q	t_PD	100	180	280	ps	Note 1, Figure 3-1
Propagation Delay SEL-to-Q		90	210	350	ps	Figure 3-1
Input-to-Input Skew	t_SKEW	—	—	20	ps	Note 2
Part-to-Part Skew		—	—	100	ps	Note 3
Random Jitter	t_JITTER	—	—	1	ps_RMS	Note 4
Crosstalk Induced Jitter		—	—	0.7	ps_PP	Note 5
Output Rise/Fall Time (20% to 80%)	t_r,t_f	20 50	80	ps	At full output swing

Note 1: Propagation delay is measured with no attenuating transmission line connected to the input.
2: Input-to-Input skew is the difference in time between both inputs and the output for the same temperature, voltage and transition.
3: Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
4: Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX .
5: Crosstalk induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while applying a similar, differential clock frequencies that are asynchronous with respect to each other at the adjacent input.

TEMPERATURE SPECIFICATIONS

Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Ambient Temperature Range	T_A	-40 —	+85 °C —
Maximum Operating Junction Temperature	T_J	— —	+125 °C —
Lead Temperature — — — +260 °C Soldering, 20 sec.
Storage Temperature Range T	S	-65 —	+150 °C —
Package Thermal Resistances (Note 1)
Thermal Resistance, 3x3 QFN-16Ld	_JA	—	75	— °C/W Still-air
	_JB	—	33	— °C/W Junction-to-board

Note 1: Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

V_CC=2.5V, V_CCO=1.2V, GND=0V, V_IN=400 mV, R_L=50 to 1.2V, Data Pattern: 2^23-1, T_A=+25^ , unless otherwise stated.

Output Swing (100mv/div) TIME (50ps/div.)

FIGURE 2-1: 6.4 Gbps, 24 inch FR4.

Output Swing (100mv/div) TIME (50ps/div.)

FIGURE 2-3: 6.4 Gbps, 9 inch FR4.

Output Swing (100mv/div) TIME (50ps/div.)

FIGURE 2-2: 6.4 Gbps, 18 inch FR4.

FIGURE 2-4: 3.2 Gbps, 24 inch FR4.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin Number	Pin Name Description
16, 14, 5	IN0, /IN0IN1, /IN1	Differential Inputs: Signals as small as 200 mV V_PK (400 m V_PP ) applied to the input of 9, 18, or 27 inches 6 mm FR4 st then terminated with the differential input. Each input pin internally terminates with 50Ω to the VT pin.
2, 3	VT0, VT1	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC-coupling. For AC-coupling, bypass VT with 0.1 μF low ESR capacitor to VCC. See the Interface Applications section.
6	EQ	Three level input for equalization control. High, float, low. EQ pin applies the same EQ setting to both inputs.
15	SEL	This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25 kΩ pull-up resistor and will default to a logic HIGH state if left open.
7	VCC	Positive Power Supply: Bypass with a 0.1 μF//0.01 μF low-ESR capacitor as close to the VCC pin as possible. Supplies input and core circuitry.
8, 13	VCCO	Output Supply: Bypass with 0.1 μF//0.01 μF low-ESR capacitors as close to the VCCO pins as possible. Supplies the output buffers.
14	GND, Exposed Pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pins.
11, 10	Q, /Q	CML Differential Output Pair: Differential buffered copy of the input signal. The output swing is typically 390 mV. See the Interface Applications section for termination information.

ripline transmission line are

TABLE 3-2: TRUTH TABLE

SEL	Output
0	IN0 Input Selected
1	IN1 Input Selected

TABLE 3-3: TRUTH TABLE

EQ	Equalization
LOW	27"
FLOAT	18"
HIGH	9"

Timing Diagrams

IN0 /INO → t_pd Q /Q

SEL → t_pd ← → t_pd Q /Q

FIGURE 3-1: Propagation Delay.

Input and Output Stage

Vcc 12.5kΩ IN 50Ω VT 50Ω 33kΩ /IN GND GND

FIGURE 3-2: Simplified Differential Input Buffer.

Vcc0 50Ω50Ω /Q Q GND

FIGURE 3-3: Simplified CML Output Buffer.

Single-Ended and Differential Swings

V_IN V_OUT 400mV (Typ.)

FIGURE 3-4: Single-Ended Swing.

VDIFF_IN: VDIFF_OUT 800mV (Typ.)

FIGURE 3-5: Differential Swing.

4.0 INTERFACE APPLICATIONS

For Input Interface Applications see Figure 4-1 through Figure 4-5 and for CML Output Termination see Figure 4-6 through Figure 4-9.

4.1 Input Termination

1.8V CML driver: Terminate input with VT tied to 1.8V. Don't terminate 100Ω differentially.

2.5V CML driver: Terminate input with either VT tied to 2.5V or 100Ω differentially.

The input cannot be DC coupled from a 1.2V CML driver.

4.2 CML Output Termination with V_CCO 1.2V

For V_CCO of 1.2V, Figure 4-6, terminate the output with 50Ω to 1.2V, not 100Ω differentially across the outputs. If AC-coupling is used, Figure 4-9, terminate into 50Ω to 1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage. Any unused output pair needs to be terminated, do not leave floating.

4.3 CML Output Termination with VCCO 1.8V

For V_CCO of 1.8V or 2.5V, Figure 4-6 and Figure 4-7, terminate with either 50Ω to 1.8V or 2.5V or 100Ω differentially across the outputs. AC- or DC-coupling is fine.

Input Interface Applications

VCC (2.5V) CML IN /IN GND SY56017R NC VT

FIGURE 4-1: CML Interface (DC-Coupled, 2.5V, 100Ω Differential).

Vcc(1.8V,2.5V,3.3V) CML GND Vcc 0.1μF IN /IN VT SY56017R

FIGURE 4-3: CML Interface (AC-Coupled).

VCC (1.8V, 2.5V) CML IN /IN GND VCC (1.8V, 2.5V) VT SY56017R

FIGURE 4-2: CML Interface (DC-Coupled, 1.8V, 2.5V, 50Ω to VCC).

VCC (3.3V, 2.5V) LVPECL IN IN GND RP RP VCC 0.1μF VT For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω. SY56017R

FIGURE 4-4: LVPECL Interface (AC-Coupled).

VCC LVDS GND VCC 0.1μF IN /IN VT SY56017R

FIGURE 4-5: LVDS Interface (AC-Coupled).

CML Output Termination

VCCO (1.2V, 1.8V, 2.5V) 50Ω50Ω Q Z0 = 50Ω IN 50Ω VCCO (1.2V, 1.8V, 2.5V) Z0 = 50Ω50Ω /Q /IN GND

FIGURE 4-6: 1.2V, 1.8V, or 2.5V CML DC-Coupled Termination.

VCCO (1.8V,2.5V) 50Ω 50Ω Q Z0= 50Ω IN 50Ω VBIAS Z0= 50Ω /IN 50Ω /Q GND

FIGURE 4-8: CML AC-Coupled Termination V_CCO 1.8V or 2.5V Only.

V_{CCO} (1.8V,2.5V) 50\Omega 50\Omega Q Z_0 = 50\Omega IN 100\Omega Z_0 = 50\Omega /IN /Q GND

FIGURE 4-7: 1.8V or 2.5V CML DC-Coupled Termination.

VCCO (1.2V) 50Ω 50Ω Q Z0 = 50Ω IN 1kΩ VBias /Q Z0 = 50Ω /IN 1kΩ 50Ω 1.2V GND

FIGURE 4-9: CML AC-Coupled Termination V_CCO 1.2V Only.

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

16-Lead QFN*

m - XXXX WNNN

Example

m - R017 5971

Legend: XX...X Product code or customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

ePb-free JEDEC ^® designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( ) e3

can be found on the outer packaging for this package.

•, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark).

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo.

Underbar (_) and/or Overbar (−) symbol may not be to scale.

16-Lead QFN 3 mm x 3 mm Package Outline and Recommended Land Pattern

TITLE

16 LEAD QFN 3x3mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING #

QFN33-16LD-PL-1

UNIT MM

PIN 1 DOT BY MARKING 3,0000±0.050 1 2 3,0000±0.050

TOP VIEW NOTE: 1, 2, 3

1.5500±0.050 Exp.DAP PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 0.5000 BSC 0.2300±0.050 1.5500±0.050 Exp.DAP 1.5000 Ref.

BOTTOM VIEW NOTE 1, 2, 3

0.850±0.050 0.000-0.050 0.2030±0.025

SIDE VIEW NOTE: 1, 2, 3

NOTE:

1. MAX PACKAGE WARPAGE IS 0.05 MM

2. MAX ALLOWABLE BURR IS 0.076 MM IN ALL DIRECTIONS

3. PIN #1 IS ON TOP WILL BE LASER MARKED

4. RED CIRCLE IN LAND PATTERN INDICATE THERMAL VIA. SIZE SHOULD BE 0.30-0.35 MM

IN DIAMETER AND SHOULD BE CONNECTED TO GND FOR MAX THERMAL PERFORMANCE

1. GREEN RECTANGLES (SHADED AREA) indicate SOLDER STENCIL OPENING ON EXPOSED

PAD AREA. SIZE SHOULD BE 0.60×0.60 MM IN SIZE, 0.20 MM SPACING.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

POD-Land Pattern drawing # QFN33-16LD-PL-1

RECOMMENDED LAND PATTERN NOTE: 4, 5

Symmetrical geometric diagram with green hatched squares and a central crosshair (no text or symbols)

STACKED-UP

0.48±0.02 0.80±0.02 0.23±0.02 1.60±0.02 2.24±0.02 3.20±0.02 0.50 BSC 1.60±0.02 2.24±0.02 3.20±0.02 EXPOSED METAL TRACE

0.70±0.02 0.40±0.02 0.10±0.02 0.23±0.02 1.40±0.02 2.24±0.02 3.04±0.02 SOLDER STENCIL OPENING

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

APPENDIX A: REVISION HISTORY

Revision A (March 2020)

• Converted Micrel document SY56017R to Microchip data sheet template DS20006320A.
• Minor text changes throughout.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

PART NO. X Device Supply Voltage X Package Temperature Range XX Tape and Reel

Device:

SY56017: Low Voltage 1.2V/1.8V/2.5V CML 2:1 MUX 6.4 Gbps with Equalization

Supply Voltage: R = 2.5V

Package:

M = 3 mm x 3 mm QFN-16

Temperature Range:

G = -40^ to 85^ (NiPdAu Lead-Free)

Special Processing:

= 100/Tube TR = 1,000/Reel

Examples:

a) SY56017RMG: SY56017, 2.5V Supply

Voltage, 3 mm x 3 mm

QFN, -40^ to +85^

Temperature Range, 100/Tube

b) SY56017RMG-TR: SY56017, 2.5V Supply

Voltage, 3 mm x 3 mm

QFN, -40^ to +85^

Temperature Range, 1,000/Reel

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

16-Lead

16-Lead

NOTES:

Note the following details of the code protection feature on Microchip devices:

- Microchip products meet the specification contained in their particular Microchip Data Sheet.

- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

- Microchip is willing to work with the customer who is concerned about the integrity of their code.

- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

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All other trademarks mentioned herein are property of their respective companies.

© 2020, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-5816-6

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China - Beijing

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China - Chengdu

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China - Chongqing

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China - Dongguan

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China - Guangzhou

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China - Hangzhou

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China - Hong Kong SAR

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China - Nanjing

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China - Qingdao

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China - Shanghai

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China - Shenyang

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China - Shenzhen

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China - Suzhou

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China - Wuhan

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China - Xian

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China - Xiamen

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China - Zhuhai

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ASIA/PACIFIC

India - Bangalore

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India - New Delhi

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India - Pune

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Japan - Osaka

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Japan - Tokyo

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Korea - Daegu

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Korea - Seoul

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Malaysia - Kuala Lumpur

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Malaysia - Penang

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Philippines - Manila

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Singapore

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Taiwan - Hsin Chu

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Taiwan - Kaohsiung

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Taiwan - Taipei

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Thailand - Bangkok

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Denmark - Copenhagen

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Finland - Espoo

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France - Paris

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Germany - Garching

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Germany - Haan

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Germany - Heilbronn

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Germany - Karlsruhe

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Germany - Munich

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Germany - Rosenheim

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Israel - Ra'anana

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Italy - Milan

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Italy - Padova

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Netherlands - Drunen

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Norway - Trondheim

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Poland - Warsaw

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Romania - Bucharest

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Spain - Madrid

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Sweden - Gothenberg

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Sweden - Stockholm

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UK - Wokingham

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