SY54016R - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY54016R Microchip

The SY54016R is a fully differential, low voltage 1.2V/1.8V CML Line Driver/Receiver with Fail-Safe Input. The SY54016R can process clock signals as fast as 2.5GHz or data patterns up to 3.2Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, as small as 100mV (200mV PP ) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an internal voltage reference is provided to bias the V T pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 95ps.

The SY54016R operates from a 2.5V ±5% core supply and a 1.8V or 1.2V ±5% output supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). The SY54016R is part of Micrel's high-speed, Precision Edge® product line.

Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

IN 50Ω VT 50Ω /IN Q /Q

Precision Edge®

Features

• 1.2V/1.8V CML LineDriver/Receiver with Fail-Safe Input
  • Guaranteed AC performance over temperature and voltage:
• DC-to- > 3.2Gbps throughput
• <370ps propagation delay (IN-to-Q)
• <95ps rise/fall times
• Ultra-low jitter design
• < 1 ps_RMS random jitter
  • High-speed CML outputs
  • 2.5V ±5%, 1.8/1.2V ±5% power supply operation
  • Industrial temperature range: -40^ to +85^
  • Available in 8-pin (2mm x 2mm) MLF package

Applications

• Data Distribution: OC-48, OC-48+FEC
• SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution

Markets

• Storage
• ATE
  • Test and measurement
• Enterprise networking equipment
  • High-end servers
  • Metro area network equipment

Precision Edge is a registered trademark of Micrel, Inc.

MLF and MicroLeadFrame are registered trademarks of Amkor Technology.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY54016RMGTR(2)	MLF-8	Industrial	016R with Pb-Free bar-line indicator	NiPdAu Pb-Free

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A=25^ , DC Electricals only.
2. Tape and Reel.

Pin Configuration

VT IN /IN GND 1 2 3 4 8 VCC 7 Q 6 /Q 5 VCCO

8-Pin MLF ^® (MLF-8)

Pin Description

Pin Number	Pin Name	Pin Function
2,3	IN, /IN	Differential Input: This input pair is the differential signal input to the device. Input accepts differential signals as small as 100mV (200mVPP). Each input pin internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state.
1	VT	Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC coupling. For AC-coupling, bypass VT with 0.1μF low ESR capacitor to VCC. See “Interface Applications” subsection and Figure 2a.
8	VCC	Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCC pin as possible. Supplies input and core circuitry.
5	VCCO	Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCCO pin as possible. Supplies the output buffer.
4	GND, Exposed pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin.
7,6	Q, /Q	CML Differential Output Pair: Differential buffered copy of the input signal. The output swing is typically 390mV. See “Interface Applications” subsection for termination information.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) ..... -0.5V to +3.0V

Supply Voltage ( V_CCO ) ..... -0.5V to +2.7V

V_CC - V_CCO <1.8V

CML Output Voltage (VOUT).... 0.6V to VCCO+0.5V

Current ( V_T )

Source or sink current on VT pin ....±100mA

Input Current

Source or sink current on (IN, /IN) ....±50mA

Maximum operating Junction Temperature ..... 125°C

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_cc ).....2.375V to 2.625V

(V_CCO) 1.14V to 1.9V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3)

MLF®

Still-air (Ⅱ JA) 93°C/W

Junction-to-board ( _JB ) 56°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter Condition	Min Typ Max	Units
V_CC	Power Supply Voltage Range	V_CC	2.375	2.5	2.625	V
		V_CCO	1.14	1.2	1.26	V
		V_CCO	1.7	1.8	1.9	V
I_CC	Power Supply Current	Max. V_CC		13	19	mA
I_CCO	Power Supply Current	No Load. Max. V_CCO		16	21	mA
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		45	50		55
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.2		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	V_IL with V_IH = 1.2V	0.2		V_IH-0.1	V
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.14		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	V_IL with V_IH = 1.14V , (1.2V-5%)	0.66		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	see Figure 3a	0.1			1.0
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	see Figure 3b	0.2			2.0
V_IN\_FSI	Input Voltage Threshold that Triggers FSI			30	100	mV
V_T\_IN	Voltage from Input to V_T					1.28

Ω

V

V

V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

CML Outputs DC Electrical Characteristics ^(5)

V_CCO = 1.14V to 1.26V R_L = 50 to V_CCO.

V_CCO = 1.7V to 1.9V , R_L = 50 to V_CCO or 100 across the outputs,

V_CC = 2.375V to 2.625V . T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter Condition	Min Typ Max	Units
V_OH Output HIGH Voltage R		L = 50 to V_CCO	V_CCO-0.020	V_CCO-0.010	V_CCO	V
V_OUT Output Voltage Swing See Figure 3a 300		390 475 mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 3b	600	780	950	mV
R_OUT	Output Source Impedance		45	50	55

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics

V_CCO = 1.14V to 1.26V R_L = 50 to V_CCO,

V_CCO = 1.7V to 1.9V, R_L = 50 to V_CCO or 100 across the outputs,

V_CC = 2.375V to 2.625V . T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Frequency	NRZ Data	3.2			Gbps
		V_OUT > 200mV Clock	2.5			GHz
t_PD	Propagation Delay IN-to-Q	V_IN : 100mV-200mV, Note 6, Figure 1a	180	300	420	ps
		V_IN : >200mV, Note 6, Figure 1a	170	250	370	ps
t_Skew	Part-to-Part Skew	Note 7			75	ps
t_Jitter	Random Jitter				1	ps_RMS
t_R t_F	Output Rise/Fall Times (20% to 80%)	At full output swing.	30	60	95	ps
	Duty Cycle	Differential I/O	47		53	%

Notes:

1. Propagation delay is measured with input t_f/t_f ≤ 300ps (20% to 80%).

2. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs. V_IN > 200mV with input t / t_4 ≤ 300ps (20% to 80%).

Functional Description

Fail-Safe Input (FSI)

The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the output when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mV_PK ( 200mV_PP ), typically 30mV_PK . Maximum frequency of the SY54016R is limited by the FSI function.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low signal swing, the FSI function will eliminate a metastable condition and guarantee a stable output. No ringing and no undetermined state will occur at the output under these conditions.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal close to the FSI threshold. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Characteristics” for detailed information

Interface Applications

For Input Interface Applications see Figures 4a-f and for CML Output Termination see Figures 5a-d.

CML Output Termination with VCCO 1.2V

For VCCO of 1.2V, Figure 5a, terminate the output with 50Ω-to-1.2V, DC-coupled, not 100Ω differentially across the outputs.

If AC-coupling is used, Figure 5d, terminate into 50Ω-to-1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage.

Do not AC couple with internally terminated receiver. For example, 50Ω ANY-IN input. AC-coupling will offset the output voltage by 200mV and this offset voltage will be too low for proper driver operation.

CML Output Termination with VCCO 1.8V

For VCCO of 1.8V, Figure 5a and Figure b, terminate with either 50Ω to 1.8V or 100Ω differentially across the outputs. AC- or DC-coupling is fine.

Input AC-Coupling

The SY54016R input can accept AC-coupling from any driver. Tie VT to VCC with a capacitor as shown in Figures 4c and 4d. VT has an internal high impedance resistor divider as shown in Figure 2a, to provide a bias voltage for AC-coupling.

Timing Diagrams

/IN IN t_pd /Q Q V_IN t_pd V_OUT

Figure 1a. Propagation Delay

Figure 1b. Fail-Safe Feature

Typical Characteristics

V_CC = 2.5V , GND = 0V, R_L = 50 to 1.2V, V_IN = 100mV , T_A = 25^ , unless otherwise stated.

Functional Characteristics

V_CC = 2.5V , GND = 0V, V_IN = 400mV , R_L = 50 to V_CCO , Data Pattern: 2^23-1 , T_A = 25^ , unless otherwise stated.

Output Eyes with V_cc0 = 1.2V Output Eyes with V
cco = 1.8V

Functional Characteristics

V_CC = 2.5V , GND = 0V, V_IN = 400mV , R_L = 50 to V_CCO , T_A = 25^ , unless otherwise stated.

Input and Output Stage

VCC 12.5K IN 50Ω VT 50Ω 33K /IN GND GND

Figure 2a. Simplified Differential Input Buffer

VCCO 50Ω 50Ω /Q Q GND

Figure 2b. Simplified CML Output Buffer

Single-Ended and Differential Swings

V_IN, V_OUT 400mV (typical)

Figure 3a. Single-Ended Swing

VDIFF_IN, VDIFF_OUT 800mV (typical)

Figure 3b. Differential Swing

Input Interface Applications

VCC (1.8V, 2.5V) CML GND IN /IN SY54016R NC VT

Figure 4a. CML Interface (DC-Coupled, 1.8V, 2.5V)

VCC (1.2V) CML GND VCC (1.2V) IN /IN SY54016R VT 0.1μF

Figure 4b. CML Interface (DC-Coupled, 1.2V)

VCC(1.8V, 2.5V, 3.3V) CML GND IN IN VCC 0.1μF VT SY54016R

Figure 4c. CML Interface (AC-Coupled)

VCC (3.3V, 2.5V) LVPECL GND Rp Rp GND IN /IN VCC 0.1μF VT SY54016R Note: For 3.3V, Rp = 100Ω. For 2.5V, Rp = 50Ω.

Figure 4d. LVPECL Interface (AC-Coupled)

VCC (2.5V) LVPECL GND IN /IN VCC 0.1μF RP VT SY54016R Note: For 2.5V, RP = 19Ω.

Figure 4e. LVPECL Interface (DC-Coupled)

VCC LVDS GND IN IN NC VT SY54016R

Figure 4f. LVDS Interface

CML Output Termination

VCCO (1.2V, 1.8V) 50Ω 50Ω Q Z0 = 50Ω IN 50Ω VCCO (1.2V, 1.8V) 50Ω Z0 = 50Ω /IN /Q GND

Figure 5a. 1.2 or 1.8V CML DC-Coupled Termination

VCCO (1.8V) 50Ω 50Ω Q Z0 = 50Ω IN 100Ω Z0 = 50Ω /Q /IN GND

Figure 5b. 1.8V CML DC-Coupled Termination

VCCO (1.8V) 50Ω 50Ω Q Z0 = 50Ω IN 50Ω VBIAS 50Ω /Z0 = 50Ω /IN /Q GND

Figure 5c. CML AC-Coupled Termination (Vcco 1.8V Only)

VCCO (1.2V) 50Ω 50Ω Q Zc= 50Ω 1.2V 50Ω IN 1kΩ VBias /Q Zc= 50Ω /IN 50Ω 1.2V GND

Figure 5d. CML AC-Coupled Termination ( V_cco 1.2V Only)

Related Product and Support Documents

Part Number Function Datasheet Link
SY54016AR	3.2Gbps Precision, 1:1 Low Voltage CML Buffer with Internal Termination	http://www.micrel.com/page.do?page=/product-info/products/sy54016ar.shtml
HBW Solutions	New Products and Termination Application Notes	http://www.micrel.com/page.do?page=/product-info/as/HBWsolutions.shtml

Package Information

NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.
DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25 on FROM TERMINAL TIP.
6. APPLIED ONLY FOR TERMINALS.
APPLIED FOR EXPOSED PAD AND TERMINALS.

8-Pin MLF® (2mm x 2mm) (MLF-8)

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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