SY56023R - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY56023R Microchip

The SY56023R is a fully-differential, low-voltage 1.2V/1.8V/2.5V CML 2x2 crosspoint switch with input equalization. The SY56023R can process clock signals as fast as 5GHz or data patterns up to 6.4Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to CML differential signals, without any level-shifting or termination resistor networks in the signal path. The differential input can also accept AC-coupled LVPECL and LVDS signals. Input voltages as small as 200mV (400mV PP ) are applied before the 9", 18" or 27" FR4 transmission line. For AC-coupled input interface applications, an internal voltage reference is provided to bias the V T pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 80ps.

The SY56023R operates from a 2.5V ±5% core supply and a 1.2V, 1.8V or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). The SY56023R is part of Micrel's high-speed, Precision Edge® product line.

Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

graph TD
    A["IN0"] --> B["50Ω"]
    C["V_D"] --> D["50Ω"]
    E["/IN0"] --> F["EQUALIZATION"]
    G["IN1"] --> H["50Ω"]
    I["V_T"] --> J["50Ω"]
    K["/IN1"] --> L["EQUALIZATION"]
    M["EQ (3-LEVEL INPUT)"] --> N["0"]
    O["0"] --> P["1"]
    Q["Q0"] --> R["/Q0"]
    S["Q1"] --> T["/Q1"]

Precision Edge is a registered trademark of Micrel, Inc.

Precision Edge®

Features

• 1.2V/1.8V/2.5V CML 2x2 crosspoint switch
• Equalizes 9, 18, 27 inches of FR4
• Guaranteed AC performance over temperature and voltage:

• DC-to > 6.4Gbps Data throughput
• DC-to > 5GHz Clock throughput
• <280 ps propagation delay (IN-to-Q)
• <15 ps output skew

• <80 ps rise/fall times

• Ultra-low jitter design

• <1 ps RMS cycle-to-cycle jitter
  • High-speed CML outputs
• 2.5V ±5% V_C , 1.2/1.8V/2.5V ±5% V_CCO power supply operation
• Industrial temperature range: -40^ to +85^
  • Available in 16-pin (3mm x 3mm) QFN package

Applications

• Data Distribution:
• SONET clock and data distribution
• Fiber Channel clock and data distribution
• Gigabit Ethernet clock and data distribution

Markets

• Storage
• ATE
  • Test and measurement
• Enterprise networking equipment
  • High-end servers
  • Metro area network equipment

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY56023RMG	QFN-16	Industrial	R023 with Pb-FreeBar-Line Indicator	NiPdAuPb-Free
SY56023RMGTR(2) QFN-16 Industrial			R023 with Pb-FreeBar-Line Indicator	NiPdAuPb-Free

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals only.
2. Tape and Reel.

Pin Configuration

IN0 SEL0 GND EQ /IN0 1 VT0 2 VT1 3 IN1 4 /IN1 SEL1 VCC VCCO 16 15 14 13 12 Q0 11 /Q0 10 Q1 9 /Q1

16-Pin QFN

Truth Table

SEL0 SEL1 Q0 Q1
L L IN0 IN0
L H IN0 IN1
H L IN1 IN0
H H IN1 IN1

EQ	EQUALIZATION
LOW	27"
FLOAT	18"
HIGH	9"

Pin Description

Pin Number	Pin Name	Pin Function
16,14,5	IN0, /IN0IN1, /IN1	Differential Inputs: Signals as small as 200mV V_PK (400m V_PP ) applied to the input of 9, 18 or 27 inches 6 mil FR4 stripline transmission line are then terminated with the differential input. Each input pin internally terminates with 50Ω to the VT pin.
23	VT0VT1	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC coupling. For AC-coupling, bypass VT with 0.1μF low-ESR capacitor to VCC. See “Interface Applications” subsection and Figure 2a.
13 EQ		Three level input for equalization control. High, float, low. EQ pin applies the same EQ setting to both inputs.
156	SEL0SEL1	These single-ended TTL/CMOS-compatible inputs, selects inputs IN0 or IN1. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open.
7 VCC		Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the V_CC pins as possible. Supplies input and core circuitry.
8 VCCO		Output Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the V_CCO pins as possible. Supplies the output buffers
14	GND, Exposed Pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pins.
12,1110,9	Q0, /Q0Q1, /Q1	CML Differential Output Pairs: Differential buffered copy of the input signal. The output swing is typically 390mV. See “Interface Applications” subsection for termination information.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc )....-0.5V to +3.0V

Supply Voltage ( V_cco ) ....-0.5V to +3.0V

CML Output Voltage ( V_OUT ) 0.6V to 3.0V

Current ( V_T )

Source or sink on VT pin ....±100mA

Input Current

Source or sink Current on (IN, /IN) ....±50mA

Maximum operating Junction Temperature ..... 125°C

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_cc )....2.375V to 2.625V

(V_cc0) 1.14V to 2.625V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3) QFN

Still-air ( _JA ) 75°C/W

Junction-to-board ( _JB ) 33°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply Voltage Range V	cc	2.375	2.5	2.625	V
		V_CCO	1.14	1.2	1.26	V
		V_CCO	1.7	1.8	1.9	V
		V_CCO	2.375	2.5	2.625	V
I_CC Power	Supply Current Max. V	cc 80 110 mA
I_CCO	Power Supply Current	No Load. V_CCO		32	42	mA
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.42		V_CC	V
V_IL Input LOW Voltage (IN, /IN)		IN, /IN1.22V = 1.7-0.475	1.22		V_IH-0.2	V
V_IN	Input Voltage Swing (IN, /IN)	see Figure 3a, Note 5, applied to input of transmission line.	0.2		1.0	V
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	see Figure 3b, Note 5, applied to input of transmission line.	0.4		2.0	V
V_T\_IN	Voltage from Input to V_T				1.28	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IN(max) is specified when V_T is floating.

CML Outputs DC Electrical Characteristics ^(6)

V_CCO = 1.14V to 1.26V R_L = 50 to V_CCO,

V_CCO = 1.7V to 1.9V , 2.375V to 2.625V , R_L = 50 to V_CCO or 100 across the outputs,

V_CC = 2.375V to 2.625V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH Output HIGH Voltage R		_L=50 to V_CCO	V_CC-0.020 V	_CC-0.010 V	_CC	V
V_OUT	Output Voltage Swing	See Figure 3a	300	390	475	mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 3b	600	780	950	mV
R_OUT	Output Source Impedance		45	50	55

LVTTL/CMOS DC Input Electrical Characteristics ^(6)

V_CC = 2.375V to 2.625V ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0		V_CC	V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

Three Level EQ Input DC Electrical Characteristics ^(6)

V_CC = 2.375V to 2.625V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		V_CC-0.3		V_CC	V
V_IL	Input LOW Voltage		0		V_EE+0.3	V
I_IH	Input HIGH Current	V_IH=V_CC			400	μA
I_IL	Input LOW Current	V_IL=GND	-480			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics

$$ V _ {C C O} = 1. 1 4 V \text { to } 1. 2 6 V R _ {L} = 5 0 \Omega \text { to } V _ {C C O}, $$

$$ V _ {C C O} = 1. 7 V \text { to } 1. 9 V, 2. 3 7 5 V \text { to } 2. 6 2 5 V, R _ {L} = 5 0 \Omega \text { to } V _ {C C O} \text { or } 1 0 0 \Omega \text { across the outputs }, $$

$$ V _ {C C} = 2. 3 7 5 V \text { to } 2. 6 2 5 V; T _ {A} = - 4 0 ^ {\circ} C \text { to } + 8 5 ^ {\circ} C, \text { unless otherwise stated. } $$

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Frequency	NRZ Data	6.4			Gbps
		V_OUT = 100mV Clock	5			GHz
t_PD	Propagation Delay IN-to-QSEL-to-Q	Note 7, Figure 1	100	180	280	ps
		Figure 1	90	210	350	ps
t_Skew	Input-to-Input Skew	Note 8		5	20	ps
	Output-to-Output Skew	Note 9		3	15	ps
	Part-to-Part Skew	Note 10			100	ps
t_Jitter	Random Jitter	Note 11			1	ps_RMS
	Crosstalk Induced Jitter(Adjacent Channel)	Note 12			0.7	ps_PP
t_R t_F	Output Rise/Fall Time(20% to 80%)	At full output swing.	20	50	80	ps

Notes:

1. Propagation delay is measured with no attenuating transmission line connected to the input.
2. Input-to-Input skew is the difference in time between both inputs and the output for the same temperature, voltage and transition.
3. Output-to-Output skew is the difference in time between both outputs under identical input transition, temperature and power supply
4. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
5. Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX .
6. Crosstalk induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while applying a similar, differential clock frequencies that are asynchronous with respect to each other at the adjacent input.

Interface Applications

For Input Interface Applications see Figures 4a-e and for CML Output Termination see Figures 5a-d.

CML Output Termination with VCCO 1.2V

For VCCO of 1.2V, Figure 5a, terminate the output with 50 Ohms to 1.2V, not 100 ohms differentially across the outputs. If AC coupling is used, Figure 5d, terminate into 50 ohms to 1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage. Any unused output pair needs to be terminated, do not leave floating.

CML Output Termination with VCCO 1.8V

For VCCO of 1.8V, Figure 5a and Figure 5b, terminate with either 50 ohms to 1.8V or 100 ohms differentially across the outputs. AC- or DC-coupling is fine.

Input Termination

1.8V CML driver: Terminate input with VT tied to 1.8V. Don't terminate 100 ohms differentially.

2.5V CML driver: Terminate input with either VT tied to 2.5V or 100 ohms differentially.

The input cannot be DC coupled from a 1.2V CML driver.

Timing Diagrams

IN0 /INO → tpd Q /Q SEL → tpd Q /Q → tpd tpd

Figure 1. Propagation Delay

Typical Characteristics

V_CC = 2.5, V_CCO = 1.2V, GND = 0V, V_IN = 400mV, R_L = 50 to 1.2V, Data Pattern: 2^23-1, T_A = 25^, unless otherwise stated.

6.4Gbps, 18 inch FR4 Output Swing (100mv/div) TIME (50ps/div.)

6.4Gbps, 9 inch FR4 Output Swing (100mv/div) TIME (50ps/div.)

Input and Output Stage

VCC 12.5k IN 50Ω VT 50Ω 33k /IN GND GND

Figure 2a. Simplified Differential Input Buffer

VCCO 50Ω 50Ω /Q Q GND

Figure 2b. Simplified CML Output Buffer

Single-Ended and Differential Swings

V_IN V_OUT 400mV (Typ.)

Figure 3a. Single-Ended Swing

VDIFF_IN VDIFF_OUT 800mV (Typ.)

Figure 3b. Differential Swing

Input Interface Applications

VCC (2.5V) CML IN /IN GND SY56023R NC VT

Figure 4a. CML Interface 100Ω Differential (DC-Coupled, 2.5V)

VCC (1.8V, 2.5V) CML IN IN GND VCC (1.8V, 2.5V) VT SY56023R

Figure 4b. CML Interface 50Ω to Vcc (DC-Coupled, 1.8V, 2.5V)

VCC(1.8V,2.5V,3.3V) CML IN /IN GND VCC 0.1μF VT SY56023R

Figure 4c. CML Interface (AC-Coupled)

VCC (3.3V, 2.5V) LVPECL IN IN Rp Rp VCC GND GND 0.1μF VT For 3.3V, Rp = 100Ω. For 2.5V, Rp = 50Ω. SY56023R

Figure 4d. LVPECL Interface (AC-Coupled)

VCC LVDS GND IN IN SY56023R 0.1μF VT

Figure 4e. LVDS Interface (AC-Coupled)

CML Output Termination

VCCO (1.2V, 1.8V) 50Ω 50Ω Q Z0 = 50Ω IN 50Ω VCCO (1.2V, 1.8V) 50Ω Z0 = 50Ω /IN /Q GND

Figure 5a. 1.2V or 1.8V CML DC-Coupled Termination

VCCO (1.8V) 50Ω 50Ω Q Z0 = 50Ω IN 100Ω Z0 = 50Ω /Q /IN GND

Figure 5b. 1.8V CML DC-Coupled Termination

VCCO (1.8V) 50Ω 50Ω Q Z0 = 50Ω IN 50Ω VBIAS Z0 = 50Ω /IN /Ω GND

Figure 5c. CML AC-Coupled Termination V_cco 1.8V Only

VCCO (1.2V) 50Ω 50Ω Q Z0 = 50Ω 1.2V 50Ω IN 1kΩ VBIAS /Ω Z0 = 50Ω /IN 50Ω 1.2V GND

Figure 5d. CML AC-Coupled Termination V_cco 1.2V Only

Related Product and Support Documents

Part Number	Function	Datasheet Link
HBW Solutions	New Products and Termination Application Notes	http://www.micrel.com/page.do?page=/product-info/as/HBWsolutions.shtml

Package Information ^(1)

Pin 1 Dot By Marking 3.000BSC 1 2 3 3.000BSC 16

TOP VIEW

1.60±0.100 Exp. DAP 0.500 BSC CHAMFER 0.30 x 45° 2 1.60±0.10 Exp. DAP 0.25° 0.400±0.050 1.500 Ref.

VARIATION A

PIN #1 ID. R0.20 1 2

VARIATION B
BOTTOM VIEW

0.850±0.050 0.05°C SEATING PLANE 0.000-0.050 0.203±0.025

SIDE VIEW

NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 005 on
3. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.
DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25 ON FROM TERMINAL TIP
A BETWEEN 0.20 AND 0.25 MM FROM TERMINAL TIP.
APPLIED ONLY FOR TERMINALS.
APPLICD FOR EXPOSED PAD AND TERMINALS.

16-Pin QFN

Note:

1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.

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