SY58038U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58038U Microchip

The SY58038U is a low-jitter, low-skew, high-speed 8:1 multiplexer with a 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. The SY58038U distributes clock frequencies from DC to 3.5GHz, and data rates to 4.5Gpbs guaranteed over temperature and voltage.

The SY58038U differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K compatible LVPECL with extremely fast rise/fall times guaranteed to be less than 100ps.

The SY58038U features a patented isolation design that significantly improves channel-to-channel crosstalk performance.

The SY58038U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY58038U is part of Micrel's high-speed, Precision Edge® product line.

Datasheets and support documentation are available on Micrel's web site at: www.micrel.com.

Precision Edge®

Features

• Selects between 1 of 8 inputs, and provides two precise, low-skew LVPECL output copies
  • Ultra-low jitter design:

- 72fms phase jitter (typical)

• Guaranteed AC performance over temperature and voltage:

• DC to 4.5Gbps throughput
• <500ps propagation delay IN-to-Q ( V_IN > 100mV )
• <100ps r t/ t f time

• <15ps skew (output-to-output)

• Unique, patented, channel-to-channel isolation design provides superior crosstalk performance

• Unique, patented, input termination and V pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
  • 800mV LVPECL output swing
  • Power supply 2.5V ±5% or 3.3V ±10%
• -40°C to +85°C temperature range
  • Available in 44-pin (7mm × 7mm) QFN package

Applications

• Data communication systems
• All SONET/SDH data/clock applications
• All Fibre Channel applications
• All Gigabit Ethernet applications

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Functional Block Diagram

graph TD
    subgraph 8:1 MUX
        IN0["IN0"] --> V_T0["V_T0"]
        V_T0 --> INV_AO0["INV-AO0"]
        INV_AO0 --> INV_T1["V_T1"]
        INV_T1 --> INV_IN1["INV_IN1"]
        INV_T1 --> INV_T2["V_T2"]
        INV_T2 --> INV_T3["V_T3"]
        INV_T3 --> INV_T4["V_T4"]
        INV_T4 --> INV_T5["V_T5"]
        INV_T5 --> INV_T6["V_T6"]
        INV_T6 --> INV_T7["V_T7"]
        INV_T7 --> INV_T8["V_T8"]
        INV_T8 --> INV_T9["V_T9"]
        INV_T9 --> INV_T10["INV_T10"]
    end

    subgraph 1:2 FANOUT
        Q0["Q0"] --> S2["S2"]
        /Q0["/Q0"] --> S2
        Q1["Q1"] --> S2
        /Q1["/Q1"] --> S2

    INV_AO0 --> INV_T1["INV-T1"]
    INV_T2 --> INV_T3["INV-T3"]
    INV_T3 --> INV_T4["INV-T4"]
    INV_T4 --> INV_T5["INV-T5"]
    INV_T5 --> INV_T6["INV-T6"]
    INV_T6 --> INV_T7["INV-T7"]
    INV_T7 --> INV_T8["INV-T8"]
    INV_T8 --> INV_T9["INV-T9"]

    INV_T1 --> INV_T4
    INV_T3 --> INV_T5
    INV_T5 --> INV_T6
    INV_T6 --> INV_T7
    INV_T7 --> INV_T8
    INV_T8 --> INV_T9

    INV_T10 --> INV_T6
    INV_T10 --> INV_T7
    INV_T10 --> INV_T8
    INV_T10 --> INV_T9

    style 8:1 MUX fill:#f9f,stroke:#333
    style 1:2 FANOUT fill:#ccf,stroke:#333

Truth Table

SEL2 SEL1 SEL0 Q /Q
LLL IN0 /IN0
LLL IN1 /IN1
LLL IN2 /IN2
LLL IN3 /IN3
LLL IN4 /IN4
LLL IN5 /IN5
LLL IN6 /IN6
LLL IN7 /IN7

Ordering Information ^(1)

Part Number	Marking	Operating Range	Package
SY58038UMY	SY58038U	-40^ to +85^	44-pin (7mm × 7mm) QFN
SY58038UMY TR ^(2)	SY58038U	-40^ to +85^	44-pin (7mm × 7mm) QFN

Notes:
1. Contact factory for die availability. Die are guaranteed at T A = +25°C, DC electricals only.
2. Tape and reel.

Pin Configuration

Pin Description

Pin Number	Pin Name	Pin Function
20, 18	IN0, /IN0
16, 14	IN1, /IN1
13, 11	IN2, /IN2	Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Refer to the Input Interface Applications section for more details.
9, 7
5, 3	IN4, /IN4
1, 43	IN5,/IN5
42, 40	IN6, /IN6
38, 36	IN7, /IN7
19,15	VT0, VT1	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. Refer to the Input Interface Applications section for more details
12, 8	VT2, VT3
4, 44	VT4, VT5
41, 37	VT6, VT7
17	VREF-AC0	Reference Voltage: This output biases to V_CC - 1.2V . It is used when AC coupling the inputs (IN, /IN). For AC-coupled applications, connect VREF-AC to the VT pin and bypass with a 0.01μF low-ESR capacitor to V_CC or GND, depending on input type. Refer to the Input Interface Applications section for more details.
10	VREF-AC1
2	VREF-AC2
39	VREF-AC3
21	SEL0	The single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open.
22	SEL1
35	SEL2
24, 27, 29, 32	VCC	Positive Power Supply. Bypass with 0.1μF//0.01μF low-ESR capacitors as close to each VCC pin.
25, 26	Q0,/Q0	Differential Outputs: These LVPECL output pairs are the outputs of the device. Unused output pairs may be left open. Each output is designed to drive 800mV into 50Ω terminated to V_CC - 2V (or V_CC - 1.2V , if AC-coupled).
30, 31	Q1,/Q1
23, 28, 33	GND, ePad	Ground. GND and exposed pad (ePad) must both be connected to the most negative potential of chip ground.

Absolute Maximum Ratings ^(3)

Power Supply Voltage ( V_cc )....-0.5V to +4.0V

Input Voltage ( V_IN ). -0.5V to V_CC

LVPECL Output Current ( I_OUT )

Continuous....50mA

Surge 100mA

Termination Current ^(6)

Source or Sink Current (on VT pin) ....±100mA

Lead Temperature (soldering, 10s)....+260°C

Storage Temperature Range ( T_s )....-65°C to +150°C

Operating Ratings ^(4)

Power Supply

Voltage (Vcc) .....+2.375V to +2.625V or +3.0V to 3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(5)

QFN ( _JA )

Still Air 24°C/W

QFN (ψ JB)

Junction-to-Board....12°C/W

DC Electrical Characteristics ^(7)

T_A = -40^ to +85^ , unless otherwise noted.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_CC Power	Supply Voltage	V_CC = 2.5V	2.375	2.5	2.625	V
		V_CC = 3.3V	3.0	3.3	3.6
I_CC	Power Supply Current	No load, maximum V_CC		120	170	mA
R_IN	Input Resistance (IN-to- V_T )		40	50	60	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		80	100	120	Ω
V_IH	Input HIGH Voltage (IN-to-/IN)	Note 8	V_CC - 1.6		V_CC	V
V_IL	Input LOW Voltage (IN-to-/IN)		0		V_IN - 0.1	V
V_IN	Input Voltage Swing (IN-to-/IN)	See Figure 1	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing (IN-to-/IN)	See Figure 2	0.2			V
V_T\_IN	IN-to- V_T (IN-to-/IN)				1.28	V
V_REF-AC	Output Reference Voltage		V_CC - 1.3	V_CC - 1.2	V_CC - 1.1	V

Notes:

1. Permanent device damage may occur if ratings in the Absolute Maximum Ratings section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB uses 4-layer 0_JA in still-air number unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IH (minimum), not lower than 1.2V.

LVPECL Output DC Electrical Characteristics ^(9)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C ≤ to +85^ C , R_L = 50 to V_CC - 2V , unless otherwise noted.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_OH Output HIGH Voltage (Q, /Q)			V_CC - 1.145		V_CC - 0.895	V
V_OL Output LOW Voltage (Q, /Q)			V_CC - 1.945		V_CC - 1.695	V
V_OUT	Output Differential Swing (Q, /Q)	See Figure 1	550	800		mV
V_DIFF\_OUT	Differential Output Voltage Swing (Q, /Q)	See Figure 2	1100	1600		mV

LVTTL/CMOS DC Electrical Characteristics ^(9)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C ≤ to +85^ C , unless otherwise noted.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_IH	Input HIGH Voltage		2.0		V_CC	V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

AC Electrical Characteristics ^(10)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C ≤ to +85^ C , R_L = 50 to V_CC - 2V , unless otherwise noted.

Symbol	Parameter		Condition	Min.	Typ.	Max.	Units
f_MAX	Maximum Operating Frequency		NRZ Data	4.5			Gbps
			V_OUT ≥ 400mV Clock	3.5	5		GHz
t_pd	Differential Propagation Delay	IN-to-Q	V_IN ≥ 100mV	280	390	500	ps
		SEL-to-Q		150		600	ps
t_pd Temp Coefficient	Differential Propagation Delay Temperature Coefficient				220		fs/°C
t_SKEW	Output-to-Output Skew		Note 11			15	ps
	Part-to-Part Skew		Note 12			150	ps
t_JITTER	RMS Phase Jitter		Carrier = 622MHzIntegration Range:12kHz - 20MHz		72		fs_rms
t_r, t_f	Output Rise/Fall Time		At full output swing, 20% to 80%	35	65	100	ps

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
2. High-frequency AC-parameters are guaranteed by design and characterization.
3. Output-to-output skew is measured between two different outputs under identical input transitions.
4. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.

Phase Noise Plot

Single-Ended and Differential Swings

V_IN' V_OUT 800mV (TYPICAL)

Figure 1. Single-Ended Voltage Swing

VDIFF_IN' VDIFF_OUT 1600mV (TYPICAL)

Figure 2. Differential Voltage Swing

Typical Operating Characteristics

V_CC = 3.3V , GND = 0, V_IN = 100mV , T_A = +25^ C , unless otherwise stated

Functional Characteristics

V_CC = 3.3V , GND = 0, V_IN = 100mV , T_A = +25^ , unless otherwise stated.

Functional Characteristics (Continued)

V_CC = 3.3V, GND = 0, V_IN = 100mV, T_A = +25^, unless otherwise stated.

Input and Output Stages

Vcc IN 50Ω VT 50Ω /IN GND

Figure 3. Simplified Differential Input Stage

Vcc /Q Q

Figure 4. Simplified LVPECL Output Stage

Input Interface Applications

VCC LVPECL GND VCC 0.01μF Rpd IN /IN VT NC VREF-AC SY58038U For VCC = 3.3V, Rpd = 50Ω For VCC = 2.5V, Rpd = 19Ω

Figure 5. LVPECL Interface (DC-Coupled)

VCC LVPECL GND Rpd GND Rpd IN /IN VCC 0.01μF SY58038U VT VREF-AC For 3.3V, Rpd = 100Ω For 2.5V, Rpd = 50Ω

Figure 6. LVPECL Interface (AC-Coupled)

VCC CML IN /IN SY58038U GND NC □ VT NC □ VREF-AC OPTION: CAN CONNECT VT TO VCC

Figure 7. CML Interface (DC-Coupled)

VCC CML GND IN /IN SY58038U VCC VT VREF-AC 0.01μF

Figure 8. CML Interface (AC-Coupled)

Input Interface Applications (Continued)

Vcc LVDS IN IN GND SY58038U NC □ VT NC □ VREF-AC

Figure 9. LVDS Interface (DC Coupled)

VCC LVDS GND IN /IN SY58038U VCC VT VREF-AC 0.01μF

Figure 10. LVDS Interface (AC Coupled)

Output Interface Applications

+3.3V Z₀ = 50Ω +3.3V R1 130Ω R1 130Ω +3.3V Z₀ = 50Ω R2 82Ω R2 82Ω

Note: For +2.5V system, R1 = 250Ω, R2 = 62.5Ω

Figure 11. Parallel Thevenin-Equivalent Termination

+3.3V Z₀ = 50Ω Z₀ = 50Ω +3.3V Vₒₓ 50Ω 50Ω C1 0.01μF (OPTIONAL) Rₑ

Note: For +2.5V system, R_b = 19 For +3.3V system, R_b = 50

Figure 12. Parallel Termination (3-Resistor)

Package Information and Recommended Landing Pattern ^(13)

PIN 1 ID 7.00±0.05 44 1 2 7.00±0.05

TOP VIEW NOTE 1.2.3

3.30±0.10 PIN #1 ID R0.20 44 0.60±0.05 1 2 + 3.30±0.10 0.20 MIN. 0.50 BSC 0.25±0.05

BOTTOM VIEW NOTE 1.2.3

0.85±0.05 0.00-0.05 0.20 REF.

SIDE VIEW NOTE 1, 2, 3

0.8±0.02 0.25±0.02 3.6±0.02 3.6±0.02 5.6±0.05 7.2±0.05 0.5 SSC

RECOMMENDED LAND PATTERN NOTE 4.5

NOTE:

1. MAX PACKAGE VARPAGE IS 0.05 MM

2. MAX ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS

3. PIN #1 IS ON TOP WILL BE LASER MARKED

4. FOR CIRCLE IN LAND PATTERN INDICATE THOMAI VIA SIZE SHOWN OF 0.20-0.25MM IN DIAMETER AND SHOWN OF CONNECTED TO CAN END MAY

THE WIND WINDS AT NEW COLDING STANDING TIPS, 2008 STANDING AS NEW WINDS AT SETTING THE WINDS AS STRAYING IN NEW LND FOR THERMAL PERFORMANCE. LOMM PITCH

K. EORTU DEPTAUNI PE /GUANER ADRAI DEBORCUIT ENI RED ETTEUCH NOFUMIC NU EVONER DAN ADRAI DORMAUNEN EITE TE BOOLAGOMM CEAATIN

S. GREEN IS 0.2MM

44-Pin 7mm × 7mm QFN (MM)

Note:

1. Package meets Level 2 qualification. All parts are dry-packaged before shipment. Exposed pads must be soldered to a ground for proper thermal management. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high-performance linear and power, LAN, and timing & communications markets. The Company's products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products. Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network of distributors and reps worldwide.

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