SY58604U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58604U Microchip

The SY58604U is a 2.5/3.3V, high-speed, fully differential LVPECL buffer optimized to provide only 108fs _RMS phase jitter. The SY58604U can process clock signals as fast as 2.5GHz or data patterns up to 3.2Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mV (200mV pp ) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated voltage reference (V REF-AC ) is provided to bias the V _T pin. The output is 800mV LVPECL, with extremely fast rise/fall times guaranteed to be less than 110ps.

The SY58604U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). For applications that require CML or LVDS outputs, consider the SY58603U and the SY58605U, buffers with 400mV and 325mV output swings respectively. The SY58604U is part of Micrel's high-speed, Precision Edge® product line.

Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

IN 50Ω V_T 50Ω /IN V_REF-AC Q /Q

Precision Edge®

Features

• Precision 800mV LVPECL buffer
- Ultra-low jitter design
- 108fs _RMS phase jitter
• Guaranteed AC performance over temperature and voltage:
- DC-to > 3.2Gbps throughput
- <350ps typical propagation delay (IN-to-Q)
- <110ps rise/fall times
- Fail Safe Input
- Prevents output from oscillating when input is invalid
• High-speed LVPECL output
• 2.5V ±5% or 3.3V ±10% power supply operation
- Industrial temperature range: -40^ to +85^
• Available in 8-pin (2mm x 2mm) DFN package

Applications

• All SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
- Backplane distribution

Markets

• Storage
• ATE
  • Test and measurement
  • Enterprise networking equipment
  • High-end servers
• Access
  • Metro area network equipment

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking
SY58604UMG	DFN-8	Industrial	604 with Pb-Free bar-line indicator
SY58604UMGTR^(2)	DFN-8	Industrial	604 with Pb-Free bar-line indicator

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A=25^ , DC Electricals only.
2. Tape and Reel.

Pin Configuration

IN VT VREF-AC /IN 1 2 3 4 8 7 6 5 VCC Q /Q GND

8-Pin DFN

Pin Description

Pin Number Pin Name Pin Function
1, 4 IN, /IN		Differential Input: This input pair is the differential signal input to the device. Input accepts DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See “Input Interface Applications” subsection for more details.
2	VT	Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection.
3	VREF-AC	Reference Voltage: This output biases to V_CC-1.2V . It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01μF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface Applications” subsection for more details.
5	GND, Exposed pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin.
6, 7 /Q, Q		LVPECL Differential Output Pair: Differential buffered output copy of the input signal. The output swing is typically 800mV. See “LVPECL Output Termination” subsection.
8	VCC	Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the V_CC pin as possible.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) -0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC+0.5V

LVPECL Output Current ( I_OUT )

Continuous....50mA

Surge 100mA

Current (V_T)

Source or sink on VT pin ....±100mA

Input Current

Source or sink Current on (IN, /IN) ....±50mA

Current ( V_REF )

Source or sink current on V REF-AC ^(4) .....±1.5mA

Maximum Operating Junction Temperature..... 125°C

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_IN )....+2.375V to +3.60V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3)

DFN

Still-air ( _JA ).... 93°C/W

Junction-to-board ( _JB )..... 56°C/W

DC Electrical Characteristics ^(5)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter Condition	Min	Typ	Max	Units
V_CC Power	Supply Voltage Range			2.375	3.0	2.5	2.625	V
						3.3	3.6
I_CC	Power Supply Current	No load, max. V_CC				30	45	mA
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)				90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN, Note 7			V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	IN, /IN			0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	see Figure 3a, Note 6			0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	see Figure 3b			0.2			V
V_IN\_FSI	Input Voltage Threshold that Triggers FSI					30	100	mV
V_REF-AC	Output Reference Voltage				V_CC-1.3	V_CC-1.2	V_CC-1.1	V
V_T\_IN	Voltage from Input to V_T							1.28

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IN (max) is specified when V_T is floating.
7. V_IH (min) not lower than 1.2V.

LVPECL Outputs DC Electrical Characteristics ^(5)

V_CC = +2.5V ± 5% or +3.3V ± 10% , R_L = 50 to V_CC-2V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter Condition	Min	Typ	Max	Units
V_OH Output	HIGH Voltage V				cc-1.145		V_CC -0.895	V
V_OL Output	LOW Voltage V				cc-1.945		V_CC -1.695	V
V_OUT	Output Voltage Swing	See Figure 3a			550	800	950	mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 3b			1100	1600		mV

AC Electrical Characteristics

V_CC = +2.5V ± 5% or +3.3V ± 10% , R_L = 50 to V_CC-2V , Input t_r/t_f ≤ 300ps ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter Condition		Min Typ Max Units
MAX	Maximum Frequency		NRZ Data 3.2 4.25 Gbps f
			V_OUT > 400mV Clock	2.5 3 GHz
t_PD	Propagation Delay IN-to-Q		V_IN: 100mV-200mV	180	320	450	ps
			V_IN: 200mV-800mV	150	230	350	ps
t_Skew	Part-to-Part Skew		Note 7			135	ps
t_Jitter	RMS Phase Jitter		Output = 622MHzIntegration Range: 12kHz - 20MHz		108		f_SRMS
t_r,tf	Output Rise/Fall Times(20% to 80%)		At full output swing.	40	75	110	ps
	Duty Cycle		Differential I/O	47		53	%

Notes:

1. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.

Phase Noise Plot

PHASE NOISE PLOT: 622MHz @ 3.3V

Functional Description

Fail-Safe Input (FSI)

The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mV_PK ( 200mV_PP ), typically 30mV_PK . Maximum frequency of SY58604U is limited by the FSI function.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low signal swing, then the FSI function will eliminate a metastable condition and guarantee a stable output. No ringing and no undetermined state will occur at the output under these conditions.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Characteristics” for detailed information.

Timing Diagrams

/IN IN t_pd /Q Q V_IN t_pd V_OUT

Figure 1a. Propagation Delay

Figure 1b. Fail Safe Feature

Typical Characteristics

V_CC = 3.3V , GND = 0V, V_IN = 100mV , R_L = 50 to V_CC - 2V , T_A = 25^ , unless otherwise stated.

Functional Characteristics

V_CC = 3.3V , GND = 0V, V_IN = 400mV , Data Pattern: 2^23-1 , R_L = 50 to V_CC-2V , T_A = 25^ , unless otherwise stated.

Functional Characteristics (continued)

V_CC = 3.3V , GND = 0V, V_IN = 400mV , R_L = 50 to V_CC - 2V , T_A = 25^ , unless otherwise stated.

Input and Output Stage

VCC IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Buffer

VCC /Q Q

Figure 2b. Simplified LVPECL Output Buffer

Single-Ended and Differential Swings

V_IN, V_OUT 800mV (typical)

Figure 3a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 1600mV (typical)

Figure 3b. Differential Voltage Swing

Input Interface Applications

VCC CML IN /IN GND SY58604U NC □ VT NC □ VREF-AC

Figure 4a. CML Interface (DC-Coupled)
Option: May connect V_T to V_CC

VCC CML GND IN IN VCC 0.1μF SY58604U VREF-AC

Figure 4b. CML Interface (AC-Coupled)

VCC LVPECL GND IN /IN 0.1μF VT NC VREF-AC R_P Note: For 3.3V, Rp = 50Ω, For 2.5V, Rp = 19Ω. SY58604U

Figure 4c. LVPECL Interface (DC-Coupled)

VCC LVPECL GND Rp Rp VCC IN /IN 0.1μF SY58604U VT VREF-AC Note: For 3.3V,RP = 100Ω. For 2.5V,RP = 50Ω.

Figure 4d. LVPECL Interface (AC-Coupled)

VCC LVDS IN /IN GND SY58604U NC □ VT NC □ VREF-AC

Figure 4e. LVDS Interface

LVPECL Output Termination

LVPECL outputs have very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω-and-100Ω-controlled impedance transmission lines. There are several techniques in terminating the LVPECL output, as shown in Figure 5a and 5b.

+3.3V Z₀ = 50Ω Z₀ = 50Ω GND +3.3V R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω GND +3.3V GND For 2.5V system: R1=250Ω, R2=62.5Ω

Figure 5a. Parallel Termination-Thevenin Equivalent

+3.3V Z₀ = 50Ω Z₀ = 50Ω GND +3.3V 50Ω 50Ω Vcc C (optional) 0.01μF R1 GND

For 2.5V system: R1 = 19Ω.
For 3.3V system: R1 = 50Ω.

Figure 5b. Three-Resistor "Y-Termination"
Related Product and Support Documents

Part Number Function Data Sheet Link
SY58603U	4.25Gbps Precision CML Buffer with Internal Termination and Fail Safe Input	http://www.micrel.com/page.do?page=/product-info/products/sy58603u.shtml
SY58605U	3.2Gbps Precision LVDS Buffer with Internal Termination and Fail Safe Input	http://www.micrel.com/page.do?page=/product-info/products/sy58605u.shtml
HBW Solutions	New Products and Termination Application Notes	http://www.micrel.com/page.do?page=/product-info/as/HBWsolutions.shtml

Package Information

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.
DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP.
6. APPLIED ONLY FOR TERMINALS.
APPLIED FOR EXPOSED PAD AND TERMINALS.
Rev. B

8-Pin (2mm x 2mm) DFN

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