SY56034AR - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY56034AR Microchip

The SY56034AR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 2:6 (2+4) MUX with crosspoint capability. The SY56034AR can process clock signals as fast as 5GHz or data patterns up to 6.4Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals as small as 100mV (200mV pp ) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an internal voltage reference is provided to bias the V T pin. The outputs are 400mV CML, with extremely fast rise/fall times guaranteed to be less than 80ps.

The SY56034AR operates from a 2.5V ±5% core supply and a 1.2V/1.8V/2.5V ±5% output supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). The SY56034AR is part of Micrel's high-speed, Precision Edge® product line.

Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

graph TD
    IN0["IN0"] --> A1["NOT"]
    Vref["Vref"] --> A2["NOT"]
    /IND["/IND"] --> A3["NOT"]
    A1 --> B1["AND Gate 1"]
    A2 --> B2["AND Gate 1"]
    A3 --> B3["AND Gate 1"]
    B1 --> Bank1["Bank 1"]
    B2 --> Bank2["Bank 2"]
    B3 --> Bank2
    Bank1 --> Q0["Q0"]
    Bank2 --> Q4["Q4"]
    /Q0 --> Q0a["/Q0"]
    /Q1 --> Q1["Q1"]
    /Q2 --> Q2["Q2"]
    /Q3 --> Q3["Q3"]
    /Q4 --> Q4a["/Q4"]
    /Q5 --> Q5["Q5"]
    /Q5a["/Q5"]
    /Q5b["/Q5"]
    SEL0["SEL0"] --> A1
    SEL1["SEL1"] --> A2
    SEL0 --> A3
    SEL1 --> A3
    style IN0 fill:#f9f,stroke:#333
    style Vref fill:#ccf,stroke:#333
    style /IND fill:#cfc,stroke:#333
    style SEL0 fill:#fcc,stroke:#333
    style SEL1 fill:#cff,stroke:#333
    style Bank1 fill:#ffc,stroke:#333
    style Bank2 fill:#ffc,stroke:#333

Precision Edge is a registered trademark of Micrel, Inc.

Precision Edge®

Features

• 1.2V/1.8V/2.5V CML 2:6 (2+4) MUX with Crosspoint Capability
• Guaranteed AC performance over temperature and voltage:

• DC-to- > 6.4Gbps throughput
• <300ps propagation delay (IN-to-Q)
• <25ps Output skew
• <80ps rise/fall times

- Ultra-low jitter design

• <1ps RMS cycle-to-cycle jitter
• <10ps PP total jitter
• <1ps RMS random jitter
• <10ps PP deterministic jitter

• High-speed CML outputs

• 2.5V ±5%, 1.2V/1.8V/2.5V ±5% power supply operation
• Industrial temperature range: -40^ to +85^
  • Available in 32-pin QFN package

Applications

• Data Distribution: OC-48, OC-48+FEC
• SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution

Markets

• Storage
• ATE
  • Test and measurement
• Enterprise networking equipment
  • High-end servers
• Access
  • Metro area network equipment

Ordering Information ^(1)

Part Number Package	Type	Operating Range	Package Marking Lead	Finish
SY56034ARMG	QFN-32	Industrial	56034AR with Pb-Free bar-line indicator	NiPdAu Pb-Free
SY56034ARMGTR^(2)	QFN-32	Industrial	56034AR with Pb-Free bar-line indicator	NiPdAu Pb-Free

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ C , DC Electricals only.
2. Tape and Reel.

Pin Configuration

GND VCC VCCO Q0 /Q0 Q1 /Q1 VCCO 32 31 30 29 28 27 26 25 VT0 1 IN0 2 /IN0 3 SEL0 4 SEL1 5 IN1 6 /IN1 7 VT1 8 GND VCCO VCCO Q2 /Q2 Q3 /Q3 VCCO GND 9 10 11 12 13 14 15 16 /VCCO

32-Pin QFN

Truth Table

SEL0 SEL1 Bank1 Bank2
L L IN0	IN0
L	H	IN0	IN1
H	L	IN1	IN0
H	H	IN1	IN1

Pin Description

Pin Number	Pin Name	Pin Function
2,36,7	IN0, /IN0IN1,/IN1	Differential Inputs: These input pairs are the differential signal inputs to the device. They accept differential signals as small as 100mV(200mVPP). Each input pin internally terminates with 50Ω to the VT pin.
18	VT0VT1	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC-coupling. For AC-coupling, bypass VT with a 0.1μF low ESR capacitor to VCC. See “Interface Applications” subsection and Figure 2a.
45	SEL0SEL1	These single-ended TTL/CMOS-compatible inputs select the inputs to the crosspoint switch. Note that each of these inputs is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open.
10, 31	VCC	Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the VCC pin as possible. Supplies input and core circuitry.
11,16,18,23,25,30	VCCO	Output Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the VCCO pins as possible. Supplies the output buffer.
9,17,24,32 GND,	Exposed pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin.
29,28	Q0, /Q0	CML Differential Output Pairs: Differential buffered copy of the selected input signal. The output swing is typically 390mV. See “Interface Applications” subsection for termination information. Output pairs Q0 to Q3 belong to Bank 1. Q4 and Q5 belong to Bank 2.
27,26	Q1, /Q1
22,21	Q2, /Q2
20,19	Q3, /Q3
15,14	Q4, /Q4
13,12	Q5, /Q5

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc )....-0.5V to +3.0V

Supply Voltage ( V_cco ) ....-0.5V to +2.7V

V_cc - V_cc0 <1.8V

Source or sink current on VT pin ....±100mA

Input Current

Source or sink current on (IN, /IN)....±50mA

Maximum operating Junction Temperature ..... 125°C

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_cc )....2.375V to 2.625V

(V_cc0) 1.14V to 2.625V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3)

QFN

Still-air ( _JA ) 50°C/W

Junction-to-board ( _JB ) 20°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply Voltage Range	V_CC	2.375	2.5	2.625	V
		V_CCO	1.14	1.2	1.26	V
		V_CCO	1.7	1.8	1.9	V
		V_CCO	2.375	2.5	2.625	V
I_CC	Power Supply Current	Max. V_CC		100	140	mA
I_CCO	Power Supply Current	No Load. Max V_CCO		96	126	mA
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN Differential Input Resistance (IN-to-/IN)			90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.2		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	V_IL with V_IH = 1.2V	0.2		V_IH-0.1	V
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.14		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	V_IL with V_IH = 1.14V (1.2V-5%)	0.66		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	see Figure 3a	0.1		1.0	V
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	see Figure 3b	0.2		2.0	V
V_T\_IN	Voltage from Input to V_T				1.28	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

CML Outputs DC Electrical Characteristics ^(5)

$$ V _ {C C O} = 1. 1 4 V \text { to } 1. 2 6 V, R _ {L} = 5 0 \Omega \text { to } V _ {C C O}, $$

$$ V _ {C C O} = 1. 7 V \text { to } 1. 9 V, 2. 3 7 5 V \text { to } 2. 6 2 5 V, R _ {L} = 5 0 \Omega \text { to } V _ {C C O} \text { or } 1 0 0 \Omega \text { across the outputs. } $$

$$ V _ {C C} = 2. 3 7 5 \mathrm{V} \text { to } 2. 6 2 5 \mathrm{V}. T _ {A} = - 4 0 ^ {\circ} \mathrm{C} \text { to } + 8 5 ^ {\circ} \mathrm{C}, \text { unless otherwise stated. } $$

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH Output HIGH Voltage R		_L=50 to V_CCO	V_CCO-0.020	V_CCO-0.010	V_CCO	V
V_OUT	Output Voltage Swing	See Figure 3a	300	390	475	mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 3b	600	780	950	mV
R_OUT	Output Source Impedance		45	50	55

LVTTL/CMOS DC Electrical Characteristics ^(5)

V_CC = 2.5V ± 5% . T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0		V_CC	V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics

$$ V _ {C C O} = 1. 1 4 V \text { to } 1. 2 6 V, R _ {L} = 5 0 \Omega \text { to } V _ {C C O}, $$

$$ V _ {C C O} = 1. 7 V \text { to } 1. 9 V, 2. 3 7 5 V \text { to } 2. 6 2 5 V, R _ {L} = 5 0 \Omega \text { to } V _ {C C O} \text { or } 1 0 0 \Omega \text { across the outputs. } $$

$$ V _ {C C} = 2. 3 7 5 \mathrm{V} \text { to } 2. 6 2 5 \mathrm{V}. T _ {A} = - 4 0 ^ {\circ} \mathrm{C} \text { to } + 8 5 ^ {\circ} \mathrm{C}, \text { unless otherwise stated. } $$

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Frequency	NRZ Data	6.4			Gbps
		V_OUT>200mV Clock	5			GHz
t_PD	Propagation Delay IN-to-QSEL-to-Q	Figure 1	150	220	300	ps
		Figure 1	100	200	300	ps
t_Skew	Input-to-Input Skew	Note 6		5	15	ps
	Output-to-Output skew	Note 7, All Outputs or Q0-Q3		7	25	ps
	Output-to-Output skew	Note 7, Q4-Q5		4	20	ps
	Part-to-Part Skew	Note 8			75	ps
t_Jitter	Data Random Jitter	Note 9			1	pS_RMS
	Deterministic Jitter	Note 10			10	pS_PP
	Clock Cycle-to-Cycle Jitter	Note 11			1	pS_RMS
	Total Jitter	Note 12			10	pS_PP
	Crosstalk Induced Jitter(Adjacent Channel)	Note 13			0.7	pS_PP
t_R, t_F	Output Rise/Fall Times(20% to 80%)	At full output swing.	20	60	80	ps
	Duty Cycle	≤4GHz Differential I/O	47		53	%
		<5GHz Differential I/O	45		55	%

Notes:

1. Input-to-Input skew is the difference in time between both inputs, measured at the same output, for the same temperature, voltage and transition.
2. Output-to-Output skew is the difference in time between both outputs, receiving data from the same input, for the same temperature, voltage and transition.
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
4. Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX
5. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2^23-1 PRBS pattern.
6. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t_JITTER_CC = T_n - T_n+1 , where T is the time between rising edges of the output signal.
7. Total jitter definition: with an ideal clock input frequency of ≤ f_MAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
8. Crosstalk-induced jitter is defined as the added jitter that results from signals applied to the adjacent channel. It is measured at the output while applying a similar, differential clock frequency to both inputs that is asynchronous with respect to each other.

Interface Applications

For Input Interface Applications, see Figures 4a through 4f. For CML Output Termination, see Figures 5a through Figure 5d.

CML Output Termination with VCCO 1.2V

For VCCO of 1.2V, Figure 5a, terminate the output with 50Ω-to-1.2V, DC coupled, not 10Ω differentially across the outputs.

If AC-coupling is used, Figure 5d, terminate into 50Ω - to-1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage.

Do not AC couple with internally terminated receiver. For example, 50 ANY -IN input. AC-coupling will offset the output voltage by 200mV and this offset voltage will be too low for proper driver operation. Any unused output pair needs to be terminated when VCCO is 1.2V, do not leave floating.

CML Output Termination with VCCO 1.8V, 2.5V

For VCCO of 1.8V or 2.5V, Figure 5a and Figure 5b, terminate with either 50 -to-1.8V or 0100 differentially across the outputs. AC- or DC-coupling is fine. See Figure 5c for AC-coupling.

Input AC-Coupling

The SY56034AR input can accept AC-coupling from any driver. Bypass VT with a 0.1μF low ESR capacitor to VCC as shown in Figures 4c and 4d. VT has an internal high impedance resistor divider as shown in Figure 2a, to provide a bias voltage for AC-coupling.

Timing Diagrams

IN /IN → tpd Q /Q SEL → tpd Q /Q → tpd tpd

Figure 1. Propagation Delay

Typical Characteristics

V_CC = 2.5V, V_CCO = 1.2V, GND = 0V, V_IN = 100mV, R_L = 50 to 1.2V, T_A = 25^, unless otherwise stated.

Functional Characteristics

V_CC = 2.5V, V_CCO = 1.2V, GND = 0V, V_IN = 400mV, R_L = 50 to 1.2V, T_A = 25^, unless otherwise stated.

3.2Gbps Output (PRBS 2 ^23 -1) Differential (Q-/Q)

Output Swing (200mV/div.) TIME (80ps/div.)

6.4Gbps Output (PRBS 2 ^23 -1) Differential (Q-/Q)

Output Swing (200mV/div.) TIME (40ps/div.)

2.5GHz Output (1010 Pattern)

5GHz Output (1010 Pattern)

Input and Output Stage

VCC 12.5K IN 50Ω VT 50Ω /IN 33K GND GND

Figure 2a. Simplified Differential Input Buffer

Vcc0 50Ω 50Ω /Q Q GND

Figure 2b. Simplified CML Output Buffer

Single-Ended and Differential Swings

V_{IN}, V_{OUT} 400mV (typical)

Figure 3a. Single-Ended Swing

VDIFF_IN, VDIFF_OUT 800mV (typical)

Figure 3b. Differential Swing

Input Interface Applications

VCC (1.8V, 2.5V) CML GND IN IN SY56034AR NC VT

Figure 4a. CML Interface (DC-Coupled, 1.8V, 2.5V) Option: V_T may be connected to V_CC

VCC (1.2V) CML VCC (1.2V) GND IN /IN SY56034AR VT 0.1μF

Figure 4b. CML Interface (DC-Coupled, 1.2V)

VCC (1.8V, 2.5V, 3.3V) CML GND VCC 0.1μF IN /IN SY56034AR VT

Figure 4c. CML Interface (AC-Coupled)

VCC (3.3V, 2.5V) LVPECL GND Rp Rp IN /IN VCC 0.1μF VT For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω. SY56034AR

Figure 4d. LVPECL Interface (AC-Coupled)

VCC (2.5V) LVPECL GND IN IN VCC 0.1μF RP VT For 2.5V, RP = 19Ω. SY56034AR

Figure 4e. LVPECL Interface (DC-Coupled)

VCC LVDS GND IN /IN NC VT SY56034AR

Figure 4f. LVDS Interface

CML Output Termination

VCCO (1.2V, 1.8V, 2.5V) 50Ω 50Ω Q Zo = 50Ω IN 50Ω VCCO (1.2V, 1.8V, 2.5V) Zo = 50Ω /IN /Ω GND

Figure 5a. 1.2V 1.8V or 2.5V CML DC-Coupled Termination

Vcc0 (1.8V, 2.5V) 50Ω 50Ω Q Z0 = 50Ω IN 100Ω Z0 = 50Ω /Q /IN GND

Figure 5b. 1.8V or 2.5V CML DC-Coupled Termination

VCCO (1.8V, 2.5V) 50Ω 50Ω Q Z0 = 50Ω IN 50Ω VBIAS Z0 = 50Ω /IN 50Ω /Ω GND

Figure 5c. CML AC-Coupled Termination (Vcc0 1.8V or 2.5V only)

VCCO (1.2V) 50Ω /Ω Zo = 50Ω Q Zo = 50Ω GND 1.2V 50Ω 1kΩ VBias 1kΩ 50Ω 1.2V

Figure 5d. CML AC-Coupled Termination ( V_CCO 1.2V only)

Related Product and Support Documents

Part Number	Function	Datasheet Link
HBW Solutions	New Products and Termination Application Notes	http://www.micrel.com/page.do?page=/product-info/as/HBWsolutions.shtml

Package Information

5.0 BSC 32 1 2 PIN #1 ID 0.20 DIA TYP. 5.0 BSC

TOP VIEW

0.25±0.10 0.50 BSC 32 PIN #1 ID R0.20 0.20 MIN. 3.10±0.10 1 2 0.40±0.05 4X 3.10±0.10

BOTTOM VIEW

0.05 C 0.85±0.05 SEATING PLANE 0.00~0.05 0.20 REF

SIDE VIEW

NOTE

1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.
   DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED
   BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP.
5. APPLIED ONLY FOR TERMINALS.
   APPLIED FOR EXPOSED PAD AND TERMINALS.

32-Pin QFN

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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