SY58610U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58610U Microchip

The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 3.2Gbps. The SY58610U is optimized to provide a buffered output of the selected input with less than 10ps_pp total jitter.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mV (200mV PP) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated reference voltage ( V_REF-AC ) is provided to bias the V_T pin. The outputs are 800mV LVPECL, with extremely fast rise/fall times guaranteed to be less than 130ps.

The SY58610U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). For applications that require CML or LVDS outputs, consider Micrel's SY58609U and SY58611U, 2:1 MUX with 400mV and 325mV output swings, respectively. The SY58610U is part of Micrel's high-speed, Precision Edge® product line.

Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

IN0 50Ω V10 50Ω /IN0 VREF-AC0 IN1 50Ω V11 50Ω /IN1 VREF-AC1 SEL (TTL/CMOS) 0 MUX 1 S Q /Q

Precision Edge®

Features

• Precision 800mV LVPECL 2:1 MUX
• Guaranteed AC performance over temperature and voltage:
- DC-to > 3.2Gbps throughput
- <370ps propagation delay (IN-to-Q)
- <130ps rise/fall times
- Fail Safe Input - Prevents outputs from oscillating when input is invalid
- Unique, patented MUX input isolation design minimizes adjacent channel crosstalk
• Ultra-low jitter design
- <1ps RMS cycle-to-cycle jitter
- <10ps PP total jitter
- <1ps RMS random jitter
- <10ps PP deterministic jitter
• High-speed LVPECL outputs
• 2.5V ±5% or 3.3V ±10% power supply operation
- Industrial temperature range: -40^ to +85^
• Available in 16-pin (3mm x 3mm) QFN package

Applications

• All SONET clock distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
- Backplane distribution.

Markets

• Storage
• ATE
  • Test and measurement
  • Enterprise networking equipment
  • High-end servers

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number Package	Type	Operating Range	Package Marking Lead	Finish
SY58610UMG	QFN-16	Industrial	610U with Pb-Free bar-line indicator	NiPdAu Pb-Free
SY58610UMGTR^(2)	QFN-16	Industrial	610U with Pb-Free bar-line indicator	NiPdAu Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.

Pin Configuration Truth Table

/IN0 IN0 NC VCC 13 15 14 13 VT0 1 12 Q VREF-AC0 2 11 GND VREF-AC1 3 10 GND VT1 4 9 /Q IN1 IN1 SEL VCC

16-Pin QFN

SEL Output

0 IN0 Selected

1 IN1 Selected

Pin Description

Pin Number	Pin Name	Pin Function
1, 4	VT0, VT1	Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection.
2, 3 VREF-AC0,VREF-AC1		Reference Voltage: These outputs bias to V_CC -1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01μF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface Applications” subsection.
5, 615, 16	IN1, /IN1IN0, /IN0	Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept DC-Coupled differential signals as small as 100mV (200m V_pp ). Each pin of the pairs internally terminates with 50Ω to the corresponding VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See “Input Interface Applications” subsection.
7	SEL	Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is V_CC /2.
8, 13	VCC	Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the V_CC pins as possible.
9, 12	/Q, Q	LVPECL Differential Output Pair: Differential buffered output copy of the selected input signal. The output swing is typically 800mV. Unused output pair may be left floating with no impact on jitter. See “LVPECL Output Termination” subsection.
10, 11	GND, Exposed Pad	Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pins.
14	NC	No connect.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc )....-0.5V to +4.0V

Input Voltage ( V_IN )....-0.5V to V_CC

LVPECL Output Current( I_OUT )

Continuous....50mA

Surge 100mA

Current ( V_T )

Source or sink on VT pin ....±100mA

Input Current

Source or sink Current on (IN, /IN) ....±50mA

Current (VREF)

Source or sink current on V _REF-AC^(4) ……±0.5mA

Maximum operating Junction Temperature ..... 125°C

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_IN )....+2.375V to +3.60V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3)

QFN

Still-air ( _JA ) 60°C/W

Junction-to-board ( _JB ) 33°C/W

DC Electrical Characteristics ^(5)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply Voltage Range		2.375	2.5	2.625	V
			3.0	3.3	3.6
I_CC	Power Supply Current	No load, max. V_CC		40	50	mA
R_DIFF\_IN Differential Input Resistance (IN-to-/IN)			90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN, Note 7	V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	IN, /IN	0.2		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	see Figure 3a, Note 6	0.1		1.0	V
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	see Figure 3b	0.2			V
V_IN\_FSI	Input Voltage Threshold that Triggers FSI			30	100	mV
V_REF-AC	AC Reference Voltage		V_CC-1.3		V_CC-1.0	V
V_T\_IN	Voltage from Input to V_T				1.28	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IN (max) is specified when V_T is floating.
7. V_IH (min) not lower than 1.2V.

LVPECL Outputs DC Electrical Characteristics ^(7)

V_CC = +2.5V ± 5% or +3.3V ± 10%, R_L = 50 to V_CC-2V; T_A = -40^ to +85^, unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	Output HIGH Voltage	Q0, /Q0, Q1, /Q1	V_CC-1.145	V	cc-0.895	V
V_OL	Output LOW Voltage	Q0, /Q0, Q1, /Q1	V_CC-1.945	V	cc-1.695	V
V_OUT	Output Voltage Swing	See Figure 3a	550	800	950	mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 3b	1100	1600		mV

LVTTL/CMOS DC Electrical Characteristics ^(70)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

Notes:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(8)

V_CC = +2.5V ± 5% or +3.3V ± 10% , R_L = 50 to V_CC-2V ; Input t_R/t_F ≤ 300ps , T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Frequency	NRZ Data	3.2			Gbps
		VOUT>400mV Clock	2.5	3		GHz
t_PD	Propagation Delay IN-to-Q	V_IN : 100mV-200mV	180	340	470	ps
		V_IN : >200mV	140	290	370	ps
	SEL-to-Q		150		450	ps
t_Skew	Input-to-Input Skew	Note 9, 10		5	20	ps
	Part-to-Part Skew	Note 11			150	ps
t_Jitter	Data Random Jitter	Note 12			1	p_RMS
	Deterministic Jitter	Note 13			10	p_PP
	Clock Cycle-to-Cycle Jitter	Note 14			1	p_RMS
	Total Jitter	Note 15			10	p_PP
t_R, t_F	Output Rise/Fall Times (20% to 80%)	At full output swing.	40	100	130	ps
	Duty Cycle	Differential I/O	47		53	%

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
   9 Input-to-input skew is the time difference between the two inputs to one output, under identical input transitions.
   10 Input-to-Input Skew is included in IN-to-Q propagation delay.
2. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at the edges at the respective inputs.
3. Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX .
4. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2^23-1 PRBS pattern.
5. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t_ITTER_CC = T_n - T_n+1 , where T is the time between rising edges of the output signal.
6. Total jitter definition: with an ideal clock input frequency of ≤ f_MAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.

Functional Description

Fail-Safe Input (FSI)

The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mV_PK ( 200mV_PP ), typically 30mV_PK . Maximum frequency of the SY58610U is limited by the FSI function.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low signal swing, such that the voltage swing across the input pair is less than 100mV, the FSI function will eliminate a metastable condition and latch the outputs to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a swing greater than 100mV.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Operating Characteristics” for detailed information.

Timing Diagrams

Figure 1a. Fail Safe Feature

/IN IN t_pd t_pd /Q Q V_IN V_OUT

Figure 1b. Propagation Delay IN-to-Q

SEL Vcc/2 Vcc/2 tpd tpd Q /Q

Figure 1c. Propagation Delay SEL-to-Q

Typical Characteristics

V_CC = 3.3V , GND = 0V, V_IN = 100mV , R_L = 50 to V_CC-2V , T_A = 25^ , unless otherwise stated.

Functional Characteristics

V_CC = 3.3V , GND = 0V, V_IN = 400mV , R_L = 50 to V_CC - 2V , T_A = 25^ , unless otherwise stated.

Functional Characteristics (continued)

V_CC = 3.3V , GND = 0V, V_IN = 400mV , R_L = 50 to V_CC-2V , T_A = 25^ , unless otherwise stated.

Input and Output Stage

VCC IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Buffer

VCC /Q Q

Figure 2b. Simplified LVPECL Output Buffer

Single-Ended and Differential Swings

V_IN, V_OUT 800mV (typical)

Figure 3a. Single-Ended Voltage Swing

VDIFF_IN VDIFF_OUT 1600mV (typical)

Figure 3b. Differential Voltage Swing

Input Interface Applications

VCC CML IN /IN GND SY58610U NC □ VT NC □ VREF-AC

Figure 4a. CML Interface (DC-Coupled)

VCC CML GND VCC 0.1μF IN /IN SY58610U VT VREF-AC

Figure 4b. CML Interface (AC-Coupled)

VCC LVPECL GND IN /IN 0.1μF VT NC VREF-AC Note: For 3.3V, Rp = 50Ω. For 2.5V, Rp = 19Ω. SY58610U

Figure 4c. LVPECL Interface (DC-Coupled)
Option: May connect V_T to V_CC

VCC LVPECL GND RP RP VCC 0.1μF IN IN SY58610U VT VREF-AC Note: For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω.

Figure 4d. LVPECL Interface (AC-Coupled)

VCC LVDS IN /IN SY58610U GND NC □ VT NC □ VREF-AC

Figure 4e. LVDS Interface

LVPECL Output Termination

LVPECL output has very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50 and 100Ω - controlled impedance transmission lines. There are several techniques in terminating the LVPECL output, as shown in Figures 5a and 5b.

+3.3V Z₀ = 50Ω Z₀ = 50Ω GND +3.3V R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω GND +3.3V GND For 2.5V system:

For 2.5V system:
R1=250Ω, R2=62.5Ω

Figure 5a. Parallel Termination-Thevenin Equivalent

+3.3V Z₀ = 50Ω Z₀ = 50Ω GND +3.3V 50Ω 50Ω Vcc C (optional) 0.01μF R1 GND

For 2.5V system: R1 = 19Ω.
For 3.3V system: R1 = 50Ω.

Figure 5b. Three-Resistor "Y-Termination"
Related Product and Support Documents

Part Number	Function	Data Sheet Link
SY58609U 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input		http://www.micrel.com/_PDF/HBW/sy58609u.pdf
SY58611U 3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input		http://www.micrel.com/_PDF/HBW/sy58611u.pdf
HBW Solutions New Products and Termination Application Notes		http://www.micrel.com/page.do?page=/product-info/as/HBWsolutions.shtml

Package Information

Pin 1 Dot By Marking 3.000BSC 1 2 3 3.000BSC 16

TOP VIEW

1.60±0.100 Exp. DAP 0.500 BSC CHAMFER 0.30 X 45° 2 1.60±0.10 Exp. DAP 0.400±0.050 1.500 Ref.

VARIATION A

R0.20 1 2

VARIATION B
BOTTOM VIEW

0.850±0.050 0.05 C SEATING PLANE 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE. WARPAGE IS 0.05 mm
3. MAXIMUM ALLOWABLE BURRS IS 0.076 nm IN ALL DIRECTIONS
4. PIN #1 ID ON TOP VILL BE LASER/INK MARKED
PIN WTD ON TOP WILL BE LASER/INK MARKED. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED
DIMENSION AFFICES TO METALIZED TERMINAL AND BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP
A BETWEEN 0.20 AND 0.25 MTPR APPLIED ONLY FOR TERMINALS
APPLIED ONLY FOR TERMINALS. APPLIED FOR EXPOSED PAD AND TERMINALS.

16-Pin (3mm x 3mm) QFN

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

© 2006 Micrel, Incorporated.