SY58028U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58028U Microchip

■ Selects 1 of 4 differential inputs
■ Provides two copies of the selected input
■ Guaranteed AC performance over temperature and voltage:
- DC-to- > 10.7Gbps data rate throughput
• < 350ps IN-to-Out pd
• < 60ps r /t f times
■ Ultra low-jitter design:
• < 1 pp total jitter (clock)
• < 1 p random jitter
• < 1 0ppdeterministic jitter
• < 0.7ps crosstalk-induced jitter
■ Unique patended input design minimizes crosstalk
■ Accepts an input signal as low as 100mV
■ Unique patented input termination and V_T pin accepts DC- and AC-coupled inputs (CML, LVPECL, LVDS)
■ Internal 50Ω output source termination
■ 400mV CML output swing ( R_L = 50 )
■ Power supply 2.5V ±5% or 3.3V ±10%
■ -40^ to +85^ temperature range
■ Available in 32-pin (5mm × 5mm) MLF® package

APPLICATIONS

■ Redundant clock and/or data distribution
■ All SONET/SDH clock/data distribution
■ Loopback
■ All Fibre Channel distribution
■ All Gigabit Ethernet clock and/or data distribution

TYPICAL PERFORMANCE

Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

Precision Edge®

DESCRIPTION

The SY58028U is a 2.5V/3.3V precision, high-speed, 4:1 differential CML multiplexer capable of handling clocks up to 7GHz and data streams up to 10.7Gbps. In addition, a 1:2 fanout buffer provides two copies of the selected inputs.

The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The outputs are 50Ω source terminated CML, with extremely fast rise/fall times guaranteed to be less than 60ps.

The SY58028U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. For applications that require LVPECL outputs, consider the SY58029U or SY58030U Multiplexers. The SY58028U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at www.micrel.com.

FUNCTIONAL BLOCK DIAGRAM

graph TD
    subgraph Input
        IN0["IN0"] --> VTO["V_T0 50Ω"]
        IN0 --> /IN0["/IN0"]
        VREF_AC0["V_REF_AC0"] --> INV1["INV1 50Ω"]
        VREF_AC1["V_REF_AC1"] --> INV2["INV2 50Ω"]
        VREF_AC2["V_REF_AC2"] --> INV3["INV3 50Ω"]
        VREF_AC3["V_REF_AC3"] --> INV4["INV4 50Ω"]
    end
    subgraph Feedback
        INV1 --> MUX["4:1 MUX"]
        INV2 --> MUX
        INV3 --> MUX
        INV4 --> MUX
    end
    MUX --> Q0["Q0"]
    MUX --> Q1["Q1"]
    MUX --> Fanout["1:2 Fanout"]
    style MUX fill:#f9f,stroke:#333
    style Q0 fill:#ccf,stroke:#333
    style Q1 fill:#ccf,stroke:#333
    style Fanout fill:#cfc,stroke:#333

PACKAGE/ORDERING INFORMATION

/IN3 VREF-AC3 VT3 IN3 /IN2 VREF-AC2 VT2 IN2 IN0 32 31 30 29 28 27 26 25 1 GND VCC Q1 /Q1 VCC NC SEL1 VCC VREF-AC0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VREF-AC1 VCC IN0 IN1 IN3 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16

32-Pin MLF ^® (MLF-32)

Ordering Information ^(1)

Part Number	Package Type	Operating Range Marking	Package Finish	Lead
SY58028UMI	MLF-32	Industrial	SY58028U	Sn-Pb
SY58028UMITR(2)	MLF-32	Industrial	SY58028U	Sn-Pb
SY58028UMG(3)	MLF-32	Industrial	SY58028U with Pb-Free bar-line indicator	Pb-Free NiPdAu
SY58028UMGTR(2, 3)	MLF-32	Industrial	SY58028Uwith Pb-Free Pb-Free bar-line indicator	Pb-Free NiPdAu

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.

PIN DESCRIPTION

Pin Number Pin	Name Pin Function
1, 4 IN0, /IN05, 8 IN1, /IN125, 28 IN2, /IN29, 32	Differential Inputs: These inputs accept AC- or DC-coupled signals as small as 100mV.Each pin of a pair internally terminates to a VT _T pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. If an input pair is not used, connect one input of the pair to ground through a 1kΩ resistor and the complement to V_CC through a 825Ω resistor. Unused V_T and V_REF-AC may also be left open. Please refer to the “Input Interface Applications” section for more details.
2, 6, 26, 30 VT0	VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT _T VT2, VT3 pin. The VT _T pin provides a center-tap to the termination network for maximum interface flexibility. See “Input Interface Applications” section for more details.
15, 18 SEL0,	SEL1 This single-ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Input logic threshold is V_CC/2 . See “Truth Table” for select control.
14, 19 NC No	Connect.
10, 13, 1617, 20, 23	VCC	Positive Power Supply: Bypass with 0.1μF||0.01μF low ESR capacitors.
11, 12/Q0, Q021, 22/Q1, Q1	Differential Outputs: These CML output pairs are copies of the selected input. Unused output pairs may be left floating. See “Output Interface” section for termination guidelines.
9, 24	GND,Exposed Pad	Ground. Ground pin and exposed pad must be connected to the same ground plane.
3, 7, 27, 31	VREF-AC0VREF-AC1VREF-AC2VREF-AC3	Reference Voltage: This reference output is equivalent to V_CC-1.4V . It is used for AC-coupled inputs. When interfacing to AC input signals, connect V_REF-AC directly to the V_T pin and bypass with 0.01μF low ESR capacitor to V_CC . See “Input Interface Applications” section. Maximum sink/source current is 0.5mA.

TRUTH TABLE

SEL1	SEL0
0	0	IN0 Input Selected
0	1	IN1 Input Selected
1	0	IN2 Input Selected
1	1	IN3 Input Selected

Absolute Maximum Ratings ^(1)

Power Supply Voltage ( V_CC ) ..... -0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

CML Output Voltage ( V_OUT )..... V_CC-1.0V to V_CC+0.5V

Termination Current ^(3)

Source or sink current on V_T pin ....±100mA Input Current

Source or sink current on IN, /IN pin ....±50mA

Lead Temperature (soldering, 20 sec.) 260°C

Storage Temperature Range ( T_S ) ..... -65°C to +150°C

Operating Ratings ^(2)

Power Supply Voltage ( V_CC ) ..... +2.375V to +2.625V ..... +3.0V to +3.6V

Ambient Temperature Range ( T_A ) ..... -40°C to +85°C

Package Thermal Resistance ^(4)

MLF ^ ( _JA ) Still-Air 35°C/W

MLF ^ ( _JB ) Junction-to-Board ....2°C/W

DC ELECTRICAL CHARACTERISTICS ^(5)

T_A=-40^ to 85^ , unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_CC	Power Supply Voltage V	_CC = 2.5V 2.375 2.5 2.625 V V_CC = 3.3V 3.0 3.3 3.6	V
I_CC	Power Supply Current	No load, max. V_CC		120	150 mA
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		80 100	120 Ω
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		40	50	60	Ω
V_IH	Input HIGH Voltage (IN-to-/IN)	Note 6	V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage (IN-to-/IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN-to-/IN)	See Figure 1a.	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing (IN-to-/IN)	See Figure 1b.	0.2			V
V_T IN	Max Input Voltage (IN-to- V_T )				1.28	V
V_REF-AC	Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability, use for input of the same package only.
4. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential (GND) on the PCB. _JB uses 4-layer _JA in still air number unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IH (min) not lower than 1.2V.

CML OUTPUT DC ELECTRICAL CHARACTERISTICS ^(7)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to 85^ C ; R_L = 100 across each output pair or equivalent; unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_OH	Output HIGH Voltage V		_CC-0.020 V	_CC	V
V_OUT	Output Voltage Swing See Figure 1a. 325 400 mV
V_DIFF\_OUT	Differential Output Voltage Swing See Figure 1b. 650 800 mV
R_OUT	Output Source Impedance 40 50 60 Ω

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS ^(7)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_IH	Input HIGH Voltage	SEL0, SEL1	2.0			V
V_IL	Input LOW Voltage	SEL0, SEL1			0.8	V
I_IH	Input HIGH Current				40	μA
I_IL	Input LOW Current				-300	μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS ^(8)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 100 across each output pair, or equivalent; T_A = -40^ to +85^ , V_IN ≥ 100mV unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
f_MAX	Maximum Operating Frequency NRZ	Data 10.7 Gbps
		V_OUT ≥ 200mV Clock 7 GHz
t_pd	Propagation Delay (Diff) (IN to Q) V (SEL to Q)	≥ 100mV	170	260	340	ps
			100		500	ps
t_pd Tempco	Differential Propagation Delay Temperature Coefficient			115		fs/°C
t_SKEW	Output-to-Output Part-to-Part	Note 9		7	20	ps
		Note 10			50	ps
t_JITTER	Data Random Jitter Deterministic Jitter	Note 11 2.5Gbps to 3.2Gbps			1	ps_RMS
		Note 12 2.5Gbps to 3.2Gbps			10	ps_PP
	Clock Cycle-to-Cycle Jitter Total Jitter	Note 13			1	ps_RMS
		Note 14			10	ps_PP
	Crosstalk Induced Jitter (Adjacent Channel)	Note 15			0.7	ps_RMS
t_r, t_f	Output Rise/Fall Time	20% to 80%, Full output swing	20	45	60	ps

Notes:

1. High frequency AC electricals are guaranteed by design and characterization.
2. Output-to-output skew is measured between outputs under identical input conditions.
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
4. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps to 3.2Gbps.
5. Deterministic jitter is measured at 2.5Gbps to 3.2Gbps, with both K28.5 and 2^23-1 PRBS pattern.
6. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T_n - T_n-1 where T is the time between rising edges of the output signal.
7. Total jitter definition: with an ideal clock input of frequency ≤ f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
8. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs.

SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_{IN}, \nV_{OUT} 400mV (Typ.)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 800mV (Typ.)

Figure 1b. Differential Voltage Swing

TIMING DIAGRAMS

IN /IN tpd tpd Q /Q VIN VOUT

Figure 2a. IN-to-Q Timing Diagram

SEL Vco/2 Vco/2 tpd tpd Q /Q VOUT

Figure 2b. SEL-to-Q Timing Diagram

SEL0 Q: SEL1 = LOW; IN0, /IN1 = LOW; /IN0, IN1 = HIGH or: SEL1 = HIGH; IN2, /IN3 = LOW; /IN2, IN3 = HIGH

SEL1 Q: SEL0 = LOW; IN0, /IN2 = LOW; /IN0, IN2 = HIGH or: SEL0 = HIGH; IN1, /IN3 = LOW; /IN1, IN3 = HIGH

FUNCTIONAL CHARACTERISTICS

V_CC = 2.5V, GND = 0, V_IN = 100mV, T_A = 25^, unless otherwise stated.

7Gbps Output (2^23-1 PRBS) Output Swing (100mV/div.) TIME (50ps/div.)

10.7Gbps Output (2²³-1 PRBS) Output Swing (100mV/div.) TIME (25ps/div.)

TYPICAL OPERATING CHARACTERISTICS

V_CC = 2.5V , GND = 0, V_IN = 100mV , T_A = 25^ , unless otherwise stated.

INPUT STAGE

VCC IN 50Ω VT 50Ω /IN GND

Figure 3. Simplified Differential Input Stage

INPUT INTERFACE APPLICATIONS

Vcc CML IN /IN GND SY58028U NC □ VREF-AC NC □ VT

Figure 4a. DC-Coupled CML Interface
Option: May connect V_T to V_CC

Vcc CML IN /IN GND Vcc 0.01μF SY58028U VREF-AC VT

Figure 4b. CML Interface (AC-Coupled)

Vcc LVPECL GND IN /IN SY58028U NC VREF-AC VCC 0.01μF Rpd For a 3.3V system, Rpd = 50Ω For a 2.5V system, Rpd = 19Ω

Figure 4c. DC-Coupled PECL Interface

Vcc LVPECL IN Rpd Rpd GND 0.01μF SY58028U IN VREF-AC VT Vcc For a 3.3V system, Rpd = 100Ω For a 2.5V system, Rpd = 50Ω

Figure 4d. AC-Coupled LVPECL Interface

Vcc LVDS IN /IN GND SY58028U NC □ VREF-AC NC □ VT

Figure 4f. LVDS Interface

OUTPUT INTERFACE APPLICATIONS

Vcc SY58028U 50Ω50Ω Q Zo = 50Ω /Ω 100Ω Zo = 50Ω 16mA GND

Figure 5a. CML DC-Coupled (100Ω Termination)

VCC SY58028U 50Ω50Ω Q ZO = 50Ω 50Ω /Q 50Ω ZO = 50Ω DC bias per application 16mA GND

Figure 5b. CML AC-Coupled (50Ω Termination)

RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION

Part Number Function Data Sheet Link
SY58028U Ultra	Precision Differential CML 4:1 MUX http://www.micrel.com/product-info/products/sy58028u.shtmlwith 1:2 Fanout and Internal I/O Termination
SY58029U	Ultra Precision Differential LVPECL 4:1 MUX with 1:2 Fanout and Internal Termination	http://www.micrel.com/product-info/products/sy58029u.shtml
SY58030U Ultra	Precision, 400mV Differential LVPECL 4:1 http://www.micrel.com/product-info/products/sy58030u.shtmlMUX with 1:2 Fanout and Internal Termination
	MLF® Application Note www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf
HBW Solutions	New Products and Applications www.micrel.com/product-info/products/solutions.shtml

32-PINMicroLeadFrame® (MLF-32)

5.0 BSC 32 1 2 PIN #1 ID 0.20 DIA TYP. 5.0 BSC

TOP VIEW

0.25地厚 32X 0.20 MIN. 3.10±0.10 0.40±0.05 4X 0.50 BSC 32 PIN #1 ID R0.20 1 2 3.10±0.10

BOTTOM VIEW

NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

SIDE VIEW

Package EP- Exposed Pad Dia CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane VFE VSE Heavy Copper Plane

PCB Thermal Consideration for 32-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 [phone] FAX + 1 (408) 474-100 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

© 2005 Micrel, Incorporated.