SY58023U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58023U Microchip

■ Guaranteed AC performance over temperature and voltage:

• 10.7Gbps data throughput

• <60ps t r /t f times
  • <285ps t pd (IN-to-Q)
• <20ps skew

■ Low jitter:

• <10ps pp total jitter (clock)
• <1ps rms random jitter (data)
• <10ps pp deterministic jitter (data)

■ Crosstalk induced jitter: <0.7ps rms
■ Accepts an input signal as low as 100mV
■ Unique input termination and V_T pin accepts DC-coupled and AC-coupled differential inputs: LVPECL, LVDS, and CML
■ 50Ω source terminated CML outputs
■ Fully differential inputs/outputs
■ Power supply 2.5V ±5% and 3.3V ±10%
■ Industrial -40°C to +85°C temperature range
■ Available in 16-pin (3mm × 3mm) MLF® package

Precision Edge®

DESCRIPTION

The SY58023U is a 2.5V/3.3V precision, high-speed, fully differential CML 2 ×2 crosspoint switch. The SY58023U is optimized to provide two identical output copies with less than 20ps of skew and ultra-low jitter. It can route clock signals as fast as 6GHz or data up to 10.7Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that allows the SY58023U to directly interface to LVPECL, LVDS, and CML differential signals (AC- or DC-coupled) as small as 100mV (200mV _pp ) without any level-shifting or termination resistor networks in the signal path. The CML outputs features 400mV typical swing into 50Ω loads, and provide an extremely fast rise/fall time guaranteed to be less than 60ps.

The SY58023U operates from a +2.5V ±5% supply or +3.3V ±10% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). For applications that require high speed dual CML switches, consider the SY58024U. The SY58023U is part of Micrel's high-speed, Precision Edge® product line.

Datasheets and support documentation can be found on Micrel's website at www.micrel.com.

APPLICATIONS

■ Gigabit Ethernet data/clock routing
■ SONET data/clocking routing
■ Switch fabric clock routing
■ Redundant switchover
■ Backplane redundancy

FUNCTIONAL BLOCK DIAGRAM

SEL0 (TTL/CMOS) IN0 50Ω V_T0 50Ω /IN0 SEL1 (TTL/CMOS) IN1 50Ω V_T1 50Ω /IN1 0 Q0 1 /Q0 0 Q1 1 /Q1

Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

PACKAGE/ORDERING INFORMATION

VT0 SEL0 GND VCC IN0 16 15 14 13 /IN0 2 12 Q0 IN1 3 11 /Q0 4 10 /IN1 9 Q1 IN1 5 6 7 8 VT1 SEL1 GND VCC

16-Pin MLF ^® (MLF-16)

Ordering Information ^(1)

Part Number	Package Type Range	Operating	Package		Lead
			Marking	Finish
SY58023UMI	MLF-16	Industrial	023U	Sn-Pb
SY58023UMITR(2)	MLF-16	Industrial	023U	Sn-Pb
SY58023UMG(3)	MLF-16	Industrial	023U with Pb-Free bar-line indicator		Pb-Free NiPdAu
SY58023UMGTR(2, 3)	MLF-16	Industrial	023U with Pb-Free bar-line indicator		Pb-Free NiPdAu

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A=25^ , DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.

PIN DESCRIPTION

Pin Number Pin	Name Pin Function
1, 2,3, 4 /IN1, IN	IN0, /IN0,1 Note that this input	Differential Signal Input: Each pin of this pair internally terminates with 50 to the VT pin. will default to an indeterminate state if left open.See “Input Interface Applications” section.
16, 5 VT0, VT	T1 Input Termination	Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See “Input Interface Applications” section.
15, 6 SEL0,	SEL1 Select Input: TT	L/CMOS select input control that selects inputs IN0, or IN1. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic High state if left open.
7, 14 GND,	Ground. Exposed pad(Exposed Pad) the	must be connected to a ground plane that is the same potential as device ground pin.
8, 13	VCC	Positive Power Supply: Bypass with 0.1 F||0.01 F low ESR capacitors as close to the pins as possible.
12, 11, 10, 9	Q0, /Q0, /Q1, Q1	CML Differential Output Pairs: Differential buffered output copy of the selected input signal. The CML output swing is typically 400mV across 100 . Unused output pairs may be left floating with no impact on jitter. See “CML Output Termination” section.

TRUTH TABLE

SEL0	SEL1	Q0	Q1
L	L	IN0	IN0
L	H	IN0	IN1
H	L	IN1	IN0
H	H	IN1	IN1

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_CC ) -0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

CML Output Voltage ( V_OUT )..... V_CC-1.0V to V_CC+0.5V

Current ( V_T )

Source or Sink Current on V_T pin ....±100mA

Input Current ( V_T )

Source or Sink Current on IN, /IN....±50mA

Lead Temperature (soldering, 20 sec.) 260°C

Storage Temperature ( T_S ) -65^ + 150^

Operating Ratings ^(2)

Supply Voltage (V _CC ) ....+2.375V to +3.60V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3)

MLF® (θJA)

Still-Air 60°C/W

500lfpm 54°C/W

MLF® (ψJB)

Junction-to-board 38°C/W

DC ELECTRICAL CHARACTERISTICS ^(4)
T_A = -40^ to +85^ .

Symbol Parameter Condition Min Typ Max Units
V_CC	Power Supply Voltage 2.5V nominal	2.375 2.5 2.625 V3.3V nominal	3.0	3.3	3.60	V
I_CC	Power Supply Current	V_CC = max., current through internal 50 source termination resistor included.		100	130	mA
V_IH	Input HIGH Voltage	IN, /IN, Note 5	V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage	IN, /IN	0		V_IH-0.1	V
V_IN	Input Voltage Swing	IN, /IN; see Figure 1a.	0.1		1.7	V
V_DIFF\_IN	Differential Input Swing	IN, /IN; see Figure 1b.	0.2			V
R_IN	IN-to- V_T Resistance		40	50	60	Ω
IN to V_T					1.28	V

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS ^(4)
V_CC = 2.5V ± 5% or 3.3V ± 10%; T_A = -40^ to 85^

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current				40	μA
I_IL	Input LOW Current		-300			μA

Notes:

1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential (GND) on the PCB. _JA uses 4-layer in still-air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IH (min) not lower than 1.2V.

CML OUTPUT DC ELECTRICAL CHARACTERISTICS ^(6)
V_CC = +3.3V ± 10% or +2.5V ± 5% ; R_L = 100 across each output pair; T_A = -40^ to +85^ , unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_OH	Output HIGH Voltage Q0, /Q0; Q1, /Q1 V	_CC -0.020 V		_CC	V
V_OUT	Output Voltage Swing Q0, /Q0; Q1, /Q1; see Figure 1a. 325 400 500 mV
V_DIFF\_OUT	Differential Voltage Swing Q0, /Q0; Q1, /Q1; see Figure 1b. 650 800 1000 mV
R_OUT	Output Source Impedance	Q0, /Q0; Q1, /Q1	40	50	60

Notes:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established

AC ELECTRICAL CHARACTERISTICS ^(7)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 100 across each output pair; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition		Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency V	IN≥100mV; V_OUT ≥200mV	Clock	6			GHz
		NRZ Data		10.7			Gbps
t_pd	Propagation Delay	IN-to-Q		135		285	ps
		SEL-to-Q		100		400	ps
t_SKEW	Channel-to-Channel Skew (Within Bank)	Note 8				20	ps
	Part-to-Part Skew	Note 9				75	ps
t_JITTER	Clock Cycle-to-Cycle Jitter	Note 10				1	ps_RMS
	Total Jitter	Note 11				10	ps_PP
	Data Random Jitter	Note 12				1	ps_RMS
	Deterministic Jitter	Note 13				10	ps_PP
	Crosstalk Induced Jitter (Adjacent Channel)	Note 14				0.7	ps_RMS
t_r,t_f	Output Rise/Fall Time	20% to 80%, at full swing.		25		60	ps

Notes:

1. Measured with 100mV input swing. High frequency AC-parameters are guaranteed by design and characterization.
2. Skew is measured between outputs of the same bank under identical transitions.
3. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
4. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T_n - T_n-1 where T is the time between rising edges of the output signal.
5. Total jitter definition: With an ideal clock input of frequency ≤ f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
6. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps–3.2Gbps.
7. Deterministic jitter is measured at 2.5Gbps–3.2Gbps with both K28.5 and 2^23 -1 PRBS pattern.
8. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying similar, differential clock frequencies that are asynchronous with respect to each other at inputs.

SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_{IN} V_{OUT} Typ. 400mV

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN VDIFF_OUT (Typ. 800mV)

Figure 1b. Differential Voltage Swing

TIMING DIAGRAM

/IN IN /Q Q VOUT = 400mV (typ.) (50Ω load) tpd tpd VOUT = 400mV (typ.) (50Ω load)

Figure 2a. AC Timing Diagram IN-to-Q

SEL VCC/2 VCC/2 tpd tpd /Q Q VOUT = 400mV (typ.) (50Ω load) IN0, /IN1 = LOW, /IN0, IN1 = HIGH

Figure 2b. AC Timing Diagram SEL-to-Q

TYPICAL OPERATING CHARACTERISTICS

V_CC = 2.5V, V_IN = 100mV, T_A = 25^ , unless otherwise noted.

Frequency vs. Amplitude

Propagation Delay vs. Temperature

Propagation Delay vs. Input Voltage Swing

Within Device Skew vs. Temperature

FUNCTIONAL CHARACTERISTICS

V_CC = 2.5V, V_IN = 100mV, T_A = 25^ , unless otherwise noted.

INPUT STAGE

VCC IN 50Ω VT 50Ω /IN GND

Figure 3. Simplified Differential Input Buffer

INPUT INTERFACE APPLICATIONS

Vcc CML IN /IN NC VT SY58023U Vcc

Option: may connect V_T to V_CC

Figure 4a. DC-Coupled CML Input Interface

VCC CML IN IN SY58023U R1 0.01μF VT R2

For 2.5V, R1 = 1kΩ, R2 = 1.1kΩ. For 3.3V, R1 = 649Ω, R2 = 1kΩ.

Figure 4b. AC-Coupled CML Input Interface

Vcc LVPECL IN /IN SY58023U 0.01μF Rpd VT Vcc

For V_CC = 2.5V , R_pd = 19 . For V_CC = 3.3V , R_pd = 50 .

Figure 4c. DC-Coupled LVPECL Input Interface

Vcc LVPECL Rpd Rpd R1 0.01μF R2 VT IN /IN SY58023U Vcc

For V_CC=2.5V , R_pd=50 , R1=1k , R2=1.1k . For V_CC=3.3V , R_pd=100 , R1=649 , R2=1k .

Figure 4d. AC-Coupled LVPECL Input Interface

Vcc LVDS IN /IN NC VT SY58023U Vcc

Figure 4e. LVDS Input Interface

CML OUTPUT TERMINATION

Figures 5 and Figure 6 illustrates how to terminate a CML output using both the AC-coupled and DC-coupled
configuration. All outputs of the SY58023U are 50Ω with a 16mA current source.

Vcc 50Ω 50Ω Q /Ω 100Ω 16mA GND

Figure 5. CML DC-Coupled Termination

Vcc 50Ω 50Ω Q 50Ω 50Ω /Q 16mA GND DC-bias per application

Figure 6. CML AC-Coupled Termination

RELATED PRODUCT AND SUPPORT DOCUMENTATION

Part Number	Function Data Sheet Link
SY58023U	Ultra-low Jitter 2x2 Crosspoint Switch w/CML Outputs and Internal I/O Termination	http://www.micrel.com/product-info/products/sy58023u.shtml
SY58024U	Ultra-low Jitter Dual 2x2 Crosspoint Switch w/CML Outputs and Internal I/O Termination	http://www.micrel.com/product-info/products/sy58024u.shtml
	16-MLF® Manufacturing Guidelines Exposed Pad Application Note	www.amkor.com/products/notes_papers/MLF_AppNote.pdf
	HBW Solutions http://www.micrel.com/product-info/as/solutions.shtml

16-PIN MicroLeadFrame® (MLF-16)

Pin 1 Dot By Marking 3.000±0.050 3.000±0.050

TOP VIEW

1.550±0.050 Exp. DAP PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 0.400±0.050 1.550±0.050 Exp. DAP 0.500 Bsc 0.230±0.050 0.400±0.050 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane Heavy Copper Plane VEE VEE

PCB Thermal Consideration for 16-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 [phone] FAX + 1 [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

© 2005 Micrel, Incorporated.