SY88083L - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY88083L Microchip

The SY88083L limiting post amplifier is designed for use in fiber-optic receivers for continuous mode, multi-rate applications from 1Gbps to 12.5Gbps.

The SY88083L contains a high-bandwidth, high-sensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables optimized system reach. Typically, 4dB of electrical hysteresis is provided to minimize LOS or SD chattering caused by noisy input signals. A logic level control pin is provided to enable user selection of an open-collector, TTL-compatible LOS or SD status indication signal with an external 5kΩ to 10kΩ pull-up resistor.

The SY88083L provides faster SD assert and LOS de-assert times than typical continuous mode devices over the entire differential input voltage range of 10mV_PP to 1800mV_PP .

The SY88083L input stage also provides a user-selectable digital offset correction (DOC) function to automatically compensate for internal device offsets in the high-speed data path.

The SY88083L provides integrated 50Ω input and output impedances to optimize the high-speed signal paths and reduce component count. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD signal. The JAM input disables only the post amplifier output.

The SY88083L operates from a single +3.3V power supply, over temperatures ranging from -40^ to +85^ .

Datasheets and support documentation are available on Micrel's web site at: www.micrel.com.

Features

• Multi-rate operation from 1.0625Gbps to 12.5Gbps
• Selectable digital offset correction for internal offset compensation in the high-speed data path
• Wide differential input range (10mV PP to 1800mV PP )
• Wide SD de-assert or LOS assert threshold range
• 4.5mV PP to 30mV PP - 4dB typical electrical hysteresis
• Fast SD assert and LOS de-assert times
• 1μs typical; 2μs maximum

- Selectable LOS or SD status signal indicator

- TTL-compatible JAM input with internal pull-up

- Low-noise CML data inputs with integrated 50Ω termination impedance to internal reference V _REF

- Low-noise CML data outputs with integrated 50Ω termination impedance

- 30ps typical rise/fall times

- Wide range power supply: 3.3V ±10%

- Industrial temperature range: -40^ to +85^

• Available in a tiny 3mm × 3mm QFN package

Applications

• 10G/8G Fibre Channel
• 10Gigabit Ethernet
- OTN equipment
• SONET OC192; SDH STM64
• WDM/DWDM systems

Markets

• Fibre Channel storage area networks
- Datacom/Enterprise
• High-performance computing
- Telecom
- Wireless base stations

Typical Application Circuit

SD/LOS_SEL SQUELCH DOC_EN DOC_EN JAM SD/LOS_SEL TEST GND 16 15 14 13 Vcc Vcc = 3.3V DATA_IN+ 100n RXIN+ 2 SY88083L 16-pin 3mm x 3mm QFN (Top View) 12 11 DATA_OUT+ 100n 50Ω Lines RXOUT+ 50Ω Lines DATA_IN- 100n RXIN- 3 10 RXOUT- 100n DATA_OUT- 9 GND 4 5 6 7 8 Vcc NC NC SD/LOS SD/LOSLVL Rsd/LOSLVL SQUELCH 10n 10n 100n

Ordering Information

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY88083LMG	3mm × 3mm QFN-16	Industrial	083L with Pb-Free bar-line indicator	NiPdAu Pb-Free
SY88083LMG TR ^(1)	3mm × 3mm QFN-16	Industrial	083L with Pb-Free bar-line indicator	NiPdAu Pb-Free

Note:

1. Tape and reel.

Pin Configuration

PIN 1 INDICATOR (TOP OF PACKAGE) DOC_EN JAM SD/LOS_SEL TEST GND 16 15 14 13 Vcc RXIN+ 2 RXIN- 3 GND 4 E-PAD (GND) (BOTTOM OF PACKAGE) 5 NC 6 7 8 SD/LOS SD/LOSLVL Vcc 12 11 10 9 SD/LOSYL IT BE CONNECTED TO NEGATIVE POWER

NOTE: E-PAD MUST BE CONNECTED TO THE PCB NEGATIVE POWER SUPPLY PLANE USING THE RECOMMENDED VIA ARRAY
16-Pin 3mm × 3mm QFN (Top View)

Pin Description

Pin Number	Pin Name	Pin Type	Pin Function
1 GND		Negative Supply Rail	Negative Supply Rail. Connect to the PCB negative power supply plane that is also connected to the ePad.
2 RXIN+		High-Speed Data Input	Differential Noninverting Data Input. LVPECL/CML compatible. AC-coupled with 100nF (high-frequency, low-ESR capacitor is recommended).Internally terminated with 50 to V_CC - 0.9V . AC-coupled only.
3	RXIN-	High-Speed Data Input	Differential Inverting Data Input. LVPECL/CML-compatible. AC-coupled with 100nF (high-frequency, low-ESR capacitor is recommended).Internally terminated by 50 to V_CC - 0.9V . AC-coupled only.
4 GND		Negative Supply Rail	Negative Supply Rail. Connect to the PCB negative power supply plane that is also connected to the ePad.
5	NC	No Connect	No Connect. Do not connect to logic circuits or power supply rails.
6	NC	No Connect	No Connect. Do not connect to logic circuits or power supply rails.
7 SD/LOS		Open Collector Logic Output	Output Status Indicator. Loss-of-signal (LOS) or signal detect (SD) open collector output externally terminated with 5k to 10k resistor to V_CC . TTL compatible.LOS = High when RXIN± amplitude falls below the threshold set at the SD/LOSLVL pin.SD = Low when RXIN± amplitude falls below the threshold set at the SD/LOSLVL pin.
8 SD/LOSLVL Analog Input			Analog control input. Sets the trigger threshold for the LOS or SD status indicator signals.If SD/LOS_SEL = High (LOS selected), connect a resistor from the SD/LOSLVL pin (loss of signal threshold level) to V_CC to adjust the LOS Assert threshold for the RXIN± data inputs.If SD/LOS_SEL = Low (SD selected), connect a resistor from the SD/LOSLVL pin (signal detect threshold level) to V_CC to adjust the SD_De-assert threshold for the RXIN± data inputs.
9, 12 V	cc	Positive Supply Rail	Positive power supply input. Bypass with a 0.1 F capacitor in parallel with a 0.01 F low-ESR capacitor to GND as close as possible to the V_CC pin.
10	RXOUT-	High-Speed Data Output	Differential inverting data output. CML compatible and internally terminated by 50 to V_CC . Can be AC- or DC-coupled to downstream devices.
11 RXOUT+		High-Speed Data Output	Differential noninverting data output. CML compatible and internally terminated by 50 to V_CC . Can be AC- or DC-coupled to downstream devices.
13	TEST	Test Pin	Factory test pin. For factory use only. Do not connect to logic circuits or power supply rails.
14	SD/LOS_SEL	Logic Level Input	Input control signal. TTL-compatible logic input signal to select LOS or SD as the output signal. Internal ~ 18k pull-up to V_CC .Default = High (NC): LOS selected – normal operationLOS/SD_SEL = Low: SD selected and JAM operation is inverted
15	JAM	Logic Level Input	Input control signal. TTL-compatible input signal that enables or disables the RXOUT± output signals. Internal 27k pull-up resistor to V_CC . Can be connected to SD/LOS to form a SQUELCH function.When SD/LOS_SEL = HighDefault = High and RXOUT± outputs are disabled.Low = RXOUT± outputs are enabledOperation is inverted when SD/LOS_SEL = Low and SD is selected.
16 DOC_EN		Logic Level Input	Input Control Signal. TTL-compatible logic input signal that enables or disables the digital offset correction (DOC) circuit.Default:DOC_EN = High = Enable with internal 18kΩ pull-up to V_CC if not connected to an external logic low or high signal.DOC_EN = Low disables the digital offset correction function.Toggling the DOC_EN signal from high to low to high will cause a reset of the DOC circuitry and initiate a new DOC routine to lock in new DOC values.Note:Digital offset correction is not applied to large input signals.
ePad GND		Negative Supply Rail	Exposed Thermal Pad. Must be soldered to PCB plane connected to the negative supply rail. The recommended via array is needed to remove heat from the device.

Absolute Maximum Ratings ^(2)

Supply Voltage ( V_cc )....0V to +4.0V

Input Voltage (RXIN±) V_cc - 1.5V to V_cc

CML Output Voltage ( V_OUT ).... V_CC - 1.0V to V_CC + 0.5V

JAM Voltage 0 to Vcc

SD/LOSLVL Voltage V_cc - 1.3V to V_cc

Lead Temperature (soldering, 20s).... 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(3)

Supply Voltage ( V_cc )....+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Junction Temperature ( T_J ) -40^ to +120^

Package Thermal Resistance ^(4)

QFN ( _JA ) Still-Air....60°C/W

QFN (ψ JB)....33°C/W

DC Electrical Characteristics

V_CC = 3.0 to 3.6V; T_A = -40^ to +85^, typical values at V_CC = 3.3V, T_A = 25^.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
I_CC	Power Supply Current	Note 5		60	75	mA
SD/LOSLVL	SD or LOS Threshold Voltage		V_CC - 1.3		V_CC	V
V_OH	RXOUT±High Voltage		V_CC - 0.020	V_CC - 0.005	V_CC	V
V_OL	RXOUT±Low Voltage		V_CC - 0.400	V_CC - 0.350	V_CC - 0.300	V
V_OS\_DOC\_ON	Differential Output Offset	Digital Offset Correction = ON		±10		mV
Z_0	Single-Ended Output Impedance		45	50	55	Ω
Z_I	Single-Ended Input Impedance		45	50	55	Ω

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions may affect device reliability.
2. The datasheet limits are not guaranteed if the device is operated beyond the recommended operating conditions.
3. Package thermal resistance assumes that the exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JB and 0_JA assumes still air and a 4-layer PCB, unless otherwise stated. It also assumes that the recommended via pattern and via sizes on the PCB are used.
4. DOC is enabled, outputs RXOUT± are loaded with external 50Ω loads, and the outputs are enabled.

TTL DC Electrical Characteristics
V_CC = 3.0 to 3.6V; T_A = -40^ C to +85^ C, typical values at V_CC = 3.3V, T_A = 25^ C.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
V_IH	JAM, DOC_EN, SD/LOS_SEL Input High Voltage		2.0			V
V_IL	JAM, DOC_EN, SD/LOS_SEL Input Low Voltage				0.8 V
I_IH	JAM, DOC_EN, SD/LOS_SEL Input High Current	V_IN = 2.7V			20	μA
		V_IN = V_CC			100
I_IL	JAM, DOC_EN, SD/LOS_SEL Input Low Current	V_IN = 0.4V	-0.3			mA
V_OH	SD or LOS Output High Level	Sourcing 100μA	2.4			V
V_OL	SD or LOS Output Low Level	Sinking 2mA			0.4 V

AC Electrical Characteristics

V_CC = 3.3V ± 10% , T_A = -40^ C to +85^ C . Typical values at V_CC = 3.3V , T_A = 25^ C ; R_LOAD = 50 to V_CC .

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
t_r, t_f	Output Rise/Fall Time(20% to 80%)	Note 6		30	45	ps
t_JITTER	Deterministic	Note 7		10		ps
	Random	Note 8		1
V_ID	Differential Input Voltage Swing	Note 10. See Figure 1.	10		1800	mV_PP
V_OD	Differential Output Voltage Swing	Note 6	600	700	800	mV_PP
t_LOS\_D; t_LOS\_A t_SD\_D; t_SD\_A	LOS De-assert, LOS Assert TimeSD De-assert, SD Assert Time	Note 11		1	2	us
LOS_AM\_10k	Medium LOS Assert Level R	_LOSLVL = 10k, Note 9		4.5		mV_PP
LOS_DM\_10k	Medium LOS De-assert Level	R_LOSLVL = 10k, Note 9		7.3		mV_PP
HYS_M\_10k	Medium LOS Hysteresis	R_LOSLVL = 10k, Note 12	2	4.1	6	dB
LOS_AH1\_1k	High1 LOS Assert Level	R_LOSLVL = 1k, Note 9		18.6		mV_PP
LOS_DH1\_1k	High1 LOS De-assert Level	R_LOSLVL = 1k, Note 9		28.3		mV_PP
HYS_H1\_1k	High1 LOS Hysteresis	R_LOSLVL = 1k, Note 12	2	3.6	6	dB
LOS_AH2\_100	High2 LOS Assert Level	R_LOSLVL = 100, Note 9		29.7		mV_PP
LOS_DH2\_100	High2 LOS De-assert Level	R_LOSLVL = 100, Note 9		44.6		mV_PP
HYS_H2\_100	High2 LOS Hysteresis	R_LOSLVL = 100, Note 12	2	3.5	6	dB
A_V(Diff)_063C	Differential Voltage Gain			44		dB
S_21\_063C	Single-Ended Small-Signal Gain		32	38		dB
t_DOC\_DELAY	DOC Delay Time			15		μs
t_DOC\_LOCK	DOC Lock Time			150		μs

Note:
6. Amplifier is in limiting mode. Input is a 200MHz square wave.
7. Deterministic jitter is measured using 10Gbps K28.5 pattern, V_ID = 20mVPP .
8. Random jitter is measured using 10Gbps K28.7 pattern, VID = 20mV_PP .
9. See "Typical Operating Characteristics" for a graph showing how to choose a particular R_LOSLVL for a particular LOS assert and its associated de-assert amplitude.
10. Differential input swing amplitude for data rates up to 12.5Gbps
11. In real world applications, the LOS de-assert/assert time can be strongly influenced by the RC time constant of the AC-coupling capacitor and the 50Ω input termination. To keep this time low, use a decoupling capacitor with the lowest value that is allowed by the data rate and the number of consecutive identical bits in the application (typical values are in the range of 0.001μF to 0.1μF).
12. This specification defines electrical hysteresis as 20log (LOS de-assert/LOS assert). The ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2, depending on the level of received optical power and ROSA characteristics.

Typical Operating Characteristics

V_CC = 3.3V, T_A = 25^, R_LOAD = 50 to V_CC, unless otherwise stated.

20 ps/div, Typical 10.3G Output with 10mVpp Input Signal

20 ps/div, Typical 12.5G Output with 10mVPP Input Signal

Functional Block Diagram

graph TD
    NC["NC"] --> Vcc["Vcc - 0.9V"]
    Vcc --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω]
    RXIN+ --> IIP["Buffer/AMP"]
    RXIN- --> IIP
    IIP --> AMP["AMP"]
    IIP --> PRE-Driver["PRE-DRIVER"]
    IMP --> Pre-Driver
    PRE-Driver --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω]
    50Ω --> 50Ω[50Ω] --> RXOUT+
    RXOUT- --> PRE-Driver
    PRE-Driver --> DC["DC"]
    PRE-Driver --> TTL["BUFFER"]
    TTL["BUFFER"] --> LevelDetect["LEVEL DETECT"]
    LevelDetect --> Delay["Delay"]
    Delay --> SD/LOSLVL["SD/LOSLVL"]
    SD/LOSLVL --> Buffer["BUFFER"]
    Buffer --> LevelDetect
    LevelDetect --> Delay
    Delay --> JAM["JAM"]
    Delay --> SD/LOS_SEL["SD/LOS_SEL"]
    Delay --> SD/LOS["SD/LOS"]
    style NC fill:#f9f,stroke:#333
    style RXIN+ fill:#ccf,stroke:#333
    style RXIN- fill:#ccf,stroke:#333
    style IIP fill:#dfd,stroke:#333
    style AMP fill:#dfd,stroke:#333
    style PRE-Driver fill:#dfd,stroke:#333
    style TTL fill:#dfd,stroke:#333
    style Speed fill:#dfd,stroke:#333
    style Delay fill:#dfd,stroke:#333
    style JAM fill:#dfd,stroke:#333
    style SD/LOS_SEL fill:#dfd,stroke:#333
    style SD/LOS fill:#dfd,stroke:#333

Functional Description

The SY88083L is a high-sensitivity, high-bandwidth limiting post amplifier. It operates from a single +3.3V power supply across the entire industrial temperature range of -40^ to +85^ .

Signals with data rates from 1.0625Gbps to 12.5Gbps and amplitudes as small as 10mV_PP are supported. Figure 1 shows the allowed input voltage swing.

Figure 1. Vis and Vid Definition

The SY88083L has a selectable SD or LOS status output signal that can be fed back to the JAM input to perform the SQUELCH function for output stability if there is no signal at the input. SD/LOSLVL sets the sensitivity of the input amplitude detection.

The SY88083L has a user-selectable, integrated digital offset correction function to cancel internally generated output offsets.

Input Amplifier/Buffer

Figure 2 shows a simplified schematic of the input stage. The high sensitivity of the input amplifier allows signals as small as 10mV_PP to be detected and amplified. The input amplifier allows input signals as large as 1800mV_PP . Input small signals are amplified with a typical 44dB differential voltage gain.

Output Buffer

The SY88083L CML output buffer is designed to drive 50Ω impedance transmission lines and is internally terminated with 50Ω to V_cc . Figure 3 shows a simplified schematic of the output stage.

Signal Detect/Loss-of-Signal (SD/LOS)

The SY88083L generates a user-selectable (SD/LOS_SEL pin) signal detect (SD) or loss-of-signal (LOS) open-collector TTL output, as shown in Figure 4. LOS is used to determine whether the input amplitude is too small to be considered as a valid input. LOS asserts high if the input amplitude falls below the threshold set by SD/LOSLVL and de-asserts low otherwise. LOS can be fed back to the JAM input to perform the SQUELCH function and to maintain output stability under a LOS condition. JAM de-asserts the true output signal low without removing the input signals. Typically, 4dB LOS hysteresis is provided to prevent chattering.

When SD/LOS_SEL is used to select the SD output on the SD/LOS pin, SD is asserted when the differential input signal amplitude exceeds the level set by the SD/LOSLVL resistor. The JAM operation is inverted when SD is selected.

Signal Detect/Loss-of-Signal Level Setting

A programmable SD/LOS level set pin (SD/LOSLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between V_cc and SD/LOSLVL sets the threshold voltage. This voltage ranges from V_cc to V_cc - 1.3V . The external resistor creates a voltage divider between V_cc and V_cc - 1.3V , as shown in Figure 5.

Hysteresis

The SY88083L provides typically 4dB LOS electrical hysteresis, which is defined as 20log (VIN LOS_De-Assert ÷ VIN LOS_Assert ). Because the relationship of the voltage output of the ROSA to optical power at its input is linear, the optical hysteresis is typically half of the electrical hysteresis reported in the datasheet. In practice the ratio between electrical and optical hysteresis is found to be between 1.5 and 1.8. Thus, 4dB electrical hysteresis corresponds to an optical hysteresis within the range of 2dB to 2.4dB.

Digital Offset Correction (DOC)

The digital offset correction (DOC) circuit compensates for the inherent offsets found in high-gain amplifier circuits and minimizes the offset seen at the outputs. DOC is a user-selectable feature using the DOC_EN pin as defined in the "Pin Description" table.

Conventional analog offset compensation techniques may be susceptible to drift from long continuous identical digit (CID) patterns. They can also add additional cost due to the extra DAC and manufacturing setup time needed to optimize each individual module. The SY88083L avoids both of these issues and provides a performance/cost optimized solution.

The DOC circuitry automatically detects any internal device offsets and locks the correction values but does not apply offset correction to large input signals.

The DOC is enabled by default unless DOC_EN is pulled low by an external logic level signal. It can be reset by toggling the DOC_EN pin high-to-low-to-high. The DOC reset routine typically completes in 200 s.

Functional Circuit Structures

0.1μF RXIN+ 0.1μF RXIN- VREF 50Ω 50Ω VCC ESD STRUCTURE

Figure 2. Input Structure

Vcc 50Ω 50Ω RXOUT+ Z0 = 50Ω RXOUT- Z0 = 50Ω 16mA ESD STRUCTURE Vcc 50Ω 50Ω 0.1μF AC-COUPLING CAPACITORS

Figure 3. Output Structure

Functional Circuit Structures (Continued)

SD/LOS

Figure 4. SD/LOS Output Structure

Vcc RSD/LOSLVL SD/LOSLVL 1.5k Vcc - 1.3V

Figure 5. SD/LOSLVL Setting Circuit

Related Product and Support Documentation

Document Number	Title	Application Note Link
AN-45	Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers	www.micrel.com/_PDF/HBW/App-Notes/an-45.pdf
SY88073L_83L_EB	SY88073L/SY88083L Evaluation Board	http://www.micrel.com/_PDF/Eval-Board/SY88073L_83L_EB.pdf

Package Information ^(12)

PIN 1 DOT BY MARKING 3.0000±0.050 1 2 3.0000±0.050

TOP VIEW NOTE: 1, 2, 3

1.5500±0.050 Exp.DAP PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 0.5000 BSC 0.2300±0.050 1.5000 Ref. 1.5500±0.050 Exp.DAP 1 2 4000±0.050

BOTTOM VIEW NOTE: 1, 2, 3

0.850±0.050 0.000-0.050 0.2030±0.025

SIDE VIEW NOTE: 1, 2, 3

0.48±0.05 0.23±0.05 0.50 BSC 1.60±0.05 2.72±0.05 1.60±0.05 2.72±0.05

RECOMMENDED LAND PATTERN NOTE: 4, 5

NOTE:

1. MAX PACKAGE WARPAGE IS 0.05 MM
2. MAX ALLOWABLE BURR IS 0.076MM IN ALL DIRECTIONS
3. PIN #1 IS ON TOP WILL BE LASER MARKED
4. RED CIRCLE IN LAND PATTERN INDICATE THERMAL VIA.
   SIZE SHOULD BE 0.30-0.3M IN DIAMETER AND SHOULD BE
   CONNECTED TO GND FOR MAX THERMAL PERFORMANCE
5. GREEN RECTANGLES (SHADED AREA) indicate SOLDER
   STENCIL OPENING ON EXPOSED PAD AREA. SIZE SHOULD BE
   0.60×0.60 MM IN SIZE, 0.20 MM SPACING.

16-Pin (3mm × 3mm) QFN-16

Note:

1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.

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