SY58627L - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58627L Microchip

The SY58627L high-speed, low jitter receive buffer is optimized for backplane and transmission line data-path management applications. The SY58627L is capable of receiving serial data up to 6.4Gbps across up to 36 inches of FR4.

The SY58627L differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal as small as 100mV_pk (AC- or DC-coupled) without any termination resistor networks in the signal path. The outputs are 50 source-terminated CML optimized to drive 400mV_pk into 50 ( 100 load across the output pair). The I/O termination is connected to a dedicated VTT pin for added bias flexibility.

The SY58627L receiver input provides four levels of equalization to compensate for degraded signals resulting from transmission losses. The equalization is programmed with a three-bit interface.

The SY58627L operates at 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY58627L is part of Micrel's high-speed, Precision Edge® product line.

All data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Precision Edge®

Features

• Sel ectable equalizing network to optimize incoming data eye pattern
  • Four selectable equalization levels
• Receives up to 36" FR4 PCB trace, or longer combinations of FR4+cable+interconnect
  • DC through 6.4Gbps data rate throughput
  • Integrated loopback capability

• Unique, flexible I/O:

• Patented, Internal termination to VTTIN pin interfaces to any differential AC- or DC-coupled signals

• 50Ω source terminated CML outputs minimize round-trip reflections
• Wide input voltage range: 100mV to 1.3V _PK
• Out put disable
• DC-offset control with VTT I/O

- Input loss-of-signal

- Hysteresis included

• 3.3V ±10% supply voltage
- -40°C to +85°C temperature range
• Available in 32-pin (5mm x 5mm) QFN package

Applications

• ATE, T&M backplane management
- Serial backplane management
• Combination FR4+cable+interconnect receiver
- Fibre Channel, GigE, SONET/SDH data transmission
- Electrical interface and interconnect applications that require DC-offset control

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax + 1 [phone] • http://www.micrel.com

Functional Block Diagram

graph TD
    A["Level Detect"] --> B["Programmable Equalization Network"]
    C["LOS"] --> B
    D["RXIN /RXIN"] --> B
    E["V_TIN"] --> B
    B --> F["0"]
    F --> G["1"]
    G --> H["Loopback MUX"]
    H --> I["LBSEL"]
    I --> J["TXLBIN /TXLBIN"]
    J --> K["100Ω Internal Termination AC-coupled Input"]
    L["V_REF_AC"] --> K
    M["V_CC"] --> N["SY58627L RX"]
    N --> O["V_CC = 3.3V ±10%, T_A = -40°C to +85°C"]
    P["V_EE"] --> Q["/RXLBEN"]
    R["V_TH"] --> S["/RXLBQ"]
    T["CML Output"] --> U["/RXEN"]
    V["V_TOUT"] --> W["/RXQ"]
    X["Connect to SY58626L RXLIN"] --> Y["/RXLBQ"]
    Z["Loopback Select Control 0 = RXIN-to-RXQ 1 = Loopback = TXLIN-to-RXQ"] --> AA["/RXLBQ"]
    AB["Loopback Select Control 0 = RXIN-to-RXQ 1 = Loopback = TXLIN-to-RXQ"] --> AC["/RXLBQ"]

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY58627LMG	QFN-32	Industrial	SY58627L withPb-Free bar-line indicator	NiPdAuPb-Free
SY58627LMGTR^(2)	QFN-32 Industrial		SY58627L withPb-Free bar-line indicator	NiPdAuPb-Free

Notes:
Contact factory for die availability. Dice are guaranteed at T_A = 25^ C , DC Electricals only.
Tape and Reel.

Pin Configuration

VCC VEE EQ0 EQ1 EQ2 VTH LOS VCC 32 31 30 29 28 27 26 25 1 ○ 24 /RXEN VEE RXIN /RXIN 23 4 22 VTTOUT VEE VTTIN /VTIN VREF-AC 7 19 18 17 VCC LBSEL TXLBIN /TXLBIN /RXLBQ /RXLBQ /RXLBEN VCC VCC VCC VCC VCC

32-Pin QFN

Pin Description

Pin Number	Pin Name	Pin Function
3, 4 RXIN, /RXIN		Differential receiver input pair: This input pair is the differential signal input to the device. It accepts AC- or DC-coupled signals as small as 100mV (200mV PP). The signal detect (SD Level) includes a small amount of hysteresis to prevent the signal detect output from oscillating when no signal is present. RXIN and /RXIN internally terminate to the VTTINpin through 50Ω. Please refer to the “Input Interface Applications” section for more details. RXIN, /RXIN differential inputs recommended be ≥ 90mVPK to ensure valid outputs. Consider disabling the outputs when the differential input is not present, or < 90mVPK (e.g.: Hot Swap Applications).
6 VTTIN		Input termination center-tap: RXIN and /RXIN terminate to VTTIN. The VTTIN pin provides a center-tap to the internal termination network for maximum interface flexibility, and DC-offset capability. Please refer to the “Input Interface Applications” section for more details.
7 VREF-AC		Reference voltage: This output biases to VCC-0.84V. It is used for AC-coupling the input pair (RXIN, /RXIN). Connect VREF-AC directly to the VTTIN pin. Bypass with 0.01μF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive the VTTIN pin. Leave VREF-AC pin floating when not used. Please refer to the “Input Interface Applications” section for more details.
27 VTH		Input logic threshold control voltage for logic control threshold settings other than LVTTL/CMOS. This input control pin can be externally biased to set the proper threshold for all the logic control pins, /RXEN, LBSEL, 3-bit equalization control, and /RXLBEN. For standard LVTTL/CMOS control, simply leave the VTH pin floating and the threshold voltage defaults to VCC/2 (When VEE = 0V). For LVPECL thresholds, set VTH to VCC-1.3V.
23 /RXEN		TTL/CMOS (or VTH controlled) compatible control input for the RXQ output pair. When pulled HIGH, the RXQ output pair is disabled. This input is internally connected to a 25kΩ pull-down resistor and will default to a logic LOW state (Enable) if left open. When disabled, the RXQ output goes LOW, and /RXQ output goes HIGH. Default threshold is VCC/2 when VTH pin is floating.
15 /RXLBEN		TTL/CMOS (or VTH controlled) compatible control input for RXLBQ output pair. When pulled HIGH, the RXLBQ output pair is disabled. This input is internally connected to a 25kΩ pull-down resistor and will default to a logic LOW state (Enable) if left open. When disabled, the RXLBQ output goes LOW, and /RXLBQ output goes HIGH. Default threshold is VCC/2 when VTH pin is floating. In normal operating mode when the RXLBQ output pair is not needed, disable the RXLBQ output pair (/RXLBEN = HIGH) to minimize noise.
10 LBSEL		Loopback MUX select control: The TTL/CMOS (or VTH controlled) compatible input selects the input to the Loopback mode multiplexer. When LBSEL input is logic HIGH, Loopback mode is selected, and the TXLBIN input pair is selected to pass through the RXQ and RXLBQ output pairs. Note that the LBSEL pin is internally connected to a 25kΩ pull-down resistor and will default to a logic LOW state if left open (normal operation). The Loopback MUX includes internal input isolation to minimize crosstalk.
11, 12	TXLBIN, /TXLBIN	Loopback differential input pair: AC-coupled, CML-compatible input. This input pair includes internal termination connected to an internal VBB for an AC-coupled bias configuration. For local Loopback operation, the TXLBIN input pair receives a signal from the SY58626L transmitter TXLBQ output pair. The input signal from TXLBIN does not have any equalization. When the SY58627L Loopback mode is selected (LBSEL = HIGH), the signal at TXLBIN is directed to the RXQ and RXLBQ output pairs.
13, 14	RXLBO,/RXLBO	Receiver loopback CML compatible output pair. When the SY58627L is in local Loopback mode (LBSEL = 1), RXLBQ output is directed from TXLBIN (no equalization). When the SY58627L is in normal mode (LBSEL = LOW) and the RXLBQ output is not required, disable the RXLBQ output (/RXLBEN = HIGH) to minimize switching noise. This differential output pair is optimized to drive 400mV_PK swing into a 50 load ( 100 across the pair). The RXLBQ output pair includes 50 internal source termination resistors.
21, 19	RXQ,/RXQ	Receiver differential CML compatible output pair: This CML-compatible output pair is the equalized signal seen at the RXIN input pair and is optimized to drive 400mV_PK swing into a 50 load ( 100 across the pair). The RXQ output pair includes 50 internal source termination resistors. When the SY58627L is in Loopback mode (LBSEL = HIGH), the RXQ output signal is directed from the unequalized TXLBIN input.
26 LOS		Loss-of-Signal output. This LVTTL/CMOS output signal switches LOW when the signal is valid and switches HIGH when the signal is not valid. This open-collector output includes an internal 5k pull-up resistor.Input signal valid, LOS = LOW , RXIN swing is >110mV_PK ( 220mV_PP ).Input signal not valid, LOS = HIGH , RXIN swing is <90mV_PK ( 180mV_PP )
20 VTTOUT		Output termination center-tap: Each side of the RXQ differential output pair terminates to the VTTOUT pin through 50 . The VTTOUT pin provides a center-tap to the output termination network for maximum interface flexibility, and DC-offset capability. Please refer to the “CML Output Interface Applications” section for more details.
28	EQ2(MSB)	TTL/CMOS (or VTH controlled) compatible, 3-bit control interface. There are four levels of equalization, as shown in the “Equalization Select Truth Table.” When the MSB is logic HIGH, the RXQ output pair will not include any equalization.
29	EQ1	000 = lowest equalization setting
30	EQ0	001 = medium equalization setting010 = medium-high equalization setting011 = highest equalization setting100 = equalization bypass
1, 8, 9, 16, 17, 24, 25	VCC	Positive Power Supply: Connect to +3.3V power supply. Bypass with 0.1 F//0.01 F low ESR capacitors as close to VCC pins as possible.
2, 5, 18, 22, 31, 32	VEE, Exposed Pad	Ground: Ground pins and exposed pad must be connected to the same ground plane.

Equalization Select Truth Table

Disable EQ (MSB = EQ2)	Equalization Select (EQ1)	Equalization Select (EQ0)	Typical FR4 Length	Equalization
0 0 0			9”	Low
0 0 1			18”	Medium Low
0 1 0			24”	Medium High
0 1 1			36”	High
1 X X NA	Disabled

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) -0.5V to +4.0V

Input Voltage ( V_IN )....-0.5V to V_CC

Input Current (RXIN, /RXIN, ≤120mins) 67mA

CML Output Current (IOUT)

Continuous (≤120mins).... 67mA

Surge 100mA

Termination Current

V_T ±100mA

V_REF-AC Current

Source/sink current on V REF-AC.... ±2mA

Lead Temperature (soldering, 20 sec.) ....+260°C

Storage Temperature ( T_s )....-65°C to 150°C

Operating Ratings ^(2)

Supply Voltage (Vcc) ....+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

QFN ( _JA )

Still-Air 34°C/W

QFN ( _JB )

Junction-to-Board 20°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ ; unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply		3.0	3.3	3.6	V
I_EE	Power Supply Current	Max V_CC , includes 50Ω internal source resistors, no external load current		210	260	mA
R_IN	Input Resistance (RXIN-to-VTTIN)		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (RXIN-to-/RXIN)		90	100	110	Ω
V_IN\_TRANS	Transmission Line Input Voltage Swing (RXIN, /RXIN)	Input signal swing applied to transmission line input up to 36 in. (driver side of RXIN)	0.20			V_PK
V_IN	Input Voltage Swing (RXIN, /RXIN)	See Figure 4a.	0.1		1.3	V_PK
V_DIFF\_IN	Differential Input Voltage Swing |RXIN-/RXIN|	See Figure 4b.	0.2			V_PP
V_IH	Input High Voltage (RXIN, /RXIN)		V_EE+1.6		V_CC	V
V_IL	Input LOW Voltage (RXIN, /RXIN)		V_EE+1.4		V_IH-0.1	V
V_TTIN	RXIN-to-VTTIN (RXIN, /RXIN)				1.5	V
V_TTIN Range	VTTIN Voltage Range	Voltage applied to VTTIN pin	V_CC-1.5		V_CC+1.5	V
V_TTOUT Range	VTTOUT Voltage Range	Voltage applied to VTTOUT pin	V_CC-0.4		V_CC	V
LOS	Loss-of-Signal Input Levels	Signal-detect Assert		110		mV_PK
		Signal-detect De-assert		90
	Input Return Loss	100MHz to 3.5GHz		10		dB
V_REF-AC	Output Reference Voltage		V_CC-0.95	V_CC-0.84	V_CC-0.7	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. T_J ≤ 125^ .

RXQ and RXLBQ Output DC Electrical Characteristics ^(5)

V_CC = 3.3V ± 10% ; V_EE = 0V ; T_A = -40^ to +85°C; R_L = 100 across output pair; unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	RXQ & RXLBQ Output High Voltage	R_L = 50 to V_cc	V_cc-0.040 V	V_cc-0.010 V	V_cc	V
V_OUT	Output Voltage Swing (RXQ, /RXQ)(RXLBQ, /RXLBQ)	See Figure 4a.	325 400	mV		P_K
V_DIFF\_OUT	RXQ & RXLBQ Differential Output Voltage Swing |RXQ-/RXQ| |RXLBQ-/RXLBQ|	See Figure 4b.	650 800	mV		P_P
R_OUT	Output Impedance		45	50	55

Logic Control DC Electrical Characteristics ^(5)

V_CC = 3.3V ± 10% ; V_EE = 0V ; T_A = -40^ to +85°C; unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage	All control input pins	V_TH+0.2	V	cc	V
V_IL	Input LOW Voltage	All control input pins	V_EE	V	_TH-0.2	V
I_IH	Input HIGH Current				300	μA
I_IL	Input LOW Current		-300			μA
V_TH	Threshold Input Voltage	Voltage applied to pin( V_EE=0V )	1.4	V_CC/2	2.6	V

TXLBIN Input DC Electrical Characteristics ^(5)

V_CC = 3.3V ± 10% ; V_EE = 0V ; T_A = -40^ to +85°C; R_L = 100 across output pair; unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
R_DIFF\_IN	Differential Input Resistance (TXLBIN-to-/TXLBIN)		90	100	110
V_IN	Input Voltage Swing (TXLBIN, /TXLBIN)	See Figure 4a.	0.1		1.3	V_PK
V_DIFF\_IN	Differential Input Voltage Swing |TXLBIN-/TXLBIN|	See Figure 4b.	0.2			V_PP

Notes:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 500lfpm Airflow. T_J≤ 125^ .

AC Electrical Characteristics ^(6)

V_CC = 3.3V ± 10% ; V_EE = 0V ; T_A = -40^ to +85°C; R_L = 100 across output pair; unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
Freq	Data Rate Throughput (RXQ & RXLBQ)	NRZ Data	DC		6.4	Gbps
tpd Differential	Propagation Delay	RXIN-to-RXQ, no equalization	150	250	450	ps
		TXLBIN-to-RXQ		250		ps
tEN	TXQ Enable/Disable Time	/TXEN		425	650	ps
tLB_EN	TXLBQ Enable/Disable Time	/TXLBEN		425		ps
tLBSEL	Loopback Select Time	LBSEL		350	600	ps
tPROG	Programming Logic Control Time	3-bit equalization control update-to-valid RXQ		1		ns
tpd Tempco	Differential Propagation Delay Temperature Coefficient			120		fs/°C
tsKEW	Part-to-Part Skew	Note 7			200	ps
tJITTER	Random Jitter (RJ)	Note 8			Note 10	ps_RMS
	Deterministic Jitter (DJ)	Note 9			Note 10	ps_PP
tr, tf	Output Rise/Fall Time (20% to 80%)	At full output swing	20	50	80	ps

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
2. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
3. Random jitter is measured with a K28.7 pattern, measured at ≤6.4Gbps.
4. Deterministic jitter is measured with both K28.5 and 2^23-1 PRBS pattern, at 4.25Gbps/6.4Gbps.
5. Contact factory for updated random jitter and deterministic jitter limits.

Detailed Description

The SY58627L is a high speed, low jitter receive buffer with integrated loopback capability. This buffer also provides input signal detect and output disable. Four selectable levels of equalization are included with the receiver. Equalization allows for faster data rates and longer distances by reducing the effects of intersymbol interference (ISI) caused by long cable and trace lengths. Input equalization supports data rates up to 6.4Gbps.

DC-Offset Capability

The SY58627L transmitter includes the VTTIN and VTTOUT pin for maximum interface flexibility and DC-offset capability for the input and output, respectively. This feature allows for interfacing with different logic families without the use of AC-coupling. The output buffer has internal 50Ω source terminated CML outputs for minimizing round-trip reflections.

Transmitter Disable and Shutdown

The SY58627L disable function is initiated by pulling /RXEN to logic HIGH. In disable mode, RXQ goes to a LOW state and /RXQ goes to a HIGH state. The threshold for /RXEN is set with the VTH pin. When the VTH pin is floating, the VTH levels are TTL/CMOS compatible with a threshold voltage at V_CC/2 ( V_EE = 0V ). For PECL compatible levels, apply a V_CC-1.3V voltage at the VTH pin. Please refer to the “Typical Operating Characteristics” for more details.

Loss-of-Signal

The SY58627L RXIN input pair provides a TTL signal detect output. The LOS output de-asserts LOW when the swing at RXIN is greater than 110mV_PK ( 220mV_PP ). SD output asserts HIGH when RXIN swing is less than 90mV_PK ( 180mV_PP ). Hysteresis is included in the LOS output to prevent oscillation when no signal is present at the RXIN input. LOS can be tied to /RXEN and /RXLBEN to provide a valid output when input amplitude is <90mV_PK or disabled.

Loopback

The SY58627L features a loopback test mode, activated by setting LBSEL to logic HIGH. Using the SY58627L with the SY58626L enables local loopback and link side loopback, shown in Figures 2b and 2c. This mode enables an external loopback path, bypassing circuitry on both local and link side. Please refer to Table 1 and Figure 3 for Loopback Control information.

graph TD
    A["Data In"] --> B["TXIN"]
    B --> C["SY58626L"]
    C --> D["PE"]
    D --> E["TXQ"]
    E --> F["Link Side Transmit"]
    C --> G["TXLBQ"]
    G --> H["Local Loopback"]
    C --> I["TXLBQ"]
    I --> J["Local Loopback"]
    C --> K["TXLBQ"]
    K --> L["Local Loopback"]
    C --> M["TXLBQ"]
    M --> N["Local Loopback"]
    C --> O["TXLBQ"]
    O --> P["Local Loopback"]
    C --> Q["TXLBQ"]
    Q --> R["Local Loopback"]
    C --> S["TXLBQ"]
    S --> T["Local Loopback"]
    C --> U["TXLBQ"]
    U --> V["Local Loopback"]
    C --> W["TXLBQ"]
    W --> X["Local Loopback"]
    C --> Y["TXLBQ"]
    Y --> Z["Local Loopback"]
    C --> AA["TXLBQ"]
    AA --> AB["Local Loopback"]
    C --> AC["TXLBQ"]
    AC --> AD["Local Loopback"]
    C --> AE["TXLBQ"]
    AE --> AF["Local Loopback"]
    C --> AG["TXLBQ"]
    AG --> AH["Local Loopback"]
    C --> AI["TXLBQ"]
    AI --> AJ["Local Loopback"]
    C --> AK["TXLBQ"]
    AK --> AL["Local Loopback"]
    C --> AM["TXLBQ"]
    AM --> AN["Local Loopback"]
    C --> AO["TXLBQ"]
    AO --> AP["Local Loopback"]
    C --> AQ["TXLBQ"]
    AQ --> AR["Local Loopback"]
    C --> AS["TXLBQ"]
    AS --> AT["Local Loopback"]
    C --> AU["TXLBQ"]
    AU --> AV["Local Loopback"]
    C --> AW["TXLBQ"]
    AW --> AX["Local Loopback"]
    C --> AY["TXLBQ"]
    AY --> AZ["Local Loopback"]
    C --> BA["TXLBQ"]
    BA --> BB["Local Loopback"]
    C --> BC["TXLBQ"]
    BC --> BD["Local Loopback"]
    C --> BE["TXLBQ"]
    BE --> BF["Local Loopback"]
    C --> BG["TXLBQ"]
    BG --> BH["Local Loopback"]
    C --> BI["TXLBQ"]
    BI --> BJ["Local Loopback"]
    C --> BK["TXLBQ"]
    BK --> BL["Local Loopback"]
    C --> BM["TXLBQ"]
    BM --> BN["Local Loopback"]
    C --> BO["TXLBQ"]
    BO --> BP["Local Loopback"]
    C --> BQ["TXLBQ"]
    BQ --> BR["Local Loopback"]
    C --> BS["TXLBQ"]
    BS --> BT["Local Loopback"]
    C --> BU["TXLBQ"]
    BU --> BV["Local Loopback"]
    C --> BW["TXLBQ"]
    BW --> BX["Local Loopback"]
    C --> BY["TXLBQ"]
    BY --> BZ["Local Loopback"]
    C --> CA["TXLBQ"]
    CA --> CB["Local Loopback"]
    C --> CC["TXLBQ"]
    CC --> CD["Local Loopback"]
    C --> CE["TXLBQ"]
    CE --> CF["Local Loopback"]
    C --> CG["TXLBQ"]
    CG --> CH["Local Loopback"]
    C --> CI["TXLBQ"]
    CI --> CJ["Local Loopback"]
    C --> CK["TXLBQ"]
    CK --> CL["Local Loopback"]
    C --> CM["TXLBQ"]
    CM --> CN["Local Loopback"]
    C --> CO["TXLBQ"]
    CO --> CP["Local Loopback"]
    C --> CY["TXLBQ"]
    CY --> CZ["Local Loopback"]
    C --> DA["TXLBQ"]
    DA --> DB["Local Loopback"]
    C --> DC["TXLBQ"]
    DC --> DE["Local Loopback"]

Figure 2a. Normal Operation

graph TD
    A["Data In"] --> B["TXIN"]
    B --> C["SY58626L"]
    C --> D["TXQ"]
    D --> E["Link Side Transmit"]
    C --> F["TXLBQ"]
    F --> G["Local Loopback"]
    C --> H["TXLBQ"]
    H --> I["Local Loopback"]
    C --> J["TXLBIN"]
    J --> K["Link Side Receive"]
    L["Data Out"] --> M["RXQ"]
    M --> N["SY58627L"]
    N --> O["TXLBIN"]
    O --> P["Local Loopback"]
    N --> Q["TXLBQ"]
    Q --> R["Local Loopback"]
    N --> S["TXLBQ"]
    S --> T["Local Loopback"]
    N --> U["TXLBQ"]
    U --> V["Local Loopback"]
    N --> W["TXLBQ"]
    W --> X["Local Loopback"]
    N --> Y["TXLBQ"]
    Y --> Z["Local Loopback"]
    N --> AA["TXLBQ"]
    AA --> AB["Local Loopback"]
    N --> AC["TXLBQ"]
    AC --> AD["Local Loopback"]
    N --> AE["TXLBQ"]
    AE --> AF["Local Loopback"]
    N --> AG["TXLBQ"]
    AG --> AH["Local Loopback"]
    N --> AI["TXLBQ"]
    AI --> AJ["Local Loopback"]
    N --> AK["TXLBQ"]
    AK --> AL["Local Loopback"]
    N --> AM["TXLBQ"]
    AM --> AN["Local Loopback"]
    N --> AO["TXLBQ"]
    AO --> AP["Local Loopback"]
    N --> AQ["TXLBQ"]
    AQ --> AR["Local Loopback"]
    N --> AS["TXLBQ"]
    AS --> AT["Local Loopback"]
    N --> AU["TXLBQ"]
    AU --> AV["Local Loopback"]

Figure 2b. Local Loopback Mode

graph TD
    A["Data In"] --> B["TXIN"]
    B --> C["SY58626L"]
    C --> D["Link Side Loopback"]
    D --> E["RXLBQ"]
    E --> F["SY58627L"]
    F --> G["Local Loopback"]
    G --> H["TXLBQ"]
    H --> I["Link Side Transmit"]
    F --> J["TXLBIN"]
    J --> K["Link Side Receive"]
    L["Data Out"] --> M["RXQ"]
    M --> N["SY58627L"]
    N --> O["TXLBIN"]
    O --> P["Local Loopback"]
    Q["/RXEN"] --> R["1"]
    S["/TXEN"] --> T["0"]
    U["/TXEN"] --> V["1"]
    W["/TXEN"] --> X["0"]
    Y["/TXEN"] --> Z["1"]
    AA["/TXEN"] --> AB["0"]
    AC["/TXEN"] --> AD["1"]
    AE["/TXEN"] --> AF["0"]
    AG["/TXEN"] --> AH["1"]
    AI["/TXEN"] --> AJ["0"]
    AK["/TXEN"] --> AL["1"]

Figure 2c. Link Side Loopback Mode

	LBSEL	/RXLBEN	/RXEN	RXQ	RXLBQ
Normal Mode	0 0 0	RXIN RXIN
	0 0 1	0 RXIN
	0 1 0	RXIN 0
	0 1 1	0 0
Link Side Loopback Mode	1 0 0	TXLBIN TXBIN
	1 0 1	0 TXBIN
	1 1 0	TXLBIN 0
	1 1 1	0 0

Table 1. Transmit Loopback Control Signal

graph LR
    RXIN --> EQ
    TXBIN --> EQ
    EQ --> B
    B --> OR1["OR"]
    B --> OR2["OR"]
    OR1 --> RXLBQ
    OR2 --> RXQ
    LBSEL --> OR1
    /RXLBEN --> OR2
    /RXEN --> OR1

Figure 3. Loopback Control

Typical Operating Characteristics

V_CC = 3.3V ± 10% ; V_IN > 400mV ; T_A = 25^ , R_L = 100 across output pair; unless otherwise stated.

8in FR4 Output With SY58627L (4.25Gbps PRBS 2 ^23 )

8in FR4 Output with SY58627L (6.4Gbps PRBS 2 ^23 )

Typical Operating Characteristics (Continued)

V_CC = 3.3V ± 10% ; V_IN > 100mV ; T_A = 25^ , R_L = 100 across output pair; unless otherwise stated.

Typical Operating Characteristics (Continued)

V_CC = 3.3V ± 10% ; V_IN > 100mV ; T_A = 25^ , R_L = 100 across output pair; unless otherwise stated.

Note:

1. Measurements made with 26AWG Amphenol Skew Clear Eye Opener Plus cable.

Single-Ended and Differential Swings

VIN, VOUT 400mVPK (Outputs)

Figure 4a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 800mVPK-PK (Outputs)

Figure 4b. Differential Voltage Swing

Input and Output Stages

VCC RXIN 50Ω VTTIN 50Ω /RXIN VEE

Figure 5a. Simplified RXIN Differential Input Stage

VTTOUT 50Ω 50Ω /RXQ, /RXLBO RXQ, RXLBQ VEE

Figure 5b. Simplified RXIN Differential Output Stage

VCC TXLBIN 50Ω Internal VBB 50Ω /TXLBIN VEE

Figure 5c. Simplified RXIN Differential Input Stage

VCC 50Ω 50Ω /RXLBQ /RXLBQ VEE

Figure 5d. Simplified RXIN Differential Output Stage

Input Interface Applications

VCC LVPECL VEE VCC 0.01μF 50Ω VEE RXIN /RXIN SY58627L VTTIN VREF-AC NC

Figure 6a. LVPECL Interface (DC-Coupled)

VCC LVPECL 100Ω 100Ω VEE VCC 0.01μF RXIN /RXIN SY58627L VTTIN VREF-AC

Figure 6b. LVPECL Interface (AC-Coupled)

VCC CML VEE RXIN /RXIN SY58627L NC □ VTTIN NC □ VREF-AC

option: may connect VTTIN to V_cc

Figure 6c. CML Interface (DC-Coupled)

VCC CML VEE RXIN /RXIN SY58627L VCC 0.01μF VTTIN VREF-AC

Figure 6d. CML Interface (AC-Coupled)

VCC LVDS VEE RXIN /RXIN SY58627L NC □ VTTIN NC □ VREF-AC

Figure 6e. LVDS Interface (DC-Coupled)

VCC SY58626L TXLBQ VEE TXLBIN /TXLBIN SY58627L NC □ VTTIN NC □ VREF-AC

Figure 6f. TXLBIN Interface (AC-Coupled)

CML Output Interface Applications

VTTOUT 50Ω 50Ω Z₀ = 50Ω /RXQ 100Ω Z₀ = 50Ω RXQ VEE

Figure 7a. CML DC-Coupled Termination

VTTOUT 50Ω 50Ω Z₀ = 50Ω /RXQ 50Ω V_BIAS 50Ω Z₀ = 50Ω RXQ V_EE

Figure 7b. CML DC-Coupled Termination

VTTOUT 50Ω 50Ω Z₀ = 50Ω /RXQ 50Ω V_BIA 50Ω Z₀ = 50Ω RXQ V_EE

Figure 7c. CML AC-Coupled Termination

RXLBQ Output Interface Applications

VCC 50Ω 50Ω Z₀ = 50Ω /RXLBQ 100Ω Z₀ = 50Ω RXLBQ VEE

Figure 7a. CML DC-Coupled Termination

VCC 50Ω 50Ω Z₀ = 50Ω /RXLBQ 50Ω V_BIAS 50Ω Z₀ = 50Ω RXLBQ V_EE

Figure 7b. CML DC-Coupled Termination

VCC 50Ω 50Ω Zo = 50Ω /RXLBO 50Ω VBL 50Ω Zo = 50Ω RXLBQ VEE

Figure 7c. CML AC-Coupled Termination

Related Product and Support Information

Part Number	Function	Data Sheet Link
SY58626L	DC-to-6.4Gbps Backplane Transmit Buffer with Selectable Output Pre-emphasis, I/O DC-Offset Control, and 200mV-3VPPOutput Swing	www.micrel.com/product-info/products/sy58626l.shtml
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

Package Information

5.0 BSC 32 1 2 PIN #1 ID 0.20 DIA TYP. 5.0 BSC

TOP VIEW

0.85±0.05 SEATING PLANE 0.00~0.05 0.20 REF

SIDE VIEW

0.25±0.05 32X 0.50 BSC 32 PIN #1 ID R0.20 0.20 MIN. 3.10±0.10 1 2 0.40±0.05 4X 3.10±0.10

BOTTOM VIEW

NOTE:

1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOVABE BURRS IS 0.076 nm IN ALL DIRECTIONS
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

32-Pin QFN

Package Notes:

1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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