SY89547L - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89547L Microchip

■ SONET/SDH multi-channel select applications
■ Fibre Channel applications
■ GigE applications

TYPICAL PERFORMANCE

Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

Precision Edge®

DESCRIPTION

The SY89547L is a precision, high-speed 4:1 differential multiplexer that provides two copies of the selected input. The high speed LVDS (350mV) compatible outputs with a guaranteed throughput of up to 3.2Gbps over temperature and voltage.

The SY89547L differential inputs include Micrel's unique, 3-pin internal termination design that allows access to the termination network through a V_T pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled without external resistor-bias and termination networks. The result is a clean, stub-free, low jitter interface solution.

The SY89547L operates from a single 3.3V supply, and is guaranteed over the full industrial temperature range ( -40^ to +85^ ). For applications that require a 2.5V supply, consider the SY89546U. For applications that only require one differential output, consider the SY89544U or SY89545L. The SY89547L is part of a Micrel's Precision Edge ^® product family. All support documentation can be found on Micrel's web site at: www.micrel.com.

FUNCTIONAL BLOCK DIAGRAM

graph TD
    subgraph Inputs
        IN0["IN0"] --> A1["NOT"]
        V_T0["V_T0"] --> A1
        /IN0["/IN0"] --> A1
        A1 --> B1["NOT"]
        V_T1["V_T1"] --> A2["NOT"]
        /IN1["/IN1"] --> A2
        A2 --> C1["NOT"]
        V_T2["V_T2"] --> A3["NOT"]
        /IN2["/IN2"] --> A3
        A3 --> D1["NOT"]
        V_T3["V_T3"] --> A4["NOT"]
        /IN3["/IN3"] --> A4
    end
    subgraph Outputs
        IN1["IN1"] --> A5["NOT"]
        V_T1["V_T1"] --> A5
        /IN1["/IN1"] --> A5
        A5 --> B5["NOT"]
        V_T2["V_T2"] --> A6["NOT"]
        /IN2["/IN2"] --> A6
        A6 --> C5["NOT"]
        V_T3["V_T3"] --> A7["NOT"]
        /IN3["/IN3"] --> A7
    end
    subgraph Outputs
        IN2["IN2"] --> A8["NOT"]
        V_T2["V_T2"] --> A8
        /IN2["/IN2"] --> A8
        A8 --> C6["NOT"]
        V_T3["V_T3"] --> A9["NOT"]
        /IN3["/IN3"] --> A9
    end
    subgraph Outputs
        IN3["IN3"] --> A10["NOT"]
        V_T3["V_T3"] --> A10
        /IN3["/IN3"] --> A10
        A10 --> C7["NOT"]
        S0["S0"] --> C8["NOT"]
    end
    subgraph Outputs
        IN1_0["IN0"] --> A1
        V_T0_0["V_T0"] --> A1
        /IN0_0["/IN0"] --> A1
        A1 --> B1_0["NOT"]
        V_T1_0["V_T1"] --> A2
        /IN1_0["/IN1"] --> A2
        A2 --> C1_0["NOT"]
        V_T2_0["V_T2"] --> A3
        /IN2_0["/IN2"] --> A3
        A3 --> C5_0["NOT"]
        V_T3_0["V_T3"] --> A4
        /IN3_0["/IN3"] --> A4
    end
    subgraph Outputs
        IN1_1["IN1"] --> A5_1["NOT"]
        V_T1_1["V_T1"] --> A5_1
        /IN1_1["/IN1"] --> A5_1
        A5_1 --> B5_1["NOT"]
        V_T2_1["V_T2"] --> A6_1["NOT"]
        /IN2_1["/IN2"] --> A6_1
        A6_1 --> C6_1["NOT"]
        V_T3_1["V_T3"] --> A7_1["NOT"]
        /IN3_1["/IN3"] --> A7_1
    end
    subgraph Outputs
        IN2_2["IN2"] --> A8_2["NOT"]
        V_T2_2["V_T2"] --> A8_2
        /IN2_2["/IN2"] --> A8_2
        A8_2 --> C7_1["NOT"]
        V_T3_2["V_T3"] --> A9_2["NOT"]
        /IN3_2["/IN3"] --> A9_2
    end
    subgraph Outputs
        IN3_3["IN3"] --> A10_3["NOT"]
        V_T3_3["V_T3"] --> A10_3
        /IN3_3["/IN3"] --> A10_3
    end
    subgraph Outputs
        IN0_0_IN0 --> B1_0_AFF
    end
    subgraph Outputs
        IN1_0_IN1 --> B1_0_SOX["TTL"]
    end
    subgraph Outputs
        IN1_1_IN1 --> B5_1_AFF
    end
    subgraph Outputs
        IN2_1_IN2 --> B5_1_SOX["TTL"]
    end
    subgraph Outputs
        IN3_1_IN3 --> B7_1_AFF
    end

PACKAGE/ORDERING INFORMATION

IN1 VT1 IN1 VCC VCC IN2 VT2 IN2 32 313029 282726 25 VCC 1 24 /IN0 2 23 VT0 3 22 IN0 4 21 VCC 5 20 SEL0 6 19 GND 7 18 VCC 8 17 9 10 11 12 13 14 15 16 GND Q0 /Q0 GND GND Q1 /Q1 GND

32-Pin MLF®

Ordering Information ^(1)

Part Number	Package Type Range	Operating	Package Marking	Finish	Lead
SY89547LMI	MLF-32	Industrial	SY89547L		Sn-Pb
SY89547LMITR(2)	MLF-32	Industrial	SY89547L		Sn-Pb
SY89547LMG(3)	MLF-32	Industrial	SY89547L with Pb-Free bar-line indicator		Pb-Free NiPdAu
SY89547LMGTR(2, 3)	MLF-32	Industrial	SY89547L with Pb-Free bar-line indicator		Pb-Free NiPdAu

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_=25^ , DC electricals only.
2. Tape and Reel.
3. Recommended for new designs.

PIN DESCRIPTION

Pin Number Pin	Name Pin Function	on
4, 2, 32, IN0, /IN0, Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs 30, 27, 25, 23, 21 IN1, /IN1, accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally IN2, /IN2, terminates to a VT _T pin through 50Ω. Note that these inputs will default to an indeterminate IN3, /IN3 state if left open. Unused differential input pairs can be terminated by connecting one input to V _CC and the complementary input to GND through a 1kΩ resistor. The VT _T pin is to be left open in this configuration. Please refer to the “Input Interface Applications” section for more details.
3, 31, 26, 22 VT0, VT1, Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT _T VT2, VT3 pin. The V _TA0 , V _TA1 , V _TB0 , V _TB1 pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details.
6, 19 SEL0, SEL1 These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold is V _CC /2.
1, 5, 8, 17, 20, 24, 28, 29	VCC	Positive Power Supply: Bypass with 0.1 F||0.01 F low ESR capacitors.
10, 11, 14, 15 Q0, /Q0, Differential Outputs: These LVDS output pairs are the outputs of the device. They are a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the “Truth Table” for details. If an output is not used, it must be terminated with 100Ω across the differential pair.
7, 9, 12, 13, 16, 18	GND, Exposed pad	Ground: Ground pin and exposed pad must be connected to the same ground plane.

Absolute Maximum Ratings ^(1)

Supply Voltage (V _CC ) ...... - 0.5V to + 4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

Termination Current ^(3)

Source or sink current on V_T ..... ±100mA

Input Current

Source or sink current on IN, /IN ....±50mA

Lead Temperature (soldering, 20 sec.) ....+260°C

Storage Temperature ( T_S ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage (V _CC ) 3.0V to 3.6V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(4)

MLF® (θJA)

Still-Air 35°C/W

500lfpm 28°C/W

MLF® (ΨJB)

Junction-to-Board 20°C/W

DC ELECTRICAL CHARACTERISTICS ^(5)

T_A = -40^ to +85^ ; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_CC	Power Supply 3.0 3.3 3.6 V
I_CC	Power Supply Current No Load, Max	V_CC^(6)		68 90	mA
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		80	100	120	Ω
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		40 50	60	Ω
V_IH	Input High Voltage (IN, /IN)		1.2		V_CC	V
V_IL	Input Low Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	Note 7	0.1		V_CC	V
V_DIFF\_IN	Differential Input Voltage Swing | IN - /IN |	Note 7	0.2			V
IN-to- V_T		Note 7			1.8 V

Notes:

1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential (GND) on the PCB. _JB uses 4-layer _JA in still-air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50Ω pull-ups.
7. See "Operating Characteristics" section for V_IN and V_DIFF_IN definition.

LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS ^(9)

V_CC = 3.3V ± 10% ; T_A = -40^ to +85^ ; R_L = 100 across Q and /Q, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_OH	Output HIGH Voltage See Figure 5a (Q, /Q)	1.475 V
V_OL	Output LOW Voltage See Figure 5a (Q, /Q)	0.925 V
V_OUT	Output Voltage Swing See Figures 1a (Q, /Q)	5a 250 350 mV
V_DIFF-OUT	Differential Output Voltage Swing | Q - /Q|	See Figure 1b	500	700		mV
V_OCM	Output Common Mode Voltage (Q, /Q)	See Figure 5b 1.125 1.275 V
V_OCM	Change in Common Mode Voltage (Q, /Q)	See Figure 5b	-50		+50	mV

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS ^(9)

V_CC = 3.3V ± 10% ; T_A = -40^ to +85^ ; unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_IH	Input HIGH Voltage		2.0		V_CC	V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current				40	A
I_IL	Input LOW Current				-300	A

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS ^(10)

V_CC = 3.3V ± 10% ; T_A = -40^ to +85^ ; R_L = 100 across Q and /Q, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
f_MAX	Maximum Operating Frequency NRZ	Data 3.2 Gbps
		V_OUT ≥ 200mV Clock 4 GHz
t_pd	Differential Propagation Delay IN-to-Q	340 440 540 ps
		SEL-to-Q	200 420 700 ps
t_SKEW	Input-to-Input Skew	Note 11		5	20	ps
	Output-to-Output Skew	Note 12		8	20	ps
	Part-to-Part Skew	Note 13			200	ps
t_JITTER	Data Random Jitter (RJ)	Note 14			1	ps_RMS
	Deterministic Jitter (DJ)	Note 15			10	ps_PP
	Clock Total Jitter (TJ)	Note 16			10	ps_PP
	Cycle-to-Cycle Jitter	Note 17			1	ps_RMS
Crosstalk	Crosstalk-Induced Jitter	Note 18			0.7	ps_RMS
t_R, t_F	Output Rise / Fall Time(20% to 80%)	At full output swing	40	80	150	ps

Notes:

1. Measured with 100mV input swing. See "Timing Diagrams" section for definition of parameters. High frequency AC parameters are guaranteed by design and characterization.
2. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew does not include the output skew.
3. Output-to-output skew is measured between two different outputs under identical input transitions.
4. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
5. RJ is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
6. DJ is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 2^23-1 PRBS pattern.
7. Total jitter definition: with an ideal clock input of frequency ≤ f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
8. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn-Tn-1 where T is the time between rising edges of the output signal.
9. Crosstalk is measured at the output while applying two similar clock frequencies to adjacent inputs that are asynchronous with respect to each other at the inputs.

SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_{IN}, \nV_{OUT} 350mV (Typ.)

Figure 1a. Single-Ended Voltage Swing

VDIFF IN: VDIFF_OUT 700mV (Typ.)

Figure 1b. Differential Voltage Swing

TIMING DIAGRAM

IN /IN Q /Q tPD

SEL SEL-to-Q ← t_pd Q /Q

Figure 2. Timing Diagram

TRUTH TABLE

IN0 IN1 IN2 IN3 SEL0 SEL1 Q /Q
0	X	X	X		0	0	0
1	X	X	X		0	0	1
X	0	X	X		1	0	0
X	1	X	X		1	0	1
X	X	0	X		0	1	0
X	X	1	X		0	1	1
X	X	X		0	1	1	0
X	X	X		1	1	1	1

FUNCTIONAL CHARACTERISTICS

V_CC = 3.3V, GND = 0V, V_IN = 100mV, T_A = 25^.

2.5Gbps Mask (2^23-1 PRBS) Output Swing (100mV/div.) TIME (100ps/div.)

FUNCTIONAL CHARACTERISTICS

V_CC = 3.3V, GND = 0V, V_IN = 100mV, T_A = 25^.

INPUT AND OUTPUT STAGE INTERNAL TERMINATION

VCC IN 50Ω VT 50Ω /IN GND

Figure 3. Simplified Differential Input Stage

INPUT INTERFACE APPLICATIONS

Vcc CML IN /IN GND NC VT SY89547L

Figure 4a. CML Interface (DC-Coupled)

VCC CML GND IN IN SY89547L VCC -1.4V VT GND

Figure 4b. CML Interface (AC-Coupled)

VCC LVPECL GND VCC 0.01αF IN /IN VT Rp For VCC = 3.3V, Rp = 50Ω SY89547L

Figure 4c. LVPECL Interface (DC-Coupled)

VCC LVPECL IN IN GND Rp Rp GND VCC-1.4V VT GND For VCC = 3.3V, Rp = 100Ω SY89547L

Figure 4d. LVPECL Interface (AC-Coupled)

Vcc LVDS GND IN /IN SY89547L NC VT

Figure 4e. LVDS Interface

OUTPUT INTERFACE APPLICATIONS

LVDS specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.

V_OH, V_OL OUT 100ΩV V_OH, V_OL GND

Figure 5a. LVDS Differential Measurement

50Ω 50Ω GND VOCM, ΔVOCM

Figure 5b. LVDS Common Mode Measurement

RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION

Part Number Function Data Sheet Link
SY89542U 2.5 V	3.2Gbps Dual, Differential 2:1 LVDS http://www.micrel.com/ PDF/HBW/sy89542u.pdfMultiplexer with Internal Input Termination
SY89543L 3.3V,	3.2Gbps Dual, Differential 2:1 LVDS http://www.micrel.com/ PDF/HBW/sy89543l.pdfMultiplexer with Internal Input Termination
SY89544U 2.5V,	3.2Gbps, Differential 4:1 LVDS Multiplexer http://www.micrel.com/ PDF/HBW/sy89544u.pdfwith Internal Input Termination	w.micrel.com/ PDF/HBW/sy89544u.pdf
SY89545L 3.3V,	3.2Gbps 4:1 LVDS Multiplexer with Internal http://www.micrel.com/ PDF/HBW/sy89545l.pdfInput Termination	w.micrel.com/ PDF/HBW/sy89545l.pdf
SY89546U 2.5V,	3.2Gbps, Differential 4:1 LVDS Multiplexer http://www.micrel.com/ PDF/HBW/SY89546u.pdfwith 1:2 Fanout and Internal Termination	w.micrel.com/ PDF/HBW/SY89546u.pdf
	MLF® Application Note www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf
HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml

32-PIN MicroLeadFrame® (MLF-32)

5.0 BSC 32 1 2 PIN #1 ID 0.20 DIA TYP. 5.0 BSC

TOP VIEW

0.25±0.05 32X 0.50 BSC 32 PIN #1 ID R0.20 0.20 MIN. 3.10±0.10 1 2 0.40±0.05 4X 3.10±0.10

BOTTOM VIEW

NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

SIDE VIEW

Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane Heavy Copper Plane Vcc Vee

PCB Thermal Consideration for 32-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 [phone] FAX + 1 [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

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