SY89546U - Multiplexeur Microchip - Free user manual and instructions

USER MANUAL SY89546U Microchip

2.5V, 3.2 Gbps Differential 4:1 LVDS Multiplexer with 1:2 Fanout and Internal Termination

Features

• Selects Among Four Differential Inputs
• Provides Two Copies of the Selected Input
  • Guaranteed AC Parameters Over Temp/Voltage:

- DC- to >3.2 Gbps Data Rat Throughput

• <620 ps In-to-Out t PD
• <150 ps t_r/t_f Time
• Unique Input Isolation Design Minimize Crosstalk

- Ultra-Low Jitter Design:

• <1 ps RMS Random Jitter
• <10 ps PP Deterministic Jitter
• <10 ps PP Total Jitter (Clock)

• <0.7 ps RMS Crosstalk Induced Jitter

• Internal Input Termination

• Unique Input Termination and VT Pin Accepts DC-Coupled and AC-Coupled Inputs (LVDS, LVPECL, CML)
  • 350 mV LVDS Output Swing
  • Power Supply 2.5V ±5%
• - 40^ C to + 85^ C Temperature Range
  • Available in 32-pin (5 mm x 5 mm) VQFN Package

Applications

• SONET/SDH Multi-Channel Select applications
• Fibre Channel Applications
- GigE application

General Description

The SY89546U is a precision, high-speed 4:1 differential multiplexer that provides two copies of the selected input. The high speed LVDS (350 mV) compatible outputs with a guaranteed throughput of up to 3.2 Gbps over temperature and voltage.

The SY89546U differential inputs include Microchip's unique 3-pin internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards, both AC- and DC-coupled without external resistor-bias and termination networks. The result is a clean, stub-free, low jitter interface solution.

The SY89546U operates from a single 2.5V supply, and is guaranteed over the full industrial temperature range ( -40^ to +85^ ). For applications that require a 3.3V supply, consider the SY89547L. Or, for applications that only require one differential output, consider the SY89544U or SY89545L. The SY89546U is part of Microchip's Precision Edge ^® product family.

Package Type

SY89546U 5 mm x 5 mm VQFN-32 (M) (Top View) IN1 VT1 /IN1 VCC VCC IN2 VT2 /IN2 VCC 32 31 30 29 28 27 26 25 1○ 24 VCC /INO 2 23 VT0 3 22 IN0 4 21 VCC 5 20 SEL0 6 19 GND 7 18 VCC 8 17 GND Q0 /Q0 GND GND Q1 /Q1 GND

Functional Block Diagram

graph TD
    subgraph Power supplies
        IN0["IN0"] --> VT0["VT0"]
        IN0 --> /IN0["/IN0"]
        VT0 --> MUX1["4:1 MUX"]
        /IN0 --> MUX1
        VT1["VT1"] --> MUX1
        /IN1["IN1"] --> MUX1
        VT1 --> MUX2["4:1 MUX"]
        /IN1 --> MUX2
        VT2["VT2"] --> MUX2
        /IN2["IN2"] --> MUX2
        VT2 --> MUX3["4:1 MUX"]
        /IN2 --> MUX3
        VT3["VT3"] --> MUX3
        /IN3["IN3"] --> MUX3
    end

    subgraph Control Inputs
        IN3["IN3"] --> SEL0["SEL0 (CMOS/TTL)"]
        IN3 --> SEL1["SEL1 (CMOS/TTL)"]
    end

    MUX1 --> S1["S1"]
    MUX2 --> S1
    MUX3 --> S1

    Q0["Q0"] --> LVDS["LVDS"]
    Q1["Q1"] --> LVDS
    LVDS --> Q0
    LVDS --> Q1

    4:1 MUX --> 0
    4:1 MUX --> 1
    4:1 MUX --> 2
    4:1 MUX --> 3
    4:1 MUX --> 4:1 MUX

    1:2 Fanout --> Q0
    1:2 Fanout --> Q1

    style Power supplies fill:#f9f,stroke:#333
    style Control inputs fill:#ccf,stroke:#333

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltage ( V_CC ) -0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

Termination Current ( I_VT ) Note 1 Source or Sink on VT Pin....±100 mA

Input Current Source or Sink Current on IN, /IN ....±50 mA

Storage Temperature Range ( T_S ) -65^ to +150^

Operating Ratings ††

Supply Voltage ( V_CC )....+2.375V to +2.675V

Ambient Temperature Range ( T_A )....-40°C to +85°C

† Notice: Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

†† Notice: The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

DC ELECTRICAL CHARACTERISTICS Note 3

Electrical Characteristics: V_CC = 2.5V ± 5% ; -40^ ≤ T_A ≤ +85^ , unless stated otherwise.

Parameters Symbol	Min. Typ.	Max. Units	Conditions
Power Supply	V_CC	2.375	2.5	2.625	V	—
Power Supply Current	I_CC	—	75	100	mA	No load, max. V_CC Note 2
Differential Input Resistance (IN-to-/IN)	R_DIFF\_IN	80	100	120	Ω	—
Input Resistance (IN-to- V_T , /IN-to- V_T )	R_IN	40	50	60 Ω	—
Input HIGH Voltage IN, /IN	V_IH	1.2	—	V_CC	V	—
Input LOW Voltage IN, /IN	V_IL	0	—	V_IH-0.1	V	—
Input Voltage Swing IN, /IN	V_IN	0.1	—	V_CC	V	Note 4
Differential Input Voltage Swing	V_DIFF\_IN	0.2	—	—	V	Note 4
Voltage from IN or /IN to V_T	IN-to- V_T	—	—	1.8	V	—

Note 1: Due to the limited drive capability use for input of the same package only.

2: Includes current through internal 50Ω pull-ups.

3: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

4: See Section 5.0, Single-Ended and Differential Swings for V_IN and V_DIFF_IN definition.

LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS Note 1

Electrical Characteristics: V_CC = 2.5V ± 5% ; -40^ ≤ T_A ≤ +85^ , R_L = 100 across Q and /Q, unless stated otherwise.

Parameter Symbol Min. Typ. Max.	Units Condition
Output High Voltage (Q, /Q) V	_OH	— — 1.475 V See Figure 8-1
Output Low Voltage (Q0, /Q)	V_OL	0.925	—	—	V See Figure 8-1
Output Voltage Swing (Q0, /Q)	V_OUT	250	350	—	mV See Figure 5-1, Figure 9-1
Differential Output Voltage Swing (Q - /Q)	V_DIFF\_OUT	500	700	—	mV See Figure 5-2
Output common Mode Voltage (Q, /Q)	V_OCM	1.125	— 1.275 V See Figure 8-2
Change in Common Mode Voltage (Q, /Q)	V_OCM	-50	—	+50	mV See Figure 8-2

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

LVTTL/CMOS OUTPUT DC ELECTRICAL CHARACTERISTICS Note 1

Electrical Characteristics: V_CC = 2.5V ± 5% ; -40^ ≤ T_A ≤ +85^ , R_L = 100 across Q and /Q, unless stated otherwise.

Parameter Symbol Min. Typ. Max.	Units Condition
Input High Voltage	V_IH	2.0	—	V_CC	V	—
Input Low Voltage	V_IL	0	—	0.8	V —
Input High Current	I_IH	-125	— 40	μA	—
Input Low Current	I_IL	-300	—	—	μA	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS Note 1

Electrical Characteristics: V_CC = 2.5V ± 5% ; -40^ ≤ T_A ≤ +85^ , R_L = 100 across Q and /Q, unless stated otherwise.

Parameter Symbol	Min. Typ.	Max. Units Condition
Maximum Operating Frequency	f_MAX	3.2 —	— Gbps	NRZ (Data)
		3 4 —	GHz V		OUT ≥ 200 mV (Clock)
Differential Propagation Delay	t_PD	330 430 530			SEL-to-Q	IN-to-Q
		200 400 700
Input-to-Input Skew	t_SKEW	— 4	20		Note 2ps
Output-to-Output Skew		—	8	20		Note 3
Part-to-Part Skew		—	—	200		Note 4
Random Jitter ( R_J )	t_JITTER	— —	1 ps		RMS	Data Note 5
Deterministic Jitter ( D_J )		— —	10	ps	PP	Data Note 6
Total Jitter ( T_J )		— —	10	ps	PP	Clock Note 7
Cycle-to-Cycle Jitter		— —	1 ps		RMS	Clock Note 8
Crosstalk-Induced Jitter Crosstalk		— — 0.7 ps			RMS	Note 9
Output Rise/Fall Time	t/t_f	35	80	150	ps	20% to 80% at full output swing

Note 1: Measured with 100 mV input swing. See Timing Diagrams for definition of parameters. High frequency AC parameters are guaranteed by design and characterization.
2: Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew does not include the output skew.
3: Output-to-output skew is measured between two different outputs under identical input transitions.
4: Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
5: Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25 Gbps and 3.2 Gbps.
6: Deterministic jitter is measured at 1.25 Gbps and 3.2 Gbps, with both K28.5 and 2^23-1 PRBS pattern.
7: Total jitter definition: with an ideal clock input of frequency ≤ f_MAX no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
8: Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T-T _n-1 where T is the time between rising edges of the output cycle.
9: Crosstalk is measured at the output while applying two similar clock frequencies to adjacent inputs that are asynchronous with respect to each other at the inputs.

TEMPERATURE SPECIFICATIONS

Parameters Symbol Min.	Typ. Max.	Units Conditions
Temperature Ranges
Ambient Temperature T	A	-40 —	+85 °C —
Lead Temperature	—	—	—	+260	°C	Soldering, 20 sec.
Storage Temperature Range	TS	-65 —	+150	°C —
Package Thermal Resistances (Note 1)
Thermal Resistance, 5x5 VQFN-32 Lead	_JA	—	35	—	°C/W	Still-air, Multi-layer PCB
			28			500 lpfm, Multi-layer PCB
	_JB	—	20	—	°C/W	Junction-to-board

Note 1: Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

V_CC = 2.5V , GND = 0V, V_IN = 100 mV , T_A = +25^ , R_L = 100 across Q and /Q, unless otherwise stated.

FIGURE 2-1: 200 MHz Output.

Output Swing (70mV/div.) TIME (100ps/div.)

FIGURE 2-4: 1 x FC Mask (2 ^23 -1 PRBS).

FIGURE 2-2: 2.5 GHz Output.

Output Swing (70mV/div.) TIME (150ps/div.)

FIGURE 2-5: 1 x GBE Mask (2 PRBS).

FIGURE 2-3: OC-12 Mask (2 ^23 -1 PRBS).

Output Swing (70mV/div.) TIME (100ps/div.)

FIGURE 2-6: 2 x FC Mask (2 ^23 -1 PRBS).

Output Swing (70mV/div.) TIME (70ps/div.)

FIGURE 2-7: 1 x GBE Mask (2 PRBS).

FIGURE 2-8: 3.2 Gbps Eye (2 ^23 -1 PRBS).

FIGURE 2-9: Output Amplitude vs. Frequency.

3.0 PHASE NOISE PLOTS

V_CC=+3.3V,T_A=+25^.

FIGURE 3-1: 100 MHz Phase Jitter, Device.

FIGURE 3-2: 100 MHz Phase Jitter, Source.

FIGURE 3-3: 156.25 MHz Phase Jitter, Device.

FIGURE 3-4: 156.25 MHz Phase Jitter, Source.

FIGURE 3-5: 622 MHz Phase Jitter, Device.

FIGURE 3-6: 622 MHz Phase Jitter, Source.

4.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 4-1.

TABLE 4-1: PIN FUNCTION TABLE

Pin Number Pin Name Description
4, 2, 21, 32, 30, 27, 25, 23, 21	IN0, /IN0 IN1, /IN1IN2, /IN2 IN3, /IN3	Differential Inputs: These inputs pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100 mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Unused differential input pairs can be terminated by connecting one input to V_CC and the complementary input to GND through a 1 kΩ resistor. The VT pin is to be left open in this configuration. Please refer to Section 8.0 “Input Interface Applications” for details.
3, 31, 26, 22 VT0,	VT1, VT2, VT3	Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT pin. The V_TA0 , V_TA1 , V_TB0 , V_TB1 pins provide a center-tap to a termination network for maximum interface flexibility. See Section 8.0 “Input Interface Applications”.
6, 19 SEL0,	SEL1	These single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexers. Note that these inputs are internally connected to a 25 kΩ pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold is V_CC/2 .
1, 5, 8, 17, 20, 24, 28, 29	VCC Positive	Power Supply: Bypass with 0.1 μF//0.01 μF low ESR capacitors.
10, 11, 14, 15 Q0,	/Q0 Q1, /Q1	Differential Outputs: These LVDS outputs pairs are the outputs of the device. They are a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to Table 4-2 for details. If an output is not used, it must be terminated with 100Ω across the differential pair.
7, 9, 12, 13, 16, 18	GND, Exposed Pad	Ground. Ground pin and exposed pad must be connected to the same ground plane.

TRUTH TABLE

TABLE 4-2: TRUTH TABLE

IN0	IN1	IN2	IN3	SEL0	SEL1	Q	/Q
0	X	X	X	0	0	0	1
1	X	X	X	0	0	1	0
X	0	X	X	1	0	0	1
X	1	X	X	1	0	1	0
X	X	0	X	0	1	0	1
X	X	1	X	0	1	1	0
X	X	X	0	1	1	0	1
X	X	X	1	1	1	1	0

5.0 SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_{IN} V_{OUT} 350mV (Typ.)

FIGURE 5-1: Single-Ended Voltage Swing.

VDIFF_IN VDIFF_OUT 700mV (Typ.)

FIGURE 5-2: Differential Voltage Swing.

6.0 TIMING DIAGRAMS

/IN IN /Q Q t_pd

SEL SEL-to-Q Q /Q t_pd

FIGURE 6-1: Timing Diagrams.

7.0 INPUT STAGE

Vcc IN 50Ω VT 50Ω /IN GND

FIGURE 7-1: Simplified Differential Input Stage.

8.0 INPUT INTERFACE APPLICATIONS

VCC CML IN /IN SY89546U NC VT

FIGURE 8-1: CML Interface (DC-Coupled).

VCC LVPECL IN Rp Rp GND GND VCC-1.4V VT GND /IN SY89546U For VCC = 2.5V, Rp = 50Ω

FIGURE 8-4: LVPECL Interface (AC-Coupled).

VCC CML IN /IN GND SY89456U VCC- 1.4V VT GND

FIGURE 8-2: CML Interface (AC-Coupled).

Vcc LVDS IN /IN SY89546U NC VT

FIGURE 8-5: LVDS Interface.

VCC LVPECL GND VCC 0.01μF IN /IN SY89546U VT Rp For VCC = 2.5V, Rp = 18Ω

FIGURE 8-3: LVPECL Interface (AC-Coupled).

9.0 OUTPUT INTERFACE APPLICATIONS

LVDS specifies a small swing of 350 mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.

V_OH, V_OL V_OH, V_OL OUT 100ΩV GND

FIGURE 9-1: LVDS Differential Measurement.

50Ω 50Ω VOCM, ΔVOCM GND

FIGURE 9-2: LVDS Common Mode Measurement.

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

32-Lead VQFN*

XXXXXXXXX

WWNNN

COO

Example

SY89546U

11924

USA

Legend: XX...X Product code or customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

eBb-free JEDEC ^® designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( ) e3

can be found on the outer packaging for this package.

•, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark).

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo.

Underbar (_) and/or Overbar (−) symbol may not be to scale.

32-Lead Very Thin Plastic Quad Flat, No Lead Package (PEA) - 5x5x0.9 mm Body [VQFN] Micrel Legacy Package QFN55-32LD-PL-1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

NOTE 1 N 1 2 (DATUM B) (DATUM A) 2X 0.10 C 2X 0.10 C TOP VIEW D2 0.10 A B K E2 A1 (A3) SEATING PLANE C SIDE VIEW NOTE 1 N L e 32X b 0.10 A B 0.05 B BOTTOM VIEW

Microchip Technology Drawing C04-1118-PEA Rev A Sheet 1 of 2

32-Lead Very Thin Plastic Quad Flat, No Lead Package (PEA) - 5x5x0.9 mm Body [VQFN] Micrel Legacy Package QFN55-32LD-PL-1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Technical line drawing of two integrated circuit chips with pinouts (no text or symbols)

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Terminals	N	32
Pitch	e	0.50 BSC
Overall Height	A	0.80	0.85	0.90
Standoff	A1	0.00	0.02	0.05
Terminal Thickness	A3	0.203 REF
Overall Length	D	5.00 BSC
Exposed Pad Length	D2 3	05	3.10 3.15
Overall Width	E	5.00 BSC
Exposed Pad Width	E2	3.05 3.10	3.15
Terminal Width	b	0.20	0.25	0.30
Terminal Length	L	0.35	0.40	0.45
	K		-

0.20 -Terminal-to-Expos

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-1118-PEA Rev A Sheet 2 of 2

32-Lead Very Thin Plastic Quad Flat, No Lead Package (PEA) - 5x5x0.9 mm Body [VQFN] Micrel Legacy Package QFN55-32LD-PL-1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

C1 X2 EV 32 1 2 Y2 C2 EV G2 ØV G1 Y1 X1 SILK SCREEN E

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.50 BSC
Optional Center Pad Width	X2			3.15
Optional Center Pad Length	Y2			3.15
	C1	Contact Pad Spacing 4.90
Contact Pad Spacing	C2		4.90
Contact Pad Width (Xnn)	X1			0.30
Contact Pad Length (Xnn)	Y1			0.90
Contact Pad to Center Pad (Xnn) G1	0.43
Contact Pad to Contact Pad (Xnn) G2	0.20
Thermal Via Diameter V			0.33
Thermal Via Pitch EV			1.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process

Microchip Technology Drawing C04-3118-PEA Rev A

NOTES:

APPENDIX A: REVISION HISTORY

Revision A (July 2023)

• Converted Micrel document SY89546U to Microchip data sheet template DS20006333A.
• Minor text changes throughout.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

PART NO. X Device Supply Voltage X Package Temperature Range XX Special Processing

Device:

SY89546: 2.5V, 3.2 Gbps Differential 4:1 LVDS Multiplexer with 1:2 Fanout and Internal Termination

Supply Voltage: U = 2.5V

Package:

M = 5 mm x 5 mm VQFN-32 (NiPdAu Lead-Free)

Temperature Range:

G = -40°C to 85°C

Special Processing:

= 60/Tray TR = 1,000/Reel

Examples:

a) SY89546UMG: SY89546, 2.5V Supply

Voltage, 3 mm x 3 mm 32-Lead

VQFN, -40^ to +85^

Temperature Range, 60/Tray

b) SY89546UMG-TR: SY89546, 2.5V Supply

Voltage, 3 mm x 3 mm 32-Lead

VQFN, -40^ to +85^

Temperature Range, 1,000/Reel

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

NOTES:

Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
- Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products.

This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https://www.microchip.com/en-us/support/design-help/client-support-services.

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Trademarks

The Microchip name and logo, the Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

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ISBN: 978-1-6683-2892-7

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