SY89840U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89840U Microchip

The SY89840U is a low jitter PECL, 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89840U unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or "runt" pulses during switchover. In addition, a unique Fail-Safe Input protection prevents metastable conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV).

The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC or DC-coupled) as small as 100mV (200mV _pp ) without any level shifting or termination resistor networks in the signal path. The output is 800mV, 100K compatible LVPECL with fast rise/fall times guaranteed to be less than 190ps.

The SY89840U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89840U is part of Micrel's high-speed, Precision Edge® product line. All support documentation can be found on Micrel's web site at: www.micrel.com.

Precision Edge®

Features

• Selects between two sources, and provides a glitch-free, stable LVPECL output
  • Guaranteed AC performance over temperature and supply voltage:
  – Wide operating frequency: 1kHz to >1.5GHz
• < 880ps In-to-Out t pd
• < 190ps t r/tf
• Unique patent-pending input isolation design minimizes crosstalk
  • Fail-safe input prevents oscillations
  • Ultra-low jitter design:
• 140fs RMS phase jitter (Typ)
• 0.7ps _rms MUX crosstalk induced jitter
• Unique patent-pending input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS)
  • 800mV LVPECL output swing
  • 2.5V ±5% or 3.3V ±10% supply voltage
• -40°C to +85°C industrial temperature range
  • Available in 16-pin (3mm x 3mm) QFN package

Applications

• Redundant clock switchover
• Failsafe clock protection

Markets

• LAN/WAN
- Enterprise servers
- ATE
• Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax + 1 [phone] • http://www.micrel.com

Typical Application

graph TD
    subgraph_Primary_Clock_From_System["Primary Clock From System"]
        IN0["IN0"] --> V_T0["V_T0"]
        IN0 --> /IN0["/IN0"]
        V_T0 --> MUX["2:1 MUX"]
        /IN0 --> MUX
        V_REF_AC0["REF-AC0"] --> MUX
    end

    subgraph_Secondary_Clock_From_Oscillator["Secondary Clock From Local Oscillator"]
        IN1["IN1"] --> V_T1["V_T1"]
        IN1 --> /IN1["/IN1"]
        V_T1 --> MUX
        /IN1 --> MUX
        V_REF_AC1["REF-AC1"] --> MUX
    end

    MUX --> S["S"]
    S --> Runt["Pulse Elimination Logic"]
    Runt --> SEL["SEL (LVTTL/CMOS)"]
    SEL --> MUX
    MUX --> 2:1["MUX"]
    2:1 --> 0["0"]
    0 --> MUX
    MUX --> 1["S"]
    1 --> Runt

Primary Clock Secondary Clock SEL Select Primary Select Secondary OUTPUT Runt pulse eliminated from output Switchover occurs Simplified Example Illustrating RPE (Runt Pulse Elimination) Circuit when Primary Clock Fails

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY89840UMG	QFN-16	Industrial	840U with bar-linePb-Free indicator	NiPdAuPb-Free
SY89840UMGTR(2)	QFN-16	Industrial	840U with bar-linePb-Free indicator	NiPdAuPb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals Only.

2. Tape and Reel.

Pin Configuration

IN1 VT1 VREF-AC1 /IN1 /IN0 16 15 14 13 VREF-AC0 2 12 VCC VT0 3 11 CAP IN0 4 10 SEL 5 6 7 8 GND VCC Q /Q VCC

16-Pin QFN (QFN-16)

Pin Description

Pin Number	Pin Name	Pin Function
4, 1,16, 13	IN0, /IN0,IN1, /IN1	Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC or DC-coupled signals as small as 100mV (200mVpp). Each pin of a pair internally terminates to a VTpin through 50Ω. Please refer to the “Input Interface Applications” section for more details.
3, 15	VT0, VT1	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See the “Input Interface Applications” section for more details.
2, 14	VREF-AC0VREF-AC1	Reference Voltage: This output biases to Vcc-1.2V. It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01μF low ESR capacitor to Vcc. Maximum sink/source current is ±1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. See “Input Interface Applications” section.
10	SEL	This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open.
5, 8, 12	VCC	Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to VCC pins as possible.
6, 7	Q, /Q	Differential Outputs: This differential LVPECL output is a logic function of the IN0, IN1, and SEL inputs. Please refer to the truth table below for details.
9	GND Exposed Pad	Ground: Ground pin and exposed pad must be connected to the same ground plane.
11	CAP	Power-On Reset (POR) Initialization capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to Vcc. The purpose is to ensure the internal RPE logic starts up in a known state. See "Power-On Reset (POR) Description" section for more details regarding capacitor selection. If this pin is tied directly to Vcc, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open.

Truth Table

INPUTS					OUTPUTS
IN0	/IN0	IN1	/IN1	SEL	Q	/Q
0	1	X	X	0	0	1
1	0	X	X	0	1	0
X	X	0	1	1	0	1
X	X	1	0	1	1	0

Absolute Maximum Ratings ^(1)

Supply Voltage (Vcc)....-0.5V to +4.0V

Input Voltage ( V_IN )....-0.5V to V_CC

LVPECL Output Current ( I_OUT )

Continuous .... ±50mA

Surge....±100mA

Termination Current

Source/Sink Current on V T ±100mA

Source/Sink Current on IN, /IN.... ±50mA

V_REF-AC Current

Source/sink current on V REF-AC ±2mA

Lead Temperature (soldering, 20 sec.) ....+260°C

Storage Temperature (Ts)....-65°C to 150°C

Operating Ratings ^(2)

Supply Voltage (Vcc) +2.375V to +2.625V

......+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

QFN ( _JA )

Still-Air 60°C/W

QFN (Ψ JB)

Junction-to-Board 33°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ ; unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply		2.375		2.625	V
			3.0		3.6	V
I_CC	Power Supply Current	No load, max V_CC .		65	95	mA
R_IN	Input Resistance(IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance(IN-to-/IN)		90	100	110	Ω
V_IH	Input High Voltage(IN, /IN)		1.2		V_CC	V
V_IL	Input Low Voltage(IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing(IN, /IN)	See Figure 1a. Note 5	0.1		V_CC	V
V_DIFF\_IN	Differential Input Voltage Swing|IN-/IN|	See Figure 1b.	0.2			V
V_IN\_FSI	Input Voltage Threshold that Triggers FSI			30	100	mV
V_T\_IN	IN-to- V_T (IN, /IN)				1.28	V
V_REF-AC	Output Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IN (max) is specified when V_T is floating.

LVPECL Outputs DC Electrical Characteristics ^(6)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C ; R_L = 50 to V_CC-2V , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	Output HIGH VoltageQ, /Q		V_CC-1.145		V_CC-0.895	V
V_OL	Output Low VoltageQ, /Q		V_CC-1.945		V_CC-1.695	V
V_OUT	Output Voltage SwingQ, /Q	See Figure 1a	550	800		mV
V_DIFF-OUT	Differential Output Voltage SwingQ, /Q	See Figure 1b	1100	1600		mV

LVTTL/CMOS DC Electrical Characteristics ^(6)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(7)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , R_L = 50 to V_CC-2V , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency	Clock	1.5	2.0		GHz
t_pd	Differential Propagation Delay In-to-QIn-to-QSEL-to-QSEL-to-Q	100mV < V_IN ≤ 200mV^(8)	480	625	880	ps
		200mV < V_IN ≤ 800mV^(8)	460	600	820	ps
		RPE enabled, see Timing Diagram			17	cycles
		RPE disabled ( V_IN = V_CC/2 )	550		900	ps
t_pd Tempco	Differential Propagation DelayTemperature Coefficient			115		fs/°C
t_SKEW	Part-to-Part Skew	Note 9			200	ps
t_Jitter	RMS Phase Jitter	Output = 622MHzIntegration Range 12mHz – 20MHz			140	fs
	Crosstalk-induced Jitter	Note 10			0.7	ps_rms
t_r, t_f	Output Rise/Fall Time (20% to 80%)	At full output swing	70	130	190	ps

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
2. Propagation delay is measured with input t_r , t_f ≤ 300ps (20% to 80%) and V_IL ≥ 800mV .
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.

10.

1. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs.

Functional Description

RPE MUX and Fail-Safe Input

The SY89840U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits:

Runt-Pulse Eliminator (RPE) Circuit:

The RPE MUX provides a “glitchless” switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to V cc, the RPE function will be disabled and the multiplexer will function as a normal multiplexer.

Fail-Safe Input (FSI) Circuit:

The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum single-ended input amplitude limit ( V_IN ), or 200mV differentially ( V_DIFF_IN ), the output will latch to the last valid clock state.

RPE and FSI Functionality

The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to "Timing Diagrams" for more detailed information.

Case #1 Two Normal Clocks and RPE Enabled

In this case the frequency difference between the two running clocks IN0 and IN1 must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz.

If the SEL input changes state to select the alternate clock, the switchover from CLK1 to CLK2 will occur in three stages.

• Stage 1: The output will continue to follow CLK1 for a limited number of pulses.
• Stage 2: The output will remain LOW for a limited number of pulses of CLK2.
  • Stage 3: The output follows CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Stage 1 Select CLK1 3 to 5 falling edges of CLK1 4 to 5 falling edges of CLK2 Stage 2 Select CLK2 Stage 3 Runt pulse eliminated from output

Timing Diagram 1

Case #2 Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE enabled).

If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages.

• Stage 1: The output will remain HIGH for a limited number of pulses of CLK2.
• Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2.
  • Stage 3: The output will follow CLK2

CLK1 CLK2 SEL Select CLK1 OUTPUT Stage 1 Select CLK1 Select CLK2 Runt pulse eliminated from output Stage 2 14 to 16 falling edges of CLK2 Stage 3

Timing Diagram 2

Note:

Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period.

Case #3 Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPE enabled).

If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages.

• Stage 1: The output will remain LOW for a limited number of falling edges of CLK2.
  • Stage 2: The output will follow CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Stage 1 Select CLK2 Stage 2 13 to 17 falling edges of CLK2

Timing Diagram 3

Case #4 Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE enabled).

If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV ( V_IN ) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending on the last valid state at the CLK1.

If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI

function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions.

Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for more detailed information.

CLK1 CLK2 SEL Select CLK1 Select CLK2 OUTPUT as in case #2 as in case #3

Timing Diagram 4

Power-On Reset (POR) Description

The SY89840U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between V_cc and the CAP pin (pin 11) controls the delay for the power-on reset function.

Calculation of the required capacitor value is based on the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V.

The following equation describes this relationship:

$$ C (\mu F) \geq \frac {t _ {d P S} (m s)}m s \mu F) / $$

As an example, if the time required for the system power supply to power up past 2.3V is 12ms, the required capacitor value on pin 11 would be:

$$ C (\mu F) \geq \frac {1 2 m s}{m s \mu F)} $$

$$ \mathrm{C} (\mu \mathrm{F}) \geq 1 \mu F $$

Typical Operating Characteristics

V_CC = 3.3V , GND = 0V, V_IN ≥ 400mV_pk , t_f/t_f ≤ 300ps , R_L = 50 to V_CC-2V , T_A = 25^ C , unless otherwise stated.

Singled-Ended and Differential Swings

V_IN, V_OUT 800mV (typical)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 1600mV (typical)

Figure 1b. Differential Voltage Swing

Input and Output Stages

VCC IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Stage

VCC /Q Q

Figure 2b. Simplified LVPECL Output Stage

Input Interface Applications

Vcc LVPECL IN /IN SY89840U Vcc 0.01μF VT Rpd GND NC VREF-AC Note: For 3.3V, Rpd = 50Ω. For 2.5V, Rpd = 19Ω.

Figure 3a. LVPECL Interface (DC-Coupled)

VCC LVPECL IN Rpd Rpd GND GND VCC 0.01μF VT VREF-AC SY89840U Note: For 3.3V, Rpd = 100Ω. For 2.5V, Rpd = 50Ω.

Figure 3b. LVPECL Interface (AC-Coupled)

VCC CML IN IN SY89840U GND NC □ VT NC □ VREF-AC Option: may connect VT to VCC

Figure 3c. CML Interface (DC-Coupled)

VCC CML GND IN IN SY89840U VCC VT VREF-AC 0.01μF

Figure 3d. CML Interface (AC-Coupled)

VCC LVDS GND IN IN SY89840U NC □ VT NC □ VREF-AC

Figure 3e. LVDS Interface

LVPECL Output Interface Applications

LVPECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. LVPECL is ideal for driving 50Ω and 100Ω controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel

Termination-Thevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.

+3.3V Z₀ = 50Ω Z₀ = 50Ω For +2.5V systems, R1 = 250Ω, R2 = 62.5Ω +3.3V R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω Vₜ = V꜀꜀ -2V

Figure 4a. Parallel Termination-Thevenin Equipment

+3.3V Z = 50Ω Z = 50Ω "source" 50Ω 50Ω Rb +3.3V "destination" Vcc C1 (optional) 0.01μF Notes:

Notes:

1. Power-saving alternative to Thevenin termination.

2. Place termination resistors as close to destination inputs as possible.

3. R_b resistor sets the DC bias voltage, equal to V_T .

4. For 2.5V systems, R_b = 19 , For 3.3V systems, R_b = 50

Figure 4b. Parallel Termination (3-Resistor)

Part Number	Function	Data Sheet Link
SY89841U	Precision LVDS Runt Pulse Eliminator 2:1 Multiplexer	www.micrel.com/product-info/products/sy89841u.shtml
SY89842U	Precision CML Runt Pulse Eliminator 2:1 Multiplexer	www.micrel.com/product-info/products/sy89842u.shtml
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

QFN-16 Package (3mmx3mm)

Pin 1 Dot By Marking 3.000±0.050 3.000±0.050

TOP VIEW

0.850±0.050 0.000-0.050 0.203±0.025

SIDE VIEW

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.550±0.050 Exp. DAP 0.400±0.050 1.550±0.050 Exp. DAP 0.230±0.050 0.500 Bsc 1.500 Ref.

BOTTOM VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX PACKAGE WARPAGE IS 0.05 mm
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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