SY89875U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89875U Microchip

■ Integrated programmable clock divider and 1:2 fanout buffer
■ Guaranteed AC performance over temperature and voltage:
• > 2.0GHz f MAX
• < 200ps t r/tf
• < 15ps within device skew
■ Low jitter design:
• < 10ps PP total jitter
• < 1ps RMS cycle-to-cycle jitter
■ Unique input termination and ¥Pin for DC-coupled and AC-coupled Inputs; CML, PECL, LVDS and HSTL
■ LVDS compatible outputs
■ TTL/CMOS inputs for select and reset
■ Parallel programming capability
■ Programmable divider ratios of 1, 2, 4, 8 and 16
■ Low voltage operation 2.5V
■ Output disable function
- -40°C to 85°C temperature range
■ Available in 16-pin (3mm x 3mm) MLP® package

APPLICATIONS

■ SONET/SDH line cards
■ Transponders
■ High-end, multiprocessor servers

FUNCTIONAL BLOCK DIAGRAM

graph TD
    S2 --> A["NOT"]
    /RESET --> B["NOT"]
    IN --> C["AND"]
    VT --> D["AND"]
    /IN --> E["AND"]
    S1 --> F["Decoder"]
    S0 --> F
    F --> G["Enable FF"]
    G --> H["Enable MUX"]
    H --> I["MUX"]
    I --> J["NOT"]
    Q0 --> K["NOT"]
    /Q0 --> L["NOT"]
    Q1 --> M["NOT"]
    /Q1 --> N["NOT"]
    VREF_AC --> F
    DividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDividedByDivd

DESCRIPTION

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through.

The differential input buffer has a unique internal termination design that allows access to the termination network through a V_T pin. This feature allows the device to easily interface to different logic standards. A V_REF-AC reference is included for AC-coupled applications.

The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN).

TYPICAL PERFORMANCE

OC-12 to OC-3 Translator/Divider CML/LVPECL/LVDS 622MHz Clock In Divide-by-4 LVDS 155.5MHz Clock Out 622MHz In IN /IN Q0 /Q0 155.5MHz Out

Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

PACKAGE/ORDERING INFORMATION

S0 S1 VCC GND 16 15 14 13 Q0 1 12 IN /Q0 2 11 VT Q1 3 10 VREF-AC /Q1 4 9 /IN 5 6 7 8 S2 NC VCC /RESET

16-Pin MLF ^® (MLF-16)

Ordering Information(1)

Part Number	Package Type	Operating Range	Package Marking	Lead	Finish
SY89875UMI	MLF-16	Industrial	875U		Sn-Pb
SY89875UMITR(2)	MLF-16	Industrial	875U		Sn-Pb
SY89875UMG(3)	MLF-16	Industrial	875U with Pb-Free bar line indicator		NiPdAu Pb-Free
SY89875UMGTR(2, 3)	MLF-16	Industrial	875U with Pb-Free bar line indicator		NiPdAu Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.

PIN DESCRIPTION

Pin Number Pin Name Pin Function
12, 9 IN, /IN Differential Input: Internal 50 termination resistors to V _T input. Flexible input accepts any differential input. See “Input Interface Applications” section.
1, 2, 3, 4	Q0, /Q0Q1, /Q1 Unused output pairs must be terminated with 100 across the different pair.
16, 15, 5	S0, S1, S2	Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25k pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is V_CC/2 .
6 NC No Connect.
8	/RESET,/DISABLE	LVTTL/CMOS Logic Levels: Internal 25k pull-up resistor. Logic HIGH if left unconnected. Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable function. The reset and disable function occurs on the next high-to-low clock input transition. Input threshold is V_CC/2 .
10 VREF-AC Reference Voltage: Equal to V _CC-1.4V (approx.). Used for AC-coupled applications only.Decouple the V_REF-AC pin with a 0.01 F capacitor. See “Input Interface Applications” section.
11	VT	Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See Figures 4a to 4f, “Input Interface Applications” section.
7, 14	VCC	Positive Power Supply: Bypass with 0.1 F //0.01 F low ESR capacitor.
13	GND Exposed	Ground. Exposed pad must be connected to the same potential as the GND pin.

TRUTH TABLE

/ RESET^(1)	S2	S1	S0	Outputs
1	0 X	X	Reference Clock (pass through)
1	1 0	0	Reference Clock ÷2
1	1 0	1	Reference Clock ÷4
1	1 1	0	Reference Clock ÷8
1	1 1	1	Reference Clock ÷16
0^(1)	X	X	X	Q = LOW, /Q = HIGHClock Disable

Note 1. Reset/Disable function is asserted on the next clock input (IN, /IN) high-to-low transition.

Absolute Maximum Ratings ^(Note 1)

Supply Voltage ( V_CC )....-0.5V to +4.0V

Input Voltage ( V_IN ) ....-0.5V to V_CC+0.3

ECL Output Current ( I_OUT )

Continuous 50mA

Surge....100mA

Input Current IN, /IN ( I_IN ) ±50mA

V_T Current ( I_VT ) ±100mA

V_REF-AC Sink/Source Current ( I_VREF-AC ), Note 3 ..... ±2mA

Lead Temperature (soldering 20 sec.) 260°C

Storage Temperature ( T_S ) -65^ to +150^

Operating Ratings ^(Note 2)

Supply Voltage ( V_CC )....+2.5V ±5%

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance

MLF ^® ( _JA )

Still-Air.... 60°C/W

500lfpm 54°C/W

MLF ^® ( _JB ), Note 4

Junction-to-Board.... 32°C/W

Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

Note 3. Due to the limited drive capability use for input of the same package only.

Note 4. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the pcb.

DC ELECTRICAL CHARACTERISTICS (Notes 1, 2)

T_A = -40^ to +85^ ; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_CC	Power Supply		2.375		2.625	V
I_CC	Power Supply Current	No load, max. V_CC		70	95	mA
R_IN	Differential Input Resistance (IN-to-/IN)		90	100	110
V_IH	Input High Voltage (IN, /IN)	Note 3	0.1	-	V_CC+0.3 V
V_IL	Input Low Voltage (IN, /IN)	Note 3	-0.3	-	V_IH-0.1	V
V_IN	Input Voltage Swing	Note 4	0.1	-	V_CC	V
V_DIFF\_IN	Differential Input Voltage Swing	Note 5	0.2	-	-	V
|I_IN|	Input Current (IN, /IN)	Note 3	-	-	45	mA
V_REF-AC	Reference Voltage	Note 6	V_CC-1.525	V_CC-1.425	V_CC-1.325	V

Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

Note 2. Specification for packaged product only.

Note 3. Due to the internal termination (see Figure 2a) the input current depends on the applied voltages at IN, /IN and V_T -inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit!

Note 4. See "Timing Diagram" for V_IN definition. V_IN (Max) is specified when V_T is floating.

Note 5. See "Typical Operating Characteristics" section for V_DIFF definition.

Note 6. Operating using V_IN is limited to AC-coupled PECL or CML applications only. Connect directly to V_T pin.

LVDS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)

V_CC = 2.5V ± 5% ; T_A = -40^ to +85^ ; Unless otherwise stated.

Symbol Parameter Condition Min Typ		Max Units
V_OUT	Output Voltage Swing	Note 3, 4	250	350	400	mV
V_OH	Output High Voltage	Note 3			1.475	V
V_OL	Output Low Voltage	Note 3	0.925			V
V_OCM	Output Common Mode Voltage	Note 4	1.125		1.375	V
V_OCM	Change in Common Mode Voltage		-50		50	mV

Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.
Note 3. Measured as per Figure 2a, 100¥ across Q and /Q outputs.
Note 4. Measured as per Figure 2b.

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS(Notes 1, 2)

V_CC = 2.5V ± 5% ; T_A = -40^ to +85^ ; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
V_IH	Input HIGH Voltage 2.0 V
V_IL	Input LOW Voltage 0.8 V
I_IH	Input HIGH Current -125 20 μA
I_IL	Input LOW Current -300 μA

Note 1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 2. Specification for packaged product only.

AC ELECTRICAL CHARACTERISTICS(Notes 1, 2)

V_CC = 2.5V ± 5% ; T_A = -40^ to +85^ ; Unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units
f_MAX	Maximum Input Frequency Output Swing 200mV 2.0 2.5 GHz
t_PD	Differential Propagation Delay Input Swing < 400mV 590 690 870 ps
	IN to Q	Input Swing 400mV 540 690 820 ps
t_SKEW	Within-Device Skew (diff.)	Note 3		5	15	ps
	Part-to-Part Skew (diff.)	Note 3			280	ps
t_RR	Reset Recovery Time	Note 4	600			ps
t_JITTER	Cycle-to-Cycle Jitter	Note 5			1	ps_RMS
	Total Jitter	Note 6			10	ps_PP
t_r,t_f	Rise/Fall Time (20% to 80%)		70 120	200 ps

Note 1. Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 100y across each output pair, unless otherwise stated.
Note 2. Specification for packaged product only.
Note 3. Skew is measured between outputs under identical transitions.
Note 4. See "Timing Diagram."
Note 5. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T_jitter_cc = T_n - T_n+1 , where T is the time between rising edges of the output signal.
Note 6. Total jitter definition: with an ideal clock input of frequency - f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.

TIMING DIAGRAM

/RESET VCC/2 tRR IN VID IN VIN Swing tPD /Q VOUT Swing Q

TYPICAL OPERATING CHARACTERISTICS

V_CC = 2.5V, T_A = 25^ , unless otherwise stated.

TYPICAL OPERATING CHARACTERISTICS (Continued)

V_CC = 2.5V, T_A = 25^ , unless otherwise stated.

DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_{IN}, V_{OUT} 350mV (typical)

Figure 1a. Single-Ended Swing

VDIFF_IN, VDIFF_OUT 700mV (typical)

Figure 1b. Differential Swing

INPUT INTERFACE APPLICATIONS

VCC 1.86k 1.86k IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Buffer

Vcc R25kΩ S0 S1 S2 /RESET R GND

Figure 2b. Simplified TTL/CMOS Input Buffer

LVDS OUTPUTS

LVDS (Low Voltage Differential Swing) specifies a small swing of 350mV typical, on a nominal 1.25V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is also kept tight, to keep EMI low.

vOH, vOL VOD 100Ω VOH, vOL GND

Figure 3a. LVDS Differential Measurement

50Ω 50Ω VOCM ΔVOCM GND

Figure 3b. LVDS Common Mode Measurement

INPUT INTERFACE APPLICATIONS

VCC CML GND IN /IN SY89875U NC □ VT NC □ VREF_AC

Figure 4a. DC-Coupled CML Input Interface

VCC CML GND IN IN SY89875U VCC 0.01μF VT VREF_AC

Figure 4b. AC-Coupled CML Input Interface

VCC PECL GND 0.01μF VCC 39Ω VCC -2V VT NC VREF_AC IN IN SY89875U VCC

Figure 4c. DC-Coupled PECL Input Interface

VCC PECL 50Ω GND 50Ω IN IN VCC VREF_AC 0.01μF SY89875U

Figure 4d. AC-Coupled CML Input Interface

Vcc LVDS GND IN IN SY89875U NC □ VT NC □ VREF_AC Vcc

Figure 4e. LVDS Input Interface

VCC HSTL IN /IN SY89875U GND NC VT VREF_AC GND VCC

Figure 4f. HSTL Input Interface

RELATED PRODUCT AND SUPPORT DOCUMENTATION

Part Number F	Function Data Sheet Link
SY89872U	2.5V, 2.5GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer w/ Internal Termination	http://www.micrel.com/product-info/products/sy89872u.shtml
	MLF® Application Note http://www.amkor.com/products/notes_papers/mlf_appnote_0902.pdf
HBW Solutions	New Products and Applications	http://www.micrel.com/product-info/products/solutions.shtml

16-PIN MicroLeadFrame ^® (MLF-16)

Pin 1 Dot By Marking 3.000±0.050 3.000±0.050

TOP VIEW

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.550±0.050 Exp. DAP 0.400±0.050 1.550±0.050 Exp. DAP 0.500 Bsc 0.230±0.050 0.400±0.050 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.000-0.050 0.203±0.025

NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

SIDE VIEW Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane VFF VFF Heavy Copper Plane

PCB Thermal Consideration for 16-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

Note 1. Package meets Level 2 moisture sensitivity classification, and are shipped in dry-pack form.
Note 2. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

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The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

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