SY89540U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89540U Microchip

The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates up to 3.2Gbps over temperature and voltage.

The SY89540U differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC or DC-coupled) as small as 100mV (200mV _pp ) without any level shifting or termination resistor networks in the signal path. The LVDS compatible outputs maintain extremely fast rise/fall times guaranteed to be less than 120ps.

The SY89540U features a patent-pending isolation design that significantly improves on channel-to-channel crosstalk performance.

The SY89540U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). The SY89540U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at www.micrel.com.

Typical Performance

Precision Edge is a registered trademark of Micrel, Inc.

Precision Edge®

Features

• Provides crosspoint switching between any input pairs to any output pair
• Patent pending, channel-to-channel isolation design provides superior crosstalk performance
• Guaranteed AC performance over temperature and voltage:
• DC-to-3.2Gbps throughput
• <480ps propagation delay
• <120ps rise/fall time
• <30ps output-to-output skew
• Ultra-low jitter design:
• 95fs RMS phase jitter (Typ)
• 0.7ps _RMS crosstalk induced jitter
• Patent pending 50Ω input termination, extended CMVR, and VT pin accepts DC- and AC-coupled differential inputs
  • 350mV LVDS output swing
  • Power supply 2.5V ±5%
• -40°C to +85°C temperature range
  • Available in 44-pin (7mm x 7mm) QFN package
• Pb-Free Green package

Applications

• All SONET/SDH channel select applications
• All Fibre Channel multi-channel select applications
• All Gigabit Ethernet multi-channel select applications

Functional Block Diagram

graph TD
    subgraph FlipFlop_1
        IN0["IN0 500"] --> A1["NOT"]
        VT0["VT0 500"] --> A1
        /IN0["/IN0"] --> A1
        Vref_AC0["Vref_AC0"] --> A1
    end
    subgraph FlipFlop_2
        IN1["IN1 500"] --> A2["NOT"]
        VT1["VT1 500"] --> A2
        /IN1["/IN1"] --> A2
        Vref_AC1["Vref_AC1"] --> A2
    end
    subgraph FlipFlop_3
        IN2["IN2 500"] --> A3["NOT"]
        VT2["VT2 500"] --> A3
        /IN2["/IN2"] --> A3
        Vref_AC2["Vref_AC2"] --> A3
    end
    A1 --> Q0["Q0"]
    A2 --> Q1["Q1"]
    A3 --> Q2["Q2"]
    A4 --> Q3["Q3"]
    Q0 --> /Q0["/Q0"]
    Q1 --> /Q1["/Q1"]
    Q2 --> /Q2["/Q2"]
    Q3 --> /Q3["/Q3"]
    SIN0["SIN0 (CMOS/TTL)"] --> CONTROL["CONTROL"]
    SIN1["SIN1 (CMOS/TTL)"] --> CONTROL
    SOUT0["SOUT0 (CMOS/TTL)"] --> CONTROL
    SOUT1["SOUT1 (CMOS/TTL)"] --> CONTROL
    CONF["CONF (CMOS/TTL)"] --> CONTROL
    LOAD["LOAD (CMOS/TTL)"] --> CONTROL

Ordering Information ^(1)

Part Number	Package Type	Temperature Range	Package Marking	Lead Finish
SY89540UMY	QFN-44	Industrial	SY89540U withPb-Free bar-line indicator	Pb-Free Matte-Sn
SY89540UMYTR^(2)	QFN-44	Industrial	SY89540U withPb-Free bar-line indicator	Pb-Free Matte-Sn

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC electrical only.
2. Tape and Reel ordering option.

Pin Configuration

GND GND VREF-AC3 IN3 VT3 /IN3 SOUT0 SOUT1 GND GND VCC VREF-AC2 44 43 42 41 40 39 38 37 36 35 34 1 ○ 33 /IN2 2 32 VT2 3 31 IN2 4 30 CONFIG 5 29 VCC 6 28 LOAD 7 27 /IN1 8 26 VT1 9 25 IN1 10 24 VREF-AC1 11 23 GND GND VREF-AC0 /IN0 VT0 IN0 SIN0 SIN1 GND GND VCC /Q3 Q3 VCC /Q2 Q2 VCC /Q1 Q1 VCC /Q0 Q0

44-Pin QFN

Pin Description

Pin Number	Pin Name	Pin Function
17, 15,10, 84, 241, 39	IN0, /IN0,IN1, /IN1,IN2, /IN2,IN3, /IN3	Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details.
16, 9,3, 40	VT0, VT1,VT2, VT3	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details.
14,11,1,42	VREF_AC0,VREF_AC1,VREF_AC2,VREF_AC3	Reference Voltage: This output biases to V_CC-1.2V . It is used when AC-coupling the inputs (IN, /IN). Connect VREF_AC to the VT pin. Bypass each VREF-AC pin with a 0.01μF low ESR capacitor. See "Input Interface Applications" section for more details.
18, 19	SIN0,SIN1	These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open.
38, 37	SOUT0,SOUT1	These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open.
5, 7	CONF,LOAD	These single-ended TTL/CMOS-compatible inputs control the transfer of the addresses to the internal multiplexers. See "Address Tables" and "Timing Diagram" sections for more details. Note that these inputs are internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open.Configuration Sequence1. Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration.2. Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration.Buffer ModeThe SY89540U defaults to buffer mode (IN to Q) if the load and configuration control signals are not exercised.
23, 24,26, 27,29, 30,32, 33	Q0, /Q0,Q1, /Q1,Q2, /Q2,Q3, /Q3,	Differential Outputs: These LVDS output pairs are the outputs of the device. Please refer to the truth table below for details. Unused output pairs may be left open. Each output is designed to drive 350mV into 100Ω across the pair.
6, 22, 25,28, 31, 34	VCC	Positive power supply. Bypass with 0.1μF//0.01μF low ESR capacitors and place as close to each V_CC pin.
12, 13, 20,21,35, 36,43, 44	GND,Exposed pad	Ground. GND and EPad must both be connected to the same ground.

Functional Description

Buffer Mode

SY89540 can be used as a 1:4 fanout buffer. This is the default mode with LOAD and CONFIG being HIGH when the device is first powered up. The SIN0 and SIN1 inputs select the input signal that will be buffered. Regardless of the output switch selection, the input signal will be buffered to all four outputs.

Crosspoint Mode

SY89540 can be programmed to take differential input signals from any input and buffer the signals to one or more outputs. Prior to configuring SIN and SOUT, LOAD and CONFIG must be LOW. To program the desired I/O combination, follow the following sequence:

1) Select the desired input with the SIN0 and SIN1 inputs and the output with the SOUT0 and SOUT1.
2) Pulse the LOAD with a positive pulse to load SIN and SOUT.
3) Pulse the CONFIG pin with a positive pulse to latched the I/O configuration.
4) This method can be used to create independent paths between inputs and outputs. Below is the truth table to create a 4:4 buffer where IN0 -> Q3, IN1 -> Q2, IN2 -> Q1, and IN3 -> Q0:

The SY89540 can be switched from crosspoint mode to a 1:4 fanout buffer simply by providing a LOW-to-HIGH pulse to the LOAD and CONFIG pins. The input configuration (SIN0:1) will select the desired input signal while the output switch will buffer the selected input signal. To get the same desired input to all four outputs (1:4), LOAD and CONFIG must be repeated four times to cover all outputs (i.e., SOUT0:1 must go through all four output combinations, repeated by LOAD and CONFIG).

Input	SIN1	SIN0	SOUT1	SOUT0	Load	Config.	Output
IN0	0	0	1	1		0	Q3
					0
IN1	0	1	1	0		0	Q2
					0
IN2	1	0	0	1		0	Q1
					0
IN3	1	1	0	0		0	Q0
					0

Table 1. 4:4 Buffer Truth Table

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) -0.5V to +4.0V

Input Voltage ( V_IN ) ......-0.5V to V_CC

CML Output Voltage (V OUT ) .... V CC -1.0V to V _CC +5.0V

Termination Current ^(3)

Source or sink current on V _T …… ±100mA

Input Current

Source or sink current on IN, /IN .... ±50mA

V_REF-AC Current

Source or sink current on V REF-AC ±2mA

Lead Temperature (soldering, 20sec.) ...... 260°C

Storage Temperature ( T_s ) ..... -65°C to +150°C

Operating Ratings ^(2)

Supply Voltage ( V_cc ) ..... +2.375V to +2.625V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(4)

QFN (θ JA)

Still-air 23°C/W

QFN (ψ JB)

Junction-to-board 12°C/W

DC Electrical Characteristics ^(5)

T_A = -40^ to +85^ , unless otherwise noted.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply	V_CC = 2.5V	2.375	2.5	2.625	V
I_CC	Power Supply Current	No load, max. V_CC		200	280	mA
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		80	100	120	Ω
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		40	50	60	Ω
V_IH	Input HIGH Voltage (IN, /IN)		1.2		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 1a.	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage |IN, /IN|	See Figure 1b.	0.2			V
IN-to- V_T	Maximum Input Voltage |IN-to- V_T |				1.28	V
V_REF-AC	Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to limited drive capability use for input of the same package only.
4. Assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB uses a 4-layer _JA in still-air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

LVDS Outputs DC Electrical Characteristics

V_CC = 2.5V ± 5% , T_A = -40^ C to +85^ C , R_L = 100 across Q and /Q, unless otherwise noted.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	Output HIGH Voltage (Q, /Q)				1.475	V
V_OL	Output LOW Voltage (Q, /Q)		0.925			V
V_OUT	Output Voltage Swing (Q, /Q)	See Figure 1a.	250	350		mV
V_DIFF\_OUT	Differential Output Voltage Swing |Q - /Q|	See Figure 1b.	500	700		mV
V_OCM	Output Common Mode Voltage (Q, /Q)	See Figure 4b.	1.125		1.275	V
V_OCM	Change in Common Mode Voltage (Q, /Q)	See Figure 4b.	-50		+50	mV

LVTTL/CMOS DC Electrical Characteristics

V_CC = 2.5V ± 5% , T_A = -40^ to +85^ , unless otherwise noted.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0		V_CC	V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current	V_IL = 0V	-300			μA

AC Electrical Characteristics ^(7)

V_CC = 2.5V ± 5% , T_A = -40^ C to +85^ C , R_L = 100 across each output pair, unless otherwise noted.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency	NRZ Data	3.2	4		Gbps
t_PD	Propagation Delay	Clock, V_OUT ≥ 200mV		4		GHz
		IN-to-Q	280	380	480	Ω
		CONFIG-to-Q	350		800
t_PD Tempco				160		fs/°C
t_S	Set-up TimeSIN-to-LOADSOUT-to-LOADLOAD-to-CONFIGCONFIG-to-LOAD		800800800950			ps
t_h	Hold TimeLOAD-to-SIN, LOAD-to-SOUT		800			ps
t_PW	Minimum LOAD and CONFIGPulse Width		800			ps
t_SKEW	Output-to-Output SkewPart-to-Part Skew	Note 8Note 9			30150	psps
t_JITTER	RMS Phase Jitter	Output = 622MHzIntegration Range 12kHz - 20MHz		95		fs
	Crosstalk-Induced Jitter	Note 10			0.7	ps_RMS
t_r , t_r	Rise/Fall Times	At full output swing (20% to 80%)	40	80	120	ps

Notes:

1. High frequency AC-parameters are guaranteed by design and characterization.
2. Output to output skew is measured between two different outputs under identical transitions. Input voltage swing is ≥100mV .
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
4. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs.

Single-Ended and Differential Swing

V_IN, V_OUT 350mV (typical)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 700mV (typical)

Figure 1b. Differential Voltage Swing

Timing Diagram

Input Address SIN[1:0] Output Address SOUT[1:0] LOAD ts (SOUT-LOAD) tpw ts (SIN-LOAD) th (LOAD-SIN/SOUT) ts (CONFIG-LOAD) config ts (LOAD-CONFIG) tpw /IN[3:0] IN[3:0] tpd tpd (CONFIG-Q) /Q[3:0] Q[3:0] Invalid** Valid**

**Invalid and Valid refers to configuration being changed. All outputs with unchanged configuration remain valid.

Figure 2. Timing Diagram
Truth Tables

Input Select Address Table
SIN1	SINO	Input
0	0	INO
0	1	IN1
1	0	IN2
1	1	IN3

Output Select Address Table
SOUT1	SOUT0	Output
0	0	Q0
0	1	Q1
1	0	Q2
1	1	Q3

Typical Operating Characteristics

V_CC = 2.5, V_IN = 100mV, at 25^.

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Empty white square with a thin black border (no text, symbols, or markings)

Empty white square with a thin black border (no text, symbols, or markings)

Empty white square with a thin black border (no text, symbols, or markings)

Functional Characteristics

V_CC = 2.5, V_IN = 100mV, at 25^.

Clock Pattern

Data Pattern

Input and Output Stage Internal Termination

VCC IN 50Ω VT 50Ω /IN GND

Figure 3. Simplified Differential Input Stage

Output Stage Internal Termination

On a nominal 1.25V common mode above ground, LVDS specifies a small swing of 350mV, typical. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum to keep EMI low.

VOUT 100Ω ±1% VOH, VOL VOH, VOL GND

Figure 4a. LVDS Differential Measurement

50Ω 50Ω VCOM VDCOM GND

Figure 4b. LVDS Common Mode Measurement

Input Interface Applications

VCC LVPECL GND IN /IN VCC 0.1μF VT NC VREF-AC RP Note: For 3.3V, RP = 50Ω. For 2.5V, RP = 19Ω. SY89540U

Figure 5a. LVPECL Interface (DC-Coupled)

VCC LVPECL IN RPG RP GND VCC 0.1μF VTC VREF-AC SY89540U IN GND Note: For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω.

Figure 5b. LVPECL Interface (AC0Coupled)

VCC CML IN /IN GND SY89540U NC □ VT NC □ VREF-AC

Figure 5c. CML Interface (DC-Coupled)

VCC CML GND VCC 0.1μF IN /IN SY89540U VT VREF-AC

Figure 5d. CML Interface (AC-Coupled)

VCC LVDS IN /IN GND SY89540U NC □ VT NC □ VREF-AC

Figure 5e. LVDS Interface

Related Product and Support Documentation

Part Number	Function	Datasheet Link
SY58540U	Ultra Precision 4x4 CML Crosspoint Switch w/Internal I/O Termination	http://www.micrel.com/product-info/products/sy89540u.shtml
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

Package Information

NOTES :
1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M. - 1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
△ DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
AND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
6. MAX. PACKAGE WARPAGE IS 0.05 mm
7. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
PIN 41 ID ON TOP WILL BE LASER MARKED
△BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
10. THIS DRAWING CONFORMES TO JEDEC REGISTERED OUTLINE MO-220

_B0	DIMENSIONS
				_D,1e
	MIN.	NOM.	MAX.
图	0.50 BSC
N	44			3
ND	11			A
NE	11
L	0.55	0.60	0.65
b	0.18	0.25	0.30	A
D2	3.20	3.30	3.40
E2	3.20	3.30	3.40
D	7.00 BSC
E	7.00 BSC
A	0.80	0.85	1.00
A1	0.00	0.02	0.05
K	0.20 MIN.
θ	0	——	12	2

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