SY89855U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89855U Microchip

The SY89855U is a 2.5V/3.3V precision, high-speed, 4:1 differential multiplexer with 100K LVPECL (800mV) compatible outputs, capable of handling clocks up to 2.5GHz and data streams up to 2.5Gbps. In addition, a 1:2 fanout buffer provides two copies of the selected inputs.

The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The outputs are 800mV LVPECL, (100K temperature compensated) with fast rise/fall times guaranteed to be less than 180ps.

The SY89855U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. For applications that require higher performance, consider the SY58029U. The SY89855U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at www.micrel.com.

Typical Performance

Precision Edge®

Features

• Select 1 of 4 differential inputs
• Provides two copies of the selected input
  • Low power 260mW ( V_cc = 2.5V )
• Guaranteed AC performance over temperature and voltage:
• DC-to->2.5Gbps data rate throughput
• <410ps In-to-Q t_pd
• <180ps t_r / t_f times

• Ultra low-jitter design:

• <10psPP total jitter (clock)
• < 1 ps_RMS random jitter
• < 10ps_PP deterministic jitter
• < 0.7ps_RMS crosstalk-induced jitter

- Unique, patent-pending input design minimizes crosstalk

• Accepts an input signal as low as 100mV

- Unique patented input termination and VT pin accepts DC- and AC-coupled inputs (CML, LVPECL, LVDS)

• 800mV 100K LVPECL output swing

• Power supply 2.5V ±5% or 3.3V ±10%

- -40°C to +85°C temperature range

• Available in 32-pin (5mm x 5mm) QFN package

Applications

• Redundant clock and/or data distribution
• All SONET/OC-3 to OC-48 clock/data distribution
- Loopback
• All Fibre Channel applications
• All GigE applications

Markets

• LAN/WAN communication
- Enterprise servers
- ATE
• Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Functional Block Diagram

graph TD
    subgraph Input
        IN0["IN0"] --> VT0["VT0"]
        VT0 --> /IN0["/IN0"]
        IN1["IN1"] --> VT1["VT1"]
        VT1 --> /IN1["/IN1"]
        IN2["IN2"] --> VT2["VT2"]
        VT2 --> /IN2["/IN2"]
        IN3["IN3"] --> VT3["VT3"]
        VT3 --> /IN3["/IN3"]
        VREF-AC0["VREF-AC0"] --> VT0
        VREF-AC0 --> VT1
        VREF-AC0 --> /IN1
        VREF-AC1["VREF-AC1"] --> VT1
        VREF-AC1 --> /IN1
        VREF-AC2["VREF-AC2"] --> VT2
        VREF-AC2 --> /IN2
        VREF-AC3["VREF-AC3"] --> VT3
        VREF-AC3 --> /IN3
    end

    subgraph Output
        4:1["MUX"] --> Q0["Q0"]
        4:1 --> Q1["Q1"]
        4:1 --> Q1_Fanout["1:2 Fanout"]
    end

    style Input fill:#f9f,stroke:#333
    style Output fill:#ccf,stroke:#333

Truth Table

SEL1	SEL0	Q
0 0 IN0 Input	Select
0 1 IN1 Input	Select
1 0 IN2 Input	Select
1 1 IN3 Input	Select

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking Lead Finish
SY89855UMG QFN	-32 Industrial S	Y89855U with	Pb-Free bar-line indicator NiPdAu Pb-Free
SY89855UMGTR(2)	QFN-32 Industrial	SY89855U	with Pb-Free bar-line indicator NiPdAu Pb-Free

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ C , DC Electricals only.
2. Tape and Reel.

Pin Configuration

/IN3 VREF-AC3 VT3 IN3 IN2 VREF-AC2 VT2 IN2 IN0 1 32 31 30 29 28 27 26 25 VT0 2 24 VREF-AC0 3 23 /Q1 /IN0 4 22 IN1 5 21 VT1 6 20 VREF-AC1 7 19 /IN1 8 18 GND VCC Q1 /VCC NC SEL1 VCC 9 10 11 12 13 14 15 16 GND VCC /Q0 Q0 VCC NC SEL0 VCC

32-Pin QFN

Pin Description

Pin Number	Pin Name Pin Function
1, 45, 825, 2829, 32	IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3	Differential Input: Each pair accepts AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. If an input is not used, connect one end of the differential pairs to ground through a 1kΩ resistor, and leave the other end to VCC through an 825Ω resistor. Unused VT and VREF-AC pins may also be left floating. Please refer to the “Input Interface Applications” section for more details.
2, 626, 30	VT0, VT1VT2, VT3	Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pin provides a center-tap to the termination network for maximum interface flexibility. See “Input Interface Applications” section for more details.
15, 18 SEL0, SEL1		This Single-Ended TTL/CMOS compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. Input logic threshold is V_CC/2 . See “Truth Table” for select control.
14, 19 NC	Not connected.
10, 13, 1617, 20, 23	VCC	Positive Power Supply: Bypass with 0.1μF||0.01μF low ESR capacitors placed as close as possible to each VCC pin.
11, 1221, 22	/Q0, Q0/Q1, Q1	Differential Outputs: These 100K-compatible (internally temperature compensated) LVPECL output pairs are copies of the selected input. Unused output pins may be left floating. See “Output Interface” for terminating guidelines.
9, 24	GND, Exposed Pad	Ground: Ground pins and exposed pad must be connected to the most negative potential of the chip.
372731	VREF-AC0,VREF-AC1,VREF-AC2,VREF-AC3	Reference Voltage: This reference output is equivalent to V_CC-1.2V . It is used for AC-coupled inputs. When interfacing to AC input signals, connect VREF-AC directly to the VT pin and bypass with a 0.01μF low ESR capacitor to VCC. See “Input Interface Applications” section. Maximum sink/source current is ± 1.5mA.

Absolute Maximum Ratings ^(1)

Supply Voltage (Vcc) -0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

LVPECL Output Current ( I_OUT )

Continuous.... ±50mA Surge .... ±100

Termination Current

Source or Sink Current on V _T …… ±100mA

Input Current

Source or Sink Current on IN, /IN.... ±50mA

Current ( V_REF-AC )

Source or Sink Current on V REF-AC.... ±2mA

Lead Temperature (soldering, 20sec.) ......260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_cc ) ....+2.375V to +2.625V .....+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

A QFN JA(θ)

Still-Air....35°C/W 500lfpm....28°C/W

QFN (B)

Junction-to-Board....16°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise noted.

Symbol	Parameter Condition	Min Typ Max Units
V_CC	Power Supply Voltage	V_CC=2.5V V_CC=3.3V	2.3753.0	2.53.3	2.6253.6	VV
I_CC	Power Supply Current	No load, max. V_CC .		65	85	mA
R_IN	Input Resistance(IN-to-VT)		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance(IN-to-/IN, /IN-to- V_T )		90	100	110	Ω
V_IH	Input High Voltage(IN, /IN)	Note 5	V_CC-1.6		V_CC	V
V_IL	Input Low Voltage(IN, /IN)		0		V_IH-0.1 V
V_IN	Input Voltage Swing(IN-to-/IN)	See Figure 1a.	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing|IN- /IN|	See Figure 1b.	0.2			V
V_T\_IN	Maximum Input Voltage(IN-to- V_T )				1.28	V
V_REF-AC	Output Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still-air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IH (min) not lower than 1.2V.

LVPECL Output DC Electrical Characteristics ^(5)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 50 to V_CC-2V ; T_A = -40^ to +85^ , unless otherwise noted.

Symbol	Parameter Condition	Min	Typ	Max	Units
V_OH	Output High Voltage (Q, /Q)				V_CC-1.145		V_CC-0.895	V
V_OL	Output Low Voltage (Q, /Q)				V_CC-1.945		V_CC-1.695	V
V_OUT	Output Voltage Swing (Q, /Q)	See Figure 1a. 400 800 mV
V_DIFF-OUT	Differential Output Voltage Swing (Q, /Q)	See Figure 1b. 800 1600 mV

LVTTL/CMOS DC Electrical Characteristics ^(5)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , unless otherwise noted.

Symbol	Parameter Condition	Min	Typ	Max	Units
V_IH Input High Voltage		2.0			V
V_IL	Input Low Voltage						0.8	V
I_IH	Input High Current	V_IN = V_CC					75	μA
I_IL Input Low Current	V	_IN = 0.5V			-300		μA

Notes:
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(6)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ to +85^ , R_L = 50 to V_CC-2V , unless otherwise stated.

Symbol	Parameter Condition Min	Typ Max Units
MAX Maximum Operating Frequency		NRZ Data 2.5 Gbps f
		Clock, V_OUT >400mV 2.5 GHz
t_pd	Propagation DelayIN-to-QSEL-to-Q	V_IN >100mV	210	300	410	ps
			100	300	500	ps
t_pd Tempco	Differential Propagation DelayTemperature Coefficient			234		fs/°C
t_SKEW	Output-to-OutputPart-to-Part	Note 7Note 8		9	20	ps
					150	ps
t_JITTER	DataRandom Jitter (RJ)Deterministic Jitter (DJ)	Note 9			1	p_S_RMS
		Note 10			10	p_S_PP
	ClockCycle-to-Cycle JitterTotal Jitter (TJ)	Note 11			1	p_S_RMS
		Note 12			10	p_S_PP
	Crosstalk-induced Jitter(Adjacent Channel)	Note 13			0.7	p_S_RMS
t_r, t_f	Output Rise/Fall Time (20% to 80%)	At full output swing.	50	100	180	ps

Notes:
6. High frequency AC electricals are guaranteed by design and characterization.
7. Output-to-output skew is measured between outputs under identical input conditions.
8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
9. Random jitter is measured with a K28.7 character pattern, measured at <f MAX.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2^23-1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T_n-T_n-1 where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input of frequency < f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
13. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs.

Typical Operating Characteristics

V_CC = 2.5V, GND = 0, V_IN = 100mV; T_A = -40^ to +85^, R_L = 50 to V_CC-2V, unless otherwise stated.

Functional Characteristics

V_CC = 3.3V ± 10% ; T_A = -40^ to +85°C, R_L = 50 to V_CC-2V , unless otherwise stated.

Single-Ended and Differential Swings

V_IN, V_OUT 800mV (typical)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN VDIFF_OUT 1600mV (typical)

Figure 1b. Differential Voltage Swing

Timing Diagram

IN /IN tpd tpd Q /Q VIN VOUT

IN-to-Q Timing Diagram

SEL VCC/2 VCC/2 tpd tpd Q /Q VOUT

SEL-to-Q Timing Diagram

Input and Output Stages

VCC IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Stage

Vcc /Q Q

Figure 2b. PECL Output Stage

Input Interface Applications

Vcc LVPECL IN /IN GND NC VREF-AC VT 0.01μF Rpd For a 3.3V system, Rpd = 50Ω For a 2.5V system, Rpd = 19Ω SY89855U

Figure 3a. LVPECL Interface (DC-Coupled)

Vcc LVPECL GND Rpd Rsd GND IN /IN SY89855U VCC 0.01μF VREF-AC VT For a 3.3V system, Rpd = 100Ω. For a 2.5V system, Rpd = 50Ω. option: may connect VT to Vcc

Figure 3b. LVPECL Interface (AC-Coupled)

Vcc CML IN IN GND SY89855U NC □ VREF-AC NC □ VT

Figure 3c. CML Interface (DC-Coupled)

Vcc CML IN /IN GND SY89855U VCC 0.01μF VREF-AC VT

Figure 3d. CML Interface (AC-Coupled)

Vcc LVDS IN IN GND SY89855U NC □ VREF-AC NC □ VT

Figure 3e. LVDS Interface

Output Interface Applications

LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing, which result in low EMI. LVPECL is ideal for driving 50Ω and 100Ω controlled impedance transmission lines. There are different techniques for terminating

LVPECL outputs: parallel termination theveninequivalent, parallel termination (3-resistor), and AC-coupled termination. Unused output pairs may be left floating; however, single-ended outputs must be terminated or balanced.

+3.3V +3.3V Z₀ = 50Ω Z₀ = 50Ω R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω +3.3V

Note:
For a 2.5V system, R1 = 250Ω, R2 = 62.5Ω.

Figure 4a. Parallel Thevenin-Equivalent Termination

+3.3V Z = 50Ω Z = 50Ω 50Ω 50Ω 50Ω Rb C1 0.01μF (optional) +3.3V "destination" Vcc

Note:
1. For a 2.5V system, Rb = 19Ω.

Figure 4b. Parallel Termination (3-Resistor)

+3.3V 0.1µF 0.1µF R 100Ω R 100Ω

Note:
For a 2.5V system, R = 50Ω.

Figure 4c. AC-Coupled Termination

+3.3V +3.3V R1 130Ω R2 82Ω Terminate unused output to Vcc-2V.

Note:
For a 2.5V system, R1 = 250Ω, R2 = 62.5 Ω.

Figure 4d. Parallel Thevenin-Equivalent Termination
Related Product and Support Documentation

Part Number Function Data Sheet Link
SY58029U	Ultra Precision Differential LVPECL 4 :1MUX with 1 :2 Fanout Internal Termination	www.micrel.com/product-info/products/sy58029u.shtml.
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

Package Information

5.0 BSC 32 1 2 PIN #1 ID 0.20 DIA TYP. 5.0 BSC

TOP VIEW

0.25±0.50 32X 0.50 BSC 32 PIN #1 ID R0.20 0.20 MIN. 3.10±0.10 0.40±0.05 4X 3.10±0.10

BOTTOM VIEW

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWAEE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

32-Pin QFN

Package EP- Exposed Pad Die CompSlide Island Heat Dissipation Heat Dissipation Heavy Copper Plane VEE VEE Heavy Copper Plane

PCB Thermal Consideration for 32-Pin QFN Package (Always solder, or equivalent, the exposed pad to the PCB)

Packages Notes:

1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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