SY58603U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58603U Microchip

The SY58603U is a 2.5/3.3V, high-speed, fully differential CML buffer optimized to provide less than 10ps_pp total jitter. The SY58603U can process clock signals as fast as 2.5GHz or data patterns up to 4.25Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC-coupled or DC-coupled) as small as 100mV (200mV pp ) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated voltage reference ( VREF-AC ) is provided to bias the V_T pin. The output is 400mV CML, with extremely fast rise/fall times guaranteed to be less than 85ps.

The SY58603U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). For applications that require LVPECL or LVDS outputs, consider the SY58604U and SY58605U, buffers with 800mV and 325mV output swings respectively. The SY58603U is part of Micrel's high-speed, Precision Edge® product line.

Data sheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

IN 50Ω V_T 50Ω /IN V_REF-AC Q /Q

Precision Edge®

Features

• Precision 400mV CML buffer
• Guaranteed AC performance over temperature and voltage:
- DC-to >4.25Gbps throughput
- <300ps propagation delay (IN-to-Q)
- <85ps rise/fall times
- Fail Safe Input
- Prevents output from oscillating when input is invalid
- Ultra-low jitter design
- <1ps RMS cycle-to-cycle jitter
- <10ps PP total jitter
- <1ps RMS random jitter
- <10ps PP deterministic jitter
• High-speed CML output
• 2.5V ±5% or 3.3V ±10% power supply operation
- Industrial temperature range: -40^ to +85^
• Available in 8-pin (2mm x 2mm) DFN package

Applications

• Data Distribution: OC-48, OC-48+FEC, XAUI
- Backplane Buffering
• SONET clock or data distribution
• Fibre Channel clock or data distribution
• Gigabit Ethernet clock or data distribution

Markets

• Storage
• ATE
  • Test and measurement
  • Enterprise networking equipment
  • High-end servers
• Access
  • Metro area network equipment

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number Package	Type	Operating Range	Package Marking Lead	Finish
SY58603UMG	DFN-8	Industrial	603 with Pb-Free bar-line indicator	NiPdAu Pb-Free
SY58603UMGTR^(2)	DFN-8	Industrial	603 with Pb-Free bar-line indicator	NiPdAu Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals only.
2. Tape and Reel.

Pin Configuration

IN 1 VT 2 VREF-AC 3 /IN 4 8 VCC 7 Q 6 /Q 5 GND

8-Pin DFN

Pin Description

Pin Number	Pin Name	Pin Function
1, 4	IN, /IN	Differential Input: This input pair is the differential signal input to the device. Input accepts DC-Coupled differential signals as small as 100mV(200mVpp). Each pin of this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See “Input Interface Applications” section for more details.
2	VT	Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section.
3	VREF-AC	Reference Voltage: This output biases to V_CC-1.2V . It is used for AC-coupling input IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01μF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA. Please refer to the “Input Interface Applications” section for more details.
5	GND Exposed pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin.
6, 7	/Q, Q	CML Differential Output Pair: Differential buffered output copy of the input signal. The output swing is typically 400mV. See “CML Output Termination” section.
8	VCC	Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the V_CC pin as possible.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc )....-0.5V to +4.0V

Input Voltage ( V_IN )....-0.5V to V_CC

CML Output Voltage ( V_OUT ) ...... V_CC-1.0V to V_CC+0.5V

Source or sink on VT pin ....±100mA

Input Current

Source or sink Current on (IN, /IN) ....±50mA

Current (VREF)

Source or sink current on V REF-AC ^(4) …… ±1.5mA

Maximum operating Junction Temperature ..... 125°C

Lead Temperature (soldering, 20sec.) 260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_IN )....+2.375V to +3.60V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3)

DFN

Still-air ( _JA ) 93°C/W

Junction-to-board ( _JB ) 56°C/W

DC Electrical Characteristics ^(5)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply Voltage Range		2.375	2.5	2.625	V
			3.0	3.3	3.6
I_CC	Power Supply Current	No load, max. V_CC		39	50	mA
R_DIFF\_IN Differential Input Resistance (IN-to-/IN)			90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN, Note 7	V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	IN, /IN	0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	see Figure 3a, Note 6	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	see Figure 3b	0.2			V
V_IN\_FSI	Input Voltage Threshold that Triggers FSI			30	100	mV
V_REF\_AC	Output Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V
V_T\_IN Voltage from Input to V _T					1.28	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IN(max) is specified when V_T is floating.
7. V_IH (min) not lower than 1.2V.

CML Output DC Electrical Characteristics ^(7)

V_CC = +2.5V ± 5% or +3.3V ± 10% , R_L = 100 across the outputs; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH Output	HIGH Voltage R	_L=50 to V_CC	V_CC-0.020	V_CC-0.010	V_CC	V
V_OUT	Output Voltage Swing	See Figure 3a	325	400		mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 3b	650	800		mV
R_OUT	Output Source Impedance		45	50	55

Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics

V_CC = +2.5V ± 5% or +3.3V ± 10% , R_L = 100 across the outputs, Input t_r/t_f : ≤ 300ps ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Frequency	NRZ Data	4.25			Gbps
		V_OUT>200mV Clock	2.5	3		GHz
t_PD	Propagation Delay IN-to-Q	V_IN:100mV-200mV	150	250	350	ps
		V_IN:200mV-800mV	120	190	300	ps
t_Skew	Part-to-Part Skew	Note 8			100	ps
t_Jitter	Data Random Jitter	Note 9			1	pS_RMS
	Deterministic Jitter	Note 10			10	pS_PP
	Clock Cycle-to-Cycle Jitter	Note 11			1	pS_RMS
	Total Jitter	Note 12			10	pS_PP
t_r,t_f	Output Rise/Fall Times (20% to 80%)	At full output swing.	30	50	85	ps
	Duty Cycle	Differential I/O	47		53	%

Notes:

1. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective inputs.
2. Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX .
3. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2^23-1 PRBS pattern.
4. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t_JITTER_CC = T_n - T_n+1 , where T is the time between rising edges of the output signal.
5. Total jitter definition: with an ideal clock input frequency of ≤ f_MAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.

Functional Description

Fail-Safe Input (FSI)

The input includes a special failsafe circuit to sense the amplitude of the input signal and to latch the output when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mV_PK ( 200mV_PP ), typically 30mV_PK . Maximum frequency of SY58603U is limited by the FSI function.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low signal swing, the FSI function will eliminate a metastable condition and guarantee a stable output. No ringing and no undetermined state will occur at the output under these conditions.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Characteristics” for detailed information.

Timing Diagrams

/IN IN t_pd t_pd /Q Q V_IN V_OUT

Figure 1a. Propagation Delay

Figure 1b. Fail Safe Feature

Typical Characteristics

V_CC = 2.5V , GND = 0V, V_IN = 100mV , R_L = 100 across the outputs, T_A = 25^ , unless otherwise stated.

Functional Characteristics

V_CC = 2.5V , GND = 0V, V_IN = 325mV , Data Pattern: 2^23-1 , R_L = 100 across the outputs, T_A = 25^ , unless otherwise stated.

Functional Characteristics (continued)

V_CC = 2.5V , GND = 0V, V_IN = 325mV , R_L = 100 across the outputs, T_A = 25^ , unless otherwise stated.

Input and Output Stage

VCC IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Buffer

Vcc 50Ω 50Ω /Q Q GND

Figure 2b. Simplified CML Output Buffer

Single-ended and Differential Swings

V_{IN}, V_{OUT} 400mV (typical)

Figure 3a. Single-Ended Swing

VDIFF_IN, VDIFF_OUT 800mV (typical)

Figure 3b. Differential Swing

Input Interface Applications

VCC CML IN /IN GND SY58603U NC □ VT NC □ VREF-AC

Figure 4a. CML Interface (DC-Coupled)
Option: May connect V_T to V_CC

VCC CML GND IN /IN VCC 0.1μF SY58603U VT VREF-AC

Figure 4b. CML Interface (AC-Coupled)

VCC LVPECL GND VCC 0.1μF RP NC VREF-AC IN /IN VT Note: For 3.3V, Rp = 50Ω. For 2.5V, Rp = 19Ω. SY58603U

Figure 4c. LVPECL Interface (DC-Coupled)

VCC LVPECL GND RP Rp VCC IN /IN 0.1μF SY58603U VT VREF-AC Note: For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω.

Figure 4d. LVPECL Interface (AC-Coupled)

VCC LVDS IN /IN SY58603U GND NC VT NC VREF-AC

Figure 4e. LVDS Interface

CML Output Termination

VCC 50Ω 50Ω Z0 = 50Ω /Q 100Ω Z0 = 50Ω Q GND

Figure 5a. CML DC-Coupled Termination

VCC 50Ω 50Ω Z0 = 50Ω /Q 50Ω Z0 = 50Ω Q 50Ω VCC GND

Figure 5b. CML DC-Coupled Termination

VCC 50Ω 50Ω Z0=50Ω /Q 50Ω VBIAS Z0=50Ω 50Ω Q GND

Figure 5c. CML AC-Coupled Termination

Related Product and Support Documents

Part Number	Function	Data Sheet Link
SY58604U 3.2Gbps Precision LVPECL Buffer with Internal Termination and Fail Safe Input		http://www.micrel.com/page.do?page=/product-info/products/sy58604u.shtml
SY58605U 3.2Gbps Precision LVDS Buffer with Internal Termination and Fail Safe Input		http://www.micrel.com/page.do?page=/product-info/products/sy58605u.shtml
HBW Solutions New Products and Termination Application Notes		http://www.micrel.com/page.do?page=/product-info/as/HBWsolutions.shtml

Package Information

PIN #1 ID BY MARKING 2.00 BSC 1.00 BSC 1 2 2.00 BSC 1.00 BSC 8

TOP VIEW

0.35±0.05 1.30±0.05 0.25+0.05 -0.07 PIN #1 R0.100 TYP 0.125±0.050 1.20±0.10 EXP. PAD 1.75 REF 0.50 BSC 0.60±0.10 EXP. PAD

BOTTOM VIEW

0.85±0.05 0.05 C SEATING PLANE 0.00-0.05 0.203±0.025

SIDE VIEW

NOTE:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. MAX. PACKAGE WARPAGE IS 0.05

3. MAXIMUM ALLOWABLE BURRS IS 0076 mm IN ALL DIRECTIONS.

4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED

BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP.

1. APPLIED ONLY FOR TERMINALS.

APPLIED FOR EXPOSED PAD AND TERMINALS.

8-Pin DFN (2mm x 2mm)

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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