SY89842U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89842U Microchip

The SY89842U is a low jitter CML, 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89842U unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or "runt" pulses during switchover. In addition, a unique Fail-Safe Input protection prevents metastable conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV).

The differential input includes Micrel's unique, 3-pin input termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mV _PP ) without any level shifting or termination resistor networks in the signal path. The output is 400mV CML with fast rise/fall times guaranteed to be less than 80ps.

The SY89842U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89842U is part of Micrel's high-speed, Precision Edge® product line. All support documentation can be found on Micrel's web site at: www.micrel.com.

Precision Edge®

Features

• Selects between two sources, and provides a glitch-free, stable CML output

• Guaranteed AC performance over temperature and supply voltage:

• Wide operating frequency: 1kHz to >1.5GHz

• < 840ps In-to-Out t pd

• < 8 0ps t r /t f

• Unique, patent-pending input isolation design minimizes crosstalk
  • Fail-safe input prevents oscillations
  • Ultra-low jitter design:

• <1psRMS random jitter

• <1ps _RMS cycle-to-cycle jitter
• <10psPP total jitter (clock)
• < 0.7ps_RMS MUX crosstalk induced jitter

- Unique patent-pending input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)

• 400mV CML output swing
• 2.5V ±5% or 3.3V ±10% supply voltage
- -40°C to +85°C industrial temperature range
• Available in 16-pin (3mm x 3mm) QFN package

Applications

• Redundant clock switchover
- Fail-safe clock protection

Markets

• LAN/WAN
- Enterprise servers
- ATE
• Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Typical Application

graph TD
    subgraph_Primary_Clock_From_System["Primary Clock From System"]
        IN0["IN0"] --> MUX["2:1 MUX"]
        VT0["VTO"] --> MUX
        /IN0["/IN0"] --> MUX
        VREF_AC0["VREF-AC0"] --> MUX
        IN1["IN1"] --> MUX
        VT1["VT1"] --> MUX
        /IN1["/IN1"] --> MUX
        VREF_AC1["VREF-AC1"] --> MUX
    end
    subgraph_Secondary_Clock_From_Local_Oscillator["Secondary Clock From Local Oscillator"]
        IN1["IN1"] --> MUX
        VT1["VT1"] --> MUX
        /IN1["/IN1"] --> MUX
        VREF_AC1["VREF-AC1"] --> MUX
    end
    MUX --> S["S"]
    S --> CML_Out["CML Output"]
    CML_Out --> Runt_Pulse_Runt["Pulse Elimination Logic"]
    Runt_Pulse_Runt --> SEL_SEL["LVTTL/CMOS"]
    SEL_SEL --> Runt_Pulse_Runt
    style Primary_Clock_From_System fill:#f9f,stroke:#333
    style Secondary_Clock_From_Local_Oscillator fill:#ccf,stroke:#333

Primary Clock Secondary Clock SEL Select Primary Select Secondary OUTPUT Runt pulse eliminated from output Switchover occurs

Simplified Example Illustrating Runt Pulse Eliminator (RPE) Circuit when Primary Clock Fails

Ordering Information ^(1)

Part Number Package Type	Operating Range	Package Marking Lead	Finish
SY89842UMG	QFN-16	Industrial	842U with Pb-Free bar-line Indicator
SY89842UMGTR(2)	QFN-16	Industrial	842U with Pb-Free bar-line Indicator

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals Only.
2. Tape and Reel.

Pin Configuration

IN1 VT1 VREF-AC1 IN1 16 15 14 13 /INO 1 12 VCC VREF-AC0 2 11 CAP VT0 3 10 SEL IN0 4 9 GND 5 6 7 8 VCC O I/O VCC

16-Pin QFN

Pin Description

Pin Number	Pin Name	Pin Function
4, 1, 16, 13	IN0, /IN0, IN1, /IN1	Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin of a pair internally terminates to a VTpin through 50Ω. Please refer to the “Input Interface Applications” section for more details.
2, 14	VREF-AC0 VREF-AC1	Reference Voltage: These outputs bias to V_CC -1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01μF low ESR capacitor to VCC. Maximum sink/source current is ±1.5mA.
3, 15 VT0, VT1		Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. See the “Input Interface Applications” section for more details.
5, 8, 12 VCC		Positive Power Supply: Bypass with 0.1μF||0.01μF low ESR capacitors as close to the VCC pins as possible.
6, 7 Q, /Q		Differential Outputs: This differential CML output is a logic function of the IN0, IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
10 SEL		This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open.
9	GND, Exposed Pad	Ground: Ground and exposed pad must be connected to the same ground plane.
11 CAP		Power-On Reset (POR) initialization capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. See “Power-On Reset (POR) Description” section for more details regarding capacitor selection. If this pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open.

Truth Table

Inputs Outputs
IN0	/IN0	IN1	/IN1	SEL	Q	/Q
0	1	X	X	0	0	1
1	0	X	X	0	1	0
X	X	0	1	1	0	1
X	X	1	0	1	1	0

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) -0.5V to +4.0V

Input Voltage ( V_IN ) ..... -0.5V to V_CC

CML Output Voltage ( V_OUT ) .. V_CC -1.0V to V_CC +0.5V

CML Input Current ( I_IN ) ....

Source/Sink Current on IN, /IN .... ±50mA

Source/Sink Current on V ±100mA

V_REF-AC Current

Source/Sink Current on V REF-AC ±2mA

Lead Temperature (soldering, 20 sec.) .....+260°C

Storage Temperature ( T_s )....-65°C to 150°C

Operating Ratings ^(2)

Supply Voltage ( V_cc )....+2.375V to +2.625V

+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

QFN (_JA)

Still-Air 60°C/W

QFN ( _JB )

Junction-to-Board 33°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply		2.3753.0		2.6253.6	VV
I_CC	Power Supply Current	No load, max V_CC		83	110	mA
R_IN	Input Resistance (IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input High Voltage (IN, /IN)		1.2		V_CC	V
V_IL	Input Low Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 1a. Note 5.	0.1		V_CC	V
V_DIFF\_IN	Differential Input Voltage Swing |IN-/IN|	See Figure 1b.	0.2			V
V_IN\_FSI	Input Voltage Threshold that Triggers FSI			30	100	mV
V_T\_IN	IN-to- V_T (IN, /IN)				1.8	V
V_REF\_AC	Output Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IN (max) is specified when V_T is floating.

CML Outputs DC Electrical Characteristics ^(6)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 100 across output pair; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH Output	HIGH VoltageQ, /Q	R_L = 50 to V_CC .	V_CC-0.020 V	V_CC-0.010	V_CC	V
V_OUT	Output Voltage SwingQ, /Q	See Figure 1a.	325	400		mV
V_DIFF-OUT	Differential Output Voltage SwingQ, /Q	See Figure 1b.	650	800		mV
R_OUT	Output Source Impedance		45	50	55

LVTTL/CMOS DC Electrical Characteristics ^(6)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(7)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 100 across output pair; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency	Clock	1.5	2.0		GHz
t_pd Differential Propagation Delay		100mV < V_IN ≤ 200mV^(8,9)	440	625	840	ps
t_pd Tempco	Differential Propagation Delay Temperature Coefficient			460		fs/°C
t_SKEW	Part-to-Part Skew	Note 10			200	ps
t_JITTER	Clock	Note 11			1	ps_RMS
	Random Jitter
	Cycle-to-Cycle Jitter	Note 12			1	ps_RMS
	Total Jitter (TJ)	Note 13			10	ps_PP
	Crosstalk-Induced Jitter	Note 14			0.7	ps_RMS
t_r,t_f	Output Rise/Fall Time (20% to 80%)	At full output swing.	30		80	ps

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
2. Propagation delay is a function of rise and fall time at IN. See "Typical Operating Characteristics" for more details.
3. Propagation delay is measured with input t_r , t_f ≤ 300ps (20% to 80%) and V_IL ≥ 800mV .
4. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
5. Random Jitter is measured with a K28.7 character pattern, measured at <f_MAX .
6. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T_n - T_n-1 where T is the time between rising edges of the output signal.
7. Total Jitter definition: with an ideal clock input of frequency <f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
8. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs.

Functional Description

RPE MUX and Fail-Safe Input

The SY89842U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits:

Runt-Pulse Eliminator (RPE) Circuit

The RPE MUX provides a "glitchless" switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to V_cc , the RPE function will be disabled and the multiplexer will function as a normal multiplexer.

Fail-Safe Input (FSI) Circuit

The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum single-ended input amplitude limit ( V_IN ), or 200mV differentially ( V_DIFF_IN ), the output will latch to the last valid clock state.

RPE and FSI Functionality

The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to "Timing Diagrams" section for detailed information.

Case #1: Two Normal Clocks and RPE Enabled

In this case, the frequency difference between the two running clocks, IN0 and IN1, must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz.

If the SEL input changes state to select the alternate clock, the switchover from CLK1 to CLK2 will occur in three stages.

- Stage 1: The output will continue to follow CLK1 for a limited number of pulses.

- Stage 2: The output will remain LOW for a limited number of pulses of CLK2.

• Stage 3: The output follows CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Runt pulse eliminated from output Stage 1 Select CLK1 Stage 2 Select CLK2 Stage 3 3 to 5 falling edges of CLK1 4 to 5 falling edges of CLK2

Timing Diagram 1

Case #2: Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE enabled).

If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages.

- Stage 1: The output will remain HIGH for a limited number of pulses of CLK2.

- Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2.

• Stage 3: The output will follow CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Runt pulse eliminated from output Stage 1 Stage 2 Stage 3 Select CLK2 14 to 16 falling edges of CLK2

Timing Diagram 2

Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period.

Case #3: Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPE enabled).

If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages.

- Stage 1: The output will remain LOW for a limited number of falling edges of CLK2.

• Stage 2: The output will follow CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Stage 1 Select CLK2 13 to 17 falling edges of CLK2 Stage 2

Timing Diagram 3

Case #4: Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE enabled).

If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV ( V_IN ) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending upon the last valid state at the CLK1

If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions.

Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Operating Characteristics” for detailed information.

CLK1 CLK2 SEL Select CLK1 Select CLK2 OUTPUT as in case #2 as in case #3

Timing Diagram 4

Power-On Reset (POR) Description

The SY89842U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between V_cc and the CAP pin (pin 11) controls the delay for the power-on reset function.

The required capacitor value calculation is based upon the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V.

The following formula describes this relationship:

$$ C (\mu F) \geq \frac {t _ {d P S} (m s)}{1 2 (m s / \mu F)} $$

As an example, if the time required for the system power supply to power up past 2.3V is 12ms, then the required capacitor value on pin 11 would be:

$$ C (\mu F) \geq \frac {1 2 m s}{1 2 (m s / \mu F)} $$

$$ C (\mu F) \geq 1 \mu F $$

Typical Operating Characteristics

V_CC = 3.3V, GND = 0V, V_IN ≥ 400mV_pk, t_r/t_f ≤ 300ps, R_L = 100 across output pair; T_A = 25^ , unless otherwise stated.

Functional Characteristics

V_CC = 3.3V , GND = 0V, V_IN ≥ 400mV_pk , t_f/t_f ≤ 300ps , R_L = 100 across output pair; T_A = 25^ , unless otherwise stated.

Singled-Ended and Differential Swings

V_IN, V_OUT 400mV (typical)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN VDIFF_OUT 800mV (typical)

Figure 1b. Differential Voltage Swing

Input Stage

VCC IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Stage

VCC 50Ω 50Ω I/Q Q GND

Figure 2b. Simplified Differential Input Stage

Input Interface Applications

VCC LVPECL GND VCC 0.01µF Rpd GND IN /IN VT VREF-AC NC SY89842U For Vcc = 3.3V, Rpd = 50Ω. For Vcc = 2.5V, Rpd = 19Ω.

Figure 3a. LVPECL Interface (DC-Coupled)

VCC LVPECL IN IN SY89842U Rpd Rpd VCC VT GND GND 0.01μF VREF-AC For Vcc = 3.3V, Rpd = 100Ω. For Vcc = 2.5V, Rpd = 50Ω.

Figure 3b. LVPECL Interface (AC-Coupled)

VCC CML IN /IN SY89842U GND NC □ VT NC □ VREF-AC Option: may connect VT to VCC Figure 3c. CML Interface (DC-Coupled)

Option: may connect V_T to V_CC

VCC CML IN IN GND VCC VT VREF-AC 0.01µF SY89842U

Figure 3d. CML Interface (AC-Coupled)

VCC LVDS IN IN GND SY89842U NC □ VT NC □ VREF-AC

Figure 3e. LVDS Interface (DC-Coupled)

CML Output Interface Applications

VCC 50Ω 50Ω Z₀ = 50Ω /Q 100Ω Z₀ = 50Ω Q GND

Figure 4a. CML DC-Coupled Termination

VCC 50Ω 50Ω Z₀ = 50Ω /Q 50Ω VCC Z₀ = 50Ω Q 50Ω GND

Figure 4b. CML DC-Coupled Termination

VCC 50Ω 50Ω Z0 = 50Ω /Q 50Ω DC-bias per application Z0 = 50Ω 50Ω Q GND

Figure 4C. CML AC-Coupled Termination

Related Product and Support Documentation

Part Number	Function	Data Sheet Link
SY89840U Precision LVPECL Runt Pulse Eliminator 2 :1 Multiplexer		www.micrel.com/product-info/products/sy89840u.shtml.
SY89841U	Precision LVDS Runt Pulse Eliminator 2 :1 Multiplexer	www.micrel.com/product-info/products/sy89841u.shtml.
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

QFN-16

Pin 1 Dot By Marking 3.000±0.050 3.000±0.050

TOP VIEW

PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 1.550±0.050 Exp. DAP 0.400±0.050 1.550±0.050 Exp. DAP 0.500 Bsc 0.230±0.050 0.400±0.050 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 nm IN ALL DIRECTIONS
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

Packages Notes:

1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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