VSC7227 - Electronic component Microchip - Free user manual and instructions

USER MANUAL VSC7227 Microchip

VSC7227 Evaluation Board

User Guide

VPPD-03088

Revision 2.0

June 2013 Vitesse Proprietary and Confidential

Vitesse

Corporate Headquarters

741 Calle Plano

Camarillo, California 93012

United States

www.vitesse.com

Vitesse Semiconductor Corporation ("Vitesse") retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer.

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Vitesse Semiconductor Corporation is a registered trademark. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders.

Copyright © 2013 Vitesse Semiconductor Corporation

Contents

Revision History 4

1 Introduction .... 5
2 General Description 6
3 Quick Start 7
4 Power Supply Options 8

4.1 AC Adapter to Wall Socket ....8
4.2 External 5V Supply ....8

5 Reference Clock Options 9

5.1 On-board 25MHz Crystal 9
5.2 External Reference Clock 9

6 Serial Interface (TWSI) 9

6.1 USBXpress® Driver Installation 9
6.2 GUI Setup 10
6.3 Main Page 11
6.4 Clocking Configuration 12

6.4.1 Using the 25MHz Crystal 12
6.4.2 Using an External Reference Clock (CLKIN, J18) 13
6.4.3 Serial Data Rates Less Than 7.5 Gbps 13

6.5 Optimizing the Input Stage 14

6.5.1 Basic Optimization 14
6.5.2 Advanced Input Stage - Further Optimization 15
6.5.3 EQ Table and Manual Mode 17
6.5.4 Logging 18

6.6 Output Stage Control 18

6.7 Data Rate Detect 18

6.8 VScope 20

6.9 Register List 21

6.10 BER 22
6.11 Save/Load All Registers 23
6.12 Scripting 24

7 Additional Information 24

Figures

Figure 1. VSC7227 Device Block Diagram ....5
Figure 2. VSC7227 Evaluation Board 6
Figure 3. VSC7227 Basic Test Setup 8
Figure 4. USBXpress in PC's Device Manager 10
Figure 5. VSC7227 GUI - EVB Selection Window 10
Figure 6. VSC7227 GUI - Main Page 11

Figure 7. VSC7227 GUI - Loading Initialization Script 12

Figure 8. VSC7227 GUI - Clocking Page 13

Figure 9. VSC7227 GUI - Advanced Clocking Page 14

Figure 10. VSC7227 GUI - Input Stage and DFE Control Page 15

Figure 11. VSC7227 Rev. A GUI - Advanced Input Stage and DFE Control Page ...... 16

Figure 12. VSC7227 Rev. B GUI - Advanced Input Stage and DFE Control Page 17

Figure 13. VSC7227 GUI - Output Stage Control Page 18

Figure 14. VSC7227 GUI - Setting Frequency Synthesizer 0 and 1 19

Figure 15. VSC7227 GUI - Data Rate Detect 20

Figure 16. VSC7227 GUI - VScope at 10.3125 Gbps 21

Figure 17. VSC7227 GUI - Register List.... 22

Figure 18. VSC7227 GUI - BER 23

Figure 19. VSC7227 GUI - Device Menu 23

Figure 20. VSC7227 GUI - uC Menu 24

Figure 21. VSC7227 GUI - Command Line Interface 24

Revision History

Revision Date Description

Rev 1.0

July 20, 2012

First release

Rev 2.0

June 20, 2013

Update the GUI section to reflect GUI v2.0

1 Introduction

The VSC7227 device is a 12-channel uni-directional lane adaptive channel extender with a CRU. This device offers input equalization, clock/data recovery, and output de-emphasis. It supports all data rates from 1 Gbps to 14.5 Gbps. The device is available in a 13 mm x 13 mm, 144 pin, flip chip ball grid array (FCBGA), and operates on a single supply of 1.2 Volts.

Various protocols and environments within its operating data rates are supported, such as, but not limited to, 10/1 Gbps Ethernet, 16G/10G/8G/4G/2G/1G Fibre Channel, 10/5/2 Gbps Infiniband, SFP+, QSFP+, CFP and CXP optical and electrical modules.

This document describes operation of the evaluation board (EVB) used for this device, designated with part number VSC7227EV.

Figure 1. VSC7227 Device Block Diagram

graph TD
    subgraph Channel 10
        A["INP1"] --> B["EQ"]
        C["INN1"] --> D["EQ"]
        E["LOS"] --> F["LOS_CH1"]
        G["REFCLKOUT"] --> H["LOS_CH0"]
        I["XTALA/CKINP"] --> J["Frequency Synthesizer"]
        K["XTALB/CKINN"] --> L["Linear Regulator"]
        M["REGCAP"] --> N["Ground"]
    end

    subgraph Channel 11
        O["VCC=1.2V"] --> P["VScope"]
        Q["VScope"] --> R["S"]
        S["CRU"] --> T["DFE"]
        U["REFCLK"] --> V["CF"]
        W["1 UI"] --> X["Tap C-1"]
        Y["1 UI"] --> Z["Tap C 0"]
        AA["1 UI"] --> AB["Tap C+1"]
        AC["1 UI"] --> AD["Tap C-1"]
        AE["1 UI"] --> AF["Tap C 0"]
        AG["1 UI"] --> AH["Tap C+1"]
        AI["MODE0"] --> AJ["Mode Logic"]
        AK["MODE1"] --> AL["Reset"]
        AM["TX0"] --> AN["RSEL0"]
        AO["TX1"] --> AP["RSEL1"]
        AQ["EQ0/DADDR0"] --> AR["EQ1/DADDR1"]
        AS["LOS0/SDA"] --> AT["LOS1/SCL"]
    end

    subgraph Digital Core
        AU["Mode Logic"] --> AV["Pin Strap Controls"]
        AW["FC"] --> AX["Output"]
    end

    B --> R
    D --> S
    F --> T
    V --> U
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> V
    V --> W
    W --> AX
    X --> AZ["Output"]
    Y --> BA["Output"]
    AB --> BB["Output"]
    AC --> BC["Output"]
    AD --> BD["Output"]
    AE --> BE["Output"]
    AF --> BF["Output"]
    AH --> BG["Output"]
    AI --> BH["Output"]
    AJ --> BI["Output"]
    AK --> BJ["Output"]
    AL --> BK["Output"]
    AM --> BL["Output"]
    AN --> BM["Output"]
    AO --> BN["Output"]
    AP --> BO["Output"]
    AQ --> BP["Output"]
    AR --> BQ["Output"]
    ASQ --> BR["Output"]
    BTQ --> BS["Output"]

Revision 2.0 Vitesse Proprietary and Confidential Page 5 of 24 June 2013

The following reference documents provide additional information about the operation of the VSC7227EV evaluation board.

• VSC7227 Datasheet (https://www.vitesse.com/products/product.php?number=VSC7227)

• VSC7227 GUI ( https://www.vitesse.com/products/product.php?number=VSC7227 )

• VSC7227 Evaluation System Schematic, Layout, and BOM (https://www.vitesse.com/products/product.php?number=VSC7227)

2 General Description

This evaluation board provides electrical connections via SMA connectors to 4 of the 12 channels of data inputs and outputs. Figure 2 shows the evaluation board.

Figure 2. VSC7227 Evaluation Board

VITESSE VSC7227 EVALUTATION BOARD VSC7227-01 REV. A SERNO 102

The VSC7227 can be used with or without an external microcontroller. In pin strap mode, various control pins can be set to configure the device for certain standalone applications. For access to all of the features of the device, the external microcontroller is used to configure internal device registers via an I2C bus. The provided graphical user interface (GUI) enables the user to access the registers. This evaluation board is initially configured to I2C mode.

An on-board 25 MHz crystal or an external clock source can be used as the reference clock to the VSC7227. However, a hardware modification needs to be made to change the reference clock source, by changing the position of R1.

NOTE: On the Revision A evaluation board, the OUTP1 and OUTN1 silkscreen markings are swapped. J6 should be OUTN1, and J8 should be OUTP1.

3 Quick Start

The following items are recommended for use during an evaluation of the VSC7227 device:

• VSC7227EV Evaluation Board (included in the kit)
- USB cable (included in the kit)
• Wall AC adaptor (included in the kit)
• CD-ROM with GUI install (often included in the kit but available on-line)
- Pattern generator
- Error detector
- Oscilloscope
• Personal computer running Windows 2K or XP
• Signal Generator (<100MHz) (optional)

A pattern generator, error detector, oscilloscope and PC are the basic instruments needed to evaluate the VSC7227 device. Simply connect the wall AC adaptor into the evaluation board and the wall socket. SW4 acts as the power on/off switch. Connect the USB cable to the evaluation board and to a PC.

Although the VSC7227 evaluation board is shipped pre-configured for I2C mode, it is recommended that the user confirm the following switch and jumper settings:

Component Pin Name State
SW1 pin 1	FCSEL0	Float
SW1 pin 2	FCSEL1	Float
SW1 pin 3	FCSEL2	Float
SW1 pin 4	FCSEL3	Float
SW1 pin 5	FCSEL4	Float
SW1 pin 6	FCSEL5	Float
SW1 pin 7	FCSEL6	Float
SW1 pin 8	FCSEL7	Float
SW2 pin 1	FCSEL8	Float
SW2 pin 2	FCSEL9	Float
SW2 pin 3	FCSEL10	Float
SW2 pin 4	FCSEL11	Float
SW2 pin 5	TX1	Float
SW2 pin 6	TX0	Float
SW2 pin 7	RSEL1	Float
SW2 pin 8	RSEL0	Float
SW3 pin 1	RESET	Float
SW3 pin 2	EQ1_ADRS1	0
SW3 pin 3	EQ0_ADRS0	0
SW3 pin 4	MODE1	0
SW3 pin 5	MODE0	0
SW3 pin 6	LOS1	Float
SW3 pin 7	LOS0	Float

Component Pin Name State

SW3 pin 8 N/C Float

J20 SDA Jumper installed

J20 SCL Jumper installed

Connect the equipment to the evaluation board as shown in Figure 3. Configure the equipment to operate at the 10 GE rate of 10.3125 Gbps. Then, follow the GUI Setup instructions in Section 6.1, and 6.2. When the "Load Init. File" is run, the evaluation board will be configured for 10.3125 Gbps traffic.

Figure 3. VSC7227 Basic Test Setup

graph TD
    A["Pattern Generator"] --> B["VSC7227 USB"]
    C["+5V or Wall Plug-in"] --> B
    B --> D["Scope"]
    B --> E["Error Detector"]
    F["Computer"] --> B
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style D fill:#dfd,stroke:#333
    style E fill:#dfd,stroke:#333

4 Power Supply Options

There are two methods to supply power to this evaluation board.

4.1 AC Adapter to Wall Socket

The evaluation board can be powered up using the 120VAC wall socket. Simply plug in the AC adapter (included in the kit) to a wall socket and the barrel end into the J31 connector. SW4 acts as the power on/off switch.

4.2 External 5V Supply

The evaluation board can also be powered by an external 5V power supply. Simply use a pair of banana jack cables to supply +5V and GND to J32 and J33 respectively. Typical current draw is about 780mA. SW4 acts as the power on/off switch.

5 Reference Clock Options

The VSC7227 device's reference clock can be provided either from the on-board 25 MHz crystal or an external clock source.

5.1 On-board 25MHz Crystal

This is the default configuration of the evaluation board upon delivery. The VSC7227's internal frequency synthesizer will multiply it to the desired rate, which can be configured via the device specific control window within the GUI. If the desired data rate is not listed under the preset list in the GUI, please contact the local applications engineer for the correct frequency synthesizer coefficients.

5.2 External Reference Clock

The VSC7227 device also supports an external clock source to be its reference clock. Changing the placement of R1, a 0 ohm resistor, to the adjacent location will route the reference clock input to an SMA input, J18, where the user can provide an external clock source.

A 25 MHz clock can be supplied to REFCLKIN, and once configured within the GUI the on-chip frequency synthesizer will provide the correct frequency for the corresponding serial data rate. If the desired data rate is not listed under the preset list in the GUI, please contact the local applications engineer for the correct frequency synthesizer coefficients.

The internal frequency synthesizer can be bypassed by supplying a clock with a frequency 1/256 of the serial data rate, and selecting "external" option for the reference clock source.

6 Serial Interface (TWSI)

The VSC7227's internal registers are accessed via a two-wire serial interface. On the evaluation board a SiLabs F340 micro-controller acts as the master device that controls both the VSC7227 and other slave devices.

6.1 USBXpress® Driver Installation

Firstly, the USBXpress Development Kit needs to be downloaded from the Silicon Labs website (URL: http://www.silabs.com/products/mcu/Pages/USBXpress.aspx). Follow the installation directions after downloading the development kit.

Once the USBXpress driver is installed, connect the USB cable to the VSC7227EV and the PC. In order to double check that the USBXpress driver is installed and recognizing the evaluation board, go to Control Panel, and click on System>Hardware>Device Manager, and inspect the Universal Serial Bus controllers listed to see if "USBXpress Device" appears. Figure 4 shows that the PC recognizes that a USBXpress Device is connected.

Figure 4. USBXpress in PC's Device Manager

System Properties System Restore Automatic Updates Remote General Computer Name Hardware Advanced Device Manager The Device Manager lists all the hardware devices installed on your computer. Use the Device Manager to change the properties of any device. Device Manager Drivers Driver Signing lets you make sure that installed drivers are compatible with Windows. Windows Update lots you set up how Windows connects to Windows Update for drivers. Driver Signing Windows Update Hardware Profiles Hardware profiles provide a way for you to set up and store different hardware configurations. Hardware Profiles OK Cancel Apply Device Manager File Action View Help Network adapters Ports (COM & LPT) Processors Sound, video and game controllers System devices Universal Serial Bus controllers Intel(R) ICH9 Family USB Universal Host Controller - 2934 Intel(R) ICH9 Family USB Universal Host Controller - 2935 Intel(R) ICH9 Family USB Universal Host Controller - 2936 Intel(R) ICH9 Family USB Universal Host Controller - 2937 Intel(R) ICH9 Family USB Universal Host Controller - 2938 Intel(R) ICH9 Family USB Universal Host Controller - 2939 Intel(R) ICH9 Family USB2 Enhanced Host Controller - 293A Intel(R) ICH9 Family USB2 Enhanced Host Controller - 293C USB Root Hub USB Root Hub USB Root Hub USB Root Hub USB Root Hub USB Root Hub USB Root Hub USBXpress Device

6.2 GUI Setup

A GUI is available at the Vitesse website or supplied on a CD-ROM with the VSC7227EV, and can be installed directly on a PC. Launch the GUI by click on the GUI icon. The initial window will appear as shown in Figure 5. The GUI will detect the serial number of the connected evaluation board(s). If there are multiple boards connected on the same PC, click on the drop down menu, and select the desired EVB serial number. The two circles will turn green when the F340 microcontroller is detected and the VSC7227 is present. Click Launch GUI.

In the case when the circle for VSC7227 Connected turns red, check the power supply. It could be that the current is limited or the VSC7227 VDD does not reach 1.2V. J34 header can be used as a checkpoint for the 1.2V rail.

Figure 5. VSC7227 GUI - EVB Selection Window

At least one Evaluation Board is available. Please select a board to connect to. Select EVB: 112 F340 Present I2C Address VSC7227 Connected 0x20 Scan For USB Devices Launch GUI

Revision 2.0 Vitesse Proprietary and Confidential Page 10 of 24 June 2013

6.3 Main Page

Figure 6 shows the GUI Main page. When the communication is successfully established, it should say "CONNECTED" at the bottom left corner of the main page. The serial number of the EVB shows up on the top left corner of the page along with the silicon revision, A or B. These items are highlighted with red arrows.

Figure 6. VSC7227 GUI - Main Page

graph TD
    subgraph Channel Setup
        direction TB
        CH0["CH0"] -->|✓| OutputSelect
        CH1["CH1"] -->|✓| OutputSelect
        CH2["CH2"] -->|✓| OutputSelect
        CH3["CH3"] -->|✓| OutputSelect
        CH4["CH4"] -->|✓| OutputSelect
        CH5["CH5"] -->|✓| OutputSelect
        CH6["CH6"] -->|✓| OutputSelect
        CH7["CH7"] -->|✓| OutputSelect
        CH8["CH8"] -->|✓| OutputSelect
        CH9["CH9"] -->|✓| OutputSelect
        CH10["CH10"] -->|✓| OutputSelect
        CH11["CH11"] -->|✓| OutputSelect
        CH12["CH12"] -->|✓| OutputSelect
        CH13["CH13"] -->|✓| OutputSelect
        CH14["CH14"] -->|✓| OutputSelect
        CH15["CH15"] -->|✓| OutputSelect
        CH16["CH16"] -->|✓| OutputSelect
        CH17["CH17"] -->|✓| OutputSelect
        CH18["CH18"] -->|✓| OutputSelect
        CH19["CH19"] -->|✓| OutputSelect
        CH20["CH20"] -->|✓| OutputSelect
        CH21["CH21"] -->|✓| OutputSelect
        CH22["CH22"] -->|✓| OutputSelect
        CH23["CH23"] -->|✓| OutputSelect
        CH24["CH24"] -->|✓| OutputSelect
        CH25["CH25"] -->|✓| OutputSelect
        CH26["CH26"] -->|✓| OutputSelect
        CH27["CH27"] -->|✓| OutputSelect
        CH28["CH28"] -->|✓| OutputSelect
        CH29["CH29"] -->|✓| OutputSelect
        CH30["CH30"] -->|✓| OutputSelect
        CH31["CH31"] -->|✓| OutputSelect
        CH32["CH32"] -->|✓| OutputSelect
        CH33["CH33"] -->|✓| OutputSelect
        CH34["CH34"] -->|✓| OutputSelect
        CH35["CH35"] -->|✓| OutputSelect
        CH36["CH36"] -->|✓| OutputSelect
        CH37["CH37"] -->|✓| OutputSelect
        CH38["CH38"] -->|✓| OutputSelect
        CH39["CH39"] -->|✓| OutputSelect
        CH40["CH40"] -->|✓| OutputSelect
        CH41["CH41"] -->|✓| OutputSelect
        CH42["CH42"] -->|✓| OutputSelect
        CH43["CH43"] -->|✓| OutputSelect
        CH44["CH44"] -->|✓| OutputSelect
        CH45["CH45"] -->|✓| OutputSelect
        CH46["CH46"] -->|✓| OutputSelect
        CH47["CH47"] -->|✓| OutputSelect
        CH48["CH48"] -->|✓| OutputSelect
        CH49["CH49"] -->|✓| OutputSelect
        CH50["CH50"] -->|✓| OutputSelect
        CH51["CH51"] -->|✓| OutputSelect
    end

    subgraph Channel Setup
        direction TB
        PowerDown["Power Down"] --> Select
        CH0["CH0"] --> Select
        CH1["CH1"] --> Select
        CH2["CH2"] --> Select
        CH3["CH3"] --> Select
        CH4["CH4"] --> Select
        CH5["CH5"] --> Select
        CH6["CH6"] --> Select
        CH7["CH7"] --> Select
        CH8["CH8"] --> Select
        CH9["CH9"] --> Select
        CH10["CH10"] --> Select
        CH11["CH11"] --> Select

    end

    subgraph Reference Clock In
        ClockOut["Clock Out"]
        ReferenceClockIn["Reference Clock In"]
    end

    subgraph Control
        ChannelInputOUT["REFCLKOUT"]
        ChannelInputPRINXXTALCKINXXTALCKINNREGCAPGNDOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT OUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUTOUT OUTOUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT ULSI SCL

    style ChannelInputOut fill:#f9f,stroke:#333,stroke-width:2px
    style ReferenceClockIn fill:#ccf,stroke:#333,stroke-width:2px

First of all, it is recommended to load the initialization script, which can be accessed by clicking Device on the top menu, and choose "Load Init. File", as shown in Figure 7. The script will power down the 8 unused channels, and set some registers in the EQ, DFE, and output blocks. A different init script will be loaded depending on the revision of the silicon. For more detailed information about which registers are being set, the script can be found in the GUI folder, normally in the Program Files folder, once the GUI is installed.

Figure 7. VSC7227 GUI - Loading Initialization Script

VSC7227 Evaluation System System uC Device Help Status BER Load Init. File Load All Registers Save All Registers I/O Expander LOS LOL CH0 n/a CH1 n/a CH2 n/a CH3 n/a Stage & DFE Control Output Stage Control Data Rate Detect Silicon Revision: B I2C Address: 0x20 VCC=1.2V IN P0 IN N0 EQ DFE CRU LOS LOS ENR

The VSC7227EV GUI has 2 panels, left side and right side. The left panel provides the alarm status of the available channels in the "Status" tab, and error counters in the "BER" tab. The right panel provides the configuration pages, register access, and other features supported by the device.

When the "Update" button in the Status panel is clicked, it will check the LOS and LOL status for all channels. The red button means Loss of Signal or Loss of Lock for the given channel, while the green button means the opposite. The gray buttons reflect that the channel or the LOS block is powered down.

The blue arrows on Figure 6 highlight the important features on this page. Each channel can be powered down individually by checking the Power Down boxes.

The VSC7227 also features an adjacent channel crossover, which is equivalent to a 2 x 2 crosspoint switch. The two adjacent channel pairs are channel n and channel n+1, where n is an even number. This feature can be enabled by clicking on the bold arrows under the "Output Select". Note that when the broadcast from adjacent channel mode is selected, as shown in the Figure 6 for channel 2 and channel 3, the LOS for channel 3 will be asserted by default, which then squelches the output of channel 3. In order to make the GUI more user friendly, the GUI will disable squelch of the output driver (set ODSQ_SRC, register 0xA9 bit 3, to 1) when the 2 x 2 crosspoint function is enabled.

6.4 Clocking Configuration

This page shows the two internal frequency synthesizers. By default, the VSC7227 operates at 10 GE with Frequency Synthesizer 0 (FSYN0) enabled, Frequency Synthesizer 1 (FSYN1) turned off, and all channels deriving their reference clock from FSYN0.

6.4.1 Using the 25MHz Crystal

If other than 10 GE data rate is desired, the user has to enter in the desired serial data rate into the FSYN0 (and/or FSYN1) box, which then will set the corresponding values for N, M, F, and R, based on a 25 MHz reference clock, and click on the "Load Frequency Plan" button. Then select the reference clock source, FSYN0 or FSYN1, for channel of interest from the drop down menu. Figure 8 shows the clocking page in the default state.

Figure 8. VSC7227 GUI - Clocking Page

VSC/227 Evaluation System System uC Devices Help Status BER Main Cooking Input Stage & DFE Control Output Stage Control Data Rate Detect VScope Register List LDS LOL Rate Ch0 25MHz crystal CH1 Reference clock input buffer Input Clock Rate 25.0 MHz Ch2 Off Load Frequency Plan Frequency Synthesis 0 Enter Data Rate 10.31.25 Gbps Ch4 Off Ch5 n/a Ch6 n/a Ch7 n/a Ch8 n/a Ch9 n/a Ch10 n/a Ch11 n/a Clock In 25.0MHz cystal Die Temp Update Global Reference Clock Input ○ 25MHz crystal ○ Reference clock input buffer Input Clock Rate 25.0 MHz ○ On Off Load Frequency Plan Ch0 FSYN0 Gbps Ch1 FSYN0 Gbps Ch2 FSYN0 Gbps Ch3 FSYN0 Gbps Ch4 FSYN0 Gbps Ch5 FSYN0 Gbps Ch6 FSYN0 Gbps Ch7 FSYN0 Gbps Ch8 FSYN0 Gbps Ch9 FSYN0 Gbps Ch10 FSYN0 Gbps Ch11 FSYN0 Gbps - CONNECTED -- LOADED DEFAULT REGISTERS - Advanced

6.4.2 Using an External Reference Clock (CLKIN, J18)

When an external reference clock source is used (see Section 5.2 for the setup), FSYN0, FSYN1, or external can be selected as the Ref Clk Source. The "external" option allows a user to input an external reference clock frequency of 1/256 of the serial data rate and thus bypass the frequency synthesizer. For example, for 10.3125 Gbps data rate, the 1/256 reference clock is 40.2832 MHz.

6.4.3 Serial Data Rates Less Than 7.5 Gbps

There are 3 VCOs (VCO0, VCO1, and VCO2) in the VSC7227, and the VCO2's lower limit is at \~7.5Gbps. Therefore, for serial data rates that is lower than 7.5 Gbps the device will treat it as a sub-rate, and use the VCO divider. For example, a serial data rate of 5 Gbps uses VCO1 and VCODIVSEL of divide-by-2.

The user can still simply type the data rate in the FSYN0 or FSYN1 data rate box, and the software will automatically select the corresponding VCO and VCO divider.

For example, if the user wants to configure CH0 to run at 10Gbps, and CH1 at 5Gbps, then there are additional steps that need to be done. When the "Advanced" box at the bottom of the page is checked, it will reveal more available options. Figure 9 shows that FSYN0 is configured for 10 Gbps, with CH0 configured for 10 Gbps, and CH1 configured for 5 Gbps by choosing "Divide by 2" under the "VCO Clock Divider" drop down menu.

Figure 9. VSC7227 GUI - Advanced Clocking Page

VSC7227 Evaluation System System UC Device Help Status: UDR Main Clocking Input Stage & DFE Control Output Stage Control Data Rate Detect VScope Register List Global Reference Clock Input 25MHz crystal Reference clock input buffer Input Clock Rate: 25.0 MHz On Off Load Frequency Flats Frequency Synthesis 0 Enter Data Rate: 10.0 Gbps Output Clock 29.0625 MHz Input Clock → Output = Input × N/M × (64/64+α) α = F/R → Output Clock N 74 F 513752 α 0.49021278587447 M 47 R 1048100 Note: It is highly recommended to keep the ration of close to 0.5 On Off Frequency Synthesis 1 Enter Data Rate: 8.0 Gbps Output Clock 31.25 MHz Input Clock → Output = Input × N/M × (64/64+α) α = F/R → Output Clock N 68 F 437024 α 0.474074974074074 M 54 R 1048410 Note: It is highly recommended to keep the ration of close to 0.5 Channel Rel Clk Source CRU Data Rate VCO Select VCO Clock Divides CH0 PSYNO 10.0 Gbps VCO 1 Divide by 1 CH1 PSYNO 5 Gbps VCO 1 Divide by 2 CH2 PSYN1 8.0 Gbps VCO 2 Divide by 1 CH3 PSYN1 2 Gbps VCO 2 Divide by 4 CH4 PSYN2 10.0 Gbps VCO 1 Divide by 1 CH5 PSYN2 10.0 Gbps VCO 1 Divide by 1 CH6 PSYN3 10.0 Gbps VCO 1 Divide by 1 CH7 PSYN3 10.0 Gbps VCO 1 Divide by 1 CH8 PSYN4 10.0 Gbps VCO 1 Divide by 1 CH9 PSYN5 10.0 Gbps VCO 1 Divide by 1 CH10 PSYN6 10.0 Gbps VCO 1 Divide by 1 CH11 PSYN7 10.0 Gbps VCO 1 Divide by 1 - CONNECTED -- LOADED DEFAULT REGISTERS - Advanced

6.5 Optimizing the Input Stage

In this page, the user can adjust the VGA, Input EQ, EQVGA, DFE, and DC offset settings for each channel. Each one has an Adaptation mode and a Manual mode.

The user needs to ensure that the correct channel is selected and check the Auto Refresh box to see the read out of each setting in real time.

6.5.1 Basic Optimization

For most applications, the user does not need to have the Advance mode enabled. In this mode, the VGA, EQ and DFE are all in Adaptive mode, as shown in Figure 10. If error free operation is still not achieved at this point, the VGA Target and/or EQ Diff sliders should be adjusted.

When the 6 EQ stages are at a high number, such as 11 or 12, EQ Diff should be lowered until the values of the 6 EQ stages are at 10 or below. The EQ Diff is a target for the equalizer block, which is the difference between the high pass filter and low pass filter values.

The VGA sets the amplitude going into the EQ block. The two numbers shown are the actual VGA Gain setting (read only), and the VGA Target, in mV. The VGA gain setting will be a large number when the serial input amplitude is small. It is recommended to increase the VGA Target if error free operation is not achieved with the default VGA Target of 63.9mV. However, when the actual VGA Gain setting number is too big,

above 85, the noise in the incoming signal will also be amplified, which is not recommended.

Figure 10. VSC7227 GUI – Input Stage and DFE Control Page

VSC 7227 Evaluation System System UC Device Help Status BER Main Clocking Input Stage & DFE Control Output Stage Control Data Rate Detect VScopy Register List Device Channel: 2 Loss LO5 LOL Detect CH0 n/a CH1 n/a CH2 n/a CH3 n/a CH4 n/a CH5 n/a CH6 n/a CH7 n/a CH8 n/a CH9 n/a CH10 n/a CH11 n/a Clock In 25.0 MHz cystal Dis Temp: Updates Variable Gain Amplifier Adaptive Mode VGA Gain 52 VGA Target $3.90 mF Input EQ Adaptation Mode EQ Table Manual Mode Reset EQ Stage: 1st 2nd 3rd 4th 5th 6th 7 6 6 6 6 6 6 6 EQ Diff Hysteresis 99 20 DFE Power Down Adaptive Mode Reset DFE Refresh Control Auto Refresh Manual Refresh -CONNECTED---LOADED REGISTERS-- Advanced

6.5.2 Advanced Input Stage - Further Optimization

When the Advanced box at the bottom of the page is checked, more controls become visible. For most applications, this would not be necessary.

The blue arrows in Figure 11 indicate the sliders or controls that are commonly used. Here are some of the steps to further optimize the VSC7227 receiver when error free operation is not achieved:

• For data rates greater than 10 Gbps, the DFE0 Dly and DFE1-3 Dly should be at Min. These are the DFE delay lines for DFE tap 0, and DFE tap 1-3. The settings for lower data rates, please refer to the Datasheet, register DFE_DELAY, address On_9E bit [15:8].
• When DFE is in Adaptive mode, check the value of DFE Tap 0, 1, 2, and 3 sliders. If the bar of any of these 4 sliders is on the red line, which means it is clipped at its limit. Increase the limit by increasing the value in the Tap 0 Max/Min Limit or Tap1-3 Limit box. Changing the value in the box will move the red line.
• The DFE Averaging slider sets the adaptation rate of the DFE block. It is recommended to set it to the slowest setting to avoid DFE tap fluctuation.

- For Revision A silicon, when DFE is in Adaptive Mode, lower the AP slider setting (the target amplitude adjustment into the DFE block) when the VF slider value is 126. Keep lowering AP until VF is lower than 80.

For Revision B silicon, when DFE is in Adaptive Mode, the VF is now the target amplitude control, while AP is the active setting, as shown in Figure 12. Increase the VF value until AP is between 60 and 80.

• Adjust EQ Diff until the desired BER is achieved. This action will increase or decrease the values of the 6 EQ stages, which are reflected in the 6 sliders.
• Adjust VGA Target to further optimize. This VGA block sets the amplitude of the signal going into the EQ block.

Figure 11. VSC7227 Rev. A GUI - Advanced Input Stage and DFE Control Page

VSC7227 Evaluation System System UC Device Help Status BER Mon Clocking Input Stage & DFE Control Output Stage Control Data Rate Detect VScope Register List Sync Timms CH0 00.00.00 Cumulative BER Error Count Fallsin Invest PRBS 2^7 CH1 00.00.00 PRBS 2^7 CH2 00.07.46 0 00000E00 PRBS 2^31 CH3 00.00.00 PRBS 2^7 Start/Stop button liner D0.07.47 [HHMM SS] Stop Checker Device Channel 2 Visible Gain Amplifier Adaptive Mode Manual Mode VGA Gain 41 Max Min Max Limit 96 Min Limit 6 VGA 63.90 mV Target VGA 4.95 mV Output EQ Adaptation Mode EQ Table Manual Mode Reset EQ Stage: 1st 2nd 3rd 4th 5th 6th 9 9 8 8 8 8 EQ Diff Hydlerim EQ Max EQ Min High Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low Post DAC Low PostDAC Lower DFE DFE Adoptive Mode Manual Mode Freeze DFE Tap 0 Tap 1 Tap 2 Tap 3 Max Max- Min Min Min -14 -28 -3 -3 Tap 0 Max Limit Tap 1-3 Limit Top D Min Limit Top D Min Limit DFE Averaging [Slomer] [Factor] DFEO Dfy DFE1-3 Dfy [Min] [Max] [Min] [Max] 77 S7 DFE DC Offset Auto Refresh Manual Refresh Log to file DC Offsets Auto Manual 1st 2nd -10 -8 Copy to ALL CH --CONNECTED -- LOADED REGISTERS-- Advanced

Figure 12. VSC7227 Rev. B GUI - Advanced Input Stage and DFE Control Page

VSC/227 Evaluation System System uC Device Help Status BER Main Clocking Input Stage & DFE Control Output Stage Control Data Rate Defect VScope Register List Device Channel: 2 LOS LOL Rate CH0 n/o CH1 n/o CH2 n/o CH3 n/o CH4 n/o CH5 n/o CH6 n/a CH7 n/a CH8 n/a CH9 n/a CH10 n/a CH11 n/a CH10 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 CH32 CH33 CH34 CH35 CH36 CH37 CH38 CH39 CH40 CH41 CH42 CH43 CH44 CH45 CH46 CH47 CH48 CH49 CH50 CH51 CH52 CH53 CH54 CH55 CH56 CH57 CH58 CH59 CH60 CH61 CH62 CH63 CH64 CH65 CH66 CH67 CH68 CH69 CH70 CH71 CH72 CH73 CH74 CH75 CH76 CH77 CH78 CH79 CH80 CH81 CH82 CH83 CH84 CH85 CH86 CH87 CH88 CH89 CH90 CH91 CH92 CH93 CH94 CH95 CH96 CH97 CH98 CH99 CH100 CH101 CH102 CH103 CH104 CH105 CH106 CH107 CH108 CH109 CH110 CH111 CH10 70.05 mV CH11 4.95 mV CH12 Max Limit 56 Min Limit 6 CH13 VGA TAPE 70.05 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.95 VGA TAPE 4.9 STAGE: 1st 2nd 3rd 4th 5th 6th Max Max Min Min EG Diff Hysteresis EQ Max EQ Min High Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Pass DAC Low Post -100 20 72 8 EG VGA Adaptation Mode ED VGA Resc 77 Manual Mode Max Limit Max Limit Min Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit Max Limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limit max limits DFE Tap 0 Tap 1 Tap 2 Tap 3 Max Max Min Min -41 -52 -15 -4 Top 0 Max Limt Top 1:3 Limt 32 80 Top 0 Min Limt VF DFE Averaging AP Max (Glower) (Foster) AP Min DFE00y DFE1-3:0y (Min) (Max) (Min) (Max) AP 46 32 Copy to ALL OH Auto Refresh Manual Release Log to No DC Offsets Auto Manual Totn End -68 1 -CONNECTED -- LOADED REGISTERS-- Advanced

• If error free operation is still not achieved, sometimes it is helpful to set the input EQ in the EQ Table mode. The default EQ Table value is 8, which means the 6 EQ stages are at 2/2/1/1/1/1. Increase the EQ Table value until the desired BER is achieved.
• Then, set the VGA in Manual mode, and increase the slider until the desired BER is achieved. It is ok to re-adjust the EQ Table again after adjusting the VGA gain value.
• At this point, if the desired BER is achieved, note down the VGA gain value and the 6 EQ stages values. Set both blocks to Adaptive mode. Then set the VGA Target value until it results in the same VGA gain value that was written down. Similarly, the EQ Diff value can be found that results in the same EQ stages values that were written down.

6.5.3 EQ Table and Manual Mode

The EQ block can also be set using EQ Table. The EQ Table has 91 settings. Each click will move 1 EQ stage by 1 click. For example, EQ Table = 6 means the value of all 6 EQ stages is 1. EQ Table = 8 means the value of 1^st and 2^nd EQ stage is 2, and the value of 3^rd to 6^th EQ stage is 1.

In manual mode, the user can freely adjust each of the EQ stages. It is recommended that the EQ Table is tried prior to the manual mode.

6.5.4 Logging

The user can log the receiver settings into a file. In the Input Stage & DFE Control window check the Log to file box, and when the Auto Refresh box is checked and the file name and location are specified, the log file is started. The log will end when the Auto Refresh box is unchecked. The log file is a .csv file which can be opened with Microsoft Excel.

6.6 Output Stage Control

Figure 13 shows the page where the user can adjust the output de-emphasis settings by simply sliding the bars up or down. The three-tap FIR architecture diagrams can be found in the datasheet.

The waveform on this page shows the effects of changing the de-emphasis taps graphically. The gray line shows the default script settings, which was configured to output a square eye. The red line shows the changes once the user adjusts any of the 3 FIR taps.

Figure 13. VSC7227 GUI - Output Stage Control Page

VSC7227 Evaluation System System uC Device Help Status BER Main Clocking Input Stage & DFE Control Output Stage Control Date Rate Detected VScope Register List LOS LOL Rate Detect Device Channel 2 To Output Control Inert Ch Output Polarity Pre Cursor C-1 Main Cursor E3 Post Cursor C+1 River/Fall Step Value 15 Tap Current: 10 mA Top Invert 20 20 ~25 mA ~25 ps 600 500 400 300 200 100 0 (mV) -200 -300 -400 -500 -600 Pre Cursor 0 dB Post Cursor 6586507 dB Show VSC7227 Default OR Plot Copy to ALL CH CONNECTED -- LOADED REGISTERS - Advanced

6.7 Data Rate Detect

The Data Rate Detect feature allows users to switch from one data rate to another, and the VSC7227 device will configure itself on the fly. For each channel, there are 4 look-up tables that are used to configure the VSC7227 to the known incoming data rates.

For revision A silicon, the Data Rate Detect is only available in Infiniband0 and Infiniband1, thus, SW1 and SW3 need to be configured as follows:

Component Pin Name State Component Pin Name State
SW1 pin 1	FCSEL0	0	SW3 pin 1	RESET Float
SW1 pin 2	FCSEL1	0	SW3 pin 2	EQ1_ADRS1 0
SW1 pin 3	FCSEL2	Float	SW3 pin 3	EQ0_ADRS0 0
SW1 pin 4	FCSEL3	Float	SW3 pin 4	MODE1	0
SW1 pin 5	FCSEL4	Float	SW3 pin 5	MODE0	1
SW1 pin 6	FCSEL5	Float	SW3 pin 6	LOS1	Float
SW1 pin 7	FCSEL6	Float	SW3 pin 7	LOS0	Float
SW1 pin 8	FCSEL7	Float	SW3 pin 8	N/C	Float

For revision B silicon, the Data Rate Detect can be operated in I2C mode.

First, the clocking needs to be configured. In this example, FSYN0 is configured for 10.3125 Gbps, and FSYN1 is configured for 8 Gbps as shown in Figure 14.

Figure 14. VSC7227 GUI - Setting Frequency Synthesizer 0 and 1

VSC7227 Evaluation System System uC Device Help Status BER Main Clocking Input Stage & DFE Control Output Stage Control Data Rate Date LOS LOL Rate Detect CH0 n/a CH1 n/a CH2 n/a CH3 n/a CH4 n/a CH5 n/a CH6 n/a CH7 n/a CH8 n/a CH9 n/a CH10 n/a CH11 n/a Global Reference Clock Input 25MHz crystal Relevance clock input buffer Input Clock Rate: 25.0 MHz On Off Load Frequency Plan Frequency Synthesizer 0 Enter Data Rate: 10.3125 Gbps On Off Frequency Synthesizer 1 Enter Data Rate: 8.0 Gbps

On the Data Rate Detect page shown in Figure 15, enter the desired data rates into each of the look-up tables and select the corresponding Reference Clock Source. In this example, the expected incoming data rates are 2 Gbps, 4 Gbps, 8 Gbps, and 10.3125 Gbps. The data rate in look-up table A needs to be lower than the data rate in look-up table B, and so on.

The DFE, EQ, and skew settings can also be individually adjusted in each look up table. Once everything is set, check the Enable box. In the Status panel, it shows which look-up table is being chosen by the device when the Update button is clicked.

Figure 15. VSC7227 GUI - Data Rate Detect

VSC7227 Evaluation System System UC Device Help Status BER Main Clocking Input Stage & DFE Control Output Stage Control Data Rate Detect VScope Register List LOS LOL Rate CH0 n/a CH1 n/a CH2 D Device Channel: 2 Auto Rate Detect Control Enable Gate Time 65.0 µs Lookup Table A Clocking Ref Clk Source FSYN1 Data Rate 2.0 Gbps Transition Density 0.5 Lookup Table B Clocking Ref Clk Source FSYN1 Data Rate 4.0 Gbps Transition Density 0.5 Lookup Table C Clocking Ref Clk Source FSYN0 Data Rate 8.0 Gbps Transition Density 0.5 Lookup Table D Clocking Ref Clk Source FSYN0 Data Rate 10.3125 Gbps Transition Density 0.5 DFE Adaptive Mode Manual Mode Freeze DFE Averaging (Slower) (Faster) DFE0 Dly DFE1-3 Dly (Min) (Max) (Min) (Max) DFE Averaging (Slower) (Faster) DFE0 Dly DFE1-3 Dly (Min) (Max) (Min) (Max) DFE Averaging (Slower) (Faster) DFE0 Dly DFE1-3 Dly (Min) (Max) (Min) (Max) DFE Averaging (Slower) (Faster) DFE0 Dly DFE1-3 Dly (Min) (Max) (Min) (Max) DFE Averaging (Slower) (Faster) DFE0 Dly DFE1-3 Dly (Min) (Max) (Min) (Max) EQ Adaptation Mode Rise/Fall EQ Table Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ Diff Rise/Fall EQ diff rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall rise/fall recovery to ALL CH Copyright to ALL CH CONNECTED Advanced

6.8 VScope

One of the VSC7227 features is an on-chip eye monitoring capability, which is called VScope. The user is able to look at the data eye of each channel at 2 different points inside the device. VScope sample points are before the DFE block and after the DFE block, which can be selected on the Vscope page as seen in Figure 16.

Click the Get Eye button to initiate a waveform capture. As there are numerous transactions to build the data eye a small progress bar window will pop up.

Figure 16. VSC7227 GUI - VScope at 10.3125 Gbps

VSC7227 Evaluation System System UC Device Help Status DEF Main Clocking Input Stage & DFE Control Output Stage Control Data Rate Detect VScope Regular List Device Channels: 2 VITESSE® Run VScope Get Eye Clear Wavelength Memory 1 2 3 4 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 CH32 CH33 CH34 CH35 CH36 CH37 CH38 CH39 CH40 CH41 CH42 CH43 CH44 CH45 CH46 CH47 CH48 CH49 CH50 CH51 CH52 CH53 CH54 CH55 CH56 CH57 CH58 CH59 CH60 CH61 CH62 CH63 CH64 CH65 CH66 CH67 CH68 CH69 CH70 CH71 CH72 CH73 CH74 CH75 CH76 CH77 CH78 CH79 CH80 CH81 CH82 CH83 CH84 CH85 CH86 CH87 CH88 CH89 CH90 CH91 CH92 CH93 CH94 CH95 CH96 CH97 CH98 CH99 Clock in 25.0 MHz cystal Update -CONNECTED -- LOADED REGISTERS-- Advanced

6.9 Register List

Reading or writing registers can be done on the Register List page as seen in Figure 17. The registers are grouped into nine tabs.

To read a register, simply click on the register name or highlight the register name and click the Read button. To write a register, highlight the desired register, enter the desired value in the Current Value box, and click Write.

For Input, DFECRU, Adaptation, Output, LOS, Data Rate Detect and VScope tabs, the read and write actions are per channel. To read or write to a different channel, click on the drop down menu under Device Channel in the top right corner. Writing to all twelve channels (broadcast) can also be done by clicking on the Broadcast Write button after entering the desired value.

For FSYN0 and FSYN1 tabs, the Broadcast Write button will write to both frequency synthesizers.

Figure 17. VSC7227 GUI - Register List

VSC7227 Evaluation System System UC Device Help Status BER Main Clicking.Input Stage & DFE Control Output Stage Control Data Rate Detect VScope Register List Device Channels: 0 Register Description Rw(15.12) EQ_SET0 Input equalizer first stage boost setting when in EQ Manual mode Rw(11.8) EQ_SET1 Input equalizer second stage boost setting when in EQ Manual mode Rw(7.4) EQ_SET2 Input equalizer third stage boost setting when in EQ Manual mode Rw(3.8) EQ_SET3 Input equalizer fourth stage boost setting when in EQ Manual mode. Register Values Selected Req Address(Hex) = 80 Page Number = 00 Register Type - RW Reset Value = 2211 Current Value : 2211 Read Write Broadcast Write ---CONNECTED --- LOADED REGISTERS--- □ Advanced

6.10 BER

The VSC7227 device has an internal error detector for each channel as seen in Figure 18. The user can simply select the desired PRBS pattern. Then, click the Start Checker button to begin error counting of all channels. The cumulative number of bit errors and the cumulative BER will be displayed for the 4 accessible channels on the evaluation board.

The button on top of the BER box will turn red when there is a sync loss, and it will turn green when sync is achieved. The Invert box is for polarity inversion.

For Revision A silicon, the error counter will automatically clear and restart when the error counter register is full, that is 10,922 bit errors. Revision B makes use of the new clock and error count mechanism and will run continuously making use of the algorithm described in the datasheet.

In order to display the bit error rate, the user needs to ensure that the CRU Data Rate is set up by entering the correct Data Rate and click the Load Frequency Plan button.

The timer at the bottom of the page shows the elapsed time since the Start Checker button is clicked. Then each individual channel error detector has each own timer, which is displayed above the Cumulative BER box for the corresponding channel. When the error counter is full, the timer for that particular channel will also be reset.

Figure 18. VSC7227 GUI - BER

VSC7227 Evaluation System System UC Device Help Status BER Sync Timer CH0 00:00:00 Cumulative BER Error Count Pattern Invert PRBS 2^7 CH1 00:00:00 PRBS 2^7 CH2 00:00:55 0.0000E00 PRBS 2^31 CH3 00:00:00 PRBS 2^7 Stait/Stop button timer 00:00:56 (HH:NM SS) Stop Checker Main Clocking Input Stage & DFE Control Output Stage Control Data Rate Detect VScope Register List Global Reference Clock Input 25MHz crystal Reference clock input buffer Input Clock Rate: 25.0 MHz On Off Load Frequency Plan Frequency Synthesizer 0 Enter Data Rate: 11.5 Gbps On Off Frequency Synthesizer 1 Enter Data Rate: 6 Gbps Channel Ref Clk Source CRU Data Rate CH0 FSYNO 11.5 Gbps CH1 FSYNO 11.5 Gbps CH2 FSYNO 11.5 Gbps CH3 FSYNO 11.5 Gbps CH4 FSYNO 11.5 Gbps CH5 FSYNO 11.5 Gbps CH6 FSYNO 11.5 Gbps CH7 FSYNO 11.5 Gbps CH8 FSYNO 11.5 Gbps CH9 FSYNO 11.5 Gbps CH10 FSYNO 11.5 Gbps CH11 FSYNO 11.5 Gbps --CONNECTED -- LOADED REGISTERS--

6.11 Save/Load All Registers

The user can save the register settings by simply selecting Device on the top menu bar, and selecting the Save All Registers menu option, as shown in Figure 19. A Save As window will pop up, asking for the file name and the save location. The file will be in a .txt format. Then, the user can simply load the saved file back into the VSC7227 at a later time using the Load All Registers selection.

Figure 19. VSC7227 GUI - Device Menu

VSC7227 Evaluation System System uC Device Help Status BER Load Default Registers Load All Registers Save All Registers Sync CH0 I/O Expander Bit Error Rate VSCOPECTRL Error Count VSCOPEPD LOWPWRADAPT_ACNT_MSB

6.12 Scripting

The user can also load a script into the GUI, which is in a .txt format. The Command Line Interface window can be launched by clicking uC on the top menu bar, and select the Vitesse Command Line Interface menu option as shown in Figure 20.

Figure 20. VSC7227 GUI - uC Menu

VSC7227 Evaluation System System uC Device Help Status BF F340 Firmware Version Reset F340 Vitesse Command Line Interface DFE Control Output Stage Output LOS Data Ra CH0 n/a EQSET45 EQBUFZONE CH1 n/a EQADAPTEN_DIFF EQTABLE

Click the Load Macro button on the Command Line Interface window, locate the script file, and hit enter. When a script is successfully loaded, a message will be displayed on the window (as shown in 0).

Figure 21. VSC7227 GUI - Command Line Interface

Vitesse Command Line Interface ASCII HEX Debug mode Load Macro Clear Hide > > > > > > > > > > > > > > > > > Sent 25 line(s) to hardware Macro Complete... > Send

7 Additional Information

For any additional information or questions regarding the devices mentioned in this document, contact your local sales representative.