SY89231U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89231U Microchip

The SY89231U is a precision, low jitter 3.2GHz ÷3, ÷5 clock divider with a LVDS output. The differential input includes Micrel's unique, 3-pin internal termination architecture that allows the input to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mV _PP ) without any level shifting or termination resistor networks in the signal path. The outputs are 325mV, 100K-compatible LVDS with fast rise/fall times guaranteed to be less than 200ps.

The SY89231U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89231U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at: www.micrel.com.

Block Diagram

IN 50Ω VT 50Ω /IN VREF-AC DIV SEL (TTLCMOS) EN (TTLCMOS) /MR (TTLCMOS) Div-by-3 Div-by-5 Q /Q

Precision Edge®

Features

• Accepts a high-speed input and provides a precision ÷ 3 and ÷ 5 sub-rate, LVDS output

• Guaranteed AC performance over temperature and supply voltage:

• DC-to >3.2GHz throughput

• <810ps Propagation Delay (In-to-Q)
• <200ps Rise/Fall times

- Ultra-low jitter design:

• <1ps _RMS random jitter
• <1psRMS cycle-to-cycle jitter
• <10pspp total jitter (clock)
• < 0.7ps_RMS MUX crosstalk induced jitter

- Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)

• Wide input voltage range V cc to GND
• 325mV LVDS output
  • 45% to 55% Duty Cycle (÷ 3)
  • 47% to 53% Duty Cycle (÷ 5)
  • 2.5V ±5% supply voltage
• -40°C to +85°C industrial temperature range
  • Available in 16-pin (3mm x 3mm) QFN package

Applications

- Fail-safe clock protection

Markets

• LAN/WAN
- Enterprise servers
- ATE
• Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax + 1 [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number Package Type	Operating Range	Package Marking Lead	Finish
SY89231UMG	QFN-16	Industrial	231U withPb-Free bar-line Indicator
SY89231UMGTR(2)	QFN-16	Industrial	231U withPb-Free bar-line Indicator

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals Only.
2. Tape and Reel.

Pin Configuration

DIV_SEL GND GND VCC IN 16 15 14 13 VT 2 12 Q VREF-AC 3 11 GND /IN 4 10 GND EN /MR NC VCC 9 /Q

16-Pin QFN

Pin Description

Pin Number	Pin Name	Pin Function
1, 4 IN, /IN		Differential Input: This input pair is the differential signal input to the device, which accepts AC- or DC-coupled signal as small as 100mV. The input internally terminates to a VT pin through 50Ω. Note that this input pair will default to an indeterminate state if left open. See “Input Interface Applications” subsection for more details.
2 VT		Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. The VT pin provides a center-tap for the input (IN, /IN) to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection for more details.
3 VREF-AC		Reference Voltage: This output biases to V_CC-1.2V . It is used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01μF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ±0.5mA. For more details, see “Input Interface Applications” subsection.
5 EN		Single-ended Input: This TTL/CMOS-compatible input disables and enables the output. It is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH. EN being synchronous, outputs will be enabled/disabled after a rising and a falling edge of the input clock. V_TH = V_CC/2 .
6 /MR		Single-ended Input: This TTL/CMOS-compatible input, when pulled LOW, asynchronously sets Q output LOW and /Q output HIGH. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. V_TH = V_CC/2 .
7 NC No Connect
8, 13 VCC		Positive Power Supply: Bypass with 0.1μF in parallel with 0.01μF low ESR capacitors as close to the V_CC pins as possible.
12, 9	Q, /Q	Differential Output: The output swing is typically 325mV. The output must be terminated with 100Ω across the pair (Q, /Q). See the “Truth Table” below for the logic function.
10, 11, 14,15	GND, Exposed Pad	Ground: Ground and exposed pad must be connected to a ground plane that is the same potential as the ground pins.
16	DIV_SEL	Single-ended Input: This TTL/CMOS-compatible input selects divide-by-3 when pulled LOW and divide-by-5 when pulled HIGH. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. V_TH = V_CC/2 .

Truth Table

Inputs Outputs
DIV_SEL	EN	/MR	Q	/Q
X	X	0	0	1
0	1	1	÷ 3	÷ 3
1	1	1	÷ 5	÷ 5
X	0	1	0	1

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) -0.5V to +4.0V

Input Voltage ( V_IN ) ......-0.5V to V_CC

LVPECL Output Current (IOUT)....±10mA

Source or sink current on V .....±100mA

Input Current

Source or sink current on (IN, /IN) .... ±50mA

Current ( V_REF-AC )

Source/Sink Current on V REF-AC ^(4) …… ±0.5mA

Maximum Operating Junction Temperature.....125°C

Lead Temperature (soldering, 20 sec.) .....+260°C

Storage Temperature ( T_s )....-65°C to 150°C

Operating Ratings ^(2)

Supply Voltage (Vcc)....+2.375V to +2.625V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

QFN ( _JA )

Still-Air 75°C/W

QFN ( _JB )

Junction-to-Board....33C/W

DC Electrical Characteristics ^(5)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply		2.375	2.5	2.625	V
I_CC	Power Supply Current	No load, max V_CC		71	95	mA
R_IN Input	Resistance (IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input High Voltage (IN, /IN)		1.2		V_CC	V
V_IL Input	Low Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 2a. Note 6.	0.1		V_CC	V
V_DIFF\_IN	Differential Input Voltage Swing |IN-/IN|	See Figure 2b.	0.2			V
V_REF-AC	Output Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V
V_T\_IN	Voltage from Input to V_T				1.8	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still air unless otherwise stated.
4. Due to limited drive capability use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IN (max) is specified when V_T is floating.

LVDS Outputs DC Electrical Characteristics ^(7)

V_CC = +2.5V ± 5% , R_L = 100 across the outputs; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OUT	Output Voltage Swing (Q, /Q)	See Figure 2a	250	325		mV
V_DIFF\_OUT	Differential Output Voltage Swing |Q – /Q|	See Figure 2b	500	650		mV
V_OCM	Output Common Mode Voltage (Q, /Q)	See Figure 5a	1.125	1.20	1.275	V
V_OCM	Change in Common Mode Voltage (Q, /Q)	See Figure 5b	-50		+50	mV

LVTTL/CMOS DC Electrical Characteristics ^(7)

V_CC = 2.5V ± 5% ; T_A = -40^ to +85°C, unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(8)
V_CC = 2.5V ± 5% ; R_L = 100 across the outputs; T_A = -40^ to +85°C, unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX Maximum Input Operating Frequency		V_OUT ≥ 200mV	3.2	4.5		GHz
tw	Minimum Pulse Width	IN, /IN	140			ps
t_pd Differential Propagation Delay In-to-Q			410	610	810	ps
		/MR(H-L)-to-Q		210	410	610
t_RR	Reset Recovery Time	/MR(L-H)-to-IN	400			ps
t_S EN	Set-up Time EN-to-IN	Note 9	50			ps
t_H EN	Hold Time IN-to-EN	Note 9	250			ps
t_skew	Part-to-Part Skew	Note 10			300	ps
t_JITTER	Clock Random Jitter	Note 11			1	ps_RMS
	Cycle-to-Cycle Jitter	Note 12			1	ps_RMS
	Total Jitter	Note 13			10	ps_PP
t_r, t_f	Output Rise/Fall Time (20% to 80%)	At full output swing.	90		200	ps
	Output Duty Cycle(÷ 3)	Duty Cycle (input): 50%; f ≤3.2GHz, Note 14	46	54	%
	Output Duty Cycle(÷ 5)	Duty Cycle (input): 50%; f ≤3.2GHz, Note 14	47	53	%

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
2. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply.
3. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
4. Random Jitter is measured with a K28.7 character pattern, measured at <f_MAX .
5. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, T_n - T_n-1 where T is the time between rising edges of the output signal.
6. Total Jitter definition: with an ideal clock input of frequency <f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
7. For Input Duty Cycle different from 50%, see "Output Duty Cycle Equation" in "Functional Description" subsection.

Functional Description

Output Duty Cycle Equation

For a non 50% input, derate the spec by:

Divide by 3:

$$ (0. 5 - \frac {1 + \frac {X}{1 0 0}}{3}) \times 1 0 0, \text {in} \% $$

Divide by 5:

$$ (0. 5 - \frac {2 + \frac {X}{1 0 0}}{5}) \times 100, \text {in} \% $$

X= input Duty Cycle, in %

Example: if a 45% input duty cycle is applied or X=45, in divide by 3 mode, the spec would expand by 1.67% to 44.3%-55.7%

Enable (EN)

EN is a synchronous TTL/CMOS-compatible input that enables/disables the outputs based on the input to this pin. Internal 25k pull-up resistor defaults the input to logic HIGH if left open. Input switching threshold is V_CC / 2 .

The Enable function operates as follows:

1. The enable/disable function is synchronous so that the clock outputs will be enabled following a rising and a falling edge of the input clock when switching from EN=LOW to EN=HIGH.

However, when switching from EN=HIGH to EN=LOW, the clock outputs will be disabled following an input clock rising edge and an output clock falling edge.

1. The enable/disable function always guarantees the full pulse width at the output before the clock outputs are disabled, non-depending on the divider ratio. Refer to Figure 1b for examples.

Divider Operation

The divider operation uses both the rising and falling edge of the input clock. For divide by 3, the falling edge of the second input clock cycle will determine the falling edge of the output. For divide by 5, the falling edge of the third input clock cycle. Refer to Figure 1c.

Timing Diagrams

/IN IN /Q Q tpd tpd VIN VOUT

Figure 1a. Propagation Delay

IN Q disabled EN IN Q disabled EN IN Q disabled EN IN Q disabled EN

Figure 1b. Enable Output Timing Diagram Examples (divide by 3)

IN 1st cycle 2nd cycle 1 1/2 Input Clock Cycles 3rd cycle 2 1/2 Input Clock Cycles Q (+3) Q (+5)

Figure 1c. Divider Operation Timing Diagram

Typical Operating Characteristics

V_CC = 2.5V , GND = 0V, t_f / t_f ≤ 300ps , R_L = 100 across the outputs; T_A = 25^ C , unless otherwise stated.

Functional Characteristics

V_CC = 2.5V , GND = 0V, V_IN = 350mV , Q = Divide by 3, t_f/t_f ≤ 300ps , R_L = 100 across the outputs; T_A = 25^ , unless otherwise stated.

Single-Ended and Differential Swings

V_IN, V_OUT 325mV (typ.)

Figure 2a. Single-Ended Voltage Swing

650mV (typ.) VDIFF_IN, VDIFF_OUT

Figure 2b. Differential Voltage Swing

Input Stage

Vcc IN 50Ω VT 50Ω /IN GND

Figure 3. Simplified Differential Input Stage

Input Interface Applications

VCC LVPECL GND VCC 0.1μF 19Ω IN /IN VT NC VREF-AC SY89231U

Figure 4a. LVPECL Interface (DC-Coupled)

VCC LVPECL 50Ω 50Ω GND GND VCC 0.1μF IN /IN SY89231U VT VREF-AC

Figure 4b. LVPECL Interface (AC-Coupled)

VCC CML IN /IN GND SY89231U NC□—VT NC□—VREF-AC

Option: may connect V_T to V_CC
Figure 4c. CML Interface (DC-Coupled)

VCC CML GND VCC 0.1μF IN /IN VT VREF-AC SY89231U

Figure 4d. CML Interface (AC-Coupled)

VCC LVDS IN /IN GND SY89231U NC □ VT NC □ VREF-AC

Figure 4e. LVDS Interface (DC-Coupled)

LVDS Output Interface Applications

LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in the ground between and LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.

VOUT 100Ω VOH, VOL VOH, VOL GND

Figure 5a. LVDS Differential Measurement

50Ω 50Ω VOCM+ ΔVOCM GND

Figure 5b. LVDS Common Mode Measurement

Related Product and Support Documentation

Part Number	Function	Datasheet Link
SY89228U	1GHz Precision, LVPECL ÷3, ÷5 Clock Divider with Fail Safe Input and Internal Termination
SY89229U	1GHz Precision, LVDS ÷3, ÷5 Clock Divider with Fail Safe Input and Internal Termination
SY89230U	3.2GHz Precision, LVPECL ÷3, ÷5 Clock Divider
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

Package Information

PIN 1 DOT BY MARKING 3.000±0.050 1 2 3.000±0.050

TOP VIEW

1.550±0.050 Exp.DAP PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 0.400±0.050 1 2 1.550±0.050 Exp.DAP 0.500 BSC 0.230±0.050 1.500 Ref.

BOTTOM VIEW

0.850±0.050 0.05 C SEATING PLANE 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABLE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.
5 APPLIED ONLY FOR TERMINALS
6 APPLIED FOR EXPOSED PAD AND TERMINALS.

16-Pin QFN

Packages Notes:

1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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