MIC5374 - Electronic component Microchip - Free user manual and instructions

USER MANUAL MIC5374 Microchip

The MIC5374/84 is a four output device with three 200mA LDOs and a real time clock (RTC) 1mA LDO which is ideal for application processor support in mobile platforms. The MIC5374 provides independent control active high enables for each of the 200mA LDOs with an additional always-on RTC LDO. The MIC5384 provides active low enables. Both the MIC5374 and MIC5384 are available in the tiny 2.5mm x 2.5mm Thin MLF® package.

The MIC5374/84 is designed for high input ripple rejection (high PSRR) and provides low output noise making it ideal for powering sensitive RF circuitry such as GPS, WiFi, and Bluetooth applications. The MIC5374/84 also incorporates a power-on-reset (POR) supervisor with adjustable delay time set by an external capacitor, and an independent input pin to monitor any voltage level. Once high, the POR output can be asserted low again by enabling the manual reset (MR) pin. When the MR pin is restored low, the POR output will re-time the delay set by the external delay capacitor.

The MIC5374/84 operates with very small ceramic output capacitors to reduce board space and component cost. It is available in various fixed output voltages. The MIC5374/84 has a junction temperature range from -40^ to 125^ .

Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Features

• 1.7V to 5.5V input supply voltage range
• Output current - 200mA LDO1/2/3, 1mA LDO4
- LDO4 – Ultra low 8μA I _BIAS for RTC support
• High output accuracy (±2%)
- Independent enable pins
• POR with user-defined voltage monitoring
- POR voltage input
- Adjustable delay time
- Manual reset pin
- Low dropout voltage – 170mV at 150mA
• High PSRR – 55dB at 1kHz on each LDO
- Stable with tiny ceramic output capacitors
- 2.5mm x 2.5mm Thin MLF 16-pin package
• Thermal-shutdown and current-limit protection

Applications

• Mobile phones
• GPS receivers
  • Application co-processors
  • PDAs and handheld devices

Typical Application

MIC5374 0.1µF BIAS OUT1 1µF INLDC1/2 OUT2 1µF INLDO3 OUT3 1µF INLDO4 OUT4 1µF EN1 POR 10k Vbias EN2 POR_IN 10k Vmonitor EN3 DLY 10k MR GND 150pF

Typical MIC5374-xxxYMT Circuit (Active High Enable)

MIC5384 BIAS OUT1 INLDO1/2 1μF OUT2 INLDO3 1μF OUT3 INLDO4 1μF OUT4 1μF EN1 POR 10k Vbias EN2 Vmonitor EN3 POR_IN 10k DLY 150pF GND MR 100k

Typical MIC5384-xxxYMT Circuit (Active Low Enable)

MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information

Part Number	Mark Code	Output Voltage^(1)	Junction Temperature Range	Package	Lead (2)
MIC5374-MG44YMT	MG44	2.8V/1.8V/1.2/1.2V	-40° to +125°C	16-Pin 2.5mm x 2.5mm Thin MLF	Pb-free
MIC5374-SJG1YMT	SJG1	3.3V/2.5V/1.8V/1.0V	-40° to +125°C	16-Pin 2.5mm x 2.5mm Thin MLF	Pb-free
MIC5384-MG44YMT	Z1U	2.8V/1.8V/1.2/1.2V	-40° to +125°C	16-Pin 2.5mm x 2.5mm Thin MLF	Pb-free
MIC5384-SJG1YMT	Z5U	3.3V/2.5V/1.8V/1.0V	-40° to +125°C	16-Pin 2.5mm x 2.5mm Thin MLF	Pb-free

Note:

1. Other voltage options available. Contact Micrel for details.
2. Lead finish is NiPdAu. Mold compound material is halogen free.

Pin Configuration

EN1 EN2 EN3 GND 16 15 14 13 OUT1 1 OUT3 INLDO1/2 2 INLDO3 OUT2 3 INLDO4 BIA5 4 OUT4 5 6 7 8 POR_IN POR DLY MR

MIC5374 16-Pin 2.5mm x 2.5mm Thin MLF (MT) (Top View)

/EN1 /EN2 /EN3 GND OUT1 16 15 14 13 INLDO1/2 2 12 OUT3 OUT2 3 11 INLDO3 BIAS 4 10 INLDO4 5 6 7 8 OUT4 POR_IN POR DLY MR

MIC5384 16-Pin 2.5mm x 2.5mm Thin MLF (MT) (Top View)

Pin Description

Pin Number	Pin Name	Pin Function
1 OUT1	Regulator Output - LDO1.
2 INLDO	1/2 Supply Input (LDO1/2).
3 OUT2	Regulator Output – LDO2.
4 BIAS	Internal Bias Supply Voltage. Must be de-coupled to ground with a 0.1μF capacitor.
5	POR_IN	Input to POR. Connect directly to output voltage or input voltage that is to be monitored for a 0.9V reference, or connect a resistor divider network to this pin to program the POR monitoring voltage.
6 POR	Power-on-Reset	Output. Open drain.
7 DLY	POR Delay Capacitor. Connect capacitor to ground to set POR delay time.
8	MR	Manual Reset Input. Manually resets output of POR and delay generator. Do not leave floating.
9 OUT4	Regulator Output - LDO4.
10	INLDO4	Supply Input (LDO4). Ultra-low IQ RTC LDO. 1.7V to 5.5V input voltage range.
11	INLDO3	Supply Input (LDO3).
12	OUT3 Regulator Output – LDO3.
13	GND	Ground.
14	EN3 or /EN3	LDO3 Enable Input. EN (MIC5374): Active High Input. Logic High = On; Logic Low = Off; /EN (MIC5384): Active Low Input. Logic High = Off; Logic Low = On. Do not leave floating.
15	EN2 or /EN2	LDO2 Enable Input. EN (MIC5374): Active High Input. Logic High = On; Logic Low = Off; /EN (MIC5384): Active Low Input. Logic High = Off; Logic Low = On; Do not leave floating.
16	EN1 or /EN1	LDO1 Enable Input. EN (MIC5374): Active High Input. Logic High = On; Logic Low = Off; /EN (MIC5384): Active Low Input. Logic High = Off; Logic Low = On; Do not leave floating.
HS Pad	EPAD	Exposed Heat Sink Pad. Connect to GND.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_INLDO1/2, INLDO3, INLDO4 ) ..... -0.3V to +6V

Bias Supply Voltage ( V_BIAS )....-0.3V to +6V

Enable Input Voltage ( V_EN1, EN2, EN3 )....-0.3V to +6V

POR Output Voltage (POR) ...... -0.3V to +6V

POR Input Voltage (POR_IN) ....-0.3V to +6V

MR Voltage (MR) -0.3V to +6V

DLY Voltage (DLY)....-0.3V to +6V

Power Dissipation .... Internally Limited ^(2)

Lead Temperature (soldering, 10s).... 260°C

Storage Temperature ( T_s ) -60^ to +150^

ESD Rating ^(3) ESD Sensitive

Operating Ratings ^(4)

Supply Voltage ^(5) ( V_INLDO1/2, INLDO3, INLDO4 ) ..... +1.7V to V_BIAS

Bias Supply Voltage ( V_BIAS )....+2.5V to +5.5V

Enable Input Voltage (V EN1, EN2, EN3 )...... 0V to V BIAS

POR Output Voltage (POR) 0V to +5.5V

POR Input Voltage (POR_IN) 0V to VBIAS

MR Voltage (MR) 0V to V_BIAS

DLY Voltage (DLY).... 0V to V _BIAS

Junction Temperature (T _J ) ...... -40°C to +125°C

Junction Thermal Resistance

2.5 x 2.5 Thin MLF 16L ( _JA ).....100°C/W

Electrical Characteristics ^(6)

(MIC5374) V_IN = V_OUT + 1V ( V_OUT is highest of the three regulator outputs); V_BIAS = V_EN1 = V_EN2 = V_EN3 = 5.5V (ON);

(MIC5384) V_IN = V_OUT + 1V ( V_OUT is highest of the three regulator outputs); V_BIAS = 5.5V ; V_/EN1 = V_/EN2 = V_/EN3 = GND (ON);

I_OUT1 = I_OUT2 = I_OUT3 = I_OUT4 = 100 A; C_OUT1 = C_OUT2 = C_OUT3 = C_OUT4 = 1 F; T_A = 25^.

Bold values indicate -40^ ≤ T_J ≤ +125^ , unless noted.

Parameter	Conditions			Min.
Output Voltage Accuracy (LDO1/2/3)	Variation from nominal V_OUT1,2,3	-2.0		+2.0	%
	Variation from nominal V_OUT1,2,3	-3.0		+3.0
Output Voltage Accuracy (LDO4 - RTC Support)	Variation from nominal V_OUT4	-4.0		+4.0	%
	Variation from nominal V_OUT4	-5.0		+5.0
Line Regulation V	_IN=V_OUT+1V to 5.5V; I_OUT=100μA 0.02 0.3	%/V
Load Regulation	I_OUT=100μA to 150mA; LDO1/2/3		0.3	1	%
	I_OUT=100μA to 1mA; LDO4	0.05	1
Dropout Voltage	I_OUT=50mA; V_OUT≥ 2.8V		60	115	mV
	I_OUT=150mA; V_OUT≥ 2.8V		170	330
	I_OUT=50mA; V_OUT<2.8V		85	145
	I_OUT=150mA; V_OUT<2.8V		275	450
Input Ground Current	EN1 or EN2 or EN3 = ON; Not including I_BIAS		10	20	μA
	LDO4; EN1 = EN2 = EN3 = OFF; Not including I_BIAS		3	8
Input Bias Current	EN1 or EN2 or EN3 = ON; with LDO4 ON		42	70	μA
	EN1 = EN2 = EN3 = ON; with LDO4 ON		106	170
Shutdown Input Ground Current	EN1 = EN2 = EN3 = OFF	0.04		2	μA
Shutdown Bias Current	EN1 = EN2 = EN3 = OFF; with LDO4 ON		8	13	μA
Ripple Rejection	f = 1kHz; C_OUT=1.0μF		55		dB
Current Limit	V_OUT=0V; LDO1/2/3	200	350	700	mA
	V_OUT=0V; LDO4	2	12	50

Notes:

1. Exceeding the absolute maximum rating may damage the device.
2. The maximum allowable power dissipation of any T_A (ambient temperature) is P_D() = (T_J() - T_A) / _JA . Exceeding the maximum allowable power dissipation will result in excessive die temperature and the regulator will go into thermal shutdown.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
4. The device is not guaranteed to function outside its operating rating.
5. For V_IN range of 1.7V to 2.5V, output current is limited to 30mA.
6. Specification for packaged product only.

Electrical Characteristics ^(6) (Continued)

(MIC5374) V_IN = V_OUT + 1V ( V_OUT is highest of the three regulator outputs); V_BIAS = V_EN1 = V_EN2 = V_EN3 = 5.5V (ON);

(MIC5384) V_IN = V_OUT + 1V ( V_OUT is highest of the three regulator outputs); V_BIAS = 5.5V ; V_/EN1 = V_/EN2 = V_/EN3 = GND (ON);

I_OUT1 = I_OUT2 = I_OUT3 = I_OUT4 = 100 A; C_OUT1 = C_OUT2 = C_OUT3 = C_OUT4 = 1 F; T_A = 25^.

Bold values indicate -40^ ≤ T_J ≤ +125^ , unless noted.

Parameter	Conditions	Min.			Typ.
Output Voltage Noise C	_OUT = 1μF,10Hz to 100kHz; I_OUT = 150mA 200 μV				RMS
Enable Input Voltage	(MIC5374) LDO OFF; (MIC5384) LDO ON			0.2	V
	(MIC5374) LDO ON; (MIC5384) LDO OFF	1.2
Enable Input Current	VIL ≤ 0.2V		0.01		μA
	VIH ≥ 1.2V		0.01
Turn-On Time C	_OUT = 1μF 80			200	μs
V_POR POR Output Low Voltage				0.2	V
DLY Pin Current Source	V_DLY = 0V	0.75	1.25	2	μA
DLY Pin Voltage Threshold		1.13	1.25	1.38	V
I_POR	POR Output Leakage Current, V_POR OFF	1		μA
V_TH	POR Undervoltage Threshold	0.873	0.9	0.927	V
V_HYS	POR Voltage Threshold Hysteresis		34		mV
I_POR\_IN	POR Input Pin Leakage Current		1		μA
Thermal Shutdown			155		°C
Thermal-Shutdown Hysteresis			10		°C

Typical Characteristics

Typical Characteristics (Continued)

Typical Characteristics (Continued)

Typical Characteristics (Continued)

Typical Characteristics (Continued)

Typical Characteristics (Continued)

Typical Characteristics (Continued)

LDO3 Output Noise Spectral Density

LDO1 PSRR ( I_OUT = 100 A )

LDO1 PSRR ( I_OUT = 150mA )

LDO2 PSRR ( I_OUT = 100 A )

LDO2 PSRR ( I_OUT = 150mA )

LDO3 PSRR (IOUT = 100μA)

LDO3 PSRR ( I_OUT = 150mA )

Functional Characteristics

Start-Up Waveform for LDO1/2/3

Shutdown Waveform for LDO1/2/3

LDO1 Load Transient (1mA to 150mA)

LDO2 Load Transient (1mA to 150mA)

LDO3 Load Transient (1mA to 150mA)

LDO1 Line Transient (4.3V to 5.5V)

Functional Characteristics (Continued)

Functional Characteristics (Continued)

MIC5374 POR with DLY and MR Waveform

Time (200μs/div)

MIC5384 POR with DLY and MR Waveform

Time (200μs/div)

Functional Diagrams

graph TD
    A["INLDO1/2 EN1"] --> B["LDO1"]
    A --> C["LDO2"]
    D["INLDO3 EN3"] --> E["LDO3"]
    F["INLDO4"] --> G["LDO4"]
    H["POR_IN MR"] --> I["REFERENCE"]
    I --> J["POR"]
    K["BIAS"] --> B
    K --> E
    K --> G
    K --> I
    K --> J
    style A fill:#f9f,stroke:#333
    style D fill:#f9f,stroke:#333
    style F fill:#f9f,stroke:#333
    style H fill:#f9f,stroke:#333
    style K fill:#ccf,stroke:#333
    style K fill:#ccf,stroke:#333

MIC5374 Block Diagram

graph TD
    A["INLDO1/2 EN1"] --> B["LDO1"]
    A --> C["LDO2"]
    D["INLDO3 EN3"] --> E["LDO3"]
    F["INLDO4"] --> G["LDO4"]
    H["POR_IN MR"] --> I["REFERENCE"]
    I --> J["POR"]
    K["BIAS"] --> B
    K --> E
    K --> G
    K --> I
    K --> J
    L["OUT1"] --> B
    L --> E
    L --> G
    M["OUT2"] --> E
    N["OUT3"] --> G
    O["OUT4"] --> G
    P["GND"] --> I
    Q["DLY"] --> J

MIC5384 Block Diagram

Pin Descriptions

INLDO

The LDO input pins INLDO1/2, INLDO3 and INLDO4 provide the input power to the linear regulators LDO1, LDO2, LDO3 and LDO4. The input operating voltage range is from 1.7V to 5.5V. For input voltages from 1.7V to 2.5V the output current must be limited to 30mA each. Due to line inductance a 1 F capacitor placed close to the INLDO pins and the GND pin is recommended. Please refer to layout recommendations.

BIAS

The BIAS pin provides power to the internal reference and control sections of the MIC5374/84. A 0.1 F ceramic capacitor must be connected from BIAS to GND for clean operation.

EN (MIC5374)

The enable pins EN1, EN2 and EN3 provide logic level control for the outputs OUT1, OUT2 and OUT3, respectively. A logic high signal on an enable pin activates the respective LDO. A logic low signal on an enable pin deactivates the respective LDO. Do not leave the EN pins floating, as it would leave the regulator in an unknown state.

/EN (MIC5384)

The enable pins /EN1, /EN2 and /EN3 provide logic level control for the outputs OUT1, OUT2 and OUT3, respectively. A logic high signal on an enable pin deactivates the respective LDO. A logic low signal on an enable pin activates the respective LDO. Do not leave the EN pins floating, as it would leave the regulator in an unknown state.

OUT

OUT1, OUT2, OUT3 and OUT4 are the output pins of each LDO. A minimum of 1 F capacitor be placed as close as possible to each of the OUT pins. A minimum voltage rating of 6.3V is recommended for each capacitor.

GND

The ground (GND) pin is the ground path for the control circuitry and the power ground for all LDOs. The current loop for the ground should be kept as short as possible. Refer to the layout recommendations for more details.

POR

The power-on-reset (POR) pin is an open drain output. A resistor (10kΩ to 100kΩ) can be used for a pull up to either the input or the output voltage of the regulator. POR is pulled high by the external pull up resistor when the voltage at DLY reaches 1.25V.

A delay can be added by placing a capacitor from the DLY pin to ground.

POR\_IN

The power-on-reset input (POR_IN) pin compares any voltage to an internal 0.9V reference. This function can be used to monitor any of the LDO outputs or any external voltage rail. When the monitored voltage is greater than 0.9V, the POR_IN flag will internally trigger a 1.25μA source current to charge the external capacitor at the DLY pin. A resistor divider network may be used to divide down the monitored voltage to be compared with the 0.9V at the POR_IN. This resistor network can change the trigger point to any voltage level. A small decoupling capacitor is recommended between POR_IN and ground to reject high frequency noise that might interfere with the POR circuit. Do not leave the POR_IN pin floating.

DLY

The delay (DLY) pin is used to set the POR delay time. Adding a capacitor to this pin adjusts the delay of the POR signal. When the POR_IN flag is triggered, a constant 1.25μA current begins to charge the external capacitor tied to the DLY pin. When the capacitor reaches 1.25V the POR flag will be pulled high by the external pull up resistor. Equation 1 illustrates how to calculate the charge time is shown:

$$ t _ {\text { DELAY }} (s) = \left(\frac {C _ {D L 4} 2 5 V}{x 1 0 2 5 . 1}\right) ^ {x} \quad E q. $$

The delay time (t) is in seconds, the delay voltage is 1.25V internally, and the external delay capacitance ( C_DLY ) is in microfarads. For a 1 F delay capacitor, the delay time will be 1 second. A capacitor at the DLY pin is recommended when the POR function is used in order to prevent unexpected triggering of the POR signal in noisy systems.

MR

The manual reset (MR) pin resets the output of POR and DLY generator regardless if the monitored voltage is in regulation or not. Applying a voltage greater than 1.2V on the MR pin will cause the POR voltage to be pulled low. When a voltage below 0.2V is applied to the MR pin, the internal 1.25 A will begin to charge the DLY pin until it reaches 1.25V. When the DLY pin reaches 1.25V, the POR voltage will be pulled high by the external pull up resistor. Do not leave the MR pin floating.

Application Information

MIC5374/84 is a four output device with three 200mA LDOs and a 1mA RTC LDO. The MIC5374/84 incorporates a POR function with the capability to monitor any voltage using POR_IN. The monitored voltage can be set to any voltage threshold level to trigger the POR flag. A delay on the POR flag may also be set with an external capacitor at the DLY pin. All the LDOs have current limit and thermal shutdown protection to prevent damage from fault conditions. MIC5374 has active high enables while the MIC5384 has active low enables.

RTC LDO

LDO4 is an always-on RTC LDO used for application processor support and can provide 1mA of output current. Power must be provided to the INLDO4 and BIAS pins to keep LDO4 enabled.

Input Capacitor

The MIC5374/84 is a high-performance, high-bandwidth device. An input capacitor of 1 F from the input pin to ground is required to provide stability. Low-ESR ceramic capacitors provide optimal performance in small board area. Additional high-frequency capacitors, such as small valued NPO dielectric type capacitors, help filter out high-frequency noise and are good practice in any RF-based circuit. X5R or X7R dielectrics are recommended for the input capacitor. Y5V dielectrics lose most of their capacitance over temperature and are therefore not recommended.

Output Capacitor

The MIC5374/84 requires an output capacitor of 1 F or greater to maintain stability. The design is optimized for use with low-ESR ceramic chip capacitors. High-ESR capacitors may cause high-frequency oscillation. The output capacitor can be increased, but performance has been optimized for a 1 F ceramic output capacitor and does not improve significantly with larger capacitance.

X7R and X5R dielectric ceramic capacitors are recommended because of their temperature performance. X7R capacitors change capacitance by 15% over their operating temperature range and are the most stable type of ceramic capacitors. Z5U and Y5V dielectric capacitors change value by as much as 50% and 60% respectively over their operating temperature ranges. To use a ceramic chip capacitor with Y5V dielectric the value must be much higher than an X7R ceramic capacitor to ensure the same minimum capacitance over the equivalent operating temperature range.

No Load Stability

Unlike many other voltage regulators, the MIC5374/84 will remain stable and in regulation with no load.

Thermal Considerations

The MIC5374/84 is designed to provide three outputs up to 200mA each of continuous current in a very small package. Maximum ambient operating temperature can be calculated based on the output current and the voltage drop across the part. For example if the input voltages are 3.6V and the output voltages are 3.3V, 2.5V, and 1.8V each with an output current = 150mA. The actual power dissipation of the regulator circuit can be determined using Equation 2:

$$ P _ {D} = \left(V _ {\text { INLDO1 / 2 }} - V _ {\text { OUT1 }}\right) I _ {\text { OUT1 }} + $$

$$ \left(V _ {\text { INLDO1 / 2 }} - V _ {\text { OUT2 }}\right) I _ {\text { OUT2 }} + $$

$$ \left(V _ {\text { INLDO3 }} - V _ {\text { OUT3 }}\right) I _ {\text { OUT3 }} + $$

$$ \left(V _ {\text {INLDO4}} - V _ {\text {OUT4}}\right) I _ {\text {OUT4}} + V _ {\text {IN}} \times I _ {\text {GND}} \quad \text {Eq. 2} $$

As the MIC5374/84 is a CMOS device, the ground current is typically <100 A over the load range, the power dissipation contributed by the ground current is <1% and may be ignored for this calculation. Since LDO4 only supplies 1mA of current, it can also be ignored for this calculation, illustrated in Equation 3:

$$ P _ {D} \approx (3. 6 V - 3. 3 V) 1 5 0 m A + (3. 6 V - 2. 5 V) 1 5 0 m A + $$

$$ (3. 6 \mathrm{V} - 1. 8 \mathrm{V}) 1 5 0 \mathrm{mA} $$

$$ P _ {D} \approx 0. 4 8 W \quad E q. 3 $$

To determine the maximum ambient operating temperature of the package, use the junction to ambient thermal resistance of the device and the following Equation 4:

$$ P _ {D (M A X)} = \left(\frac {T - T _ {A J (M A X)}}{\theta_ {J A}}\right) E q. 4 $$

$$ T _ {J (M A X)} = 1 2 5 ^ {\circ} C $$

$$ \theta_ {\mathrm{JA}} = 1 0 0 ^ {\circ} \mathrm{C} / \mathrm{W} $$

Substituting P_D for P_D(max) and solving for the ambient operating temperature will give the maximum operating conditions for the regulator circuit.

The maximum power dissipation must not be exceeded for proper operation.

For example, when operating the MIC5374-SJG1YMT at an input voltage of 3.6V and 150mA load on LDO1, LDO2 and LDO3 with a minimum layout footprint, the maximum ambient operating temperature T_A can be determined as in Equation 5:

$$ 0. 4 8 \mathrm{W} = (1 2 5 ^ {\circ} \mathrm{C} - \mathrm{T} _ {\mathrm{A}}) / (1 0 0 ^ {\circ} \mathrm{C} / \mathrm{W}) $$

$$ T _ {A} = 7 7 ^ {\circ} \mathrm{C} \quad \text { Eq. } 5 $$

Therefore the maximum ambient operating temperature of 77^ C is allowed in a 2.5mm x 2.5mm Thin MLF package for the voltage options specified and at the maximum load of 150mA on each output. For a full discussion of heat sinking and thermal effects on voltage regulators, refer to the “Regulator Thermals” section of Micrel’s Designing with Low-Dropout Voltage Regulators handbook. This information can be found on Micrel’s website at:

http://www.micrel.com/_PDF/other/LDOBk_ds.pdf

Typical Circuit (MIC5374-xxxxYMT)

U1 MIC5374-xxxxYMT BIAS C1 0.1μF INLDO1/2 C2 1μF INLDO3 C3 1μF INLDO4 C4 1μF EN1 EN2 EN3 MR R4 100k OUT1 C7 1μF OUT2 C6 1μF OUT3 C5 1μF OUT4 C8 1μF POR POR_IN DLY GND R10 VBIAS 10k VMONITOR C9 R5 R6 C10 150pF

Bill of Materials

Item	Part Number		Manufacturer Description
C1	C1005X5R1A104K	^(1) TDKapacitor, 0.1μF Ceramic, 10V, X5R, Size 0402 1
C2, C3, C4, C5, C6, C7, C8	C1005X5R1A105K TDK	Capacitor, 1μF Ceramic, 10V, X5R, Size 0402 7
C9	Optional
C10	C1005C0G1H151J	TDK	Capacitor, 150pF Cermaic, 50V, C0G, Size 0402	1
R4	CRCW0402100KFKED	Vishay ^(2)	100kΩ, 1%, 0402	1
R5, R6	Optional	Vishay	Optional	2
R10	CRCW040210KFKED	Vishay	10kΩ, 1%, 0402	1
U1	MIC5374-xxxxYMT	Micrel, Inc. ^(3)	High-Performance Active High Enable Triple 200mA LDO with 1mA RTC LDO	1

Notes:
1. TDK: www.tdk.com.
2. Vishay: www.vishay.com.
3. Micrel, Inc.: www.micrel.com.

Typical Circuit (MIC5384-xxxxYMT)

U1 MIC5384-xxxxYMT BIAS OUT1 C1 0.1µF INLDO1/2 OUT2 C2 1µF INLDO3 OUT3 C3 1µF INLDO4 OUT4 C4 1µF EN1 POR VBIAS EN2 POR_IN VMONITOR EN3 C9 R5 R6 DLY GND C10 150pF R4 100k

Bill of Materials

Item	Part Number		Manufacturer Description
C1	C1005X5R1A104K	^(1) D Kapacitor, 0.1μF Ceramic, 10V, X5R, Size 0402 1
C2, C3, C4, C5, C6, C7, C8	C1005X5R1A105K TDK	Capacitor, 1μF Ceramic, 10V, X5R, Size 0402 7
C9	Optional
C10	C1005C0G1H151J	TDK	Capacitor, 150pF Cermaic, 50V, C0G, Size 0402	1
R4	CRCW0402100KFKED	Vishay ^(2)	100kΩ, 1%, 0402	1
R5, R6	Optional	Vishay	Optional	2
R10	CRCW040210KFKED	Vishay	10kΩ, 1%, 0402	1
U1	MIC5384-xxxxYMT	Micrel, Inc. ^(3)	High-Performance Active Low Enable Triple 200mA LDO with 1mA RTC LDO	1

Notes:
1. TDK: www.tdk.com.
2. Vishay: www.vishay.com.
3. Micrel, Inc.: www.micrel.com.

PCB Layout Recommendations

Recommended Top Layout

ICREF1JC 408-344-0800 I/O *NT OHPB R0H2 BD# 04010-DL TMYXXX\A7\88\G4\xxxxYMT

Recommended Bottom Layout

Package Information

PIN 1# DOT BY MARKING 2.50±0.05 2.50±0.05

TOP VIEW

0.20±0.05 1.40±0.05 Exp.DAP 0.35±0.05 0.40 Bsc 1.20 Ref. PIN #1 ID R0.10 1.40±0.05 Exp.DAP

BOTTOM VIEW

0.55±0.05 0.00-0.05 0.15 Ref.

SIDE VIEW
NOTES
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.08 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER MARKED.

16-Pin 2.5mm x 2.5mm Thin MLF (MT)

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