SY89847U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89847U Microchip

1.5 GHz Precision LVDS 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination

Features

• Selects Between Two Sources and Provides 5 Precision LVDS Copies
• Fail Safe Input Prevents Outputs from Oscillating when Input is Invalid
• Guaranteed AC Performance over Temperature and Supply Voltage:
• DC-to >1.5 GHz Throughput
• <1000 ps Propagation Delay (IN-to-Q)
• <210 ps Rise/Fall Times

- Ultra-Low Jitter Design:

• < 1 RM\$ Random Jitter
• < 1 RMS Cycle-to-Cycle Jitter
• < 1 0pp Total Jitter (Clock)
• < 0 . RMB MUX Crosstalk Induced Jitter

- Unique, Patented MUX Input Isolation Design Minimizes Adjacent Channel Crosstalk

- Unique, Patented Internal Termination and V_T Pin Accepts DC- and AC-Coupled Inputs (CML, PECL, LVDS)

- Wide Input Voltage Range V_CC to GND

• 2.5V ±5% Supply Voltage

- - 40^ C to + 85^ C Industrial Temperature Range

• Available in 32-Pin (5 mm x 5 mm) QFN Package

Applications

• Fail Safe Clock Protection
  • Ultra-Low Jitter LVDS Clock Distribution
  • Rack-Based Telecom/Datacom

Markets

• LAN/WAN
- Enterprise Servers
- ATE
• Test and Measurement

General Description

The SY89847U is a 2.5V, 1:5 LVDS fanout buffer with a 2:1 differential input multiplexer (MUX). A unique fail safe input (FSI) protection prevents metastable output conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops significantly below 100 mV).

The differential input includes Microchip's unique, 3-pin internal termination architecture that can interface to any differential signal (AC- or DC-coupled) as small as 100 mV (200 mV) without any level shifting or termination resistor networks in the signal path. The outputs are LVDS compatible with very fast rise/fall times guaranteed to be less than 210 ps.

The SY89847U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89847U is part of Microchip's high-speed, Precision Edge® product line.

Package Type

SY89847U 5 mm x 5 mm QFN-32 (M) (Top View) VREF-AC0 GND GND VCC VCC Q0 /Q0 VCC 32 31 30 29 28 27 26 25 VT0 1 IN0 2 /IN0 3 OE 4 SEL 5 IN1 6 /IN1 7 VT1 8 VREF-AC1 GND GND VCC VCC /Q4 Q4 VCC 24 23 22 21 20 19 18 17 1 5 1 4 1 3 1 2 1 1 1 0 1 1 1 2 1 3 1 4 Q1 /Q1 VCC Q2 /Q2 VCC Q3 /Q3

Functional Block Diagram

graph TD
    IN0["IN0"] -->|50Ω| NOT1["NOT"]
    V_T0["V_T0"] -->|50Ω| NOT2["NOT"]
    /IN0["/IN0"] -->|50Ω| NOT3["NOT"]
    V_REF_AC0["V_REF_AC0"] -->|50Ω| NOT4["NOT"]
    IN1["IN1"] -->|50Ω| NOT5["NOT"]
    V_T1["V_T1"] -->|50Ω| NOT6["NOT"]
    /IN1["/IN1"] -->|50Ω| NOT7["NOT"]
    V_REF_AC1["V_REF_AC1"] -->|50Ω| NOT8["NOT"]
    NOT1 --> SEL["SEL"]
    NOT2 --> SEL
    NOT3 --> SEL
    NOT4 --> SEL
    NOT5 --> SEL
    NOT6 --> SEL
    NOT7 --> SEL
    NOT8 --> SEL
    SEL --> OE["OE"]
    OE --> EnableLogic["Enable Logic"]
    EnableLogic --> Q0["Q0"]
    EnableLogic --> Q1["Q1"]
    EnableLogic --> Q2["Q2"]
    EnableLogic --> Q3["Q3"]
    EnableLogic --> Q4["Q4"]

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltage ( V_CC )....-0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

LVPECL Output Current ( I_OUT ) Continuous....50 mA Surge....100 mA

Current ( V_T ) Source or Sink on V_T Pin....±100 mA

Input Current Source or Sink Current on IN, /IN ....±50 mA

Current (VREF) Source or Sink Current on VREF-AC (Note 1).... ±0.5 mA

Operating Ratings ††

Supply Voltage ( V_CC )....+2.375V to +2.625V

† Notice: Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

†† Notice: The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

Note 1: Due to the limited drive capability, use for input of the same package only.

DC ELECTRICAL CHARACTERISTICS (Note 1)

Electrical Characteristics: T_A = -40^ to +85^ , unless otherwise stated.

Parameters Sym.	Min. Typ.	Max. Units Conditions
Power Supply V	CC	2.375 2.5	2.625 V —
Power Supply Current I	CC	— 90	130 mA No load, max. V			cc
Input Resistance (IN-to-VT)	RIN	45	50	55	Ω	—
Differential Input Resistance (IN-to-/IN)	RDIFF_IN	90	100	110	Ω	—
Input High Voltage (IN, /IN)	VIH	0.1	—	VCC	V	—
Input Low Voltage (IN, /IN)	VIL	0	—	VIH-0.1	V —
Input Voltage Swing (IN, /IN)	VIN	0.1	—	1.0	V	Note 2, See Figure 5-6
Different Input Voltage Swing |IN, /IN|	VDIFF_IN	0.2	—	2.0	V	See Figure 5-7
Input Voltage Threshold that Triggers FSI	VIN_FSI	— 30	100 mV —
Output Reference Voltage	VREF-AC	VCC-1.3	VCC-1.2	VCC-1.1	VI	VREF-AC = ±0.5 mA
Voltage from Input to VT	VT_IN	—	—	1.28	V —

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
2: V_IN(MAX) is specified when V_T is floating.

LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS (Note 1)

Electrical Characteristics: V_CC = +2.5V ± 5% , R_L = 100 across the outputs; T_A = -40^ to +85^ , unless otherwise stated.

Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
Output Voltage Swing (Q, /Q)	V_OUT	250	325	—	mV	See Figure 5-6
Differential Output Voltage Swing |Q, /Q|	V_DIFF\_OUT	500	650	—	mV	See Figure 5-7
Output Common Mode Voltage (Q, /Q)	V_OCM	1.125	1.20	1.275	V	See Figure 7-1
Change in Common Mode Voltage (Q, /Q)	V_OCM	-50	—	50	mV	See Figure 7-2

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS (Note 1)

Electrical Characteristics: V_CC = 2.5V ± 5% ; T_A = -40^ C to +85^ C , unless otherwise stated.

Parameter Symbol	Min. Typ.	Max. Units	Condition
Input High Voltage V	IH	2.0 — —	V —
Input Low Voltage V	IL	—	—	0.8	V	—
Input High Current	IH	-125 —	30 μA —
Input Low Current	IL	-300 —	— μA —	—

Note 1: The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS (Note 1)

Electrical Characteristics: V_CC = 2.5V ± 5% , R_L = 100 across the outputs, Input t_f/t_f ≤ 300 ps; T_A = -40^ to +85^ , unless otherwise stated.

Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
Maximum Operating Frequency	f_MAX	1.5	2.0	—	GHz	V_OUT ≥ 200 mV, V_IN ≥ 200 mV
		1.0	1.5	—		V_OUT ≥ 200 mV, V_IN ≥ 100 mV
Differential Propagation Delay IN-to-Q	t_pd	600	820	1100	ps	Note 2, 100 mV < V_IN ≤ 200 mV
Differential Propagation Delay IN-to-Q		500	720	1000		Note 2, IN-to-Q, 200 mV < V_IN ≤ 800 mV
Differential Propagation Delay SEL-to-Q		400	600	800		V_TH=V_CC/2
Set-Up Time OE-to-IN	t_S	300	—	—	ps	Note 3
Hold Time IN-to-OE	t_H	800	—	—	ps	Note 3
Differential Propagation Delay Temperature Coefficient	t_pd tempco	—	256	—	fs/°C	—
Output-to-Output Skew	t_SKEW	—	5	20	ps	Note 4
Input-to-Input Skew		—	5	15		Note 5
Part-to-Part Skew		—	—	300		Note 6
Clock Random Jitter	t_JITTER	—	—	1	ps_RMS	Note 7
Cycle-to-Cycle Jitter		—	—	1	ps_RMS	Note 8
Total Jitter		—	—	10	ps_PP	Note 9
Crosstalk-Induced Jitter		—	—	0.7	ps_RMS	Note 10

AC ELECTRICAL CHARACTERISTICS (CONTINUED) (Note 1)

Electrical Characteristics: V_CC = 2.5V ± 5% , R_L = 100 across the outputs, Input t_r/t_f ≤ 300 ps; T_A = -40^ to +85^ , unless otherwise stated.

Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
Output Rise/Fall Time (20% - 80%)	t_f/t_f	70 120	210 ps	At full output swing.
Duty Cycle —		47 —	53		%	V_IN >200 mV
		45 —	55 100 mV ≤ V			_IN ≤ 200 mV

Note 1: High-frequency AC parameters are guaranteed by design and characterization.
2: Propagation delay is measured with input t_r , t_f ≤ 300 ps (20% to 80%). The propagation delay is a function of the rise and fall times at IN. See Typical Performance Curves for details. t_pd varies with input t_r/t_f .
3: Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply.
4: Output-to-Output skew is measured between two different outputs under identical transitions.
5: Input-to-Input skew is the time difference between the two inputs to one output, under identical input transitions.
6: Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
7: Random Jitter is measured with a K28.7 character pattern, measured at <f_MAX .
8: Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, T_n - T_n-1 where T is the time between rising edges of the output signal.
9: Total Jitter definition: with an ideal clock input of frequency <f_MAX no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
10: Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs.

TEMPERATURE SPECIFICATIONS

Parameters	Sym.	Min.	Typ.	Max.	Units	Conditions
Temperature Ranges
Operating Ambient Temperature Range	T_A	-40 —	+85 °C		—
Maximum Operating Junction Temperature	T_J	—	—	+125	°C	—
Lead Temperature	—	—	—	+260	°C	Soldering, 20 sec.
Storage Temperature Range	T_S	-65 —	+150 °C		—
Package Thermal Resistances (Note 1)
Thermal Resistance, 5x5 QFN-32Ld	_JA	—	50	—	°C/W	Still-air
	_JB	—	31	—	°C/W	Junction-to-board

Note 1: Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA values are determined for a 4-layer board in still-air number, unless otherwise stated.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

V_CC = 2.5V , GND = 0V, t_f/t_f ≤ 300 ps, V_IN = 100 mV, R_L = 100 across the outputs, T_A = +25^ C , unless otherwise stated.

FIGURE 2-1: Frequency Response.

FIGURE 2-4: Propagation Delay vs. Input Rise/Fall Time.

FIGURE 2-2: Propagation Delay vs. Input Rise/Fall Time.

FIGURE 2-5: Propagation Delay vs. Input Rise/Fall Time.

FIGURE 2-3: Propagation Delay vs. Input Rise/Fall Time.

V_CC = 2.5V , GND = 0V, V_IN = 250 mV, R_L = 100 across the outputs, T_A = +25^ , unless otherwise stated.

FIGURE 2-6: 200 MHz Clock.

FIGURE 2-9: 1.5 GHz Clock.

FIGURE 2-7: 500 MHz Clock.

FIGURE 2-8: 1 GHz Clock.

3.0 ADDITIVE PHASE NOISE PLOT

Additive jitter is defined as the RMS Jitter of the device added to the input signal and is calculated in Equation 3-1.

EQUATION 3-1:

DeviceAdditiveJitter OutputRMSJitter ^2 -InputRMSJitter ^2

FIGURE 3-1: Integrated Phase Noise Plot of SY89847U (Device) and the Source (Input Signal).

From the plot shown in Figure 3-1, the device additive jitter can be calculated as follows.

EQUATION 3-2:

CalculatedAdditiveJitter93.23 ^2 -92384s=

4.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 4-1.

TABLE 4-1: PIN FUNCTION TABLE

Pin Number Symbol Description
1, 8 VT0, VT1		Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin. The VT pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility. See the Input Interface Applications section.
2, 36, 7	IN0, /IN0IN1, /IN1	Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100 mV. The input pairs internally terminate to a VT pin through 50Ω. Each input has level shifting resistors of 3.72 kΩ to VCC. This allows a wide input voltage range from VCC to GND. See Figure 5-8, Simplified Differential Input Stage for details. Note that these inputs will default to a valid (either high or low) state if left open. See the Input Interface Applications section.
10, 11, 30, 31	GND, Exposed Pad	Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pins.
4	OE	Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q4 outputs. It is internally connected to a 25 kΩ pull-up resistor and will default to a logic high state if left open. When disabled, Q goes low and /Q goes high. OE being synchronous, outputs will be enabled/disabled following a rising and a falling edge of the input clock. V_TH = V_CC/2 .
5 SEL		Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25 kΩ pull-up resistor and will default to logic high state if left open. V_TH = V_CC/2 .
9, 32	VREF-AC1VREF-AC0	Reference Voltage: These outputs bias to V_CC - 1.2V . They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01 μF low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ±0.5 mA. See the Input Interface Applications section.
12, 13, 16, 19, 22, 25, 28, 29	VCC	Positive Power Supply: Bypass with 0.1 μF||0.01 μF low ESR capacitors as close to the VCC pins as possible.
27, 2624, 2321, 2018, 1715, 14	Q0, /Q0Q1, /Q1Q2, /Q2Q3, /Q3Q4, /Q4	LVDS Differential Output Pairs: Differential copies of the selected input signal. The output swing is typically 325 mV. Used and unused outputs must be terminated with 100Ω across the pair (Q, /Q). These differential LVDS outputs are a logic function of the IN0, IN1, and SEL inputs. See Table 4-2.

TABLE 4-2: TRUTH TABLE

Inputs Outputs
I	N	0 /	I	N	0	I
0	1	X	X	0	0	1
1	0	X	X	0	1	0
X	X	0	1	1	0	1
X	X	1	0	1	1	0

N

5.0 FUNCTIONAL DESCRIPTION

5.1 Clock Select (SEL)

SEL is an asynchronous TTL/CMOS compatible input that selects one of the two input signals. Internal 25 kΩ pull-up resistor defaults the input to logic high if left open. Input switching threshold is V_CC/2 . Refer to Figure 5-1.

5.2 Output Enable (OE)

OE is a synchronous TTL/CMOS compatible input that enables/disables the outputs based on the input to this pin. The enable function is synchronous so that the clock outputs will be enabled or disabled following a rising and a falling edge of the input clock. Refer to Figure 5-2. Internal 25 kΩ pull-up resistor defaults the input to logic high if left open. Input switching threshold is V_CC/2 .

5.3 Fail-Safe Input (FSI)

The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100 mV_PK(200 mV_PP) , typically 30 mV_PK . Refer to Figure 5-4.

5.4 Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low signal swing such that the voltage swing across the input pair is significantly less than 100 mV, FSI function will eliminate a metastable condition and latch the outputs to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a typical swing greater than 30 mV.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to the Typical Performance Curves for detailed information.

Timing Diagrams

SEL Vcc/2 Vcc/2 tpd tpd Q /Q

FIGURE 5-1: SEL-to-Q Delay.

Disabled Enabled IN OE /Q Q

FIGURE 5-2: Enable Output Timing Diagram.

/IN IN t_pd /Q Q V_IN t_pd V_OUT

FIGURE 5-3: Propagation Delay.

FIGURE 5-4: Fail-Safe Feature.

OE Vcc/2 Vcc/2 IN /tS tH /IN

FIGURE 5-5: Setup and Hold Time.

Single-Ended and Differential Swings

V_IN, V_OUT 325mV (typ.)

FIGURE 5-6: Single-Ended Voltage Swing.

650mV (typ.) VDIFF_IN, VDIFF_OUT

FIGURE 5-7: Differential Voltage Swing.

Input Stage

VCC 1.86kΩ 1.86kΩ 1.86kΩ IN 50Ω VT 50Ω /IN GND

FIGURE 5-8: Simplified Differential Input Stage.

6.0 INPUT INTERFACE APPLICATIONS

VCC LVPECL GND VCC 0.1μF 19Ω IN /IN VT NC VREF-AC SY89847U

FIGURE 6-1: LVPECL Interface (DC-Coupled).

VCC CML GND IN /IN VCC 0.1μF VT VREF-AC SY89847U

FIGURE 6-4: CML Interface (AC-Coupled).

VCC LVPECL 50Ω 50Ω GND GND VCC 0.1μF IN IN SY89847U VT VREF-AC

FIGURE 6-2: LVPECL Interface (AC-Coupled).

VCC LVDS IN /IN SY89847U GND NC□ VT NC□ VREF-AC

FIGURE 6-5: LVDS Interface (DC-Coupled).

VCC CML IN /IN SY89847U GND NC□ VT NC□ VREF-AC

FIGURE 6-3: CML Interface (DC-Coupled).

7.0 LVDS OUTPUT INTERFACE APPLICATIONS

LVDS specifies a small swing of 325 mV, typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in the ground between and LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low.

100Ω VOUT VOH, VOL VOH, VOL GND

FIGURE 7-1: LVDS Differential Measurement.

50Ω 50Ω VOCM ΔVOCM GND

FIGURE 7-2: LVDS Common Mode Measurement.

8.0 PACKAGING INFORMATION

8.1 Package Marking Information

32-Pin QFN*

XXXXXXXXX WWNNN XXX

Example

SY89847U 28892 USA

Legend: XX...X Product code or customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

ePb-free JEDEC ^® designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

•, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark).

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo.

Underbar (_) and/or Overbar (−) symbol may not be to scale.

32-Lead 5 mm x 5 mm QFN Package Outline and Recommended Land Pattern

TITLE

32 LEAD QFN 5x5mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING #	QFN55-32LD-PL-5	UNIT	MM
LEAD FRAME	NiPdAu	LEAD FINISH	NiPdAu

PN 1 DOT BY MARKING 32 D 1 2 E eee

TOP VIEW

D bbb ddd e 32 PIN #1 ID R0.20 E2 1 2 L D2

BOTTOM VIEW

	DIMENSION IN mm
SYMBOL	MIN	NOM	MAX
A	0.80	0.85	1.00
A1	0.00	0.02	0.05
A3	0.20 (REF)
D	5.00 BSC
D2	3.00	3.10	3.20
E	5.00 BSC
E2	3.00	3.10	3.20
L	0.35	0.40	0.45

SIDE VIEW

0.50±0.02 0.2±0.01 3.40±0.02 4.20±0.03 755 0.50 BSC

RECOMMENDED LAND PATTERN NOTE 10.12

	b (mm)			ø (mm)
N	MIN	NOM	MAX	MIN	NOM	MAX
32	0.18	0.25	0.30	0.50 BSC

TOLERANCE OF FORM AND POSITION
coa	0.15
bbb	0.10
ccc	0.10
ddd	0.05
eee	0.08

NOTE:

1. REFER TO JEDEC STANDARD MO-220 VHHD-2.

2. DIMENSION "6" APPLIES TO METALIZED TERMINAL AND IS MEASURED

BETWEEN 0.15mm TO 0.30mm FROM THE TERMINAL TIP.

1. "aaa" THE BILATERAL PROFILE TOLERANCE THAT CONTROLS THE POSITION OF THE PLASTIC BODY SIDES.

THE CENTERS OF THE PROFILE ZONES ARE DEFINED BY THE BASIC DIMENSIONS "D" AND "E".

1. "bob" THE TOLERANCE THAT CONTROLS THE POSITION OF THE ENTIRE TERMINAL PATTERN WITH RESPECT TO DATUM'S A AND B. THE

CENTER OF THE TOL FRANCE ZONE OF EACH TERMINAL IS DEFINED BY THE BASIC DIMENSION "p" AS RELATED TO DATUM A AND B

S. 'eee' THE TOLERANCE LOCATED PARALLEL TO THE SEATING PLANE IN WHICH THE TOP SURFACE OF THE PACKAGE MUST BE LOCATED

A 'www' THE TOI FRANCE THAT CONTROLS THE POSITION OF THE TERMINALS TO EACH OTHER. THE CENTERS OF THE PROFILE ZONE ARE

DEFINED BY BASIC DIMENSION "e".

1. 'pee' THE UNILATERAL TOLERANCE LOCATED ABOVE THE SEATING PLANE WHEREIN THE BOTTOM SURFACE OF THE TERMINALS MUST BE LOCATED.

2. THE TOLERANCE THAT CONTROLS THE POSITION OF THE EXPOSED METAL HEAT FEATURE. THE CENTER OF THE TOLERANCE ZONE WILL BE

THE DATUM'S DEFINED BY THE CENTERLINES OF THE PACKAGE BODY.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.

NOTES:

APPENDIX A: REVISION HISTORY

Revision A (October 2018)

• Converted Micrel document SY89847U to Microchip data sheet template DS20006101A.
• Minor text changes throughout.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

PART NO. X Device Input Voltage X Package Temperature Range -XX Tape and Reel

Device:

SY89847: 1.5 GHz Precision, LVDS 1:5 Fanout Buffer

with 2:1 MUX and Fail-Safe Input with Internal Termination

Input Voltage: U = 2.5V/3.3V

Package: M = 5 mm x 5 mm QFN-32

Temperature Range:

G = -40°C to 85°C (NiPdAu Lead-Free)

Special Processing:

= 60/Tube

TR = 1,000/Reel

Examples:

a) SY89847UMG: SY89847, 2.5V/3.3V Input

Voltage, 5 mm x 5 mm 32-Lead

QFN, -40^ to +85^

Temperature Range, 60/Tube

b) SY89847UMG-TR: SY89847, 2.5V/3.3V Input

Voltage, 5 mm x 5 mm 32-Lead

QFN, -40^ to +85^

Temperature Range, 1,000/Reel

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELQQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949=

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3837-3

Worldwide Sales and Service

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: [phone]

Fax: [phone]

Technical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: [phone]

Fax: [phone]

Austin, TX

Tel: [phone]

Boston

Westborough, MA

Tel: [phone]

Fax: [phone]

Chicago

Itasca, IL

Tel: [phone]

Fax: [phone]

Dallas

Addison, TX

Tel: [phone]

Fax: [phone]

Detroit

Novi, MI

Tel: [phone]

Houston, TX

Tel: [phone]

Indianapolis

Noblesville, IN

Tel: [phone]

Fax: [phone]

Tel: [phone]

Los Angeles

Mission Viejo, CA

Tel: [phone]

Fax: [phone]

Tel: [phone]

Raleigh, NC

Tel: [phone]

New York, NY

Tel: [phone]

San Jose, CA

Tel: [phone]

Tel: [phone]

Canada - Toronto

Tel: [phone]

Fax: [phone]

ASIA/PACIFIC

Australia - Sydney

Tel: [phone]

China - Beijing

Tel: [phone]

China - Chengdu

Tel: [phone]

China - Chongqing

Tel: [phone]

China - Dongguan

Tel: [phone]

China - Guangzhou

Tel: [phone]

China - Hangzhou

Tel: [phone]

China - Hong Kong SAR

Tel: [phone]

China - Nanjing

Tel: [phone]

China - Qingdao

Tel: [phone]

China - Shanghai

Tel: [phone]

China - Shenyang

Tel: [phone]

China - Shenzhen

Tel: [phone]

China - Suzhou

Tel: [phone]

China - Wuhan

Tel: [phone]

China - Xian

Tel: [phone]

China - Xiamen

Tel: [phone]

China - Zhuhai

Tel: [phone]

ASIA/PACIFIC

India - Bangalore

Tel: [phone]

India - New Delhi

Tel: [phone]

India - Pune

Tel: [phone]

Japan - Osaka

Tel: [phone]

Japan - Tokyo

Tel: [phone]

Korea - Daegu

Tel: [phone]

Korea - Seoul

Tel: [phone]

Malaysia - Kuala Lumpur

Tel: [phone]

Malaysia - Penang

Tel: [phone]

Philippines - Manila

Tel: [phone]

Singapore

Tel: [phone]

Taiwan - Hsin Chu

Tel: [phone]

Taiwan - Kaohsiung

Tel: [phone]

Taiwan - Taipei

Tel: [phone]

Thailand - Bangkok

Tel: [phone]

Tel: [phone]

Fax: [phone]

Denmark - Copenhagen

Tel: [phone]

Fax: [phone]

Finland - Espoo

Tel: [phone]

France - Paris

Tel: [phone]

Fax: [phone]

Germany - Garching

Tel: [phone]

Germany - Haan

Tel: [phone]

Germany - Heilbronn

Tel: [phone]

Germany - Karlsruhe

Tel: [phone]

Germany - Munich

Tel: [phone]

Fax: [phone]

Germany - Rosenheim

Tel: [phone]

Israel - Ra'anana

Tel: [phone]

Italy - Milan

Tel: [phone]

Fax: [phone]

Italy - Padova

Tel: [phone]

Netherlands - Drunen

Tel: [phone]

Fax: [phone]

Norway - Trondheim

Tel: [phone]

Poland - Warsaw

Tel: [phone]

Romania - Bucharest

Tel: [phone]

Spain - Madrid

Tel: [phone]

Fax: [phone]

Sweden - Gothenberg

Tel: [phone]

Sweden - Stockholm

Tel: [phone]

UK - Wokingham

Tel: [phone]

Fax: [phone]