SY89464U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY89464U Microchip

The SY89464U is a low jitter 1:10 LVPECL fanout buffer with a 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike standard multiplexers, the SY89464U's unique 2:1 Runt Pulse Eliminator (RPE) MUX prevents any short cycles or "runt" pulses during switchover. In addition, a unique Fail-Safe Input (FSI) protection prevents metastable output conditions when the selected input clock fails to a DC voltage (voltage between the pins of the differential input drops below 100mV).

The differential input includes Micrel's unique, 3-pin internal termination architecture that allows customers to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mV PP) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K-compatible LVPECL with fast rise/fall times guaranteed to be less than 220ps.

The SY89464U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89464U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at: www.micrel.com.

Precision Edge®

Features

• Selects between two sources, and provides 10 precision LVPECL copies

• Guaranteed AC performance over temperature and supply voltage:

• Wide operating frequency: 1kHz to >1.5GHz

• < 1100ps In-to-Out t pd

• < 2 20ps t_r/t_f

• Unique, patent-pending MUX input isolation design minimizes adjacent channel crosstalk
  • Fail-Safe Input prevents oscillations
  • Ultra-low jitter design:

• < 1 ps _RMS random jitter

• <1psRMS cycle-to-cycle jitter
• <10psPP total jitter (clock)
• < 0.7ps_RMS MUX crosstalk induced jitter

- Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)

• 800mV LVPECL output
• 2.5V ±5% or 3.3V ±10% supply voltage
- Output enable
- -40°C to +85°C industrial temperature range
• Available in 44-pin (7mm x 7mm) QFN package

Applications

• Redundant clock switchover
- Fail-safe clock protection

Markets

• LAN/WAN
- Enterprise servers
- ATE
• Test and measurement

Precision Edge is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Typical Application

graph TD
    subgraph_Primary_Clock_From_System["Primary Clock From System"]
        IN0["IN0"] --> MUX["2:1 MUX"]
        VT0["VT0"] --> MUX
        /IN0["/IN0"] --> MUX
        VREF_AC0["VREF-AC0"] --> MUX
        IN1["IN1"] --> MUX
        VT1["VT1"] --> MUX
        /IN1["/IN1"] --> MUX
        VREF_AC1["VREF-AC1"] --> MUX
    end
    subgraph_Secondary_Clock_From_Local_Oscillator["Secondary Clock From Local Oscillator"]
        IN0 --> MUX
        VT0 --> MUX
        /IN0 --> MUX
        VREF_AC0 --> MUX
        IN1 --> MUX
        VT1 --> MUX
        /IN1 --> MUX
        VREF_AC1 --> MUX
    end
    MUX --> Q0_Q9["Q0-Q9"]
    MUX --> Q0_Q9_bar["/Q0-/Q9"]
    MUX --> EN_TTL_CMOS["EN (TTL/CMOS)"]
    MUX --> D_Q["D Q"]
    MUX --> SEL_LVTTL_CMOS["SEL (LVTTL/CMOS)"]
    SEL_LVTTL_CMOS --> Runt_Pulse_Elimination_Logic["Runt Pulse Elimination Logic"]

Primary Clock Secondary Clock SEL Select Primary Select Secondary OUTPUT Runt pulse eliminated from output Switchover occurs

Simplified Example Illustrating Runt Pulse Eliminator (RPE) when Primary Clock Fails

Ordering Information ^(1)

Part Number Package Type	Operating Range	Package Marking Lead	Finish
SY89464UMY	QFN-44	Industrial	SY89464U with Pb-Free bar-line Indicator
SY89464UMYTR(2)	QFN-44	Industrial	SY89464U with Pb-Free bar-line Indicator

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC Electricals Only.
2. Tape and Reel.

Pin Configuration

VCC VCC SEL VCC Q0/Q0 /Q1/Q1 /Q2/Q2 /VCC GND 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 VCC IN0 VT0 VREF-AC0 /IN0 GND IN1 VT1 VREF-AC1 /IN1 GND 33 32 31 30 29 28 27 26 25 24 23 CAP VCC EN VCC /Q9 Q9 /Q8 Q8 Q7 Q7 VCC

44-Pin QFN

Pin Description

Pin Number	Pin Name	Pin Function
2, 57, 10	IN0, /IN0IN1, /IN1	Differential Inputs: These input pairs are the differential signal inputs to the device. These inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin of a pair internally terminates to a VT pin through 50Ω. Please refer to the “Input Interface Applications” section for more details.
4, 9	VREF-AC0VREF-AC1	Reference Voltage: These outputs bias to VCC-1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01μF low ESR capacitor to VCC. Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is ±1.5mA. Please refer to the “Input Interface Applications” section for more details.
3, 8 VT0, VT1		Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT0 and VT1 pins provide a center-tap to a termination network for maximum interface flexibility. Please refer to the “Input Interface Applications” section for more details.
13, 15, 22, 23, 2833, 34, 41, 43, 44	VCC	Positive Power Supply: Bypass with 0.1μF||0.01μF low ESR capacitors as close to the VCC pins as possible.
40, 3938, 3736, 3532, 3130, 2927, 2625, 2421, 2019, 1817, 16	Q0, /Q0Q1, /Q1Q2, /Q2Q3, /Q3Q4, /Q4Q5, /Q5Q6, /Q6Q7, /Q7Q8, /Q8Q9, /Q9	Differential Outputs: These differential LVPECL outputs are a logic function of the IN0, IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
42 SEL		This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state if left open. VTH= VCC/2.
1, 6, 11	GND, Exposed Pad	Ground: Ground and exposed pad must be connected to the same ground plane.
12 CAP		Power-On Reset (POR) initialization capacitor. When using the multiplexer with RPE capability, this pin is tied to a capacitor to VCC. The purpose is to ensure the internal RPE logic starts up in a known state. See “Power-On Reset (POR) Description” section for more details regarding capacitor selection. If this pin is tied directly to VCC, the RPE function will be disabled and the multiplexer will function as a normal multiplexer. The CAP pin should never be left open or tied directly to GND.
14 EN		Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9 outputs. It is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. When disabled, CLK output goes LOW and /CLK goes HIGH. EN being synchronous, outputs will be enabled/disabled when they are in LOW state. Thus, a runt pulse is avoided if the device is enable/disabled by an asynchronous control. VTH= VCC/2.

Truth Table

Inputs Outputs
IN0	/IN0	IN1	/IN1	SEL	Q	/Q
0 1	X	X	0	0 1
1 0	X	X	0	1 0
X	X	0	1	1	0	1
X	X	1	0	1	1	0

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc ) ....-0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

LVPECL Output Current (IOUT) ....

Continuous....50mA Surge....100mA

Input Current ( I_IN ) ....

IN, /IN .... ±50mA V_T .... ±100mA

V_REF-AC Current Source/Sink Current on V REF-AC ....±2mA

Lead Temperature (soldering, 20 sec.) .....+260°C

Storage Temperature ( T_s )....-65°C to 150°C

Operating Ratings ^(2)

Supply Voltage (V _CC )...... +2.375V to +2.625V ......+3.0V to +3.6V

Ambient Temperature ( T_A )....-40°C to +85°C

Package Thermal Resistance ^(3)

QFN ( _JA ) Still-Air 24.4°C/W

QFN ( _JB ) Junction-to-Board 8.1°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_CC	Power Supply		2.375	2.5	2.625	V
			3.0	3.3	3.6	V
I_CC	Power Supply Current	No load, max V_CC		120	160	mA
R_IN	Input Resistance (IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input High Voltage (IN, /IN)		1.2		V_CC	V
V_IL	Input Low Voltage (IN, /IN)		0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	See Figure 1a. Note 5.	0.1		2.5	V
V_DIFF\_IN	Differential Input Voltage Swing |IN-/IN|	See Figure 1b.	0.2			V
V_IN\_FSI	Input Voltage Threshold that Triggers FSI			30	100	mV
V_T\_IN	IN-to- V_T (IN, /IN)				1.28	V
V_REF-AC	Output Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. _JA and _JB values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IN (max) is specified when V_T is floating.

LVPECL Outputs DC Electrical Characteristics ^(6)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 50 to V_CC - 2V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH Output	HIGH VoltageQ, /Q		V_CC-1.145	V	_CC-0.895	V
V_OL	Output LOW VoltageQ, /Q		V_CC-1.945	V	_CC-1.695
V_OUT	Output Voltage SwingQ, /Q	See Figure 1a.	550	800		mV
V_DIFF\_OUT	Differential Output Voltage SwingQ, /Q	See Figure 1b.	1100	1600		mV

LVTTL/CMOS DC Electrical Characteristics ^(6)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		30	μA
I_IL	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics ^(7)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 50 to V_CC - 2V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX Maximum Operating Frequency V		OUT ≥ 400mV	1.5	2.0		GHz
t_pd	Differential Propagation Delay In-to-Q	100mV < V_IN ≤ 200mV^(8)	550	800	1150	ps
	In-to-Q	200mV < V_IN ≤ 800mV^(8)	500	750	1100	ps
	SEL-to-Q	RPE enabled, see Timing Diagram			17	cycles
	SEL-to-Q	RPE disabled ( V_SEL = V_CO/2 )	600		1200	ps
t_pd Tempco	Differential Propagation Delay Temperature Coefficient			500		fs/°C
t_S EN	Set-up Time EN-to-CLK	Note 9	0			ps
t_H EN	Hold Time CLK-to-EN	Note 9	650			ps
t_SKEW	Output-to-Output Skew	Note 10		5	25	ps
	Part-to-Part Skew	Note 11			300	ps
t_JITTER	Clock Random Jitter	Note 12			1	p s_RMS
	Cycle-to-Cycle Jitter	Note 13			1	p s_RMS
	Total Jitter	Note 14			10	p s_PP
	Crosstalk-Induced Jitter	Note 15			0.7	p s_RMS
t_r, t_f	Output Rise/Fall Time (20% to 80%)	At full output swing.	70		220	ps

Notes:

1. High-frequency AC-parameters are guaranteed by design and characterization.
2. Propagation delay is measured with input t_f , t_f ≤ 300ps (20% to 80%) and V_IL ≥ 800mV . The propagation delay is function of the rise and fall times at IN. See “Typical Operating Characteristics” for details.
3. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply.
4. Output-to-Output skew is measured between two different outputs under identical transitions.
5. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
6. Random Jitter is measured with a K28.7 character pattern, measured at <f_MAX .
7. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, T_n - T_n-1 where T is the time between rising edges of the output signal.
8. Total Jitter definition: with an ideal clock input of frequency < f_MAX , no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
9. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs.

Functional Description

RPE MUX and Fail-Safe Input

The SY89464U is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. It features two unique circuits:

Runt-Pulse Eliminator (RPE) Circuit

The RPE MUX provides a “glitchless” switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. The design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pairs, IN0 or IN1. Thus, either input pair may be defined as the primary input). If not required, the RPE function can be permanently disabled to allow the switchover between inputs to occur immediately. If the CAP pin is tied directly to V_cc , the RPE function will be disabled and the multiplexer will function as a normal multiplexer.

Fail-Safe Input (FSI) Circuit

The FSI function provides protection against a selected input pair that drops below the minimum amplitude requirement. If the selected input pair drops sufficiently below the 100mV minimum single-ended input amplitude limit ( V_IN ), or 200mV differentially ( V_DIFF IN ), then the output will latch to the last valid clock state.

RPE and FSI Functionality

The basic operation of the RPE MUX and FSI functionality is described with the following four case descriptions. All descriptions are related to the true inputs and outputs. The primary (or selected) clock is called CLK1; the secondary (or alternate) clock is called CLK2. Due to the totally asynchronous relation of the IN and SEL signals, and an additional internal protection against metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. Refer to "Timing Diagrams" section for detailed information.

Case #1: Two Normal Clocks and RPE-Enabled

In this case, the frequency difference between the two running clocks, IN0 and IN1, must not be greater than 1.5:1. For example, if the IN0 clock is 500MHz, the IN1 clock must be within the range of 334MHz to 750MHz.

If the SEL input changes state to select the alternate clock, the switchover from CLK1 to CLK2 will occur in three stages.

• Stage 1: The output will continue to follow CLK1 for a limited number of pulses.
• Stage 2: The output will remain LOW for a limited number of pulses of CLK2.
  • Stage 3: The output follows CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Runt pulse eliminated from output Stage 1 Select CLK1 Stage 2 Select CLK2 Stage 3 3 to 5 falling edges of CLK1 4 to 5 falling edges of CLK2

Timing Diagram 1

Case #2: Input Clock Failure: Switching from a selected clock stuck HIGH to a valid clock (RPE-enabled).

If CLK1 fails HIGH before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in three stages.

- Stage 1: The output will remain HIGH for a limited number of pulses of CLK2.

- Stage 2: The output will switch to LOW and then remain LOW for a limited number of falling edges of CLK2.

• Stage 3: The output will follow CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Runt pulse eliminated from output Stage 1 Stage 2 Stage 3 Select CLK2 14 to 16 falling edges of CLK2

Timing Diagram 2

Note: Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2 period.

Case #3: Input Clock Failure: Switching from a selected clock stuck Low to a valid clock (RPE-enabled).

If CLK1 fails LOW before the RPE MUX selects CLK2 (using the SEL pin), the switchover will occur in two stages.

- Stage 1: The output will remain LOW for a limited number of falling edges of CLK2.

• Stage 2: The output will follow CLK2.

CLK1 CLK2 SEL Select CLK1 OUTPUT Stage 1 Select CLK2 13 to 17 falling edges of CLK2 Stage 2

Timing Diagram 3

Case #4: Input Clock Failure: Switching from the selected clock input stuck in an undetermined state to a valid clock input (RPE-enabled).

If CLK1 fails to an undetermined state (e.g., amplitude falls below the 100mV ( V_IN ) minimum single-ended input limit, or 200mV differentially) before the RPE MUX selects CLK2 (using the SEL pin), the switchover to the valid clock CLK2 will occur either following Case #2 or Case #3, depending upon the last valid state at the CLK1.

If the selected input clock fails to a floating, static, or extremely low signal swing, including 0mV, the FSI function will eliminate any metastable condition and guarantee a stable output signal. No ringing and no undetermined state will occur at the output under these conditions.

Please note that the FSI function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend upon rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information.

CLK1 CLK2 SEL Select CLK1 Select CLK2 OUTPUT as in case #2 as in case #3

Timing Diagram 4

Enable Output (EN) Description

The enable function is synchronous so that the outputs will be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt pulse when the device is enabled/disabled as can happen with asynchronous control.

Disable Output(s):

1. EN toggles from High-to-Low
2. Output(s) follow the selected Clock input
3. Output (CLK) goes to a logic LOW level (/CLK goes to a logic HIGH), after next High-to-Low transition of the selected input. See Timing Diagram 5.

Enable Output(s):

1. EN toggles from Low-to-High.
2. Output(s) follow the selected clock after next HIGH-to-LOW transition of the selected input. See "Timing Diagram 5."

EN Vcc/2 Vcc/2 /CLK ts th CLK /Q Q

Timing Diagram 5

Power-On Reset (POR) Description

The SY89464U includes an internal power-on reset (POR) function to ensure the RPE logic starts-up in a known logic state once the power-supply voltage is stable. An external capacitor connected between V_cc and the CAP pin (pin 12) controls the delay for the power-on reset function.

The required capacitor value calculation is based upon the time the system power supply needs to power up to a minimum of 2.3V. The time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3V.

The following formula describes this relationship:

$$ C (\mu F) \geq \frac {t _ {d P S} (m s)}{1 2 (m s / \mu F)} $$

As an example, if the time required for the system power supply to power up past 2.3V is 12ms, then the required capacitor value on pin 12 would be:

$$ C (\mu F) \geq \frac {1 2 m s}{1 2 (m s / \mu F)} $$

$$ \mathrm{C} (\mu \mathrm{F}) \geq 1 \mu \mathrm{F} $$

Typical Operating Characteristics

V_cc = 3.3V, GND = 0V, t / t ≤ 300ps, R_L = 50 to V_cc-2V; T_A = 25^ C, unless otherwise stated.

Functional Characteristics

V_cc = 2.5V, GND = 0V, V_IN ≥ 400mV_pk, t_r/t_f ≤ 300ps, R_L = 50 to V_cc-2V; T_A = 25^, unless otherwise stated.

Single-Ended and Differential Swings

V_IN, V_OUT 800mV (typical)

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN, VDIFF_OUT 1600mV (typical)

Figure 1b. Differential Voltage Swing

Input and Output Stages

VCC IN 50Ω VT 50Ω /IN GND

Figure 2a. Simplified Differential Input Stage

VCC I/Q Q

Figure 2b. Simplified Differential Output Stage

Input Interface Applications

VCC LVPECL GND VCC 0.01μF Rpd GND IN /IN VT VREF-AC NC SY89464U For VCC = 3.3V, Rpd = 50Ω. For VCC = 2.5V, Rpd = 19Ω.

Figure 3a. LVPECL Interface (DC-Coupled)

VCC LVFECL IN IN SY89464U Rpd Rp GND GND VCC VT VREF-AC 0.01μF For VCC = 3.3V, Rpd = 100Ω. For VCC = 2.5V, Rpd = 50Ω.

Figure 3b. LVPECL Interface (AC-Coupled)

VCC CML IN /IN SY89464U GND NC □ VT NC □ VREF-AC Option: may connect Vr to Vcc

Figure 3c. CML Interface (DC-Coupled)

VCC CML GND VCC 0.01μF IN /IN VT VREF-AC SY89464U

Figure 3d. CML Interface (AC-Coupled)

VCC LVDS IN IN GND SY89464U NC □ VT NC □ VREF-AC

Figure 3e. LVDS Interface (DC-Coupled)

PECL Output Interface Applications

PECL has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low EMI. PECL is ideal for driving 50Ω- and 100Ω-controlled impedance transmission lines. There are several techniques for terminating the PECL output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and AC-coupled termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.

+3.3V ZD = 50Ω ZO = 50Ω For +2.5V systems, R1 = 250Ω, R2 = 62.5Ω +3.3V R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω VT = VCC -2V

Figure 4a. Parallel Termination-Thevenin Equivalent

+3.3V Z = 50Ω Z = 50Ω "source" 50Ω 50Ω Rb +3.3V "destination" VCC C1 (optional) 0.01μF Notes:

1. Power-saving alternative to Thevenin termination.
2. Place termination resistors as close to destination inputs as possible.
3. R_D resistor sets the DC bias voltage, equal to V_T
4. For 2.5V systems, R_b = 19 , For 3.3V systems, R_b = 50

Figure 4b. Parallel Termination (3-Resistor)
Related Product and Support Documentation

Part Number	Function	Data Sheet Link
SY89465U	Precision LVDS Runt Pulse Eliminator 2 :1 MUX with 1:10 Fanout Buffer and Internal Termination	www.micrel.com/product-info/products/sy89465u.shtml.
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

44-Pin QFN

NOTES :

1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M. - 1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS, 0 IS IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

△ DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP, IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA

△ND AND NE PETER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY

1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL [phone] FAX [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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