SY54020R - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY54020R Microchip

The SY54020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable (/EN) and Fail-Safe Input (FSI). The Enable is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. When this device is used as a clock fanout, disabling the downstream clock may reduce system power. FSI is a special circuit designed to sense the amplitude of the input signal and to latch the output when an invalid or no signal is present at the input. The SY54020R can process clock signals up to 2.5 GHz or data patterns up to 3.2Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals as small as 100mV (200mV pp ) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an internal voltage reference is provided to bias the V T pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 100ps.

The SY54020R operates from a 2.5V ±5% core supply and a 1.2V, 1.8V or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range (-40°C to +85°C).

Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com.

Functional Block Diagram

graph TD
    IN["IN"] --> A["NOT"]
    VT["VT"] --> A
    /IN["/IN"] --> A
    A --> B["D Flip-Flop 1"]
    A --> C["D Flip-Flop 2"]
    B --> D["Output Q0"]
    B --> E["Output Q1"]
    B --> F["Output Q2"]
    C --> G["Output Q3"]
    C --> H["Output Q4"]
    I["EN (TTL/CMOS)"] --> J["D Flip-Flop 1"]
    I --> K["D Flip-Flop 2"]
    J --> L["Q0"]
    J --> M["Q1"]
    J --> N["Q2"]
    J --> O["Q3"]
    K --> P["Q0"]
    K --> Q["Q1"]
    K --> R["Q2"]
    K --> S["Q3"]

Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology.

Precision Edge®

Features

• 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with FSI
• Active-low Enable (/EN) input to disable the outputs
• Guaranteed AC performance over temperature and voltage:
- DC-to > 3.2Gbps Data throughput
- DC-to > 2.5GHz Clock throughput
- <400 ps propagation delay (IN-to-Q)
- <20ps within-device skew
- <100 ps rise/fall times

- Ultra-low jitter design

- < 1 ps_RMS cycle-to-cycle jitter

• High-speed CML outputs

- 2.5V ±5% V CC , 1.2/1.8V/2.5V ±5% V CCO power supply operation

- Industrial temperature range: -40^ to +85^

• Available in 16-pin (3mm x 3mm) MLF® package

Applications

• SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution

Markets

• Storage
• ATE
  • Test and measurement
• Enterprise networking equipment
  • High-end servers
• Access
  • Metro area network equipment

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • http://www.micrel.com

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY54020RMG	MLF-16	Industrial	020R with Pb-Free bar-line indicator	NiPdAu Pb-Free
SY54020RMGTR(2)	MLF-16	Industrial	020R with Pb-Free bar-line indicator	NiPdAu Pb-Free

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ C , DC Electricals only
2. Tape and Reel.

Pin Configuration

VCC Q0 /Q0 VCCO VT 16 15 14 13 IN 2 /IN 3 /EN 4 12 Q1 11 /Q1 10 Q2 9 /Q2 5 6 7 8 GND /Q3 Q3 VCCO

16-Pin MLF ^® (MLF-16)

Pin Description

Pin Number Pin	Name Pin Function
2,3	IN, /IN	Differential Input: This input pair is the differential signal input to the device. It accepts differential signals as small as 100mV (200mV _PP ). Each input pin internally terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail-Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. Please refer to the “Interface Applications” section for more details.
1	VT	Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC coupling. For AC coupling, bypass VT with 0.1μF low ESR capacitor to VCC. See “Interface Applications” subsection and Figure 2a.
4	/EN	Single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. The input -switching threshold is Vcc/2. Note that this input is internally connected to a 25kΩ pull-down resistor and will default to a logic LOW state (Enabled) if left open. Outputs are disabled when /EN is high. See Figure 1b for more details.
16	VCC	Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the Vcc pin as possible. Supplies input and core circuitry.
8,13	VCCO	Output Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the VccO pin as possible. Supplies the output buffers.
5	GND, Exposed pad	Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin.
15,14	Q0, /Q0	CML Differential Output Pairs: Differential buffered copy of the input signal. The output swing is typically 380mV. See “Interface Applications” subsection for termination information.
12,11	Q1, /Q1
10,9	Q2, /Q2
7,6	Q3, /Q3

Truth Table

IN	/IN	/EN		Q
0	1		0
1	0		0
X	X		1^(1)	0 1^(1)

Note:

1. See timing diagram, Figure 1b.

Absolute Maximum Ratings ^(1)

Supply Voltage ( V_cc )....-0.5V to +3.0V

Supply Voltage ( V_CCO )....-0.5V to +2.7V

V_CC - V_CCO <1.8V

CML Output Voltage (VOUT).... 0.6V to VccO+0.5V

Current ( V_T )

Source or sink current on VT pin....±100mA

Input Current

Source or sink current on (IN, /IN)....±50mA

Maximum operating Junction Temperature .....125°C

Lead Temperature (soldering, 20sec.).....260°C

Storage Temperature ( T_s ) -65^ to +150^

Operating Ratings ^(2)

Supply Voltage ( V_cc ).....2.375V to 2.625V

(V_cc0) 1.14V to 2.625V

Ambient Temperature ( T_A ) -40^ to +85^

Package Thermal Resistance ^(3)

MLF®

Still-air ( _JA ) 75°C/W

Junction-to-board ( _JB ) 33°C/W

DC Electrical Characteristics ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter Condition	Min Typ Max	Units
V_CC	Power Supply Voltage Range	V_CC	2.375	2.5	2.625	V
		V_CCO	1.14	1.2	1.26	V
		V_CCO	1.7	1.8	1.9	V
		V_CCO	2.375	2.5	2.625	V
I_CC	Power Supply Current	Max. V_CC		42	58	mA
I_CCO	Power Supply Current	No Load. V_CCO		64	84	mA
R_IN	Input Resistance (IN-to- V_T , /IN-to- V_T )		45	50	55	Ω
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)		90	100	110	Ω
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.2		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	Min. V_IL with V_IH = 1.2V	0.2		V_IH-0.1	V
V_IH	Input HIGH Voltage (IN, /IN)	IN, /IN	1.14		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)	V_IL with V_IH = 1.14V , (1.2V-5%)	0.66		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)	see Figure 3a	0.1		1.0	V
V_DIFF\_IN	Differential Input Voltage Swing (|IN - /IN|)	see Figure 3b	0.2		2.0	V
V_T\_IN	Voltage from Input to V_T				1.28	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and 0_JA values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

CML Outputs DC Electrical Characteristics ^(5)

V_CCO = 1.14V to 1.26V, R_L = 50 to V_CCO,

V_CCO = 1.7V to 1.9V ; 2.375V to 2.625V , R_L = 50 to V_CCO or 100 across the outputs,

V_CC = 2.375V to 2.625V. T_A = -40^ to +85^, unless otherwise stated.

Symbol	Parameter Condition	Min Typ Max	Units
V_OH Output HIGH Voltage R		_L=50 to V_CCO	V_CCO-0.020	V_CCO-0.010	V_CCO	V
V_OUT Output Voltage Swing See Figure 3a 300 390 475 mV
V_DIFF\_OUT	Differential Output Voltage Swing	See Figure 3b	600	780	950	mV
R_OUT	Output Source Impedance		45	50	55

LVTTL/CMOS DC Electrical Characteristics ^(5)

V_CC = 2.5V ± 5% , T_A = -40^ C to +85^ C , unless otherwise stated.

Symbol	Parameter Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage				2.0		V_CC	V
V_IL	Input LOW Voltage						0.8	V
I_IH	Input HIGH Current	V_IH = V_CC					200	μA
I_IL	Input LOW Current	V_IL = 0V			-5	75	μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics

$$ V _ {C C O} = 1. 1 4 V \text { to } 1. 2 6 V, R _ {L} = 5 0 \Omega \text { to } V _ {C C O} $$

$$ V _ {C C O} = 1. 7 V \text { to } 1. 9 V, 2. 3 7 5 V \text { to } 2. 6 2 5 V, R _ {L} = 5 0 \Omega \text { to } V _ {C C O} \text { or } 1 0 0 \Omega \text { across the outputs. } $$

$$ V _ {C C} = 2. 3 7 5 \mathrm{V} \text { to } 2. 6 2 5 \mathrm{V}. T _ {\mathrm{A}} = - 4 0 ^ {\circ} \mathrm{C} \text { to } + 8 5 ^ {\circ} \mathrm{C}, \text { unless otherwise stated. } $$

Symbol	Parameter	Condition	Min	Typ	Max	Units
MAX	Maximum Data Rate/ Frequency			NRZ Data 3.2 Gbps f
				V_OUT>200mV clock			2.5 GHz
t_PD	Propagation Delay IN-to-Q			V_IN>200mV Note 6, Fig. 1a			200	300	400	ps
				V_IN:100mV-200mV, Note 6, Fig. 1a			240	360	490
t_S	Setup Time /EN							150		ps
t_H	Hold Time /EN							250		ps
t_SKEW	Output-to-Output skew			Note 7				5	20	ps
	Part-to-Part Skew			Note 8					75	ps
t_Jitter	Data Random Jitter			Note 9					1	p s_RMS
	Deterministic Jitter			Note 10					10	p s_PP
	Clock Cycle-to-Cycle Jitter			Note 11					1	p s_RMS
	Total Jitter			Note 12					10	p s_PP
t_R,t_F	Output Rise/Fall Times (20% to 80%)			Input <300mV			35	60	100	ps
	Duty Cycle			Differential I/O ≤2.5GHz			47		53	%

Notes:
6. Propagation delay is measured with input tr/tf ≤ 300ps (20 to 80%)
7. Output-to-Output skew is the difference in time between both outputs, receiving data from the same input, for the same temperature, voltage and transition.
8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges of the respective inputs.
9. Random jitter is measured with a K28.7 pattern, measured at ≤ f_MAX .
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2^23-1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. t_JITTER_CC = T_n - T_n+1 , where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of ≤ f_MAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.

Functional Description

Fail-Safe Input (FSI)

The input of this device has a built-in FSI circuit that senses the input amplitude and latches the output when the input signal is not present or when its amplitude drops below 100mV_PK ( 200mV_PP ), typically 30mV_PK . Maximum frequency of the SY54020R is limited by the FSI function.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely low input signal swing, the FSI function will eliminate a metastable condition and guarantee a stable output. No ringing and no undetermined state will occur at the output under these conditions.

Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal close to the FSI threshold. Due to the FSI function, the propagation delay will depend upon rise and fall time of the input signal and on its amplitude. Refer to “Typical Characteristics” for detailed information.

Interface Applications

For Input Interface Applications, see Figures 4a through 4f. For CML Output Termination, see Figures 5a through 5d.

CML Output Termination with VCCO 1.2V

For VCCO of 1.2V, Figure 5a, terminate the output with 50Ω to 1.2V, DC-coupled, not 100Ω differentially across the outputs.

If AC-coupling is used, Figure 5d, terminate into 50Ω to 1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage. Do not AC-couple with internally terminated receiver, such as 50Ω ANY-IN input. AC-coupling will offset the output voltage by 200mV and this offset voltage will be too low for proper driver operation. Any unused output pair needs to be terminated when VCCO is 1.2V, do not leave floating.

CML Output Termination with VCCO 1.8V, 2.5V

For VCCO of 1.8V and 2.5V, Figure 5a and Figure 5b, terminate with either 50Ω to VCCO or 100Ω differentially across the outputs. See Figure 5c for AC-coupling.

Input AC-Coupling

The SY54020R input can accept AC-coupling from any driver. Bypass VT with a 0.1μF low ESR capacitor to VCC, as shown in Figures 4c and 4d. VT has an internal high impedance resistor divider as shown in Figure 2a, to provide a bias voltage for AC-coupling.

Timing Diagrams

IN /IN Q /Q tpd

Figure 1a. Propagation Delay

IN /tS /tH /EN Q

Figure 1b. Output Enable/Disable Timing

Figure 1c. Fail-Safe Feature

Typical Characteristics

V_CC = 2.5V, V_CCO = 1.2V GND = 0V, V_IN = 400mV, R_L = 50 to 1.2V, T_A = 25^ , unless otherwise stated.

Functional Characteristics

V_CC = 2.5V, V_CCO = 1.2V GND = 0V, V_IN = 400mV, R_L = 50 to 1.2V, T_A = 25^ , unless otherwise stated.

Input and Output Stage

VCC 12.5K IN 50Ω VT 50Ω /IN 33K GND GND

Figure 2a. Simplified Differential Input Buffer

Vcc0 50Ω 50Ω /Q Q GND

Figure 2b. Simplified CML Output Buffer

Single-Ended and Differential Swings

V_{IN}, V_{OUT} 400mV (typical)

Figure 3a. Single-Ended Swing

VDIFF_IN, VDIFF_OUT 800mV (typical)

Figure 3b. Differential Swing

Input Interface Applications

VCC(1.8V, 2.5V) CML GND IN /IN SY54020R NC VT

Figure 4a. CML Interface (DC-Coupled, 1.8V, 2.5V)
Option: may connect V_T to V_CC

VCC(1.2V) CML VCC(1.2V) GND 0.1μF IN /IN VT SY54020R

Figure 4b. CML Interface (DC-Coupled, 1.2V)

VCC (1.8V, 2.5V, 3.3V) CML GND VCC 0.1μF IN /IN SY54020R VT

Figure 4c. CML Interface (AC-Coupled)

VCC(3.3V, 2.5V) LVPECL GND RP Rp VCC IN /IN SY54020R 0.1μF VT For 3.3V, Rp = 100Ω. For 2.5V, Rp = 50Ω.

Figure 4d. LVPECL Interface (AC-Coupled)

VCC(2.5V) LVPECL GND IN /IN VCC 0.1μF Rp VT SY54020R For 2.5V, Rp = 19Ω.

Figure 4e. LVPECL Interface (DC-Coupled)

VCC LVDS GND IN /IN SY54020R NC VT

Figure 4f. LVDS Interface

CML Output Termination

VCCO (1.2V, 1.8V, 2.5V) 50Ω 50Ω Q Z0= 50Ω IN 50Ω VCCO (1.2V, 1.8V, 2.5V) 50Ω Z0= 50Ω /IN /Q GND

Figure 5a. 1.2V, 1.8V or 2.5V CML DC-Coupled Termination

VCCO (1.8V, 2.5V) 50Ω 50Ω Q Z0 = 50Ω IN 100Ω Z0 = 50Ω /IN /Q GND

Figure 5b. 1.8V or 2.5V CML DC-Coupled Termination

VCCO (1.8V, 2.5V) 50Ω 50Ω Q Z0 = 50Ω IN 50Ω VBIAS 50Ω Z0 = 50Ω /IN /Ω GND

Figure 5c. CML AC-Coupled Termination ( V_cco 1.8V or 2.5V )

VCCO (1.2V) 50Ω 50Ω Q Zo = 50Ω 1.2V 50Ω IN 1kΩ VBias 1kΩ /IN Zo = 50Ω /Q 50Ω 1.2V GND

Figure 5d. CML AC-Coupled Termination ( V_cco 1.2V only)

Package Information

Pin 1 Dot By Marking 3.000BSC 1 2 3 3.000BSC 16

TOP VIEW

1.60±0.100 Exp. DAP 0.500 BSC CHAMFER 0.30 X 45° 1 2 1.60±0.10 Exp. DAP 0.25±0.50 0.400±0.050 1.500 Ref.

VARIATION A

R0.20 1 2

VARIATION B
BOTTOM VIEW

0.850±0.050 0.05 C SEATING PLANE 0.000-0.050 0.203±0.025

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.
DIMENSION APPLIES TO METALIZED TERMINAL AND IS MEASURED
BETWEEN 0.20 AND 0.25 mm FROM TERMINAL TIP.
6. APPLIED ONLY FOR TERMINALS.
APPLIED FOR EXPOSED PAD AND TERMINALS.

16-Pin MLF ^® (3mm x3mm) (MLF-16)

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

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