SY58033U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58033U Microchip

■ Precision 1:8, 400mV LVPECL fanout buffer
■ Low-jitter performance:
- 76fsRMS phase jitter (typ)
■ Guaranteed AC performance over temperature and voltage:
• Clock frequency range: DC to 5.5GHz
• <80ps tr/t_f times
• <280ps t_pd
- <20ps skew
■ 100k LVPECL compatible outputs
■ Fully differential inputs/outputs
■ Accepts an input signal as low as 100mV
■ Unique input termination and ¥ pin accepts DC-coupled and AC-coupled differential inputs: (LVPECL, LVDS, and CML)
■ Power supply 2.5V ±5% or 3.3V ±10%
■ Industrial temperature range: -40^ to +85^
■ Available in 32-pin (5mm x 5mm) QFN Package

Precision Edge®

DESCRIPTION

The SY58033U is a 2.5V/3.3V precision, high-speed, fully differential 400mV LVPECL 1:8 fanout buffer. The SY58033U is optimized to provide eight identical output copies with less than 20ps of skew and only 76fs _RMS phase jitter. It can process clock signals as fast as 5.5GHz.

The differential input includes Micrel's unique, 3-pin input termination architecture that allows the SY58033U to directly interface to LVPECL, CML, and LVDS differential signal (AC- or DC-coupled) without any level-shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter solution. The LVPECL (100k temperature compensated) outputs feature a 400mV typical swing into 50 ohms loads, and provide an extremely fast rise/fall time guaranteed to be less than 80ps.

The SY58033U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). Other high-speed 1:8 fanout buffers include the CML SY58031U and the 800mV LVPECL SY58032U. The SY58033U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at www.micrel.com.

APPLICATIONS

■ All SONET and all GigE clock distribution
■ All Fibre Channel clock and data distribution
■ Network routing engine timing distribution
■ High-end, low-skew multiprocessor synchronous clock distribution

FUNCTIONAL BLOCK DIAGRAM

graph TD
    A["N 500 V1 IN"] --> B["Inverter"]
    B --> C["Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7"]
    D["VDD+DC"] --> B
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#fcc,stroke:#333

Precision Edge is a registered trademark of Micrel, Inc.

PACKAGE/ORDERING INFORMATION

VCC GND IN VT VREF-AC /IN GND VCC IQ 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

32-Pin QFN (QFN-32)

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking
SY58033UMG(3)	QFN-32Pb-Free	Industrial SY58033U withPb-Free bar-line indicator
SY58033UMGTR(2, 3)	QFN-32Pb-Free	Industrial SY58033U withPb-Free bar-line indicator

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC electricals only. All devices are Pb-Free.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.

PIN DESCRIPTION

Pin Number Pin Name Pin Function
3,6 IN, /IN Differential Signal Input: See “Input Interface Applications” section.		Each pin of this pair internally terminates with 50Ω to the T pin. Note that this input will default to an indeterminate state if left open.
4 VT Input Termination Center-Tap: Each input (IN, /IN) to the flexibility. See “Input Interface Applications” section.		T pin provides a
2,7,17,24 Exposed Pad as the ground pin.		Ground. Exposed pad must be connected to a ground plane that is the same potential
1,8,9,16, 18,23,25,32	VCC pins as possible.	Positive Power Supply: Bypass with 0.1μF||0.01μF low ESR capacitors as close to the
31,30,29,28,27, 26,22,21,20,19, 15,14,13,12, 11,10 Q6, /Q6, Q7, /Q7	Q0,/Q0, Q1,/Q1, Q2, /Q2, Q3, /Q3 Q4, /Q4, Q5, /Q5,	400mV LVPECL Differential Output Pairs: Differential buffered output copy of the input signal. The LVPECL output swing is typically 400mV into 50Ω. Unused output pairs may be left floating with no impact on jitter. See “LVPECL Output” section.
5 VREF-AC Bias Reference Voltage: Equal to V CC-1.2V (approx.), and used for AC-coupled applications. See “Input Interface Applications” section. When using V CC. Maximum sink/source current is 0.5mA.

Absolute Maximum Ratings ^(1)

Power Supply Voltage (V _CC )......-0.5V to +4.0V

Input Voltage ( V_IN ) ....-0.5V to V_CC

Current ( V_T )

Source or sink current on V_T pin.... ±100mA

Input Current ( V_T )

Source or sink current on IN, /IN .... ±50mA

Current ( V_REF )

Source or sink current on V_REF-AC^(3) ..... ±1.5mA

Lead Temperature Soldering (20 sec.) 260°C

Storage Temperature Range ( T_S ) ..... -65°C to +150°C

Operating Ratings ^(2)

Power Supply Voltage (V _CC ) ...... +2.375V to +3.60V

Ambient Temperature Range ( T_A ) ..... -40°C to +85°C

Package Thermal Resistance ^(4)

QFN ( _JA )

Still-Air 35°C/W

QFN ( _JB )

Junction-to-Board 20°C/W

DC ELECTRICAL CHARACTERISTICS ^(5)

T_ = -40^ to +85^ .

Symbol	Parameter	Condition	Min	Typ	Max Units
V_CC	Power Supply Voltage				2.5V nominal3.3V nominal	2.3753.0	2.53.3	2.6253.6	VV
I_CC	Power Supply Current				V_CC = max. No. load includes current through 50 pull-ups.		180	250	mA
V_IH	Input HIGH Voltage				IN, /IN, Note 6	V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage				IN, /IN	0		V_IH-0.1	V
V_IN	Input Voltage Swing				IN, /IN, see Figure 1a.	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing|IN0, /IN0|, |IN1, /IN1|				IN, /IN, see Figure 1b.	0.2			V
R_IN	In-to- V_T Resistance					40	50	60	Ω
V_T IN	Max. In-to- V_T (IN, /IN)							1.28	V
V_REF-AC						V_CC-1.3	V_CC-1.2	V_CC-1.1	V

LVPECL DC ELECTRICAL CHARACTERISTICS ^(5)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 50 to V_CC - 2V ; T_A = -40^ to +85^ unless otherwise stated

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	Output HIGH Voltage		V_CC-1.145		V_CC-0.895	V
V_OL Output	LOW Voltage	V	V_CC-1.545		V_CC-1.295	V
V_OUT	Output Voltage Swing	see Figure 1a.	150	400		mV
V_DIFF\_OUT	Differential Voltage Swing	see Figure 1b.	300	800		mV

Notes:

1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability, use for input of the same package only.
4. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential (GND) on the PCB. _JB uses 4-layer _JA in still-air number unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V_IH (min) not lowers than 1.2V.

AC ELECTRICAL CHARACTERISTICS ^(7)
V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 50 to V_CC - 2V ; T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency V				OUT≥200mV	Clock 5.5	GHz
t_pd	Propagation Delay (IN-to-Q)						130	200	280	ps
t_pd tempco	Differential Propagation Delay Temperature Coefficient							35		fs/°C
t_SKEW	Output-to-Output Skew(within device)				Note 8			7	20	ps
	Part-to-Part Skew				Note 9				100	ps
t_JITTER	RMS Phase Jitter				Output = 622MHzIntegration Range 12kHz - 20MHz			76		fs
t_r, t_f	Output Rise/Fall Time				20% to 80%, at full output swing.		20	50	80	ps

Notes:

1. High frequency AC electricals are guaranteed by design and characterization. All outputs loaded with 50Ω to V CC -2V, V IN z 100mV.
2. Output-to-output skew is measured between outputs under identical conditions.
3. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Part-to-part skew includes variation in t_pd .

PHASE NOISE

Phase Noise Plot: 622MHz @ 3.3V

SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_IN, V_OUT 400mV (Typ.)

Figure 1a. Single-Ended Voltage Swing

V_DIFF_IN V_DIFF_OUT 500mV (Typ.)

Figure 1b. Differential Voltage Swing

TIMING DIAGRAM

/IN IN tPD tPD /Q Q VIN VOUR

TYPICAL OPERATING CHARACTERISTICS

V_CC=2.5V , GND=0, V_IN=100mV , T_A=25^ , unless otherwise stated.

INPUT BUFFER

VCC IN SD2 VT SD2 /IN GND

Figure 2. Simplified Differential Input Buffer

INPUT INTERFACE APPLICATIONS

VCC CMOS IN IN BY62033U NC VREF4-C NC VT

Figure 3a. DC-Coupled CML Input Interface
Option: May connect V_T to V_CC .

VCC CMOS GND IN /IN VCC B163032U VREF-C VT

Figure 3b. AC-Coupled CML Input Interface

VCC LVPEC GND IN /IN BY62033 U VCC 0.01μF VT RSD For 2.5V, RSD = 19Ω For 3.3V, RSD = 50Ω

Figure 3c. LVPECL Input Interface

VCC LVPBCL GND Rp4 Rp4 GND IN /IN BY62022U VREF-4C VT VCC For 3.3V, Rp = 100Ω For 2.5V, Rp = 50Ω

Figure 3d. AC-Coupled LVPECL Input Interface

VCC LVDS GND IN IN B Y62022U NC □ VREFc NC □ VT

Figure 3e. LVDS Input Interface

LVPECL OUTPUT

LVPECL has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low electromagnetic interference (EMI). LVPECL is ideal for driving 50Ω and 100Ω controlled impedance transmission lines. There are several techniques in terminating the LVPECL output, which are the Parallel Termination-Thevenin Equivalent, the Parallel Termination (3-Resistor), and the AC-Coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.

+3.3V Z₀ = 50Ω Z₀ = 50Ω For +2.5V systems, R1 = 250Ω R2 = 62.9Ω +3.3V R1 130Ω R1 130Ω +3.3V R2 82Ω R2 82Ω Vₜ = Vₒc -2V

Figure 4. Parallel Termination-Thevenin Equivalent

+3.3V Z = 50Ω Z = 50Ω source +3.3V destination 50Ω 50Ω Rb Vcc C1 (optional) 0.01μF

Notes:

1. Power saving alternative to Theuerin termination.

2. Place eminotion resistors as dose to des inhalon inputs as possible.

3. R_b resistors is the DC bias voltage, equal to V_T .

4. For 2.5V systems, R_b = 190 ; For 3.3V systems, R_b = 500

Figure 5. Parallel Termination (3-Resistor)
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION

Part Number	Function Data Sheet Link
SY58031U Outputs and Internal I/O Termination	Ultra-Precision 1:8 Fanout Buffer with 400mV CML	http://www.micrel.com/product-info/products/sy58031u.shtml
SY58032U Ultra-Precision 1:8 Fanout Buffer with LVPECL http://www.micrel.com/product-info/products/sy58032u.shtml
SY58033U Outputs and Internal Termination	Ultra-Precision 1:8 Fanout Buffer with 400mV LVPECL	http://www.micrel.com/product-info/products/sy58033u.shtml
32-MLF Application Note	® Manufacturing Guidelines Exposed Pad www.amkor.com	m/products/notes_papers/MLF_AppNote_0902.pdf
HBW Solutions	http://www.micrel.com/product-info/as/solutions.shtml	____

32-PIN QFN (QFN-32)

3.0 mm 32 1 2 PN #1 D 0.26 mA TYP. 3.0 mm

TOP VIEW

0.25±0.32 1.50 ±1 PIN # D 90.80 0.50 310±0.10 0.40±0.05 4K 310±0.10

BOTTOM VIEW

0.86±0.05 BEATING PLANE 0.00~0.05 0.20 REF

NOTE:
L ALL DIMENSIONS ARE ON MOLLOMETERS
2 MAX PACKAGE WARPAGE IS 003 mm
MAXIMUM ALLOWANCE BUEES @ 0.076 mm DI ALL DIRECTIONS
4. PJN ML 10 ON TOP WILL BE LASER/INK MARKET

SIDE VIEW

Compressor Heat Disputator Heavy Copper/Plure Heavy Copper/Plure Vcc

PCB Thermal Consideration for 32-Pin QFN Package (Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 [phone] FAX + 1 [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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