SY58013U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58013U Microchip

■ Precision 1:2, 400mV LVPECL fanout buffer
■ Low jitter performance:
- 55fsRMS phase jitter (typ)
■ Accepts an input signal as low as 100mV
■ Guaranteed AC performance over temperature and voltage:
- >6GHz fMAX clock
• < 80ps t/tf times
• < 250ps t_pd
- < 15ps max. skew
■ Unique input termination and ¥ pin accepts DC-coupled and AC-coupled differential inputs: LVPECL, LVDS and CML
■ 400mV LVPECL compatible outputs
■ Power supply 2.5V ±5% and 3.3V ±10%
- -40°C to +85°C temperature range
■ Available in 16-pin (3mm x 3mm) QFN package

APPLICATIONS

■ All SONET and All GigE clock distribution
■ Fibre Channel clock and data distribution
■ Backplanes
■ Data distribution: OC-48, OC-48+FEC, XAUI
■ High-end, low-skew, multiprocessor synchronous clock distribution

FUNCTIONAL BLOCK DIAGRAM

graph TD
    IN["IN"] --> A["NOT"]
    V_T["V_T"] --> A
    /IN["/IN"] --> A
    A --> B["NOT"]
    V_T --> C["NOT"]
    /IN --> C
    C --> D["Q0"]
    C --> E["Q1"]
    D --> F["Q0"]
    E --> G["Q1"]

Precision Edge is a registered trademark of Micrel, Inc.

Precision Edge®

DESCRIPTION

The SY58013U is a 2.5V/3.3V precision, high-speed, fully differential 1:2 LVPECL fanout buffer. Optimized to provide two identical output copies with less than 15ps of skew and only 55fs_RMS phase jitter, the SY58013U can process clock signals as fast as 6GHz or data patterns up to 10.7Gbps.

The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS, and CML differential signals, (AC- or DC-coupled) as small as 100mV without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an on-board output reference voltage ( V_REF-AC ) is provided to bias the V_T pin. The outputs are 400mV LVPECL compatible, with extremely fast rise/fall times guaranteed to be less than 80ps.

The SY58013U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (-40°C to +85°C). For applications that require greater output swing or CML compatible outputs, consider the SY58012U 1:2 fanout buffer with 800mV LVPECL outputs, or the SY58011U 1:2 fanout buffer with 400mV CML outputs. The SY58013U is part of Micrel's high-speed, Precision Edge® product line. Datasheets and support documentation can be found on Micrel's web site at www.micrel.com.

TYPICAL PERFORMANCE

2GHz with 100mV Input

PACKAGE/ORDERING INFORMATION

VCC VDD VDD VCC IN VT VREF-AC VIN 18 15 14 13 1 2 2 9 4 5 6 r 3 VCC VDD VDD VCC 12 11 10 9 Q0 /Q0 /Q1 Q1

16-Pin QFN

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking
SY58013UMG ^(3)	QFN-16 Pb-Free	Industrial	013U withPb-Free bar-line indicator
SY58013UMGTR ^(2, 3)	QFN-16 Pb-Free	Industrial	013U withPb-Free bar-line indicator

Notes:

1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC electricals only. All devices are Pb-Free.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.

PIN DESCRIPTION

Pin Number Pin Name Pin Function
1, 4 IN, /IN Differential input: This input terminated with 50 state	ohms to the V	put pair is the signal to be buffered. Each pin is internally _T pin. Note that this input will default to an indeterminate if left open. See “Input Interface Applications” section.
2See “Input Interface Applications” section.	VT	Input Termination Center-Tap: Each input terminates to this pin. The V_T pin provides a center-tap for each input (IN, /IN) to a termination network for maximum interface flexibility.
3 VREF-AC Reference inputs (IN, /IN). Connect V capacitor to V Applications” section.	Reference Output Voltage: This output biases to V_CC -1.2V . It is used for AC-coupled _REF-AC directly to the V_T pin. Bypass with 0.01μF low ESR _CC . Maximum current source or sink is 0.5mA. See “Input Interface
5, 8, 13, 16	VCC	Positive Power Supply: Bypass with 0.1μF//0.01μF low ESR capacitors as close to the V_CC pins as possible.
6, 7, 14, 15(Exposed Pad) as the ground pin.	GND,
12, 119, 10 jitter. See “LVPECL Output Termination” section.	Q0, /Q0, Q1, /Q1	LVPECL Differential Output Pairs: Differential buffered output copy of the input signal. The output swing is typically 400mV. Unused output pairs may be left floating with no impact on

Absolute Maximum Ratings ^(Note 1)

Power Supply Voltage ( V_CC ) -0.5V to +4.0V

Input Voltage ( V_IN ) -0.5V to V_CC

Output Current (IOUT)

Continuous 50mA

Surge 100mA

V_T Current

Source or sink current on V_T pin.... ±100mA

Input Current

Source or sink current on (IN, /IN) .... ±50mA

V_REF Current

Source or sink current on V_REF -AC, Note 4 .... ±1.5mA

Soldering, (20 sec.) 260°C

Storage Temperature Range (T _STORE ) ...... -65 to +150°C

Operating Ratings ^(Note 2)

Power Supply Voltage ( V_CC ) ..... +2.375V to +3.60V

Operating Temperature Range ( T_A ) ..... -40°C to +85°C

Package Thermal Resistance, Note 3

QFN ( _JA )

Still-Air 60°C/W

500lpfm 54°C/W

QFN (_JB) 33°C/W

DC ELECTRICAL CHARACTERISTICS(Note 5)
T_A=-40^ to +85^

Symbol Parameter Condition Min Typ Max		Units
V_CC	Power Supply Voltage		2.375		3.60	V
I_CC	Power Supply Current Max. V	_CC , no load		75	90	mA
V_IH	Input HIGH Voltage	IN, /IN, Note 6	V_CC-1.6		V_CC	V
V_IL	Input LOW Voltage	IN, /IN	0		V_IH-0.1	V
V_IN	Input Voltage Swing	IN, /IN; see Figure 1a	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage	IN, /IN; see Figure 1b	0.2			V
R_IN	In to V_T Resistance		40	50	60	ohms
V_REF-AC	Output Reference Voltage		V_CC-1.3	V_CC-1.2	V_CC-1.1	V
IN to V_T					1.28	V

LVPECL DC ELECTRICAL CHARACTERISTICS(Note 5)
V_CC = 3.3V ± 10% or V_CC = 2.5 ± 5% ; R_L = 50ohms to V_CC - 2V ; T_A = -40^ C to 85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	Output HIGH Voltage	Q0, /Q0, Q1, /Q1	V_CC-1.145	V_CC-1.020	V_CC-0.895	V
V_OL	Output LOW Voltage	Q0, /Q0, Q1, /Q1	V_CC-1.545	V_CC-1.420	V_CC-1.295	V
V_OUT	Output Voltage Swing	Q0, /Q0, Q1, /Q1; see Figure 1a	200	400		mV
V_DIFF\_OUT	Differential Output Voltage Swing	Q0, /Q0, Q1, /Q1; see Figure 1b	400	800		mV

Note 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
Note 4. Due to the limited drive capability, use for input of the same package only.
Note 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Note 6. V _IH (min) not lower than 1.2V.

AC ELECTRICAL CHARACTERISTICS(Note 7)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C ; R_L = 50ohms to V_CC-2V , unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

f_MAX	Maximum Operating Frequency NRZ Data V	10 Gbps
		OUT x 200mV	Clock	6			GHz
t_pd	Propagation Delay	V_IN × 100mV		100	180	250	ps
t_CHAN	Channel-to-Channel Skew	Note 8			4	15	ps
t_SKEW	Part-to-Part Skew	Note 9				100	ps
t_JITTER	Random Jitter	Output = 622MHzIntegration Range: 12kHz-20MHz			55		fs
t_r, t_f	Output Rise/Fall Time	20% to 80%, at full output swing		20	50	80	ps

Note 7. High frequency AC electricals are guaranteed by design and characterization.
Note 8. Skew is measured between outputs of the same bank under identical transitions.
Note 9. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.

THMIAKEDNAXCREAM

Phase Noise Plot: 622MHz @ 3.3V

TIMING DIAGRAM

V_IN V_OUT (Typ. +00m V)

Figure 1a. Single-Ended Voltage Swing

V_{DIFF_IN} V_{DIFF_OUT} (Typ. 500mV)

Figure 1b. Differential Voltage Swing

TYPICAL OPERATING CHARACTERISTICS

V_CC = 3.3V , GND = 0, V_IN = 100mV , T_A = 25^ , unless otherwise stated.

FUNCTIONAL CHARACTERISTICS

V_CC = 3.3V, V_EE = 0V, V_IN = 100mV, T_A = 25^ , unless otherwise stated.

10.7Gbps Output Output Swing (100mV/6x) Measure 2 TIME (25ps/div.)

(2 ^23 -1 PRBS Pattern)

INPUT STAGE

Vcc IN 50Ω VT 50Ω GND IN

Figure 2. Simplified Differential Input Buffer

INPUT INTERFACE APPLICATIONS

VCC LVPCL IN VIN BY62012U VT VRSF-AC 0.01μF Rp NC Note: For VCC = 2.5V system, Rm = 19Ω For VCC = 3.3V system, Rm = 50Ω

Figure 3a. DC-Coupled LVPECL Input Interface

VCC D:\PBCL IN VIN BY680 12 U VT VRSF\AC 0.01μF VCC Note: For VCC = 2.5V, Rμ = 50Ω For VCC = 3.3V, Rμ = 100Ω

Figure 3b. AC-Coupled LVPECL Input Interface

Vcc D/DS IN /IM BY620 13 U NC □ V'T NC □ VRSF NC Vcc

Figure 3c. LVDS Input Interface

VCC CMN L IN IN BY620 18U MC VT MC VREFAC VCC

Figure 3d. DC-Coupled CML Input Interface (option: may connect V_T to V_CC )

VCC CML IN IN BY62013U VT VRSF-AC DDIμF VCC

Figure 3e. AC-Coupled CML Input Interface

OUTPUT TERMINATION RECOMMENDATIONS

LVPECL outputs have very low output impedance (open emitter), and small signal swing which results in low EMI (electro-magnetic interference). The LVPECL is ideal for driving 50 ohms and 100 ohms controlled impedance transmission lines. In addition, LVPECL is compatible for driving standard PECL inputs since PECL inputs require only 100mV input swing. Further, there are several techniques in terminating the LVPECL outputs, as shown in Figure 4 through 6.

+3.3V Z₀ = 50Ω Z₀ = 50Ω R1 130Ω +3.3V R1 130Ω +3.3V R2 82Ω R2 82Ω Vₜ = Vₒₒ -2V

Figure 4. Parallel Termination-Thevenin Equivalent
Note 1. For +2.5V systems: R1 = 250 ohms, R2 = 62.5 ohms
Note 2. For +3.3V systems: R1 = 130 ohms, R2 = 82 ohms

+3.3V Z = 50Ω Z = 50Ω source 50Ω 50Ω 50Ω 50Ω Rb C1 0.01μF (optional) destination

+3.3V +3.3V Q R1 130Ω Z0 = 50Ω R2 82Ω VT = Vcc -2V +3.3V R1 130Ω R4 1kΩ VT = Vcc -1.3V +3.3V R2 82Ω R3 1.6kΩ

Figure 6. Terminating Unused I/O
Note 1. Unused output (/Q) must be terminated to balance the output.
Note 2. For+2.5Vsystems: R1=250ohms, R2=62.5ohms, R3=1.25kohms, R4=1.2k ohms.

For +3.3V systems: R1 = 130 ohms, R2 = 82 ohms, R3 = 1k ohms, R4 = 1.6k ohms.

Note 3. Unused output pairs (Q and /Q) may be left floating.

Figure 5. Three-Resistor "Y-Termination"

Note 1. Power-saving alternative to Thevenin termination.

Note 2. Place termination resistors as close to destination inputs as possible.

Note 3. R_b resistor sets the DC bias voltage, equal to V_T .

For +2.5V systems R _h = 39 ohms.

For +3.3V systems R _b = 46 ohms to 50 ohms.

Note 4. C1 is an optional bypass capacitor intended to compensate for any t r/tf mismatches.

RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION

Part Number	Function	Data Sheet Link
SY58011U	7GHz, 1:2 CML Fanout Buffer/Translator With Internal I/O Termination	http://www.micrel.com/product-info/prod/ucts/sy58011u.shtml
SY58012U	5GHz, 1:2 LVPECL Fanout Buffer/Translator With Internal Input Termination	http://www.micrel.com/product-info/products/sy58012u.shtml
SY58013U	6GHz, 1:2 Fanout Buffer/Translator w/400mV LVPECL Outputs and Internal Input Termination	http://www.micrel.com/product-info/products/sy58013u.shtml
	16-MLF® Manufacturing Guidelines Exposed Pad Application Note	www.amkor.com/products/notes_papers/mlf_AppNote_0902.pdf
M-0317	HBW Solutions	http://www.micrel.com/product-info/as/solutions.shtml

16-PIN QFN (QFN-16)

Pin L Dot By Marking 3.000±0.051 3.000±0.050

TOP VIEW

1.55±0.150 Exp. 0.45 PIN 4L IDENTIFICATION CHAMFER 0.301 X 43° 0.400±0.150 0.301 Res LS60+0.050 Exp. 0.45 0.400±0.050 LS60 Ref.

BOTTOM VIEW

0.86 D=1.05D 0.01-1.05D 0.203+1.025

SIDE VIEW

NOTE

1. ALL IDENTISING ARE DU KILLIMETERS.

B. MAX PACKAGE WRAPAGE (1:40 pm.

1. MAXIMUM ALLOWANCE NUMBER 12 0076 N/A IN ALL directions

2. PDN \$10 ON TOP VILL BE LAGERON KNOED.

Dle Compulsation Heat Dissipation Heat Dissipation Heavy Copper Plate VH VH Heavy Copper Plate

PCB Thermal Consideration for 16-Pin QFN Package
(Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

Note 1. Package meets Level 2 qualification.

Note 2. All parts are dry-packaged before shipment.

Note 3. Exposed pads must be soldered to a ground for proper thermal management.

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The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

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