SY58022U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58022U Microchip

5.5 GHz, 1:4 Fanout Buffer/Translator with 400 mV LVPECL Outputs and Internal Input Termination

Features

• Precision 1:4, 400 mV LVPECL Fanout Buffer
- Ensured AC Performance over Temperature and Voltage:

->5.5 GHz f MAX Clock
- <80 ps t_r/t_f Times
- <250 ps (V IN ≥300 mV) tPD
- <15 ps Maximum Skew

• Low Jitter Performance: 60 fs RMS Phase Jitter
• Accepts an Input Signal as Low as 100 mV
• Unique Input Termination and VT Pin Accepts DC-and AC-Coupled Differential Inputs: LVPECL, LVDS, and CML
  • 400 mV LVPECL Compatible Outputs
  • Power Supply: 2.5V ±5% and 3.3V ±10%
• 40^ to +85^ Temperature Range
  • Available in a 16-Lead 3 mm x 3 mm VQFN Package

Applications

• All SONET and All GigE Clock Distribution
  • Fibre Channel Clock and Data Distribution
• Backplane Distribution
  • Data Distribution: OC-48, OC-48+FEC, XAU
  • High-End, Low-Skew, Multiprocessor Synchronous Clock Distribution

General Description

The SY58022U is a 2.5V/3.3V precision, high-speed, fully differential 1:4 LVPECL fanout buffer. Optimized to provide four identical output copies with less than 15 ps of skew and less than 10 ps PP total jitter, the SY58022U can process clock signals as fast as 5.5 GHz.

The differential input includes Microchip's unique, 3-pin input termination architecture interfaces to differential LVPECL, CML, and LVDS signals (AC- or DC-coupled) as small as 100 mV without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an on-board output reference voltage ( V_REF-AC ) is provided to bias the VT pin. The outputs are 400 mV LVPECL compatible with extremely fast rise/fall times ensured to be less than 80 ps.

The SY58022U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is ensured over the full industrial temperature range (-40°C to +85°C). For applications that require greater output swing or CML compatible outputs, consider the SY58021U 1:4 fanout buffer with LVPECL outputs, or the SY58020U 1:4 fanout buffer with 400 mV CML outputs.

Package Type

SY58022U 3 mm x 3 mm VQFN (M) (Top View) GND Q0 /Q0 VCC IN 1516914 VT 12 Q1 VREF-AC 11 /Q1 /IN 3 10 Q2 /IN 4 9 /Q2 5 6 7 8 GND /Q3 Q3 VCC

Functional Block Diagram

graph TD
    IN["IN"] -->|50Ω| A["Inverter"]
    VT["VT"] -->|50Ω| A
    /IN["/IN"] -->|50Ω| A
    A --> Q0["Q0"]
    A --> Q1["Q1"]
    A --> Q2["Q2"]
    A --> Q3["Q3"]
    Q0 --> Q0_out["/Q0"]
    Q1 --> Q1_out["/Q1"]
    Q2 --> Q2_out["/Q2"]
    Q3 --> Q3_out["/Q3"]
    VREF_AC["VREF-AC"] --> A
    style VREF_AC stroke:#ff0000,stroke-width:2px

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Power Supply Voltage (VCC)	-0.5V to +4.0V
Input Voltage (VIN)	-0.5V to VCC
Continuous Output Current (IOUT)	50 mA
Surge Output Current (IOUT)	100 mA
Source or Sink Current on VT Pin	±100 mA
Source or Sink Current on (IN, /IN) Pins	±50 mA
Source or Sink Current on VREF-AC Pin (Note 1)	±1.5 mA

Operating Ratings ††

Power Supply Voltage ( V_CC )....+2.375V to +3.60V

† Notice: Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

†† Notice: The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

Note 1: Due to the limited drive capability, use for input of the same package only.

DC ELECTRICAL CHARACTERISTICS

T_A = -40^ to +85^ . Note 1

Parameters Symbol	Min. Typ.	Max. Units		Conditions
Power Supply Voltage	V_CC	2.375	2.5	2.625	V	V_CC = 2.5V
		3.0	3.3	3.6		V_CC = 3.3V
Power Supply Current	I_CC	—	125	160	mA	No load, V_CC = Max.
Input High Voltage	V_IH	1.2	—	V_CC	V	—
Input Low Voltage	V_IL	0	—	V_IH - 0.1	V	IN, /IN
Input Voltage Swing	V_IN	0.1	—	3.6	V	IN, /IN; See Figure 4-1
Differential Input Voltage	V_DIFF\_IN	0.2	—	3.4	V	IN, /IN; See Figure 4-2
IN-to-VT Resistance	R_IN	40	50	60 Ω	—
Output Reference Voltage	V_REF-AC	V_CC - 1.3	V_CC - 1.2	V_CC - 1.1	V	—
IN-to-VT Voltage	V_T\_IN	—	—	1.28	V	—

Note 1: The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established.

LVPECL DC ELECTRICAL CHARACTERISTICS

V_CC = 3.3V ± 10% or V_CC = 2.5 ± 5% ; R_L = 50 to V_CC - 2V ; T_A = -40^ to +85^ , unless otherwise stated. Note 1

Parameter Symbol	Min. Typ.	Max. Units Condition
Output High Voltage V	_OH	V_CC - 1.145 V	_CC - 1.020 V	_CC - 0.895 V	—
Output Low Voltage V	_OL	V_CC - 1.545 V	_CC - 1.420 V	_CC - 1.295 V	—
Output Voltage Swing	V_OUT	150	400	650	mV	See Figure 4-1
Differential Output Swing	V_DIFF\_OUT	300	800	1300	mV	See Figure 4-2

Note 1: The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS

V_CC = 2.5V ± 5% or 3.3V ± 10% ; R_L = 50 to V_CC - 2V ; T_A = -40^ to +85^ , unless otherwise stated.

Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
Maximum Operating Frequency	f_MAX	5.5	—	—	GHz	Clock, V_OUT ≥ 200 mV
		—	10	—	Gbps	NRZ Data
Propagation Delay	t_PD	130	200	280 ps	—
Channel-to-Channel Skew	t_CHAN	—	4	15	ps	Note 1
Part-to-Part Skew	t_SKEW	—	—	50	ps	Note 2
RMS Phase Jitter	t_JITTER	—	60	—	fs	Output = 622 MHz, Integration range: 12 kHz to 20 MHz
Output Rise/Fall Time	t_f/t_f	20	50	80	ps	20% to 80%, At full swing

Note 1: Skew is measured between outputs of the same bank under identical transitions.
2: Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.

TEMPERATURE SPECIFICATIONS

Parameters	Symbol	Min.	Typ.	Max.	Units	Conditions
Temperature Ranges
Operating Temperature Range	T_A	-40	— +85	°C	—
Lead Temperature	—	—	—	+260	°C	Soldering, 20 sec.
Storage Temperature Range	T_S	-65	—	+150	°C	—
Package Thermal Resistances
Thermal Resistance, 3x3 VQFN 16-Ld	_JA	—	60	—	°C/W	Still-air
			54			500 lpfm
	_JB	—	33	—	°C/W	Junction-to-board, Note 1

Note 1: Thermal performance assumed exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

V_CC = 3.3V, V_EE = 0V, V_IN = 100 mV, T_A = +25^ , unless otherwise stated.

FIGURE 2-1: Amplitude vs. Frequency.

FIGURE 2-4: Propagation Delay vs. Temperature.

FIGURE 2-2: Skew vs. Temperature.

FIGURE 2-5: 4 GHz Output.

FIGURE 2-3: Propagation Delay vs. Input Voltage Swing.

FIGURE 2-6: 2.5 GHz Output.

FIGURE 2-7: 1.25 GHz Output.

FIGURE 2-8: 200 MHz Output.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin Number	Pin Name Description
1, 4 IN, /IN		Differential Input: This input pair receives the signal to be buffered. Each pin is internally terminated with 50 to the VT pin. Note that this input will default to an indeterminate state if left open. See theInput Interface Applicationssection.
2	VT	Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to the termination network for maximum interface flexibility. See theInput Interface Applicationssection.
3 VREF-AC		Reference Output Voltage: This output biases to V_CC - 1.2V . It is used when AC-coupling to differential inputs. Connect VREF-AC directly to the VT pin. Bypass with 0.01 F low ESR capacitor to VCC. See theInput Interface Applicationssection.
8, 13 VCC		Positive Power Supply: Bypass with 0.1 F//0.01 F low-ESR capacitors as close to the pins as possible. A 0.01 F capacitor should be as close to the VCC pin as possible.
5, 16	GND, Exposed Pad	Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin.
14, 15	/Q0, Q0	LVPECL Differential Output Pairs: Differential buffered output copy of the input signal. The output swing is typically 400 mV . Proper termination is 50 to V_CC - 2V at the receiving end. Unused output pairs may be left floating with no impact on jitter or skew. See theOutput Termination Recommendationssection.
11, 12	/Q1, Q1
9, 10	/Q2, Q2
6, 7	/Q3, Q3

4.0 SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_{IN}, V_{OUT} 400mV

FIGURE 4-1: Single-Ended Voltage Swing.

VDIFF_IN VDIFF_OUT 800mV

FIGURE 4-2: Differential Voltage Swing.

5.0 TIMING DIAGRAM

/IN IN /Q Q t_pd

FIGURE 5-1: Timing Diagram.

6.0 INPUT STAGE

Vcc IN 50Ω VT 50Ω /IN GND

FIGURE 6-1: Simplified Differential Input Stage.

7.0 INPUT INTERFACE APPLICATIONS

Vcc LVPECL IN /IN SY58022U VT Rpd NC VREF-AC 0.01μF For Vcc = 2.5V, Rpd = 19Ω. For Vcc = 3.3V, Rpd = 50Ω.

FIGURE 7-1: DC-Coupled LVPECL Input Interface.

Vcc CML IN /IN SY58022U VT VREF-AC 0.01μF Vcc

FIGURE 7-4: AC-Coupled CML Input Interface.

VCC LVPECL Rpd Rpd 0.01 F IN /IN SY58022U VT VREF-AC VCC Rpd = 100Ω for a 3.3V system. Rpd = 50Ω for a 2.5V system.

FIGURE 7-2: AC-Coupled LVPECL Input Interface.

VCC CML IN /IN NC VT NC VREF-AC SY58022U (Option: May connect VT to VCC)

FIGURE 7-5: CML Input Interface.

VCC LVDS IN /IN NC □ VT NC □ VREF-AC SY58022U VCC

FIGURE 7-3: LVDS Input Interface.

8.0 OUTPUT TERMINATION RECOMMENDATIONS

LVPECL outputs have very low output impedance (open emitter), and small signal swing which results in low EMI (electro-magnetic interference). The LVPECL is ideal for driving 50Ω-controlled and 100Ω-controlled impedance transmission lines. In addition, LVPECL is compatible for driving standard PECL inputs because PECL inputs require only 100 mV input swing. Further, there are several techniques in terminating the LVPECL outputs, as shown in Figure 8-1 through Figure 8-3.

+3.3V Z₀ = 50Ω Z₀ = 50Ω R1 130Ω +3.3V R1 130Ω +3.3V R2 82Ω R2 82Ω Vₜ = Vₓₓ -2V

FIGURE 8-1: Parallel Termination – Thevenin Equivalent.
Note: For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω. For +3.3V systems: R1 = 130Ω, R2 = 83Ω.

+3.3V +3.3V Z = 50 Ω SY58022U Z = 50 Ω "source" "destination" 50Ω 50Ω 50Ω Rb C1 0.01μF (optional)

FIGURE 8-2: Three-Resistor "Y-Termination".
Note: Power-saving alternative to Thevenin termination. Place termination resistors as close to destination inputs as possible. R_b resistor sets the DC bias voltage, equal to V_T . For +2.5V systems, R_b = 19 . For 3.3V systems, R_b = 46 to 50Ω. C1 is an optional bypass capacitor intended to compensate for any/ t_f mismatches.

+3.3V +3.3V R1 130Ω Zo = 50Ω +3.3V R1 130Ω R4 1kΩ VT = VCC -1.3V +3.3V Q /SY58022U /Q VT = VCC -2V R2 82Ω R2 82Ω R3 1.6kΩ

FIGURE 8-3: Terminating Unused I/O.
Note: Unused output (/Q) must be terminated to balance the output. For +2.5V systems: R1 = 250Ω, R2 = 62.5Ω, R3 = 1.25 kΩ, R4 = 1.2 kΩ. For +3.3V systems: R1 = 130Ω, R2 = 82Ω, R3 = 1 kΩ, R4 = 1.6 kΩ. Unused output pairs (Q and /Q) may be left floating.

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

16-Lead VQFN* Example

m- XXXX WNNN

m - 022U 5EM9

Legend: XX...X Product code or customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week '01')
NNN Alphanumeric traceability code
eBb-free JEDEC ^® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( ) e3
can be found on the outer packaging for this package.
•, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark).

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo.

Underbar (_) and/or Overbar (−) symbol may not be to scale.

16-Lead Very Thin Plastic Quad Flat, No Lead Package (NCA) - 3x3x1.0 mm Body [VQFN] With 1.55 mm Exposed Pad; Micrel Legacy Package QFN33-16LD-PL-1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

NOTE1 1 2 (DATUM B) (DATUM A) 2X 0.05 C 2X 0.05 C TOP VIEW D2 0.10 A B E2 K NOTE 1 e 16X b BOTTOM VIEW 16X 0.08 C // 0.10 C A1 (A3) SEATING PLANE C SIDE VIEW

Microchip Technology Drawing C04-1103-NCA Rev C Sheet 1 of 2

16-Lead Very Thin Plastic Quad Flat, No Lead Package (NCA) - 3x3x1.0 mm Body [VQFN] With 1.55 mm Exposed Pad; Micrel Legacy Package QFN33-16LD-PL-1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Technical line drawing of two integrated circuit chips with pinouts (no text or symbols)

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Terminals	N	16
Pitch	e	0.50 BSC
Overall Height	A	0.80	0.90	1.00
Standoff	A1	0.00	0.02	0.05
Terminal Thickness	A3	0.203 REF
Overall Length	D	3.00 BSC
Exposed Pad Length	D2 1	50	1.55 1.60
Overall Width	E	3.00 BSC
Exposed Pad Width	E2	1.50	1.55	1.60
Terminal Width	b	0.18	0.23	0.28
Terminal Length	L	0.35	0.40	0.45
	K 0.33 REFTerminal-to-Exposed-Pad

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-1103-NCA Rev C Sheet 2 of 2

16-Lead Very Thin Plastic Quad Flat, No Lead Package (NCA) - 3x3x1.0 mm Body [VQFN] With 1.55 mm Exposed Pad; Micrel Legacy Package QFN33-16LD-PL-1

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

C1 X2 G2 C2 Y2 G1 Y1 X1 SILK SCREEN E

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.50 BSC
Center Pad Width	X2			1.60
Center Pad Length	Y2			1.60
	C1	Contact Pad Spacing 2.72
Contact Pad Spacing	C2		2.72
Contact Pad Width (Xnn)	X1			0.23
Contact Pad Length (Xnn)	Y1			0.48
Contact Pad to Center Pad (Xnn) G1	0.32
Contact Pad to Contact Pad (Xnn) G2	0.27

Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-3103-NCA Rev C

APPENDIX A: REVISION HISTORY

Revision A (August 2023)

• Converted Micrel document SY58022U to Microchip data sheet template DS20006800A.
• Swapped Figure 7-4 and Figure 7-5. These were sorted incorrectly in the legacy document.
• Minor text changes throughout.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Part No. X X X

Device

-XX

Supply

Voltage

Package

Temperature

Range

Media Type

Examples:

a) SY58022UMG:

SY58022, 2.5V/3.3V Supply Voltage, 16-Lead VQFN, -40°C to +85°C Temperature Range, 100/Tube

b) SY58022UMG-TR:

SY58022, 2.5V/3.3V Supply Voltage, 16-Lead VQFN, -40°C to +85°C Temperature Range, 1,000/Reel

Device:

SY58022: 5.5 GHz 1:4 Fanout Buffer/Translator with

400 mV LVPECL Outputs and Internal Input Termination

Supply Voltage: U = 2.5V/3.3V

Package: M = 3 mm x 3 mm 16-Lead VQFN

Temperature

G = -40°C to +85°C

Range:

Media Type:

= 100/Tube

TR = 1,000/Reel

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

NOTES:

Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
- Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable" Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products.

This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https://www.microchip.com/en-us/support/design-help/client-support-services.

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All other trademarks mentioned herein are property of their respective companies.

© 2023, Microchip Technology Incorporated and its subsidiaries.

All Rights Reserved.

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