SY58035U - Electronic component Microchip - Free user manual and instructions

USER MANUAL SY58035U Microchip

■ Provides six ultra-low skew copies of the selected input
■ 2:1 MUX input included for clock switchover applications
■ Guaranteed AC performance over temperature and voltage:

• Clock frequency range: DC to > 4.5GHz
• <320ps IN-to-OUT t pd
• <110ps t r /t f times
• <20ps skew (output-to-output)

■ Ultra-low jitter design:
- 50fs_RMS phase jitter (typ)
■ Low supply voltage operation: 2.5V and 3.3V
■ Unique input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, PECL, LVDS)
■ Unique input isolation design minimizes crosstalk
■ 100K LVPECL compatible output swing
■ -40^ to +85^ temperature range
■ Available in 32-pin (5mm x 5mm) MLF® package

Precision Edge®

DESCRIPTION

The SY58035U is a 2.5V/3.3V precision, high-speed, 1:6 fanout capable of handling clocks up to 4.5GHz. A differential 2:1 MUX input is included for redundant clock switchover applications.

The differential input includes Micrel's unique, 3-pin input termination architecture that allows the device to interface to any differential signal (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The outputs are LVPECL (100K, temperature compensated), with extremely fast rise/fall times guaranteed to be less than 110ps.

The SY58035U operates from a 2.5V ±5% supply or a 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. For applications that require CML outputs, consider the SY58034U or for 400mV LVPECL outputs the SY58036U. The SY58035U is part of Micrel's high-speed, Precision Edge® product line.

All support documentation can be found on Micrel's web site at www.micrel.com.

APPLICATIONS

■ Redundant clock distribution
■ All SONET/SDH clock/data distribution
■ All Fibre Channel distribution
■ All Gigabit Ethernet clock distribution

FUNCTIONAL BLOCK DIAGRAM

graph TD
    A["IN0"] --> B["50Ω"]
    C["V_T0"] --> D["50Ω"]
    E["/IN0"] --> F["0"]
    G["V_REF_AC0"] --> H["1"]
    I["IN1"] --> J["50Ω"]
    K["V_T1"] --> L["50Ω"]
    M["/IN1"] --> N["0"]
    O["V_REF_AC1"] --> P["1"]
    Q["SEL (TTL/CMOS)"] --> R["2:1 Mux"]
    R --> S["Mux"]
    T["1:6 Fanout"] --> U["Q0"]
    T --> V["/Q0"]
    T --> W["Q1"]
    T --> X["/Q1"]
    T --> Y["Q2"]
    T --> Z["/Q2"]
    T --> AA["Q3"]
    T --> AB["/Q3"]
    T --> AC["Q4"]
    T --> AD["/Q4"]
    T --> AE["Q5"]
    T --> AF["/Q5"]

Precision Edge is a registered trademark of Micrel, Inc.

MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

PACKAGE/ORDERING INFORMATION

GND SEL VCC Q0 /Q0 Q1 /Q1 VCC IN0 32 31 30 29 28 27 26 25 1○ 24 VTC VREF-AC0 3 23 Q2 /IN0 4 22 Q1/Q2 IN1 5 21 Q3 VT1 6 20 /Q3 VREF-AC1 7 19 VCC /IN1 8 18 GND GND NC VCC /Q5 Q5 /Q4 Q4 VCC

32-Pin MLF ^® (MLF-32)

Ordering Information ^(1)

Part Number	Package Type	Operating Range	Package Marking	Lead Finish
SY58035UMI	MLF-32	Industrial	SY58035U	Sn-Pb
SY58035UMITR(2)	MLF-32	Industrial	SY58035U	Sn-Pb
SY58035UMG(3)	MLF-32	Industrial	SY58035U with Pb-Free bar-line indicator	NiPdAu Pb-Free
SY58035UMGTR(2, 3)	MLF-32	Industrial	SY58035U with Pb-Free bar-line indicator	NiPdAu Pb-Free

Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25^ , DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.

PIN DESCRIPTION

Pin Number Pin	Name Pin Function
1,4 IN0, /IN0 Differential Input: These input pairs are the differential signal inputs to the device. These 5,8 IN1, /IN1 inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50y. Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details.
2,6 interface flexibility. See “Input Interface Applications” section for more details.
31 that this input is SEL internally connected to a 25kΩ pull-up resistor and will default to a logic high state if left open. The MUX select switchover function is asynchronous.
10	NC	No connect.
11, 16, 18, 23, 25, 30	VCC close to	Positive Power Supply: Bypass with 0.1μF || 0.01μF low ESR capacitors and place as the VCC pin as possible.
29, 28 27, 26 22, 21 20, 19 15, 14 13, 12	Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, Q4, /Q4, Q5, /Q5	Differential Outputs: These 100K (temperature compensated) LVPECL output pairs are low skew copies of the selected input. Please refer to the “Truth Table” for details.
9, 17, 24, 32 Exposed Pad		Ground: Ground pin and exposed pad must be connected to the same ground plane.
3,7 VREF-AC1 (IN, /IN) Due to the limited drive capability, the VREF-AC pin is only intended to drive its respective		Reference Voltage: These output biases to V_CC -1.2V. It is used for AC-coupling inputs Connect V REF-AC directly to the VT pin. Bypass with 0.01μF low ESR capacitor to V See “Input Interface Applications” section. Maximum sink/source current is ±1.5mA.

TRUTH TABLE

SEL
0	IN0 Input Selected
1	IN1 Input Selected

Absolute Maximum Ratings ^(1)

Power Supply Voltage ( V_CC ) .....-0.5V to +4.0V

Input Voltage ( V_IN ) ....-0.5V to V_CC

LVPECL Output Current ( I_OUT )

Continuous 50mA

Surge 100mA

Termination Current

Source or sink current on V_T pin.... ±100mA

Input Current

Source or sink current on IN, /IN pin .... ±50mA

Source or sink current on VREF-AC pin .... ±2mA

Lead Temperature (soldering, 10 sec.) 220°C

Storage Temperature Range ( T_S ) ..... -65°C to +150°C

Operating Ratings ^(2)

Power Supply Voltage ( V_CC ) ..... +2.375V to +2.625V ..... +3.0V to +3.6V

Ambient Temperature Range ( T_A ) ..... -40°C to +85°C

Package Thermal Resistance ^(3)

MLF® (θJA)

Still-Air 35°C/W

MLF® (ΨJB)

Junction-to-Board 16°C/W

DC ELECTRICAL CHARACTERISTICS ^(4)

T_A = -40^ to +85^ , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max Units
V_CC	Power Supply Voltage					2.375	2.5	2.625	V
						3.0	3.3	3.6	V
I_CC	Power Supply Current				No load, max. V_CC		185	250 mA
R_DIFF\_IN	Differential Input Resistance (IN-to-/IN)					90	100	110	Ω
R_IN	Input Resistance (IN-to- V_T )					45	50	55	Ω
V_IH	Input HIGH Voltage (IN, /IN)					V_CC-1.2		V_CC	V
V_IL	Input LOW Voltage (IN, /IN)					0		V_IH-0.1	V
V_IN	Input Voltage Swing (IN, /IN)				See Figure 1a	0.1		1.7	V
V_DIFF\_IN	Differential Input Voltage Swing |IN, /IN|				See Figure 1b	0.2			mV
V_T-IN	IN to V_T (IN, /IN)							1.28	V
V_REF-AC	Reference Voltage					V_CC-1.3	V_CC-1.2	V_CC-1.1	V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Thermal performance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. _JB and _JA are shown for a 4-layer PCB in a still air environment, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. V_IH (min) not lower than 1.2V.

LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS ^(6)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to +85^ C ; R_L = 50 to V_CC-2V , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_OH	Output	HIGH Voltage	V				_CC^-1.145	V	_CC^-0.895	V
V_OL	Output	LOW Voltage	V				_CC^-1.945	V	_CC^-1.695	V
V_OUT		Output Differential Swing			See Figure 1a		550	800		mV
V_DIFF\_OUT		Differential Output Voltage Swing			See Figure 1b		1.1	1.6		V

LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS ^(6)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to 85^ C , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
V_IH	Input HIGH Voltage		2.0			V
V_IL	Input LOW Voltage				0.8	V
I_IH	Input HIGH Current		-125		40	μA
I_IL	Input LOW Current		-300			μA

Note:

1. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC ELECTRICAL CHARACTERISTICS ^(7)

V_CC = 2.5V ± 5% or 3.3V ± 10% ; T_A = -40^ C to 85^ C , R_L = 50 to V_CC - 2V , unless otherwise stated.

Symbol	Parameter	Condition	Min	Typ	Max	Units
f_MAX	Maximum Operating Frequency V			OUT ≥ 400mV 4.5 5.5 GHz
t_pd	Differential Propagation Delay (IN0 or IN1-to-Q) (SEL-to-Q)						170	240	320	ps
							100	220	400	ps
t_pd Tempco	Differential Propagation Delay Temperature Coefficient							70		fs/°C
t_SKEW	Output-to-Output Part-to-Part			Note 8					20	ps
				Note 9					100	ps
t_JITTER	RMS Phase Jitter			Output: 622MHz Integration Range: 12kHz to 20MHz				50		fs
	Adjacent Channel Crosstalk-Induced Jitter			Note 10					0.7	ps_rms
t_r, t_f	Output Rise/Fall Time			Full Swing, 20% to 80%			35		110	ps

Notes:
7. High frequency AC electricals are guaranteed by design and characterization.
8. Output-to-output skew is measured between outputs under identical transitions.
9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
10. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs.

PHASE NOISE

Phase Noise Plot: 622MHz @ 3.3V

SINGLE-ENDED AND DIFFERENTIAL SWINGS

V_IN, 800mV (Typ.) V_OUT

Figure 1a. Single-Ended Voltage Swing

VDIFF_IN VDIFF_OUT 1.6V (Typ.)

Figure 1b. Differential Voltage Swing

TIMING DIAGRAMS

IN /IN Q /Q Input-to-Q tpd SEL Vcc/2 Vcc/2 Q /Q tpd tpd SEL-to-Q tpd

TYPICAL OPERATING CHARACTERISTICS

V_CC = 2.5V , GND = 0, V_IN = 100mV , R_L = 50 to V_CC-2V ; T_A = 25^ , unless otherwise stated.

FUNCTIONAL CHARACTERISTICS

V_CC = 3.3V , GND = 0, V_IN = 100mV , R_L = 50 to V_CC - 2V ; T_A = 25^ , unless otherwise stated.

INPUT AND OUTPUT STAGES

VCC IN 50Ω VT 50Ω /GND /IN

Figure 2a. Simplified Differential Input Stage

VCC /Q Q

Figure 2b. Simplified LVPECL Output Stage

INPUT INTERFACE APPLICATIONS

VCC LVPECL IN /IN GND VCC 0.01μF Rpd SY58035U VREF-ACNC VT For 3.3V, Rpd = 50Ω For 2.5V, Rpd = 19Ω

Figure 3a. LVPECL Interface (DC-Coupled)

Vcc LVPECL IN Rpd Rpd GND VCC VREF-AC 0.01μF VT For 3.3V, Rpd = 100Ω For 2.5V, Rpd = 50Ω SY58035U

Figure 3b. LVPECL Interface (AC-Coupled)

VCC CML IN /IN GND NC □ VREF-AC NC □ VT Option: May connect VT to VCC SY58035U

Figure 3c. CML Interface (DC-Coupled)

VCC CML GND IN /IN SY58035U VCC 0.01μF VREF-AC VT

Figure 3d. CML Interface (AC-Coupled)

Vcc LVDS IN IN GND SY58035U NC □ VREF-AC NC □ VT

Figure 3e. LVDS Interface

OUTPUT INTERFACE APPLICATIONS

LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing, which results in low EMI. LVPECL is ideal driving 50Ω and 100Ω controlled impedance transmission lines. There are several techniques for terminating the LVECL output: parallel-thevenin equivalent

and parallel termination (3-resistor). Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.

+3.3V Z₀ = 50Ω Z₀ = 50Ω R1 130Ω +3.3V R1 130Ω +3.3V R2 82Ω R2 82Ω Note: For 2.5V systems: R1 = 250Ω,R2 = 62.5Ω

Figure 4a. Parallel Thevenin-Equivalent Termination

Z = 50Ω Z = 50Ω 50Ω 50Ω 50Ω Rb C1 0.01μF (optional) V3.3+V noit Note: For 2.5V systems: Rb = 19Ω

Figure 4b. Parallel Termination (3-Resistor)

RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION

Part Number	Function	Data Sheet Link
SY58034U	6GHz, 1:6 CML Fanout Buffer with 2:1MUX Input and Internal I/O Termination	http://www.micrel.com/product-info/products/sy58034u.shtml
SY58036U	6GHz, 1:6 400mV LVPECL Fanout Buffer with 2:1MUX Input and Internal Termination	http://www.micrel.com/product-info/products/sy58036u.shtml
	MLF® Application Note	www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf
HBW Solutions	New Products and Applications	www.micrel.com/product-info/products/solutions.shtml

32-PIN MicroLeadFrame® (MLF-32)

PIN #1 ID 0.20 DIA TYP. 32 1 2 ① 5.0 BSC 5.0 BSC

TOP VIEW

0.25±0.05 32X 0.50 BSC 32 0.20 MIN. 3.10±0.10 0.40±0.05 4X 3.10±0.10 PIN #1 ID R0.20

BOTTOM VIEW

SIDE VIEW
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. MAX. PACKAGE WARPAGE IS 0.05 mm.
3. MAXIMUM ALLOWABE BURRS IS 0.076 mm IN ALL DIRECTIONS.
4. PIN #1 ID ON TOP WILL BE LASER/INK MARKED.

Package EP- Exposed Pac Die CompSide Island Heat Dissipation Heat Dissipation Heavy Copper Plane Heavy Copper Plane V∞ V∞

PCB Thermal Consideration for 32-Pin MLF® Package
(Always solder, or equivalent, the exposed pad to the PCB)

Package Notes:

1. Package meets Level 2 qualification.
2. All parts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 [phone] FAX + 1 [phone] WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.

© 2005 Micrel, Incorporated.