MCP4023 - Potentiomètre numérique Microchip - Free user manual and instructions

USER MANUAL MCP4023 Microchip

Low-Cost NV Digital POT with WiperLock™ Technology

Features

• Nonvolatile Digital Potentiometer in SOT-23, SOIC, MSOP and DFN Packages
- 64 Taps: 63 Resistors with Taps to Terminal A and Terminal B
• Simple Up/Down (U/D) Protocol
• Power-on Recall of Saved Wiper Setting
• Resistance Values: 2.1 kΩ, 5 kΩ, 10 kΩ or 50 kΩ
- Low Tempco:
- Absolute (Rheostat): 50 ppm (0°C to 70°C Typ.)
- Ratiometric (Potentiometer): 10 ppm (Typ.)
- Low Wiper Resistance: 75 (Typ.)
- WiperLock™ Technology to Secure the wiper setting in nonvolatile memory (EEPROM)
• High-Voltage Tolerant Digital Inputs: up to 12.5V
- Low-Power Operation: 1 A Max Static Current
- Wide Operating Voltage: 2.7V to 5.5V
- Extended Temperature Range: -40^ to +125^
- Wide Bandwidth (-3 dB) Operation: - 4 MHz (Typ.) for 2.1 kΩ Device

Description

The MCP4021/2/3/4 devices are nonvolatile, 6-bit digital potentiometers that can be configured as either a potentiometer or rheostat. The wiper setting is controlled through a simple Up/Down (U/D) serial interface.

These device's implement Microchip's WiperLock technology, which allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin.

Package Types

MCP4021 SOIC, MSOP, DFN VDD 1 8 U/D VSS 2 7 NC A 3 6 B W 4 5 CS MCP4022 SOT-23-6 RheostatPotention VDD 1 A 6 A VSS 2 5 W U/D 3 B 4 CS MCP4023 SOT-23-6 Potentiometer VDD 1 A 6 A VSS 2 5 W U/D 3 B 4 CS MCP4024 SOT-23-5 Rheostat VDD 1 W 5 W VSS 2 B A 4 CS U/D 3 B 4 CS

Block Diagram

graph TD
    A["V_DD"] --> B["Power-Up and Brown-Out Control"]
    C["V_SS"] --> B
    D["CS"] --> E["2-Wire Interface and Control Logic"]
    F["U/D"] --> E
    B --> G["Wiper Register (Resistor Array)"]
    E --> G
    G --> H["A"]
    G --> I["W"]
    G --> J["B"]
    K["EEPROM and WiperLock Technology"] --> G

Device Features

Device	Wiper Configuration	Memory Type	Resistance (typical)		# of Steps	V_DD Operating Range	Control Interface	WiperLock Technology
			Options (kΩ)	Wiper (Ω)
MCP4021	Potentiometer (1)	EE	2.1, 5.0, 10.0, 50.0	75	64	2.7V - 5.5V	U/D	Yes
MCP4022	Rheostat	EE	2.1, 5.0, 10.0, 50.0	75	64	2.7V- 5.5V	U/D	Yes
MCP4023	Potentiometer	EE	2.1, 5.0, 10.0, 50.0	75	64	2.7V - 5.5V	U/D	Yes
MCP4024	Rheostat	EE	2.1, 5.0, 10.0, 50.0	75	64	2.7V - 5.5V	U/D	Yes

Note 1: Floating either terminal (A or B) allows the device to be used in Rheostat mode.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

V_DD 6.5V

and U/D inputs w.r.t V_SS -0.3V to 12.5V

A, B and W terminals w.r.t V_SS ____ -0.3V to V_DD + 0.3V

Current at Input Pins ....±10 mA

Current at Supply Pins ....±10 mA

Current at Potentiometer Pins ....±2.5 mA

Storage temperature -65^ to +150^

Ambient temp. with power applied ....-55°C to +125°C

ESD protection on all pins ....≥4 kV (HBM), ≥400V (MM)

Maximum Junction Temperature ( T_J ) .....+150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

AC/DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. T_A = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD = 5.5V, VSS = 0V,\(T_A = +25°C .
Parameters Sym Min Typ	Max Units		Conditions
Operating Voltage Range	V_DD	2.7	—	5.5	V
Input Voltage	V_CS	V_SS	—	12.5	V	The pin will be at one of three input levels ( V_IL, V_IH or V_IHH ). (Note 6)
Supply Current	I_DD	—	45	—	μA	5.5V, = V_SS, f_U/ = 1 MHz
		—	15	—	μA	2.7V, = V_SS, f_U/ = 1 MHz
		—	0.3	1	μA	Serial Interface Inactive ( = V_IH, U/ = V_IH )
		—	0.6	3	mA	EE Write cycle, T_A = +25°C
Resistance(± 20%)	R_AB	1.68	2.1	2.52	kΩ	-202 devices (Note 1)
		4.0	5	6.0	kΩ	-502 devices (Note 1)
		8.0	10	12.0	kΩ	-103 devices (Note 1)
		40.0	50	60.0	kΩ	-503 devices (Note 1)
Resolution	N	64			Taps	No Missing Codes
Step Resistance	R_S	—	R_AB/63	—	Ω	Note 6

Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at V_W with V_A = V_DD and V_B = V_SS . (-202 devices V_A = 4V ).
3: MCP4021/23 only, test conditions are: I_W = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:

Device Resistance	Current at Voltage		Comments
	5.5V	2.7V
2.1 kΩ	2.25 mA	1.1 mA	MCP4022 includes V_WZSE MCP4024 includes V_WFSE
5 kΩ	1.4 mA	450 μA
10 kΩ	450 μA	210 μA
50 kΩ	90 μA	40 μA

5: Resistor terminals A, W and B's polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance ( R_W ), which changes significantly over voltage and temperature. See Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. T_A = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD = 5.5V, VSS = 0V,\(T_A = +25°C .
Parameters	Sym	Min	Typ	Max	Units	Conditions
Wiper Resistance (Note 3, Note 4)	R_W	—70	125 Ω 5.5V
		—70	325 Ω 2.7V
Nominal Resistance Tempco	R/ T	—	50	—	ppm/°C	T_A = -20°C to +70°C
		—100	— ppm/°CT			A = -40°C to +85°C
		—150	— ppm/°CT			A = -40°C to +125°C
Ratiometeric Tempco V	W_A/ T	—	10	—	ppm/°C	MCP4021 and MCP4023 only, code = 1Fh
Full-Scale Error	V_WFSE	-0.5	-0.1	+0.5	LSb	Code 3Fh (MCP4021/23 only)
Zero-Scale Error	V_WZSE	-0.5	+0.1	+0.5	LSb	Code 00h (MCP4021/23 only)
Monotonicity	N	Yes			Bits
Potentiometer Integral Non-linearity	INL	-0.5	±0.25	+0.5	LSb	MCP4021/23 only (Note 2)
Potentiometer Differential Nonlinearity	DNL	-0.5	±0.25	+0.5	LSb	MCP4021/23 only (Note 2)
Resistor Terminal Input Voltage Range (Terminals A, B and W)	V_A,V_W,V_B	Vss —	V	DD	V	Note 5, Note 6
Maximum current through A, W or B	I_W	—	—	2.5	mA	Note 6
Leakage current into A, W or B	I_WL	—100	— nA	MCP4021 A = W = B = V
		—100	— nA	MCP4022/23 A = W = V
		—100	— nA	MCP4024 W = V
Capacitance ( P_A )	C_AW	—75	— pF	f=1 MHz, code = 1Fh
Capacitance ( P_w )	C_W	—120	— pF	f=1 MHz, code = 1Fh
Capacitance ( P_B )	C_BW	—75	— pF	f=1 MHz, code = 1Fh
Bandwidth -3 dB	BW	—	4	—	MHz	-202 devices	Code = 1F, output load = 30 pF
		—	2	—	MHz	-502 devices
		—	1	—	MHz	-103 devices
		—200	— kHz	-503		devices

Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at V_W with V_A = V_DD and V_B = V_SS . (-202 devices V_A = 4V ).
3: MCP4021/23 only, test conditions are: I_W = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:

Device Resistance	Current at Voltage		Comments
	5.5V	2.7V
2.1 kΩ	2.25 mA	1.1 mA	MCP4022 includes V_WZSE MCP4024 includes V_WFSE
5 kΩ	1.4 mA	450 μA
10 kΩ	450 μA	210 μA
50 kΩ	90 μA	40 μA

5: Resistor terminals A, W and B's polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance ( R_W ), which changes significantly over voltage and temperature. See Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. T_A = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD = 5.5V, V_SS = 0V, T_A = +25°C .
Parameters	Sym	Min	Typ	Max	Units	Conditions
Rheostat Integral Non-linearityMCP4021 (Note 4, Note 8)MCP4022 and MCP4024 (Note 4)	R-INL	-0.5 ±0.	.25 +0.5 L	Sb -202		devices(2.1 kΩ)	5.5V
		-8.5 +4	.5 +8.5 LSb	2.7V (Note 7)
		-0.5 ±0.	.25 +0.5 L	Sb -502		devices(5 kΩ)	5.5V
		-5.5 +2	.5 +5.5 LSb	2.7V (Note 7)
		-0.5 ±0.	.25 +0.5 L	Sb -103		devices(10 kΩ)	5.5V
		-3 +1	+3 LSb 2.7V (Note 7)
		-0.5 ±0.	.25 +0.5 L	Sb -503		devices(50 kΩ)	5.5V
		-1 +0.	.25 +1 LSb	2.7V (Note 7)
Rheostat Differential Non-linearityMCP4021 (Note 4, Note 8)MCP4022 and MCP4024 (Note 4)	R-DNL	-0.5 ±0.	.25 +0.5 L	Sb -202		devices(2.1 kΩ)	5.5V
		-1 +0.5	+2 LSb 2.7V (Note 7)
		-0.5 ±0.	.25 +0.5 L	Sb -502		devices(5 kΩ)	5.5V
		-1	+0.25	+1.25	LSb		2.7V (Note 7)
		-0.5 ±0.	.25 +0.5 L	Sb -103		devices(10 kΩ)	5.5V
		-1	0	+1	LSb		2.7V (Note 7)
		-0.5 ±0.	.25 +0.5 L	Sb -503		devices(50 kΩ)	5.5V
		-0.5	0	+0.5	LSb		2.7V (Note 7)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at V_W with V_A = V_DD and V_B = V_SS . (-202 devices V_A = 4V ).
3: MCP4021/23 only, test conditions are: I_W = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:

Device Resistance	Current at Voltage		Comments
	5.5V	2.7V
2.1 kΩ	2.25 mA	1.1 mA	MCP4022 includes V_WZSE MCP4024 includes V_WFSE
5 kΩ	1.4 mA	450 μA
10 kΩ	450 μA	210 μA
50 kΩ	90 μA	40 μA

5: Resistor terminals A, W and B's polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance ( R_W ), which changes significantly over voltage and temperature. See Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. T_A = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD = 5.5V, V_SS = 0V,\(T_A = +25°C .
Parameters	Sym	Min	Typ	Max	Units	Conditions
Digital Inputs/Outputs (CS, U/D)
Input High Voltage V	IH	0.7 V_DD	—	—	V
Input Low Voltage V	IL	—	—	0 DD	V 3	V
High-Voltage Input Entry Voltage(Threshold for WiperLock Technology)	V_IHH	8.5^(9)	—	1 (6) 2	V +7°C to 5125°C
		9.0 —	12.5	(6)	V -40°C to +125°C
High-Voltage Input Exit Voltage V	IHH	—	—	V_DD+0.8^(6)	V
Pull-up/Pull-down Resistance	R_CS	—	16	—	kΩ	V_DD=5.5V, V_CS=3V
Weak Pull-up/Pull-down Current	I_PU	— 170	—	μA	V	D_D=5.5V, V_CS=3V
Input Leakage Current	I_IL	-1	—	1	μA	V_IN=V_DD
and U/D Pin Capacitance	C_IN, C_OUT	—	10	—	pF	f_C=1 MHz
RAM (Wiper) Value
Value Range	N	0h	—	3Fh	hex
EEPROM
Endurance	E_ndurance	—	1M	—	Cycles
EEPROM Range	N	0h	—	3Fh	hex
Initial Factory Setting	N	1Fh			hex	WiperLock Technology = Off
Power Requirements
Power Supply Sensitivity(MCP4021 and MCP4023 only)	PSS	—	0.0015	0.0035	%/%	V_DD=4.5V to 5.5V, V_A=4.5V,Code=1Fh
		—	0.0015	0.0035	%/%	V_DD=2.7V to 4.5V, V_A=2.7V,Code=1Fh

Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at V_W with V_A = V_DD and V_B = V_SS . (-202 devices V_A = 4V ).
3: MCP4021/23 only, test conditions are: I_W = 1.9 mA, code = 00h.
4: MCP4022/24 only, test conditions are:

Device Resistance	Current at Voltage		Comments
	5.5V	2.7V
2.1 kΩ	2.25 mA	1.1 mA	MCP4022 includes V_WZSE MCP4024 includes V_WFSE
5 kΩ	1.4 mA	450 μA
10 kΩ	450 μA	210 μA
50 kΩ	90 μA	40 μA

5: Resistor terminals A, W and B's polarity with respect to each other is not restricted.
6: This specification by design
7: Non-linearity is affected by wiper resistance ( R_W ), which changes significantly over voltage and temperature. See Section 6.0, "Resistor" for additional information.
8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
9: This parameter is not tested, but specified by characterization.

CS U/D W tLUC tLCUF tLO 1/fUD tHI tLCUR tS tCSLO tCSHI tLUC tLCUF ts ts

FIGURE 1-1: Increment Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): V_DD=+2.7V to 5.5V, T_A=-40°C to +125°C .
Parameters Sym Min	Typ Max Units Conditions
Low Time t	CSLO	5	—	—	μ	s
High Time t	CSHI	500	—	—	ns
U/ to Hold Time	t_LUC	500	—	—	ns
to U/ Low Setup Time t	LCUF	500	—	—	ns
to U/ High Setup Time	t_CUR	3	—	—	μ	s
U/ High Time	t_HI	500	—	—	ns
U/ Low Time	t_LO	500	—	—	ns
Up/Down Toggle Frequency	f_UD	—	—	1	MHz
Wiper Settling Time	t_S	0.5	—	—	μs	2.1 kΩ, C_L=100 pF
		1	—	—	μs	5 kΩ, C_L=100 pF
		2	—	—	μs	10 kΩ, C_L=100 pF
		10	5	—	μs	50 kΩ, C_L=100 pF
Wiper Response on Power-Up	t_PU	—	200	—	ns
Internal EEPROM Write Time	twc	—	—	5	ms	@25°C
		—	—	10	ms	-40°C to +125°C

CS U/D W tLUC tLCUR tHI 1/fUD tLO ts tCSLO tCSHI tLUC tLCUF ts

FIGURE 1-2: Decrement Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): V_DD=+2.7V to 5.5V, T_A=-40°C to +125°C .
Parameters Sym Min	Typ Max Units Conditions
Low Time t	CSLO	5	—	—	μ	s
High Time	t_CSHI	500	—	—	ns
U/D to Hold Time	t_LUC	500	—	—	ns
to U/D Low Setup Time t	LCUF	500	—	—	ns
to U/D High Setup Time	t_LCUR	3	—	—	μ	s
U/D High Time	t_HI	500	—	—	ns
U/D Low Time	t_LO	500	—	—	ns
Up/Down Toggle Frequency	f_UD	—	—	1	MHz
Wiper Settling Time	t_S	0.5	—	—	μs	2.1 kΩ, C_L=100 pF
		1	—	—	μs	5 kΩ, C_L=100 pF
		2	—	—	μs	10 kΩ, C_L=100 pF
		10	5	—	μs	50 kΩ, C_L=100 pF
Wiper Response on Power-Up	t_PU	—	200	—	ns
Internal EEPROM Write Time	twc	—	—	5	ms	@25°C
		—	—	10	ms	-40°C to +125°C

CS 12V 5V tHUC tHCUF tLO 1/fUD U/D tHCUR tHI W tCSLO tCSHI tHUC tHCUF tS

FIGURE 1-3: High-Voltage Increment Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): V_DD=+2.7V to 5.5V, T_A=-40°C to +125°C .
Parameters Sym Min	Typ Max Units Conditions
Low Time t	CSLO	5	—	—	μ	s
High Time t	CSHI	500 —	—	ns
U/D High Time	t_HI	500 —	—	ns
U/D Low Time	t_LO	500 —	—	ns
Up/Down Toggle Frequency	f_UD	—	—	1	MHz
HV U/D to CS Hold Time	t_HUC	1.5	—	—	μs
HV CS to U/D Low Setup Time	t_HCUF	8	—	—	μ	s
HV CS to U/D High Setup Time	t_HCUR	4.5	—	—	μs
Wiper Settling Time	t_S	0.5	—	—	μs	2.1 kΩ, C_L=100 pF
		1	—	—	μs	5 kΩ, C_L=100 pF
		2	—	—	μs	10 kΩ, C_L=100 pF
		10	5	—	μs	50 kΩ, C_L=100 pF
Wiper Response on Power-Up	t_PU	—	200	—	ns
Internal EEPROM Write Time	twc	—	—	5	ms	@25°C
		—	—	10 ms	-40°C to +125°C

CS 12V 5V U/D W tHUC tHI tHCUR tLO ts 1/fUD tHUC tHCUF tCSLO tCSHI tsLO ts

FIGURE 1-4: High-Voltage Decrement Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): V_DD=+2.7V to 5.5V, T_A=-40°C to +125°C .
Parameters Sym Min	Typ Max Units Conditions
Low Time t	CSLO	5	—	—	μ	s
High Time t	CSHI	500	—	—	ns
U/D High Time	t_HI	500	—	—	ns
U/D Low Time	t_LO	500	—	—	ns
Up/Down Toggle Frequency	f_UD	—	—	1	MHz
HV U/D to Hold Time	t_HUC	1.5	—	—	μs
HV to U/D Low Setup Time	t_HCUF	8	—	—	μ	s
HV to U/D High Setup Time	t_HCUR	4.5	—	—	μs
Wiper Settling Time	t_S	0.5	—	—	μs	2.1 kΩ, C_L=100 pF
		1	—	—	μs	5 kΩ, C_L=100 pF
		2	—	—	μs	10 kΩ, C_L=100 pF
		10	5	—	μs	50 kΩ, C_L=100 pF
Wiper Response on Power-Up	t_PU	—	200	—	ns
Internal EEPROM Write Time	twc	—	—	5	ms	@25°C
		—	—	10	ms	-40°C to +125°C

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD = +2.7V to +5.5V , V_SS = G N D .
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range T	A	-40 —	+125 °C
Operating Temperature Range T	A	-40 —	+125 °C
Storage Temperature Range	T_A	-65 —	+150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23	θ_JA	—	255	—	°C/W
Thermal Resistance, 6L-SOT-23	θ_JA	—	230	—	°C/W
Thermal Resistance, 8L-DFN (2x3)	θ_JA	—	85	—	°C/W
Thermal Resistance, 8L-MSOP	θ_JA	—	206	—	°C/W
Thermal Resistance, 8L-SOIC θ	JA	—	117	—	°C/W

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A=+25^ , V_DD=5V , V_SS=0V .

FIGURE 2-1: Device Current (I DD ) vs. U/D Frequency ( fU/D ) and Ambient Temperature ( V_DD = 2.7V and 5.5V).

FIGURE 2-4: CS Pull-up/Pull-down Resistance ( R_CS ) and Current ( I_CS ) vs. CS Input Voltage ( V_CS ) ( V_DD = 5.5V ).

FIGURE 2-2: Write Current (I WRITE) vs. Ambient Temperature and V_DD .

FIGURE 2-5: CS High Input Entry/Exit Threshold vs. Ambient Temperature and V_DD .

FIGURE 2-3: Device Current (I SHDN) vs. Ambient Temperature and V_DD . ( = V_DD) .

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-6: 2.1 k Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-8: 2.1 k ΩRheo Mode - R_W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-7: 2.1 k Ω Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

FIGURE 2-9: 2.1 k ΩRheo Mode - R_W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

Note: Unless otherwise indicated, T_A = +25^ C , V_DD = 5V , V_SS = 0V .

FIGURE 2-10: 2.1 k Ω-Nominal

Resistance ( ) vs. Ambient Temperature and V_DD .

FIGURE 2-11: 2.1 k -R_WB() vs. Wiper Setting and Ambient Temperature.

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-12: 2.1 k Ω-Low-Voltage Decrement Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-15: 2.1 k -Low-Voltage Increment Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-13: 2.1 k Ω-Low-Voltage Decrement Wiper Settling Time ( V_DD = 5.5V ).

FIGURE 2-16: 2.1 k -Low-Voltage Increment Wiper Settling Time ( V_DD = 5.5V ).

FIGURE 2-14: 2.1 k Ω-Power-Up Wiper Response Time.

Note: Unless otherwise indicated, T_A=+25^ , V_DD=5V , V_SS=0V .

FIGURE 2-17: 5 k Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-19: 5 k Ω Rheo Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-18: 5 k Ω Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

FIGURE 2-20: 5 k Ω Rheo Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-21: 5 k -Nominal Resistance ( ) vs. Ambient Temperature and V_DD .

FIGURE 2-22: 5 k - R_WB() vs. Wiper Setting and Ambient Temperature.

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-23: 5 k Ω - Low-Voltage Decrement Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-25: 5 k Ω - Low-Voltage Increment Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-24: 5 k Ω - Low-Voltage Decrement Wiper Settling Time ( V_DD = 5.5V ).

FIGURE 2-26: 5 k Ω - Low-Voltage Increment Wiper Settling Time ( V_DD = 5.5V ).

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-27: 10 k Ω Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-29: 10 k Ω Rheo Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-28: 10 k Ω Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

FIGURE 2-30: 10 k Ω Rheo Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-31: 10 k Ω-Nominal Resistance (Ω) vs. Ambient Temperature and V_DD .

FIGURE 2-32: 10 k - R_WB () vs. Wiper Setting and Ambient Temperature.

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-33: 10 k Ω - Low-Voltage Decrement Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-35: 10 k Ω - Low-Voltage Increment Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-34: 10 k Ω - Low-Voltage Decrement Wiper Settling Time ( V_DD = 5.5V ).

FIGURE 2-36: 10 k Ω - Low-Voltage Increment Wiper Settling Time ( V_DD = 5.5V ).

Note: Unless otherwise indicated, T_A=+25^ , V_DD=5V , V_SS=0V .

FIGURE 2-37: 50 k Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-39: 50 k Ω Rheo Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 5.5V ).

FIGURE 2-38: 50 k Ω Pot Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

FIGURE 2-40: 50 k Ω Rheo Mode - R_W() , INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature ( V_DD = 2.7V ).

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-41: 50 k Ω-Nominal Resistance
(Ω) vs. Ambient Temperature and V_DD .

FIGURE 2-42: 50 k - R_WB () vs. Wiper
Setting and Ambient Temperature.

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-43: 50 k Ω - Low-Voltage Decrement Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-46: 50 k Ω - Low-Voltage Increment Wiper Settling Time ( V_DD = 2.7V ).

FIGURE 2-44: 50 k Ω - Low-Voltage Decrement Wiper Settling Time ( V_DD = 5.5V ).

FIGURE 2-47: 50 k Ω - Low-Voltage Increment Wiper Settling Time ( V_DD = 5.5V ).

FIGURE 2-45: 50 k Ω – Power-Up Wiper Response Time.

Note: Unless otherwise indicated, T_A = +25^ , V_DD = 5V , V_SS = 0V .

FIGURE 2-48: -3 dB Bandwidth vs. Temperature.

V_IN OFFSET GND A DUT B W +5V - 2.5V DC V_OUT

FIGURE 2-49: -3 dB Bandwidth Test Circuit.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin Number			Symbol	Pin Type	Buffer Type	Function
MCP4021(SOIC-8)	MCP4022MCP4023(SOT-23-6)	MCP4024(SOT-23-5)
1	1	1	V_DD	P — Positive Power Supply Input
2	2	2	V_SS	P — Ground
3 6 —	A I/O	A Potentiometer	Terminal	A
4	5	5	W	I/O	A	Potentiometer Wiper Terminal
5	4	4		I	TTL	Chip Select Input
6	—	—	B	I/O	A	Potentiometer Terminal B
7	—	—	NC	—	—	No Connection
8	3	3	/D	I	TTL	Increment/ Input

Legend: TTL = TTL compatible input A = Analog input
I = Input O = Output
P = Power

3.1 Positive Power Supply Input (V DD)

The V_DD pin is the device's positive power supply input. The input power supply is relative to V_SS and can range from 2.7V to 5.5V. A decoupling capacitor on V_DD (to V_SS ) is recommended to achieve maximum performance.

3.2 Ground (V ss)

The V_SS pin is the device ground reference.

3.3 Potentiometer Terminal A

The terminal A pin is connected to the internal potentiometer's terminal A (available on some devices). The potentiometer's terminal A is the fixed connection to the 0x3F terminal of the digital potentiometer.

The terminal A pin is available on the MCP4021, MCP4022 and MCP4023 devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on terminal A must be between V_SS and V_DD .

The terminal A pin is not available on the MCP4024. The potentiometer's terminal A is internally floating.

3.4 Potentiometer Wiper (W) Terminal

The terminal W pin is connected to the internal potentiometer's terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on terminal W must be between V_SS and V_DD .

3.5 Potentiometer Terminal B

The terminal B pin is connected to the internal potentiometer's terminal B (available on some devices). The potentiometer's terminal B is the fixed connection to the 0x00 terminal of the digital potentiometer.

The terminal B pin is available on the MCP4021 device. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between V_SS and V_DD .

The terminal B pin is not available on the MCP4022, MCP4023 and MCP4024 devices.

For the MCP4023 and MCP4024, the internal potentiometer's terminal B is internally connected to V_SS . Terminal B does not have a polarity relative to terminals W or A. Terminal B can support both positive and negative current.

For the MCP4022, terminal B is internally floating.

3.6 Chip Select (CS)

The pin is the chip select input. Forcing the pin to V_IL enables the serial commands. These commands can increment and decrement the wiper. Depending on the command, the wiper may (or may not) be saved to nonvolatile memory (EEPROM). Forcing the pin to V_IHH enables the high-voltage serial commands. These commands can increment and decrement the wiper and enable or disable the WiperLock technology. The wiper is saved to nonvolatile memory (EEPROM).

The pin has an internal pull-up resistor. The resistor will become “disabled” when the voltage on the pin is below the V_IH level. This means that when the pin is “floating”, the pin will be pulled to the V_IH level (serial communication (the U/D pin) is ignored). And when the pin is driven low ( V_IL ), the resistance becomes very large to reduce the device current consumption when serial commands are occurring. See Figure 2-4 for additional information.

3.7 Increment/Decrement (U/D)

The U/D pin input is used to increment or decrement the wiper on the digital potentiometer. An increment moves the wiper one step toward terminal A, while a decrement moves the wiper one step toward terminal B.

4.0 GENERAL OVERVIEW

The MCP402X devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired.

Applications generally suited for the MCP402X devices include:

• Set point or offset trimming
• Sensor calibration
• Selectable gain and offset amplifier designs
• Cost-sensitive mechanical trim pot replacement

The digital potentiometer is available in four nominal resistances ( R_AB ), where the nominal resistance is defined as the resistance between terminal A and terminal B. The four nominal resistances are 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ.

There are 63 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 63 resistors thus providing 64 possible settings (including terminal A and terminal B).

Figure 4-1 shows a block diagram for the resistive network of the device. Equation 4-1 shows the calculation for the step resistance, while Equation 4-2 illustrates the calculation used to determine the resistance between the wiper and terminal B.

A N = 63 3Fh Rs N = 62 3Eh Rs N = 61 3Dh Rs N = 1 01h Rs N = 0 00h B Analog Mux

Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. This variation effects the smaller resistance devices (2.1 kΩ) more.
FIGURE 4-1: Resistor Block Diagram.

EQUATION 4-1: R S CALCULATION

$$ R _ {S} \quad \frac {R _ {A B}}{6 3} $$

EQUATION 4-2: R WB CALCULATION

$$ R _ {W B} = \frac {R _ {A B} N}{6 3} R _ {W} $$

$$ N = 0 \text { to } 6 3 (\text { decimal }) $$

1 LSb is the ideal resistance difference between two successive codes. If we use N = 1 and R_W = 0 in Equation 4-2, we can calculate the step size for each increment or decrement command.

The MCP4021 device offers a voltage divider (potentiometer) with all terminals available on pins.

The MCP4022 is a true rheostat, with terminal A and the wiper (W) of the variable resistor available on pins.

The MCP4023 device offers a voltage divider (potentiometer) with terminal B connected to ground.

The MCP4024 device is a rheostat device with terminal A of the resistor floating, terminal B connected to ground, and the wiper (W) available on pin.

The MCP4021 can be externally configured to implement any of the MCP4022, MCP4023 or MCP4024 configurations.

4.1 Serial Interface

A 2-wire synchronous serial protocol is used to increment or decrement the digital potentiometer's wiper terminal. The Increment/Decrement (U/D) protocol utilizes the CS and U/D input pins. Both inputs are tolerant of signals up to 12.5V without damaging the device. The CS pin can differentiate between two high-voltage levels, V_IH and V_IHH . This enables additional commands without requiring additional input pins. The high-voltage commands ( V_IHH on the CS pin) are similar to the standard commands, except that they control (enable, disable, ...) the state of the nonvolatile WiperLock technology feature.

The simple U/D protocol uses the state of the U/D pin at the falling edge of the CS pin to determine if Increment or Decrement mode is desired. Subsequent rising edges of the U/D pin move the wiper.

The wiper value will not underflow or overflow. The new wiper setting can be saved to EEPROM, if desired, by selecting the state of the U/D pin during the rising edge of the CS pin.

The nonvolatile wiper enables the MCP4021/2/3/4 to operate stand alone (without microcontroller control).

4.2 The WiperLock Technology

The MCP4021/2/3/4 device's WiperLock technology allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin.

The WiperLock technology prevents the serial commands from doing the following:

• Incrementing or decrementing the wiper setting
• Writing the wiper setting to the nonvolatile memory

Enabling and disabling the WiperLock technology feature requires high-voltage serial commands ( = V_IHH ). Incrementing and decrementing the wiper requires high-voltage commands when the feature is enabled. The high-voltage threshold ( V_IHH ) is intended to prevent the wiper setting from being altered by noise or intentional transitions on the U/D and pins, while still providing flexibility for production or calibration environments.

Both the and U/D input pins are tolerant of signals up to 12V. This allows the flexibility to multiplex the digital pot's control signals onto application signals for manufacturing/calibration.

4.3 Power-up

When the device powers up, the last saved wiper setting is restored.

While V_DD < V_min (2.7V), the electrical performance may not meet the data sheet specifications (see Figure 4-2). The wiper may be unknown or initialized to the value stored in the EEPROM. Also the device may be capable of incrementing, decrementing and writing to its EEPROM, if a valid command is detected on the CS and U/D pins.

The default settings of the MCP4021/2/3/4 device's from the factory are shown in Table 4-1.

TABLE 4-1: DEFAULT FACTORY SETTINGS SELECTION

Package Code	Default POR Wiper Setting	Wiper Code	WiperLoc Technology Setting	Typical RAB Value
-202	Mid-scale 1Fh	Disabled	2.1 kΩ
-502	Mid-scale 1Fh	Disabled	5.0 kΩ
-103	Mid-scale 1Fh	Disabled	10.0 kΩ
-503	Mid-scale 1Fh	Disabled	50.0 kΩ

It is good practice in your manufacturing flow to configure the device to your desired settings.

4.4 Brown-Out

If the device V_DD is below the specified minimum voltage, care must be taken to ensure that the CS and U/D pins do not “create” any of the serial commands.

When the device V_DD drops below V_min (2.7V), the electrical performance may not meet the data sheet specifications (see Figure 4-2). The wiper may be unknown or initialized to the value stored in the EEPROM. Also the device may be capable of incrementing, decrementing and writing to its EEPROM if a valid command is detected on the CS and U/D pins.

4.5 Serial Interface Inactive

The serial interface is inactive any time the pin is at V_IH and all write cycles are completed.

FIGURE 4-2: Power-up and Brown-out.

5.0 SERIAL INTERFACE

5.1 Overview

The MCP4021/2/3/4 utilizes a simple 2-wire interface to increment or decrement the digital potentiometer's wiper terminal (W), store the wiper setting in nonvolatile memory and turn the WiperLock technology feature on or off. This interface uses the Chip Select (CS) pin, while the U/D pin is the Up/Down input.

The Increment/Decrement protocol enables the device to move one step at a time through the range of possible resistance values. The wiper value is initialized with the value stored in the internal EEPROM upon power-up. A wiper value of 00h connects the wiper to terminal B. A wiper value of 3Fh connects the wiper to terminal A. Increment commands move the wiper toward terminal A, but will not increment to a value greater than 3Fh. Decrement commands move the wiper toward terminal B, but will not decrement below 00h.

Refer to Section 1.0 "Electrical Characteristics", AC/DC Electrical Characteristics table for detailed input threshold and timing specifications.

Communication is unidirectional. Therefore, the value of the current wiper setting cannot be read out of the MCP402X device.

5.2 Serial Commands

The MCP402X devices support 10 serial commands. The commands can be grouped into the following types:

• Serial Commands
  • High-voltage Serial Commands

All the commands are shown in Table 5-1.

The command type is determined by the voltage level on the pin. The initial state that the pin must be driven is V_IH . From V_IH , the two levels that the pin can be driven are:

If the pin is driven from V_IH to , a serial command is selected. If the pin is driven from V_IH to V_IHH , a high-voltage serial command is selected.

High-voltage serial commands control the state of the WiperLock technology. This is a unique feature, where the user can determine whether or not to "lock" or "unlock" the wiper state.

High-voltage serial commands increment/decrement the wiper regardless of the status of the WiperLock technology.

TABLE 5-1: COMMANDS

Command Name	Saves Wiper Value in EEPROM	High Voltage on CS pin?	After Command Wiper is “locked”/ ” unlocked”	Works when Wiper is “locked”?
Increment without Writing Wiper Setting to EEPROM	—	—	unlocked	Note 1
Increment with Writing Wiper Setting to EEPROM	Yes	—	unlocked	Note 1
Decrement without Writing Wiper Setting to EEPROM	—	—	unlocked	Note 1
Decrement with Writing Wiper Setting to EEPROM	Yes	—	unlocked	Note 1
Write Wiper Setting to EEPROM	Yes	—	unlocked	Note 1
High-Voltage Increment and Disable WiperLock Technology	Yes	Yes	unlocked	Yes
High-Voltage Increment and Enable WiperLock Technology	Yes	Yes	locked	Yes
High-Voltage Decrement and Disable WiperLock Technology	Yes	Yes	unlocked	Yes
High-Voltage Decrement and Enable WiperLock Technology	Yes	Yes	locked	Yes
Write Wiper Setting to EEPROM and Disable WiperLock Technology	Yes	Yes	unlocked	Yes
Write Wiper Setting to EEPROM and Enable WiperLock Technology	Yes	Yes	locked	Yes

Note 1: This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled).

5.2.1 INCREMENT WITHOUT WRITING WIPER SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a high state ( V_IH ) prior to achieving a low state ( V_IL ) on the CS pin. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. This is shown in Figure 5-1.

After the wiper is incremented to the desired position, the pin should be forced to V_IH to ensure that "unexpected" transitions (on the U/D pin do not cause the wiper setting to increment. Driving the pin to V_IH should occur as soon as possible (within device specifications) after the last desired increment occurs.

The EEPROM value has not been updated to this new wiper value, so if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with the wiper setting in the EEPROM.

After the pin is driven to V_IH (from V_IL ), any other serial command may immediately be entered. This is since an EEPROM write cycle ( t_wc ) is not active.

Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored.

Note: If WiperLock technology enabled, wiper will not move.

FIGURE 5-1: Increment without Writing Wiper Setting to EEPROM.

5.2.2 INCREMENT WITH WRITING WIPER SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a high state ( V_IH ) prior to achieving a low state ( V_IL ) on the CS pin. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. This is shown in Figure 5-2.

After the wiper is incremented to the desired position, the U/D pin should be driven low ( V_IL ). Then when the CS pin is forced to V_IH , the wiper value is written to the EEPROM. Therefore, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the EEPROM).

To ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment, the U/D pin should be driven low and the CS pin forced to V_IH as soon as possible (within device specifications) after the last desired increment occurs.

After the pin is driven to V_IH (from V_IL ), all other serial commands are ignored until the EEPROM write cycle ( t_wc ) completes.

Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored.

Note: If WiperLock technology enabled, wiper will not move.

FIGURE 5-2: Increment with Writing Wiper Setting to EEPROM.

5.2.3 DECREMENT WITHOUT WRITING WIPER SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a low state ( V_IL ) prior to achieving a low state ( V_IL ) on the CS pin. Subsequent rising edges of the U/D pin will decrement the wiper setting toward terminal B. This is shown in Figure 5-3.

After the wiper is decremented to the desired position, the U/D pin should be forced low ( V_IL ) and the CS pin should be forced to V_IH . This will ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to decrement. Driving the CS pin to V_IH should occur as soon as possible (within device specifications) after the last desired increment occurs.

The EEPROM value has not been updated to this new wiper value, so, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with the wiper setting in the EEPROM.

After the pin is driven to V_IH (from V_IL ), any other serial command may immediately be entered, since an EEPROM write cycle ( t_WC ) is not started.

Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored.

Note: If WiperLock technology enabled, wiper will not change.

FIGURE 5-3: Decrement without Writing Wiper Setting to EEPROM.

5.2.4 DECREMENT WITH WRITING WIPER SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a low state ( V_IL ) prior to achieving a low state ( V_IL ) on the CS pin. Subsequent rising edges of the U/D pin decrement the wiper setting (toward terminal B). This is shown in Figure 5-4.

After the wiper is decremented to the desired position, the U/D pin should remain high ( V_IH ). Then when the CS pin is raised to V_IH , the wiper value is written to the EEPROM. Therefore, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the EEPROM).

To ensure that "unexpected" transitions on the U/D pin do not cause the wiper setting to decrement, the U/D pin should be driven low ( V_IL ) and the CS pin forced to V_IH as soon as possible (within device specifications) after the last desired increment occurs.

After the pin is driven to V_IH (from V_IL ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored.

Note: If WiperLock technology enabled, wiper will not change.

FIGURE 5-4: Decrement with Writing Wiper Setting to EEPROM.

5.2.5 WRITE WIPER SETTING TO EEPROM

To write the current wiper setting to EEPROM, force both the pin and U/D pin to V_IH . Then force the pin to V_IL . Before there is a rising edge on the U/D pin, force the pin to V_IH . This causes the wiper setting value to be written to EEPROM.

Note: After the U/D pin is forced to V _IL , each rising edge on the U/D pin will cause the wiper to increment.

This is the same command as the "Increment with Writing Wiper Setting to EEPROM" command, but the U/D pin is held at V_IL , so the wiper is not incremented.

When the pin is forced to V_IH , the wiper value is written to the EEPROM. Therefore, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the EEPROM).

To ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment, force the CS pin to V_IH as soon as possible (within device specifications) after the U/D pin is forced to V_IL .

After the pin is driven to V_IH (from V_IL ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

CS V_IH V_IL t_WC U/D V_IH 5 6 V_IL EEPROM X X+4 Wiper X+4 WiperLock Technology Enable WiperLock Technology WiperLock Technology Disable

FIGURE 5-5: Write Wiper Setting to EEPROM.

5.2.6 HIGH-VOLTAGE INCREMENT AND DISABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to a high state ( V_IH ) prior to the CS pin being driven to V_IHH . Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. Set the U/D pin to the high state ( V_IH ) prior to forcing the CS pin to V_IH . This begins a write cycle and disables the WiperLock technology feature (See Figure 5-6).

After the pin is driven to V_IH (from V_IIHH ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored.

FIGURE 5-6: High-Voltage Increment and Disable WiperLock Technology.

5.2.7 HIGH-VOLTAGE INCREMENT AND ENABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to a high state ( V_IH ) prior to the CS pin being driven to V_IHH . Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. Set the U/D pin to the low state ( V_IL ) prior to forcing the CS pin to V_IH . This begins a write cycle and enables the WiperLock technology feature (See Figure 5-7).

After the pin is driven to V_IH (from V_IIHH ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored.

FIGURE 5-7: High-Voltage Increment and Enable WiperLock Technology.

5.2.8 HIGH-VOLTAGE DECREMENT AND DISABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to a low state ( V_IL ) prior to the CS pin being driven to V_IHH . Subsequent rising edges of the U/D pin decrement the wiper setting toward terminal B. Set the U/D pin to the low state ( V_IL ) prior to forcing the CS pin to V_IH . This begins a write cycle and disables the WiperLock Technology feature (See Figure 5-8).

After the pin is driven to V_IH (from V_IIHH ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored.

FIGURE 5-8: High-Voltage Decrement and Disable WiperLock Technology.

5.2.9 HIGH-VOLTAGE DECREMENT AND ENABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to the low state ( V_IL ) prior to driving the CS pin to V_IHH . Subsequent rising edges of the U/D pin decrement the wiper setting toward terminal B. Set the U/D pin to a high state ( V_IH ) prior to forcing the CS pin to V_IH . This begins a write cycle and enables the WiperLock technology feature (See Figure 5-9).

After the pin is driven to V_IH (from V_IIHH ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored.

FIGURE 5-9: High-Voltage Decrement and Enable WiperLock Technology.

5.2.10 WRITE WIPER SETTING TO

EEPROM AND DISABLE WiperLock TECHNOLOGY

This mode is achieved by keeping the U/D pin static (either at V_IL or at V_IH ), while the CS pin is driven from V_IH to V_IHH and then returned to V_IH . When the falling edge of the CS pin occurs (from V_IHH to V_IH ), the wiper value is written to EEPROM and the WiperLock technology is disabled (See Figure 5-10).

To ensure that unexpected transitions on the U/D pin do not cause the wiper setting to change, force the CS pin to V_IH as soon as possible (within device specifications) after the CS pin is forced to V_IHH .

After the pin is driven to V_IH (from V_IHH ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

CS V_IH V_IHH U/D EEPROM X Wiper X+4 WiperLock Technology WiperLock Technology Enable WiperLock Technology Disable t_WC V_IH V_IL X+4

FIGURE 5-10: Write Wiper Setting to EEPROM and Disable WiperLock Technology.

5.2.11 WRITE WIPER SETTING TO

EEPROM AND ENABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D and CS pins to a high state ( V_IH ) prior to the CS pin being driven to V_IHH (from V_IH ). Set the U/D pin to a low state ( V_IL ) prior to forcing the CS pin to V_IH (from V_IHH ). This begins a write cycle and enables the WiperLock technology feature (See Figure 5-11).

To ensure that "unexpected" transitions on the U/D pin do not cause the wiper setting to increment, force the CS pin to V_IH as soon as possible (within device specifications) after the U/D pin is forced to V_IL .

After the pin is driven to V_IH (from V_IHH ), all other serial commands are ignored until the EEPROM write cycle ( t_WC ) completes.

FIGURE 5-11: Write Wiper Setting to EEPROM and Enable WiperLock Technology.

5.3 CS High Voltage

Depending on the requirements of the system, the use of high voltage ( V_IHH ) on the pin, may or may not be required during system operation. Table 5-2 shows possible system applications, and whether a high voltage ( V_IHH ) is required on the system.

The MCP402X supports six high-voltage commands (the CS input voltage must meet the VIHH specification).

TABLE 5-2: HIGH-VOLTAGE APPLICATIONS

System Operation	High Voltage
Production calibration only - system should not update wiper setting	From Calibration Unit
WiperLock Technology disabled during system operation	Not Required
Wiper setting can be updated and “locked” during system operation	Required

5.3.1 TECHNIQUES TO FORCE THE CS PIN TO V_IHH

The circuit in Figure 5-12 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the CS pin is controlled by the PIC® microcontrollers (MCUs) IO2 pin.

When the SHDN pin is low, the TC1240A is on and the V_OUT voltage is 2 × V_DD . The resistor R_1 allows the CS pin to go higher than the voltage such that the PIC MCU's IO2 pin "clamps" at approximately V_DD .

PIC® MCU IO1 IO2 TC1240A VIN SHDN VOUT C+ C- C1 R1 CS MCP402X C2

FIGURE 5-12: Using the TC1240A to Generate the V_IHH Voltage.

The circuit in Figure 5-13 shows the method used on the MCP402X Nonvolatile Digital Potentiometer Evaluation Board. This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficient voltage level on the pin to change the stored value of the wiper. The MCP402X Non-volatile Digital Potentiometer Evaluation Board User's Guide (DS51546) contains a complete schematic.

GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock.

For the serial commands, configure the GP2 pin as an input (high impedance). The output state of the GP0 pin will determine the voltage on the pin ( V_IL or V_IH ).

For high-voltage serial commands, force the GP0 output pin to output a high level ( V_OH ) and configure the GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the CS pin (when the system voltage is approximately 5V).

PIC10F206 GP0 R1 GPO GPO C1 MCP402X CS C2

FIGURE 5-13: MCP402X Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to Generate the V_IHH Voltage.

6.0 RESISTOR

Digital potentiometer applications can be divided into two categories:

• Rheostat configuration
- Potentiometer (or voltage divider) configuration

Figure 6-1 shows a block diagram for the MCP402X resistors.

A N = 63 | 3Fh Rw (1) Rs N = 62 | 3Eh Rw (1) Rs N = 61 | 3Dh Rw (1) Rs N = 1 | 01h Rw (1) Rs N = 0 | 00h B Analog Mux W

Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. This variation effects the smaller resistance devices (2.1 kΩ) more.
FIGURE 6-1: Resistor Block Diagram.

Step resistance ( R_S ) is the resistance from one tap setting to the next. This value will be dependent on the R_AB value that has been selected. Table 6-1 shows the typical step resistances for each device.

The total resistance of the device has minimal variation due to operating voltage (see Figure 2-6, Figure 2-17, Figure 2-27 or Figure 2-37).

TABLE 6-1: TYPICAL STEP RESISTANCES

Part Number	Typical Resistance (Ω)
	Total ( R_AB )	Step (R s)
MCP402X-202E 2100	33.33
MCP402X-502E 5000	79.37
MCP402X-103E 10000	158.73
MCP402X-503E 50000	793.65

Terminal A and B, as well as the wiper W, do not have a polarity. These terminals can support both positive and negative current.

6.1 Resistor Configurations

6.1.1 RHEOSTAT CONFIGURATION

When used as a rheostat, two of the three digital potentiometer's terminals are used as a resistive element in the circuit. With terminal W (wiper) and either terminal A or terminal B, a variable resistor is created. The resistance will depend on the tap setting of the wiper and the wiper's resistance. The resistance is controlled by changing the wiper setting.

The unused terminal (B or A) should be left floating. Figure 6-2 shows the two possible resistors that can be used. Reversing the polarity of the A and B terminals will not affect operation.

A B W ⇒ R_{AW} or R_{BW} Resistor

FIGURE 6-2: Rheostat Configuration.

This allows the control of the total resistance between the two nodes. The total resistance depends on the "starting" terminal to the wiper terminal. At the code 00h, the R_BW resistance is minimal ( R_W ), but the R_AW resistance in maximized ( R_AB + R_W ). Conversely, at the code 3Fh, the R_AW resistance is minimal ( R_W ), but the R_BW resistance in maximized ( R_AB + R_W ).

The resistance step size ( R_S ) equates to one LSb of the resistor.

Note: To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 2.5 mA.

The change in wiper-to-end terminal resistance over temperature is shown in Figure 2-6, Figure 2-17, Figure 2-27 and Figure 2-37. The most variation over temperature will occur in the first few codes due to the wiper resistance coefficient affecting the total resistance. The remaining codes are dominated by the total resistance tempco R_AB .

6.1.2 POTENTIOMETER

CONFIGURATION

When used as a potentiometer, all three terminals are tied to different nodes in the circuit. This allows the potentiometer to output a voltage proportional to the input voltage. This configuration is sometimes called voltage divider mode. The potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in Figure 6-3. Reversing the polarity of the A and B terminals will not affect operation.

V₁ A B W V₃ V₂

FIGURE 6-3: Potentiometer Configuration.

The temperature coefficient of the R_AB resistors is minimal by design. In this configuration, the resistors all change uniformly, so minimal variation should be seen.

The wiper resistor temperature coefficient is different from the R_AB temperature coefficient. The voltage at node V_3 (Figure 6-3) is not dependent on this wiper resistance, just the ratio of the R_AB resistors, so this temperature coefficient in most cases can be ignored.

Note: To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 2.5 mA.

6.2 Wiper Resistance

Wiper resistance is the series resistance of the wiper. This resistance is typically measured when the wiper is positioned at either zero-scale (00h) or full-scale (3Fh).

The wiper resistance in potentiometer-generated voltage divider applications is not a significant source of error.

The wiper resistance in rheostat applications can create significant nonlinearity as the wiper is moved toward zero-scale (00h). The lower the nominal resistance, the greater the possible error.

Wiper resistance is significant depending on the devices operating voltage. As the device voltage decreases, the wiper resistance increases (see Figure 6-4 and Table 6-2).

In a rheostat configuration, this change in voltage needs to be taken into account, particularly for the lower resistance devices. For the 2.1 kΩ device, the maximum wiper resistance at 5.5V is approximately 6% of the total resistance, while at 2.7V, it is approximately 15.5% of the total resistance.

In a potentiometer configuration, the wiper resistance variation does not effect the output voltage seen on the terminal W pin.

The slope of the resistance has a linear area (at the higher voltages) and a nonlinear area (at the lower voltages), where resistance increases faster than the voltage drop (at low voltages).

R_W V_DD Note: The slope of the resistance has a linear area (at the higher voltages) and a non-linear area (at the lower voltages).

FIGURE 6-4: Relationship of Wiper Resistance ( R_W ) to Voltage.

Since there is minimal variation of the total device resistance over voltage, at a constant temperature (see Figure 2-6, Figure 2-17, Figure 2-27 or Figure 2-37), the change in wiper resistance over voltage can have a significant impact on the INL and DNL error.

TABLE 6-2: TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE

Resistance (Ω)					R_W/R_S(%)^(1)			R_W/R_AB(%)^(2)
Typical		Wiper W)			(R R_W =Typical	R_W =Max@ 5.5V	R_W =Max@ 2.7V	R_W =Typical	R_W =Max@ 5.5V	R_W =Max@ 2.7V
Total( R_AB )	Step( R_S )	Typical	Max @5.5V	Max @2.7V
2100	33.33	75	125	325	225.0%	375.0%	975.0%	3.57%	5.95%	15.48%
5000	79.37	75	125	325	94.5%	157.5%	409.5%	1.5%	2.50%	6.50%
10000	158.73	75	125	325	47.25%	78.75%	204.75%	0.75%	1.25%	3.25%
50000	793.65	75	125	325	9.45%	15.75%	40.95%	0.15%	0.25%	0.65%

Note 1: R_S is the typical value. The variation of this resistance is minimal over voltage.
2: R_AB is the typical value. The variation of this resistance is minimal over voltage.

6.3 Operational Characteristics

Understanding the operational characteristics of the device's resistor components is important to the system design.

6.3.1 ACCURACY

6.3.1.1 Integral Nonlinearity (INL)

INL error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point after offset and gain errors have been removed. These endpoints are from 0x00 to 0x3F. Refer to Figure 6-5.

Positive INL means higher resistance than ideal. Negative INL means lower resistance than ideal.

FIGURE 6-5: INL Accuracy.

6.3.1.2 Differential Non-Linearity (DNL)

DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSb wide.

FIGURE 6-6: DNL Accuracy.

6.3.1.3 Ratiometric Temperature Coefficient

The ratiometric temperature coefficient quantifies the error in the ratio R_AW/R_WB due to temperature drift. This is typically the critical error when using a potentiometer device (MCP4021 and MCP4023) in a voltage divider configuration.

6.3.1.4 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies the error in the end-to-end resistance (nominal resistance R_AB ) due to temperature drift. This is typically the critical error when using a rheostat device (MCP4022 and MCP4024) in an adjustable resistor configuration.

6.3.2 MONOTONIC OPERATION

Monotonic operation means that the device's resistance increases with every step change (from terminal A to terminal B or terminal B to terminal A).

The wiper resistance is different at each tap location. When changing from one tap position to the next (either increasing or decreasing), the R_W is less than the R_S . When this change occurs, the device voltage and temperature are the same for the two tap positions.

FIGURE 6-7: Resistance, R

BW·

7.0 DESIGN CONSIDERATIONS

In the design of a system with the MCP402X devices, the following considerations should be taken into account:

• The power supply
• The layout

7.1 Power Supply Considerations

The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 7-1 illustrates an appropriate bypass strategy.

In this example, the recommended bypass capacitor value is 0.1 F. This capacitor should be placed as close (within 4 mm) to the device power pin ( V_DD ) as possible.

The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, V_DD and V_SS should reside on the analog plane.

VDD 0.1 μF A W B MCP4021/2/3/4 U/D CS PIC® Microcontroller VSS VSS 0.1 μF VDD

FIGURE 7-1: Typical Microcontroller Connections.

7.2 Layout Considerations

Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP402X's performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals.

If low noise is desired, breadboards and wire-wrapped boards are not recommended.

8.0 APPLICATIONS EXAMPLES

Nonvolatile digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP4021/2/3/4 devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations ( V_DD = 2.7V to 5.5V).

8.1 Set Point Threshold Trimming

Applications that need accurate detection of an input threshold event often need several sources of error eliminated. Use of comparators and operational amplifiers (op amps) with low offset and gain error can help achieve the desired accuracy, but in many applications, the input source variation is beyond the designer's control. If the entire system can be calibrated after assembly in a controlled environment (like factory test), these sources of error are minimized, if not entirely eliminated.

Figure 8-1 illustrates a common digital potentiometer configuration. This configuration is often referred to as a "windowed voltage divider". Note that R_1 and R_2 are not necessary to create the voltage divider, but their presence is useful when the desired threshold has limited range. It is "windowed" because R_1 and R_2 can narrow the adjustable range of V_TRIP to a value much less than V_DD - V_SS . If the output range is reduced, the magnitude of each output step is reduced. This effectively increases the trimming resolution for a fixed digital potentiometer resolution. This technique may allow a lower-cost digital potentiometer to be utilized (64 steps instead of 256 steps).

The MCP4021's and MCP4023's low DNL performance is critical to meeting calibration accuracy in production without having to use a higher precision digital potentiometer.

EQUATION 8-1: CALCULATING THE WIPER SETTING FROM THE DESIRED V _TRIP

$$ V _ {T R I P} = V _ {D D} \left(\frac {R _ {2} + R _ {W B}}{R _ {1} + R _ {A B} + R _ {2}}\right) $$

$$ R _ {A B} = R _ {\text { Nominal }} $$

$$ R _ {W B} \quad R _ {A B} = \left(\frac {D}{6 3}\right) $$

$$ D \quad \left(\left(\frac {V _ {T R I P}}{V _ {D D}}\right) \quad R _ {1} + R _ {A B} + R _ {2} - \left(\text { （ } _ {2}\right) \quad 6 3 \bullet \quad\right) $$

Where:

$$ D = \text { Digital Potentiometer Wiper Setting } (0 - 6 3) $$

MCP4021 VDD R1 A CS U/D W VOUT B R2

FIGURE 8-1: Using the Digital Potentiometer to Set a Precise Output Voltage.

8.1.1 TRIMMING A THRESHOLD FOR AN OPTICAL SENSOR

If the application has to calibrate the threshold of a diode, transistor or resistor, a variation range of 0.1V is common. Often, the desired resolution of 2 mV or better is adequate to accurately detect the presence of a precise signal. A "windowed" voltage divider, utilizing the MCP4021 or MCP4023, would be a potential solution, as shown in Figure 8-2.

VDD Rsense VCC+ Comparator MCP4021 CS U/D A W VTRIP + MCP6021 VCC- R1 R2 0.1 μF

FIGURE 8-2: Set Point or Threshold Calibration.

8.2 Operational Amplifier Applications

Figure 8-3, Figure 8-4 and Figure 8-5 illustrate typical amplifier circuits that could replace fixed resistors with the MCP4021/2/3/4 to achieve digitally-adjustable analog solutions.

Figure 8-4 shows a circuit that allows a non-inverting amplifier to have its' offset and gain to be independently trimmed. The MCP4021 is used along with resistors R1 and R2 to set the offset voltage. The sum of R1 + R2 resistance should be significantly greater (> 100 times) the resistance value of the MCP4021. This allows each increment or decrement in the MCP4021 to be a fine adjustment of the offset voltage. The input voltage of the op amp ( V_IN ) should be centered at the op amps V_W voltage. The gain is adjusted by the MCP4022. If the resistance value of the MCP4022 is small compared to the resistance value of R3, then this is a fine adjustment of the gain. If the resistance value of the MCP4022 is equal (or large) compared to the resistance value of R3, then this is a course adjustment of the gain. In general, trim the course adjustments first and then trim the fine adjustments.

MCP4021 VIN R3 A B W R4 - Op Amp + VDD R1 A W B R2 MCP402X VOUT MCP6001

FIGURE 8-3: Trimming Offset and Gain in an Inverting Amplifier.

VDD + Op Amp VDD VIN - Vw VOUT R1 A W B R2 MCP4021 A W R3 MCP4022

FIGURE 8-4: Trimming Offset and Gain in a Noninverting Amplifier.

MCP4021 R3 A B W Pot2 VDD R1 A W B Pot1 R2 MCP4022 VIN Op Amp + MCP6021 VOUT fc I / 2π·REq·C Thevenin Equivalent REq = R1 RA B - RWB || 2 + (RWB) + )

FIGURE 8-5: Programmable Filter.

8.3 Temperature Sensor Applications

Thermistors are resistors with very predictable variation with temperature. Thermistors are a popular sensor choice when a low-cost, temperature-sensing solution is desired. Unfortunately, thermistors have nonlinear characteristics that are undesirable, typically requiring trimming in an application to achieve greater accuracy. There are several common solutions to trim and linearize thermistors. Figure 8-6 and Figure 8-7 are simple methods for linearizing a 3-terminal NTC thermistor. Both are simple voltage dividers using a Positive Temperature Coefficient (PTC) resistor ( R_1 ) with a transfer function capable of compensating for the linearity error in the Negative Temperature Coefficient (NTC) thermistor.

The circuit, illustrated by Figure 8-6, utilizes a digital rheostat for trimming the offset error caused by the thermistor's part-to-part variation. This solution puts the digital potentiometer's R_W into the voltage divider calculation. The MCP4021/2/3/4's R_AB temperature coefficient is 50 ppm (-20°C to +70°C). R_W 's error is substantially greater than R_AB 's error because R_W varies with V_DD , wiper setting and temperature. For the 50 kΩ devices, the error introduced by R_W is, in most cases, insignificant as long as the wiper setting is >6. For the 2 kΩ devices, the error introduced by R_W is significant because it is a higher percentage of R_WB . For these reasons, the circuit illustrated in Figure 8-6 is not the most optimum method for "exciting" and linearizing a thermistor.

VDD R1 NTC Thermistor VOUT R2 A W MCP4022

FIGURE 8-6: Thermistor Calibration using a Digital Potentiometer in a Rheostat Configuration.

The circuit illustrated by Figure 8-7 utilizes a digital potentiometer for trimming the offset error. This solution removes R_W from the trimming equation along with the error associated with R_W · R_2 is not required, but can be utilized to reduce the trimming “window” and reduce variation due to the digital potentiometer’s R_AB part-to-part variability.

VDD R1 NTC Thermistor MCP4021 VOUT R2

FIGURE 8-7: Thermistor Calibration using a Digital Potentiometer in a Potentiometer Configuration.

8.4 Wheatstone Bridge Trimming

Another common configuration to “excite” a sensor (such as a strain gauge, pressure sensor or thermistor) is the wheatstone bridge configuration. The wheatstone bridge provides a differential output instead of a single-ended output. Figure 8-8 illustrates a wheatstone bridge utilizing one to three digital potentiometers. The digital potentiometers in this example are used to trim the offset and gain of the wheatstone bridge.

VDD MCP4022 2.1 kΩ VOUT MCP4022 50 kΩ MCP4022 50 kΩ

FIGURE 8-8: Wheatstone Bridge Trimming.

9.0 DEVELOPMENT SUPPORT

9.1 Evaluation/Demonstration Boards

Currently there are three boards that are available that can be used to evaluate the MCP4021/2/3/4 family of devices.

1. The MCP402X Digital Potentiometer Evaluation Board kit (MCP402XEV) contains a simple demonstration board utilizing a PIC10F206, the MCP4021 and a blank PCB, which can be populated with any desired MCP4021/2/3/4 device in a SOT-23-5, SOT-23-6 or 150 mil SOIC 8-pin package.

This board has two push buttons to control when the PIC ^® microcontroller generates MCP402X serial commands. The example firmware demonstrates the following commands:

• Increment
• Decrement
  • High-Voltage Increment and Enable WiperLock Technology
  • High-Voltage Decrement and Enable WiperLock Technology
  • High-Voltage Increment and Disable WiperLock Technology
  • High-Voltage Decrement and Disable WiperLock Technology

The populated board (with the MCP4021) can be used to evaluate the other MCP402X devices by appropriately jumpering the PCB pads.

1. The SOT-23-5/6 Evaluation Board (VSUPEV2) can be used to evaluate the characteristics of the MCP4022, MCP4023 and MCP4024 devices.
2. The 8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board (SOIC8EV) can be used to evaluate the characteristics of the MCP4021 device in either the SOIC or MSOP package.
3. The MCP4XXX Digital Potentiometer Daughter Board allows the system designer to quickly evaluate the operation of Microchip Technology's MCP42XXX and MCP402X Digital Potentiometers. The board supports two MCP42XXX devices and an MCP402X device, which can be replaced with an MCP401X device.

The board also has a voltage doubler device (TC1240A), which can be used to show the WiperLock Technology feature of the MCP4021.

These boards may be purchased directly from the Microchip web site at www.microchip.com.

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

5-Lead SOT-23 (MCP4024)

XXNN

Example:

DP25

Part Number Code
MCP4024T-202E/OT DPNN
MCP4024T-502E/OT DQNN
MCP4024T-103E/OT DRNN
MCP4024T-503E/OT DSNN

Note: Applies to 5-Lead SOT-23

6-Lead SOT-23 (MCP4022 / MCP4023)

XXNN

Example:

BA25

Part Number	Code
	MCP4022	MCP4023
MCP402xT-202E/CH	BANN BENN
MCP402xT-502E/CH	BBNN BFNN
MCP402xT-103E/CH	BCNN BGNN
MCP402xT-503E/CH	BDNN BHNN

Note: Applies to 6-Lead SOT-23

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week '01')

NNN Alphanumeric traceability code

e3 Pb-free JEDEC designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

Package Marking Information

XXX YWW NN PIN 1

Example:8-Lead DFN (2x3) (MCP40

AAA 640 25 PIN 1

Part Number Code

MCP4021T-202E/MC AAA

MCP4021T-502E/MC AAB

MCP4021T-103E/MC AAC

MCP4021T-503E/MC AAD

Note: Applies to 8-Lead DFN

8-Lead MSOP (MCP4021)

XXXXXXXX YWWNNN

Example:

402122 640256

8-Lead SOIC (150 mil) (MCP4021)

XXXXXXXXX XXXXXXXXYWW ○ NNN

Example:

402153E SN e3 1640 256

Part Numbers		Code
8L-MSOP 8L-SOIC
MCP4021-202E/MS	MCP4021-202E/SN 22
MCP4021-502E/MS	MCP4021-502E/SN 52
MCP4021-103E/MS	MCP4021-103E/SN 13
MCP4021-503E/MS	MCP4021-503E/SN 53

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

0.20 C 2X D e1 A N E1/2 E1 E/2 E (DATUM D) (DATUM A-B) NOTE 1 1 2 e NX bB 0.15 C D 2X TOP VIEW

A A A2 A SEE SHEET 2 A1 SIDE VIEW 0.20 C SEATING PLANE C

Microchip Technology Drawing C04-028D [OT] Sheet 1 of 2

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

c L L1 θ c

VIEW A-A SHEET 1

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N	6
Pitch	e	0.95 BSC
Outside lead pitch	e1	1.90 BSC
Overall Height	A	0.90	-	1.45
Molded Package Thickness	A2	0.89	-	1.30
Standoff	A1	-	-	0.15
Overall Width	E	2.80 BSC
Molded Package Width	E1	1.60 BSC
Overall Length	D	2.90 BSC
Foot Length	L	0.30	-	0.60
Footprint	L1	0.60 REF
Foot Angle		0°	-	10°
Lead Thickness	c	0.08	-	0.26
Lead Width	b	0.20 -		0.51

Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only

Microchip Technology Drawing C04-091D [OT] Sheet 2 of 2

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

X 5 SILK SCREEN Y Z C G 1 2 E GX

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits			NOM	MAXMIN
Contact Pitch	E	0.95 BSC
Contact Pad Spacing	C		2.80
Contact Pad Width (X5)	X			0.60
Contact Pad Length (X5)	Y			1.10
Distance Between Pads	G	1.70
Distance Between Pads GX 0.35
Overall Width	Z			3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091A [OT]

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

2X 0.15 C A-B D e1 A E1 E2 E 2X 0.20 C A-B 2X 0.15 C D 6X b ∅ 0.20 M A-E D

TOP VIEW

SEATING PLANE A A2 A1 SIDE VIEW 6X 0.10 C

c R1 R L2 GAUGE PLANE L ( L1 ) Θ END VIEW

Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Isometric line drawing of an integrated circuit chip with four pins (no text or symbols)

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Leads	N	6
Pitch	e	0.95 BSC
Outside lead pitch	e1	1.90 BSC
Overall Height	A	0.90	-	1.45
Molded Package Thickness	A2	0.89	1.15	1.30
Standoff	A1	0.00	-	0.15
Overall Width	E	2.80 BSC
Molded Package Width	E1	1.60 BSC
Overall Length	D	2.90 BSC
Foot Length	L	0.30	0.45	0.60
Footprint	L1	0.60 REF
Seating Plane to Gauge Plane L1	0.25 BSC
Foot Angle		0^	-	10^
Lead Thickness	c	0.08	-	0.26
Lead Width	b	0.20 -		0.51

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

GX Y Z C G G SILK SCREEN X E

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits			NOM	MAXMIN
Contact Pitch	E	0.95 BSC
Contact Pad Spacing	C		2.80
Contact Pad Width (X3)	X			0.60
Contact Pad Length (X3)	Y			1.10
Distance Between Pads	G	1.70
Distance Between Pads GX 0.35
Overall Width	Z			3.90

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2028B (CH)

8-Lead Plastic Dual Flat, No Lead Package (MC) - 2x3x0.9 mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.50 BSC
Overall Height	A	0.80	0.90	1.00
Standoff	A1	0.00	0.02	0.05
Contact Thickness	A3	0.20 REF
Overall Length	D	2.00 BSC
Overall Width	E	3.00 BSC
Exposed Pad Length	D2	1.30	-	1.55
Exposed Pad Width	E2	1.50	-	1.75
Contact Width	b	0.20	0.25	0.30
Contact Length	L	0.30	0.40	0.50
Contact-to-Exposed Pad	K	0.20	-	-

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-123C

8-Lead Plastic Dual Flat, No Lead Package (MC) - 2x3x0.9mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

W2 G C1 T2 E X1 Y1 SILK SCREEN

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.50 BSC
Optional Center Pad Width	W2			1.45
Optional Center Pad Length	T2			1.75
Contact Pad Spacing	C1		2.90
Contact Pad Width (X8)	X1			0.30
Contact Pad Length (X8)	Y1			0.75
Distance Between Pads	G	0.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2123B

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

2X 0.20 H D/2 A E/2 D E1/2 E1 N E/2 E NOTE 1 1 2 N/2 0.25 C e B NX b Φ 0.13 M C A-B D TOP VIEW A A2 A1 SEATING PLANE SIDE VIEW C H SEE DETAIL C END VIEW

Microchip Technology Drawing C04-111C Sheet 1 of 2

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

SEATING PLANE L (L1) GAUGE PLANE c φ

DETAIL C

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Number of Pins	N		8
Pitch	e	0.65 BSC
Overall Height	A	-	-	1.10
Molded Package Thickness	A2	0.75	0.85	0.95
Standoff	A1	0.00	-	0.15
Overall Width	E	4.90 BSC
Molded Package Width	E1	3.00 BSC
Overall Length	D	3.00 BSC
Foot Length	L	0.40	0.60	0.80
Footprint	L1	0.95 REF
Foot Angle		0°	-	8°
Lead Thickness	c	0.08	-	0.23
Lead Width	b	0.22	-	0.40

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-111C Sheet 2 of 2

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

X Y Z C G1 SILK SCREEN GX E

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.65 BSC
Contact Pad Spacing	C		4.40
Overall Width	Z			5.85
Contact Pad Width (X8)	X1			0.45
Contact Pad Length (X8)	Y1			1.45
Distance Between Pads	G1	2.95
Distance Between Pads	GX	0.20

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2111A

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

Isometric line drawing of an integrated circuit chip with four pins (no text or symbols)

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
	NNumber of Pins 8
Pitch	e	1.27 BSC
			AOvera15Height
				--1.25A2Molded Package Thickness
Standoff §	A1			0.25-0.10
		6.00 BSCEOverall Width
		3.90 BSCE1Molded Package Width
		4.90 BSCDOverall Length
Chamfer (Optional)	h	0.25	-	0.50
Foot Length	L	0.40	-	1.27
Footprint	L1	1.04 REF
Foot Angle 0° - 8°	φ
Lead Thickness	c			0.25-0.17
Lead Width	b			0.51-0.31
Mold Draft Angle Top	α			15°-5°
Mold Draft Angle Bottom	β			15°-5°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

C SILK SCREEN Y1 X1 E

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	1.27 BSC
	CContact Pad Spacing40
Contact Pad Width (X8)	X1			0.60
Contact Pad Length (X8)	Y1			1.55

Notes:

Dimensioning and tolerancing per ASME Y14.5M1.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2057-SN Rev B

NOTES:

APPENDIX A: REVISION HISTORY

Revision F (December 2017)

The following is the list of modifications:

1. Updated the High-Voltage Input Entry Voltage entry in the "AC/DC Characteristics" table.
2. Updated Table 6-1 "Typical Step Resistances".

Revision E (December 2006)

The following is the list of modifications:

1. Added device designators in conditions column to associate units (MHz) in Bandwidth -3 dB parameter in the table "AC/DC Characteristics" table.
2. Added device designations in conditions column for R-INL and R-DNL specifications.
3. Added disclaimers to package outline drawings.

Revision D (October 2006)

The following is the list of modifications:

1. Changed the EEPROM write cycle time (T _WC ) from a maximum of 5 ms to a maximum of 10 ms (overvoltage and temperature) with a typical of 5 ms.
2. For the 10 kΩ device, the rheostat differential nonlinearity specification at 2.7V was changed from ±0.5 LSb to ±1.0 LSb.
3. Figure 2-9 in Section 2.0 "Typical Performance Curves" was updated with the correct data.
4. Added Figure 2-48 for -3 db Bandwidth information.
5. Updated available Development Tools.
6. Added disclaimer to package outline drawings.

Revision C (November 2005)

The following is the list of modifications:

1. Enhanced Descriptions.
2. Reordered Sections.
3. Added 8-lead MSOP and DFN packages.

Revision B (April 2005)

The following is the list of modifications:

1. Updated part numbers in Product Identification Section (PIS).
2. Added Appendix A: Revision History.

Revision A (April 2005)

• Original release of this document.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

XXX

X

IXX

Device

Resistance Version

Temperature Package Range

Device: MCP4021: Single Potentiometer with U/D Interface

MCP4021T: Single Potentiometer with U/D Interface (Tape and Reel) (SOIC, MSOP)

MCP4022: Single Rheostat with U/D _ interface

MCP4022T: Single Rheostat with U/D interface

(Tape and Reel) (SOT-23-6)

MCP4023: Single Potentiometer to GND with U/D Interface

MCP4023T: Single Potentiometer to GND with U/D Interface (Tape and Reel) (SOT-23-6)

MCP4024: Single Rheostat to GND with U/D Interface

MCP4024T: Single Rheostat to GND with U/D Interface (Tape and Reel)(SOT-23-5)

Resistance Version: 202 = 2.1 kΩ

502 = 5 kΩ

103 = 10 kΩ

503 = 50 kΩ

Temperature Range: E = -40°C to +125°C

Package: CH = Plastic Small Outline Transistor, 6-lead

MC = Plastic Dual Flat No Lead (2x3x0.9 mm), 8-lead

MS = Plastic MSOP, 8-lead

SN = Plastic SOIC, (150 mil Body), 8-lead

OT = Plastic Small Outline Transistor, 5-lead

Examples:

a) MCP4021-103E/MS: 10 kΩ, 8-LD MSOP

b) MCP4021-103E/SN: 10 kΩ 8-LD SOIC

c) MCP4021T-103E/MC: T/R, 10 kΩ, 8-LD DFN

d) MCP4021T-103E/MS: T/R, 10 kΩ, 8-LD MSOP

e) MCP4021T-103E/SN: T/R, 10 kΩ, 8-LD SOIC

f) MCP4021-202E/MS: 2.1 kΩ, 8-LD MSOP

g) MCP4021-202E/SN: 2.1 kΩ, 8-LD SOIC

h) MCP4021T-202E/MC: T/R, 2.1 kΩ, 8-LD DFN

i) MCP4021T-202E/MS: T/R, 2.1 kΩ, 8-LD MSOP

i) MCP4021T-202E/SN: T/R, 2.1 kΩ, 8-LD SOIC

k) MCP4021-502E/MS: 5 kΩ, 8-LD MSOP

I) MCP4021-502E/SN: 5 kΩ, 8-LD SOIC

m) MCP4021T-502E/MC: T/R, 5 kΩ, 8-LD DFN

n) MCP4021T-502E/MS: T/R, 5 kΩ, 8-LD MSOP

o) MCP4021T-502E/SN: T/R, 5 kΩ, 8-LD SOIC

p) MCP4021-503E/MS: 50 kΩ, 8-LD MSOP

q) MCP4021-503E/SN: 50 kΩ, 8-LD SOIC

r) MCP4021T-503E/MC: T/R, 50 kΩ, 8-LD DFN

s) MCP4021T-503E/MS: T/R, 50 kΩ, 8-LD MSOP

t) MCP4021T-503E/SN: T/R, 50 kΩ, 8-LD SOIC

a) MCP4022T-202E/CH 2.1 kΩ, 6-LD SOT-23

b) MCP4022T-502E/CH 5 kΩ, 6-LD SOT-23

c) MCP4022T-103E/CH 10 kΩ, 6-LD SOT-23

d) MCP4022T-503E/CH 50 kΩ, 6-LD SOT-23

a) MCP4023T-202E/CH 2.1 kΩ, 6-LD SOT-23

b) MCP4023T-502E/CH 5 kΩ, 6-LD SOT-23

c) MCP4023T-103E/CH 10 kΩ, 6-LD SOT-23

d) MCP4023T-503E/CH 50 kΩ, 6-LD SOT-23

a) MCP4024T-202E/OT 2.1 kΩ, 5-LD SOT-23

b) MCP4024T-502E/OT 5 kΩ, 5-LD SOT-23

c) MCP4024T-103E/OT 10 kΩ, 5-LD SOT-23

d) MCP4024T-503E/OT 50 kΩ, 5-LD SOT-23

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949=

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELoQ, KEELoQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQL, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestlC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-2436-9

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