AT86RF232 - Electronic component Microchip - Free user manual and instructions

USER MANUAL AT86RF232 Microchip

• High Performance RF-CMOS 2.4GHz radio transceiver targeted for IEEE® 802.15.4, ZigBee®, RF4CE, 6LoWPAN, and ISM applications
  • Industry leading link budget:

- Receiver sensitivity -100dBm

- Programmable output power from -17dBm up to +3dBm

• Ultra-low current consumption:

- SLEEP = 0.4μA

• TRX_OFF = 330μA
• RX_ON = 11.8mA (LISTEN)

• BUSY_TX = 13.8mA (at max. transmit power)

• Ultra-low supply voltage (1.8V to 3.6V) with internal regulator
  • Support for coin cell operation

• Optimized for low BoM cost and ease of production:

- Few external components necessary (crystal, capacitors and antenna)

- Easy to use interface:

• Registers, frame buffer and AES accessible through fast SPI
• Only two microcontroller GPIO lines necessary
• One interrupt pin from radio transceiver
• Clock output

• Radio transceiver features:

• 128-byte FIFO (SRAM) for data buffering
• Fully integrated, fast settling PLL to support Frequency Hopping
• Battery monitor
• Fast Wake-Up time < 0.4msec

- Special IEEE 802.15.4 ^TM -2011 hardware support:

• FCS computation and Clear Channel Assessment
• RSSI measurement, Energy Detection and Link Quality Indication

• MAC hardware accelerator:

• Automated acknowledgement, CSMA-CA and retransmission
• Automatic address filtering
• Automated FCS check

- Extended feature set hardware support:

• AES 128-bit hardware accelerator
• Antenna Diversity
• True Random Number Generation for security application

• Commercial temperature range:

- 0°C to +70°C

• I/O and packages:

• 32-pin low-profile QFN package 5 x 5 x 0.9mm ^4
• RoHS/Fully Green

• Compliant to IEEE 802.15.4-2011, IEEE 802.15.4-2006 and IEEE 802.15.4-2003
• Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210

Low Power, 2.4GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE and ISM Applications

AT86RF232

PRELIMINARY

Rev. 8321A-MCU Wireless-10/11

1 Pin-out Diagram

Figure 1-1. Atmel AT86RF232 Pin-out Diagram.

AVSS AVSS AVDD EVDD AVSS XTAL1 XTAL2 32 31 30 29 28 27 26 25 AVSS 1 AVSS 2 AVSS 3 RFP 4 RFN 5 AVSS 6 DVSS 7 /RST 8 AT86RF232 exposed paddle AVSS 24 /SEL 23 MOSI 22 DVSS 21 MISO 20 SCLK 19 DVSS 18 CLKM 17 DIG1 DIG2 SLP_TR DVSS DVDD DVDD DEVDD DVSS

Note: 1. The exposed paddle is electrically connected to the die inside the package. It shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability.

1.1 Pin Descriptions

Table 1-1. Atmel AT86RF232 Pin Description.

Pins	Name	Type	Description
1	AVSS	Ground	Analog ground
2	AVSS	Ground	Analog ground
3	AVSS	Ground	Ground for RF signals
4	RFP	RF I/O	Differential RF signal
5	RFN	RF I/O	Differential RF signal
6	AVSS	Ground	Ground for RF signals
7	DVSS	Ground	Digital ground
8	/RST	Digital input	Chip reset; active low
9	DIG1	Digital output (Ground)	1. Antenna Diversity RF switch control, see Section 11.32. If disabled, pull-down enabled (DVSS)
10	DIG2	Digital output (Ground)	1. Antenna Diversity RF switch control (DIG1 inverted), see Section 11.32. RX Frame Time Stamping, see Section 11.43. TX Frame Time Stamping, see Section 11.44. If functions disabled, pull-down enabled (DVSS)
11	SLP_TR	Digital input	Controls sleep, transmit start, receive states; active high, see Section 6.5
12	DVSS	Ground	Digital ground
13, 14	DVDD	Supply	Regulated 1.8V voltage regulator; digital domain, see Section 9.4
15	DEVDD	Supply	External supply voltage; digital domain
16	DVSS	Ground	Digital ground
17	CLKM	Digital output	Master clock signal output; low if disabled, see Section 9.6
18	DVSS	Ground	Digital ground
19	SCLK	Digital input	SPI clock
20	MISO	Digital output	SPI data output (master input slave output)
21	DVSS	Ground	Digital ground
22	MOSI	Digital input	SPI data input (master output slave input)
23	/SEL	Digital input	SPI select, active low
24	IRQ	Digital output	1. Interrupt request signal; active high or active low; configurable2. Frame Buffer Empty Indicator; active high, see Section 11.5
25	XTAL2	Analog input	Crystal pin, see Section 9.6
26	XTAL1	Analog input	Crystal pin or external clock supply, see Section 9.6
27	AVSS	Ground	Analog ground
28	EVDD	Supply	External supply voltage, analog domain
29	AVDD	Supply	Regulated 1.8V voltage regulator; analog domain, see Section 9.4
30, 31, 32	AVSS	Ground	Analog ground
Paddle	AVSS	Ground	Analog ground; Exposed paddle of QFN package

1.2 Analog and RF Pins

1.2.1 Supply and Ground Pins

EVDD, DEVDD

EVDD and DEVDD are analog and digital supply voltage pins of the Atmel® AT86RF232 radio transceiver.

AVDD, DVDD

AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators can be configured for external supply.

For details, refer to Section 9.4.

AVSS, DVSS

AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB.

1.2.2 RF Pins

RFN, RFP

A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by rejecting any spurious emissions originated from other digital ICs such as a microcontroller.

A simplified schematic of the RF front end is shown in Figure 1-2.

Figure 1-2. Simplified RF Front-end Schematic.

AT86RF232PCB LNA RX PA TX 0.9V CM Feedback M0 RXTX

The RF port is designed for a 100 differential load. A DC path between the RF pins is allowed. A DC path to ground or supply voltage is not allowed.

The RF port DC values depend on the operating state, see Chapter 7. In TRX_OFF state, when the analog front-end is disabled (see Section 7.1.2.3), the RF pins are pulled to ground, preventing a floating voltage.

In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be <30pF to ensure the stability of this common-mode feedback loop.

In receive mode, the RF port provides a low-impedance path to ground when transistor M0, see Figure 1-2, pulls the inductor center tap to ground. A DC voltage drop of 20mV across the on-chip inductor can be measured at the RF pins.

1.2.3 Crystal Oscillator Pins

XTAL1, XTAL2

The pin 26 (XTAL1) of Atmel AT86RF232 is the input of the reference oscillator amplifier (XOSC), the pin 25 (XTAL2) is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9.6.

When using an external clock reference signal, XTAL1 shall be used as input pin. For further details, refer to Section 9.6.3.

1.2.4 Analog Pin Summary

Table 1-2. Analog Pin Behavior – DC values.

Pin	Values and Conditions	Comments
RFP/RFN	V_DC = 0.9V (BUSY\_TX) V_DC = 20mV (receive states) V_DC = 0mV (otherwise)	DC level at pins RFP/RFN for various transceiver states.AC coupling is required if a circuitry with DC path to ground or supply is used. Serial capacitance and capacitance of each pin to ground must be < 30pF.
XTAL1/XTAL2	V_DC = 0.9V at both pins C_PAR = 3pF	DC level at pins XTAL1/XTAL2 for various transceiver states.Parasitic capacitance ( C_par ) of the pins must be considered as additional load capacitance to the crystal.
DVDD	V_DC = 1.8V (all states, except SLEEP) V_DC = 0mV (otherwise)	DC level at pin DVDD for various transceiver states.Supply pins (voltage regulator output) for the digital 1.8V voltage domain, recommended bypass capacitor 100nF.
AVDD	V_DC = 1.8V (all states, except P_ON, SLEEP, RESET, and TRX_OFF) V_DC = 0mV (otherwise)	DC level at pin AVDD for various transceiver states.Supply pin (voltage regulator output) for the analog 1.8V voltage domain, recommended bypass capacitor 100nF.

1.3 Digital Pins

The Atmel AT86RF232 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Chapter 6.

Additional digital output signals DIG1 and DIG2 are provided to control external blocks, that is for Antenna Diversity RF switch control, see Section 11.3.

1.3.1 Driver Strength Settings

The driver strength of all digital output pins (MISO, IRQ, DIG1, and DIG2) and CLKM pin are fixed. The capacitive load should be as small as possible as, not larger than 50pF.

1.3.2 Pull-up and Pull-down Configuration

All digital input pins are internally pulled-up or pulled-down in radio transceiver state P_ON, see Section 7.1.2.1. Table 1-3 summarizes the pull-up and pull-down configuration.

Table 1-3. Pull-up / Pull-Down Configuration of Digital Input Pins.

Pins	H = pull-up, L = pull-down
/RST	H
/SEL	H
SCLK	L
MOSI	L
SLP_TR	L

In all other radio transceiver states, no pull-up or pull-down circuitry is connected to any of the digital input pins mentioned in Table 1-3. In RESET state, the pull-up or pull-down resistors are not enabled.

If the additional digital output signals DIG1 or DIG2 are not activated, these pins are pulled-down to digital ground.

2 Disclaimer

Typical values contained in this datasheet are based on simulations and testing. Minimum and maximum values are available when the radio transceiver has been fully characterized.

3 Overview

The Atmel AT86RF232 is a low-power 2.4GHz radio transceiver designed for consumer ZigBee/IEEE 802.15.4, RF4CE, 6LoWPAN, and 2.4GHz ISM band applications. The radio transceiver is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip. Therefore, the AT86RF232 is particularly suitable for applications like:

• 2.4GHz IEEE 802.15.4 and ZigBee systems
- RF4CE systems
- 6LoWPAN systems
- Wireless sensor networks
• Residential and commercial automation
- Health care
- Consumer electronics
- PC peripherals

The AT86RF232 can be operated by using an external microcontroller like Atmel AVR ^® microcontrollers. A comprehensive software programming description can be found in reference [6], AT86RF232 Software Programming Model.

4 General Circuit Description

This single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation and demodulation including time and frequency synchronization and data buffering. The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed.

The Atmel AT86RF232 block diagram is shown in Figure 4-1.

Figure 4-1. AT86RF232 Block Diagram.

graph TD
    subgraph "Antenna Diversity"
        A["AD"] --> B["LNA"]
        B --> C["PPF EPF ADC"]
        C --> D["×"]
        D --> E["×"]
        E --> F["Limiter"]
        F --> G["AGC"]
        G --> H["Control Logic"]
    end

    subgraph "Configuration Registers"
        I["TX BBP"] --> J["Frame Buffer"]
        K["DVREG"] --> L["SPI (Slave)"]
        M["/SEL"] --> N["MISO"]
        O["MOSI"] --> P["SCLK"]
        Q["SCLK"] --> R["IQ"]
        S["CLKM"] --> T["DIG2"]
        U["/RST"] --> V["SLP_TR"]
    end

    X["XTAL1"] --> Y["XOSC"]
    Z["XTAL2"] --> AA["XOSC"]
    AB["RFP"] --> AC["LNA"]
    AD["RFN"] --> AE["LNA"]
    AF["XT Data"] --> AG["PLL PA"]
    AH["RTN, BATMON"] --> AI["FFTN, BATMON"]
    AJ["RSSI"] --> AK["Limiter"]
    AL["PGP"] --> AM["LNA"]
    AN["AGC"] --> AO["Control Logic"]
    AP["XT Data"] --> AQ["Configuration Registers"]
    AR["Frame Buffer"] --> AS["SPI (Slave)"]
    AT["Frame Buffer"] --> AU["Configuration Registers"]
    AV["Configuration Registers"] --> AW["Configuration Registers"]
    AX["Configuration Registers"] --> AY["Configuration Registers"]
    AZ["Configuration Registers"] --> BA["Configuration Registers"]
    BB["Configuration Registers"] --> BC["Configuration Registers"]
    BD["Configuration Registers"] --> BE["Configuration Registers"]
    BF["Configuration Registers"] --> BG["Configuration Registers"]
    BH["Configuration Registers"] --> BI["Configuration Registers"]
    BJ["Configuration Registers"] --> BK["Configuration Registers"]
    BL["Configuration Registers"] --> BM["Configuration Registers"]
    BN["Configuration Registers"] --> BO["Configuration Registers"]
    BP["Configuration Registers"] --> BQ["Configuration Registers"]
    BR["Configuration Registers"] --> BS["Configuration Registers"]
    BT["Configuration Registers"] --> BU["Configuration Registers"]
    BV["Configuration Registers"] --> BW["Configuration Registers"]
    BX["Configuration Registers"] --> BY["Configuration Registers"]
    BZ["Configuration Registers"] --> CA["Configuration Registers"]
    CB["Configuration Registers"] --> DA["Configuration Registers"]
    DB["Configuration Registers"] --> DBA["Configuration Registers"]
    DC["Configuration Registers"] --> DBB["Configuration Registers"]
    DD["Configuration Registers"] --> DBC["Configuration Registers"]
    DBE["Configuration Registers"] --> DCB["Configuration Registers"]
    DCF["Configuration Registers"] --> DCG["Configuration Registers"]
    DCG --> DBH["Configuration Registers"]
    DBH --> DCI["Control Logic"]
    DCI --> DBJ["Control Logic"]
    DBJ --> DCK["Control Logic"]
    DCK --> DBL["Control Logic"]
    DCL --> DBM["Control Logic"]
    DCM --> DBN["Control Logic"]
    DCN --> DBO["Control Logic"]
    DCO --> DBP["Control Logic"]
    DCP --> DBQ["Control Logic"]
    DCQ --> DBR["Control Logic"]
    DCW --> DBS["Control Logic"]
    DCY --> DBT["Control Logic"]
    DCU --> DBU
    DCV --> DBV
    DCW --> DBW
    DCX --> DBX
    DCY --> DBY
    DCZ --> DBZ
    DCY --> DBX
    DCY --> DBY

The received RF signal at pin 5 (RFN) and pin 6 (RFP) is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the digital base band receiver (RX BBP).

The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding (spreading) according to [1] and [2]. The modulation signal is generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA).

Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V supply.

An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data.

The configuration of the Atmel AT86RF232, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines.

The AT86RF232 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP state.

To improve the reliability of an RF connection the RF performance can further be improved by using Antenna Diversity.

Additional features of the Extended Feature Set, see Chapter 11, are provided to simplify the interaction between radio transceiver and microcontroller.

5 Application Circuits

5.1 Basic Application Schematic

A basic application schematic of the Atmel AT86RF232 with a single-ended RF connector is shown in Figure 5-1. The 50Ω single-ended RF input is transformed to the 100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, optional capacitor C4 improves matching if required.

Figure 5-1. Basic Application Schematic.

AT86RF232 DVSS AVSS AVSS AVSS AVDD EVDD AVSS XTAL1 XTAL2 CB1 CB2 CX1 CX2 XTAL VDD 32 31 30 29 28 27 26 25 AVSS AVSS AVSS AVDD EVDD AVSS XTAL1 XTAL2 AVSS AVSS AVSS AVSS AVDD AVDD AVSS XTAL1 XTAL2 RV C4 B1 C1 C2 RFP RFN AVSS DVSS /RST DIG1 DIG2 SLP_TR DVSS DVDD DVDD DEVDD DVSS IRQ 24 /SEL 23 MOSI 22 DVSS 21 MISO 20 SCLK 19 DVSS 18 R1 VDD CLKM 17 C3 CB3 CB4 Digital Interface

The power supply decoupling capacitors (CB2, CB4) are connected to the external analog supply pin 28 (EVDD) and external digital supply pin 15 (DEVDD). Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. All decoupling and bypass capacitors should be placed as close as possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance.

The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of the reference frequency, large parasitic capacitances should be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O signals.

Crosstalk from digital signals on the crystal pins or the RF pins can degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close to the Atmel AT86RF232 CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the pin 17 (CLKM) is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization.

The ground plane of the application board should be separated into four independent fragments, the analog, the digital, the antenna and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds.

Table 5-1. Example Bill of Materials (BoM) for Basic Application Schematic.

Designator	Description	Value	Manufacturer	Part Number	Comment
B1	SMD balun	2.45GHz	Wuerth	748421245	2.45GHz Balun
B1(alternatively)	SMD balun / filter	2.45GHz	Johanson Technology	2450FB15L0001	2.45GHz Balun / Filter
CB1	LDO VREG bypass capacitor	100nF	Generic		X7R 10% 16V (0402)
CB2	Power supply decoupling	1μF	AVX Murata	0603YD105KAT2A GRM188R61C105KA12D	X5R 10% 16V (0603)
CB4
CX1, CX2	Crystal load capacitor	12pF	AVX Murata	06035A120JA GRM1555C1H120JA01D	COG 5% 50V (0402)
C1, C2	RF coupling capacitor	22pF	Murata Epcos AVX	GRM1555C1H220JA01J B37920 06035A220JAT2A	C0G 5% 50V (0402 or 0603)
C3	CLKM low-pass filter capacitor	2.2pF	AVX Murata	06035A229DA GRP1886C1H2R0DA01	COG ±0.5pF 50V (0603)
					Designed for _f_KM =1MHz
C4 (optional)	RF matching				Value depends on final PCB implementation
R1	CLKM low-pass filter resistor	680Ω			Designed for _f_KM =1MHz
XTAL	Crystal	CX-4025 16MHz SX-4025 16MHz	ACAL Taitjen Siward	XWBBPL-F-1 A207-011

5.2 Extended Feature Set Application Schematic

The Atmel AT86RF232 supports additional features like:

• Security Module (AES) Section 11.1
• Random Number Generator Section 11.2
- Antenna Diversity uses pins DIG1(/2) Section 11.3
- RX and TX Frame Time Stamping (TX_ARET) uses pin DIG2 Section 11.4

• Frame Buffer Empty Indicator uses pin IRQ Section 11.5

• Dynamic Frame Buffer Protection Section 11.6

An extended feature set application schematic illustrating the use of the AT86RF232 Extended Feature Set, see Chapter 11, is shown in Figure 5-2 Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations.

Figure 5-2. Extended Feature Application Schematic.

ANT0 SW1 Ant1 RF-Switch Balun B1 AVSS AVSS AVSS AVDD EVDD AVSS XTAL1 XTAL2 AT86RF232 1 2 3 4 5 6 7 8 RFP RFN AVSS DVSS /RST DIG1 DIG2 SLP_TR DVSS DVDD DVDD DEVDD DVSS CB1 CB2 CB3 CB4 CB1 CX1 XTAL CX2 IRQ 24 /SEL 23 MOSI 22 DVSS 21 MISO 20 SCLK 19 DVSS 18 R1 CLKM 17 C3 V_DD

In this example, a balun (B1) transforms the differential RF signal at the Atmel AT86RF232 radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 5-1. During receive mode the radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is selected (SW2) by the Antenna Diversity RF switch control pin 9 (DIG1), refer to Section 11.3.

RX and TX Frame Time stamping is implemented through pin 10 (DIG2), refer to Section 11.4.

The security engine (AES) does not require specific circuitry to operate, for details refer to Section 11.1.

6 Microcontroller Interface

This section describes the Atmel AT86RF232 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see Figure 6-1. The SPI timing and protocol are described below.

Figure 6-1. Microcontroller to AT86RF232 Interface.

graph LR
    A["Microcontroller AT86RF232 SPI"] --> B["SPI - Master"]
    A --> C["SPI - Slave"]
    B --> D["/SEL /SEL"] --> E["/SEL"] --> F["MOSI"] --> G["MOSI"] --> H["MISO"] --> I["SCLK"] --> J["MISO"] --> K["SCLK"] --> L["GPIO1/CLK"] --> M["CLKM"] --> N["CLKM"] --> O["GPIO2/IRQ"] --> P["IQ"] --> Q["IRQ"] --> R["GPIO3"] --> S["SLP_TR"] --> T["SLP_TR"] --> U["GPIO4"] --> V["/RST"] --> W["/RST"] --> X["GPIO5 DIG2"] --> Y["DIG2"] --> Z["GPIO1/CLK"] --> AA["CLKM"] --> AB["CLKM"] --> AC["GPIO2/IRQ"] --> AD["IQ"] --> AE["IRQ"] --> AF["GPIO3"] --> AG["SLP_TR"] --> AH["SLP_TR"] --> AI["GPIO4"] --> AJ["/RST"] --> AK["/RST"]
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#fcc,stroke:#333
    style E fill:#cff,stroke:#333
    style F fill:#ffc,stroke:#333
    style G fill:#ffc,stroke:#333
    style H fill:#ffc,stroke:#333
    style I fill:#ffc,stroke:#333
    style J fill:#ffc,stroke:#333
    style K fill:#ffc,stroke:#333
    style L fill:#ffc,stroke:#333
    style M fill:#ffc,stroke:#333
    style N fill:#ffc,stroke:#333
    style O fill:#ffc,stroke:#333
    style P fill:#ffc,stroke:#333
    style Q fill:#ffc,stroke:#333
    style R fill:#ffc,stroke:#333
    style S fill:#ffc,stroke:#333
    style T fill:#ffc,stroke:#333
    style U fill:#ffc,stroke:#333
    style V fill:#ffc,stroke:#333
    style W fill:#ffc,stroke:#333
    style X fill:#ffc,stroke:#333
    style Y fill:#ffc,stroke:#333

Microcontrollers with a master SPI such as Atmel AVR family interface directly to the AT86RF232. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 6-1 introduces the radio transceiver I/O signals and their functionality.

Table 6-1. Signal Description of Microcontroller Interface.

Signal	Description
/SEL	SPI select signal, active low
MOSI	SPI data (master output slave input) signal
MISO	SPI data (master input slave output) signal
SCLK	SPI clock signal
CLKM	Optional, Clock output, refer to Section 9.6.4, usable as:- microcontroller clock source- high precision timing reference
IRQ	Interrupt request signal, further used as:- Frame Buffer Empty indicator, refer to Section 11.5
SLP_TR	Multi purpose control signal (functionality is state dependent, see Section 6.5):- Sleep/Wakeup enable/disable SLEEP state- TX start BUSY_TX_(ARET) state
/RST	AT86RF232 reset signal, active low
DIG2	Optional,- IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.4- Signals frame transmit within TX_ARET mode for TX Time Stamping

6.1 SPI Timing Description

Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode.

In asynchronous mode, the maximum SCLK frequency f_async is limited to 7.5MHz. The signal at pin 17 (CLKM) is not required to derive SCLK and may be disabled to reduce power consumption and spurious emissions.

Figure 6-2 and Figure 6-3 illustrate the SPI timing and introduces its parameters. The corresponding timing parameter definitions t_1 - t_9 are defined in Section 12.4.

Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t_5 , t_6 , t_8 , t_9 .

/SEL SCLK MOSI MISO t0 t8 t5 t6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Figure 6-3. SPI Timing, Detailed Drawing of Timing Parameters t_1 to t_4 .

/SEL SCLK MOSI MISO t₁ t₂ t₃ t₄ Bit 7 Bit 6 Bit 5 Bit 7 Bit 6 Bit 5

The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H.

An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in Section 6.2.

/SEL = L enables the MISO output driver of the Atmel AT86RF232. The MSB of MISO is valid after t_1 (see Section 12.4 parameter) and is updated at each falling edge of SCLK. If the driver is disabled, there is no internal pull-up circuitry connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor.

Note: 1. When both /SEL and /RST are active, the MISO output driver is also enabled.

Referring to Figure 6-2 and Figure 6-3 Atmel AT86RF232 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t_3 and t_4 , refer to Section 12.4 parameters.

This SPI operational mode is commonly known as "SPI mode 0".

6.2 SPI Protocol

Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 6-2) with MSB first. This command byte defines the SPI access mode and additional mode-dependent information.

Table 6-2. SPI Command Byte Definition.

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0	Access Mode	Access Type
1	0	Register address [5:0]						Register access	Read access
1	1	Register address [5:0]							Write access
0	0	1	reserved					Frame Buffer access	Read access
0	1	1	reserved						Write access
0	0	0	reserved					SRAM access	Read access
0	1	0	reserved						Write access

Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte (see value "PHY_STATUS" in Figure 6-4 to Figure 6-14) is set to zero after reset. To transfer status information of the radio transceiver to the microcontroller, the content of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). For details, refer to Section 6.3.1.

In Figure 6-4 to Figure 6-14 and the following chapters logic values stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return values on MISO stated as XX shall be ignored by the microcontroller.

The different access modes are described within the following sections.

6.2.1 Register Access Mode

A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit[7] = 1), a read/write select bit (bit[6]), and a 6-bit register address.

On read access, the content of the selected register address is returned in the second byte on MISO (see Figure 6-4).

Figure 6-4. Packet Structure - Register Read Access.

byte 1 (command byte) → byte 2 (data byte) 1 ADDRESS[5:0]0 XXMOSI PHY_STATUS(1) READ DATA[7:0]MISO

Note: 1. Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for details refer to Section 6.3.

On write access, the second byte transferred on MOSI contains the write data to the selected address (see Figure 6-5).

Figure 6-5. Packet Structure - Register Write Access.

byte 1 (command byte) byte 2 (data byte) 1 ADDRESS[5:0]1 WRITE DATA[7:0]MOSI PHY_STATUS XXMISO

Each register access must be terminated by setting /SEL = H.

Figure 6-6 illustrates a typical SPI sequence for a register access sequence for write and read respectively.
Figure 6-6. Example SPI Sequence – Register Access Mode.

/SEL Register Write Access SCLK Register Read Access MOSI WRITE COMMAND WRITE DATA READ COMMAND XX MISO PHY_STATUS XX PHY_STATUS READ DATA

6.2.2 Frame Buffer Access Mode

The Atmel AT86RF232 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in Section 9.3. An introduction to the IEEE 802.15.4 frame format can be found in Section 8.1.

Frame Buffer read and write accesses are used to read or write frame data (PSDU and additional information) from or to the Frame Buffer. Each access starts with /SEL = L followed by a command byte on MOSI. If this byte indicates a frame read or write access, the next byte PHR indicates the frame length followed by the PSDU data, see Figure 6-7 and Figure 6-8.

On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO starting with the second byte. After the PSDU data, three more bytes are transferred containing the link quality indication (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of the received frame, for LQI details refer to Section 8.6. The Figure 6-7 illustrates the packet structure of a Frame Buffer read access.

Figure 6-7. Packet Structure - Frame Read Access.

byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) MOSI 0 0 1 reserved[4:0] XX XX ... MISO PHY_STATUS PHR[7:0] PSDU[7:0] ... byte n-1 (data byte) byte n (data byte)

The structure of RX_STATUS is described in Table 6-3.

Table 6-3. Structure of RX_STATUS.

Bit	7	6	5	4
	RX_CRC_VALID	TRAC_STATUS			RX_STATUS
Read/Write	R	R	R	R
Reset value	0	0	0	0
Bit	3	2	1	0
	reserved				RX_STATUS
Read/Write	R	R	R	R
Reset value	0	0	0	0

Note: 1. More information to RX_CRC_VALID, see Section 8.2.5, and to TRAC_STATUS, see Section 7.2.6.

On Frame Buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the payload data (PSDU) as shown by Figure 6-8.

Figure 6-8. Packet Structure - Frame Write Access.

byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) 0 es rdr [7:0]MOS PSDU[7:0] ... PSDU[7:0] PSDU[7:0] PHY_STATUSMISO XX XX ... XX XX

The number of bytes n for one frame access is calculated as follows:

Read Access: n = 5 + frame_length

[PHY_STATUS, PHR byte, PSDU data, LQI, ED, and RX_STATUS]

Write Access: n = 2 + frame_length

[command byte, PHR byte, and PSDU data]

Each read or write of a data byte automatically increments the address counter of the Frame Buffer until the access is terminated by setting /SEL = H. A Frame Buffer read access may be terminated (/SEL = H) at any time without affecting the Frame Buffer content. Another Frame Buffer read operation starts again at the PHR field.

The content of the Atmel AT86RF232 Frame Buffer is overwritten by a new received frame or a Frame Buffer write access.

Figure 6-9 and Figure 6-10 illustrate an example SPI sequence of a Frame Buffer access to read a frame with 2-byte PSDU and write a frame with 4-byte PSDU.

Figure 6-9. Example SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU.

/SEL SCLK MOSI COMMAND XX XX XX XX XX XX MISO PHY_STATUS PHR PSDU 1 PSDU 2 LQI ED RX_STATUS

Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4-byte PSDU.

/SEL SCLK MOSI COMMAND PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4 MISO PHY_STATUS XX XXXX XXXX

Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further details, refer to Section 9.3.

Notes: 1. The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile.
2. To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to Section 11.6.
3. For exceptions, receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to Section 7.2.4.

6.2.3 SRAM Access Mode

The SRAM access mode allows accessing dedicated bytes within the Atmel AT86RF232 Frame Buffer or AES address space, refer to Section 11.1.

During frame receive after occurrence of interrupt IRQ_2 (RX_START) an SRAM access can be used to upload the PHR field while preserving Dynamic Frame Buffer Protection, see Section 11.6.

Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in Table 6-2. The following byte indicates the start address of the write or read access.

SRAM address space:

• Frame Buffer: 0x00 to 0x7F
• AES: 0x82 to 0x94

On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence (see Figure 6-11).

Figure 6-11. Packet Structure – SRAM Read Access.

byte 1 (command byte) byte 2 (address) byte 3 (data byte) MOSI 0 0 0 reserved[4:0] ADDRESS[7:0] XX ... XX MISO PHY_STATUS XX DATA[7:0] ... DATA[7:0] DATA[7:0]

On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see Figure 6-12).

Figure 6-12. Packet Structure – SRAM Write Access.

byte 1 (command byte) byte 2 (address) byte 3 (data byte) 0 eserved address DATA[7:0] ... DATA[7:0] DATA[7:0] PHY_STATUSMISO XX XX ... XX XX

As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H.

Figure 6-13 and Figure 6-14 illustrate an example SPI sequence of an Atmel AT86RF232 SRAM access to read and write a data package of five byte length respectively.

Figure 6-13. Example SPI Sequence – SRAM Read Access of a 5-byte Data Package.

/SEL SCLK MOSI COMMAND ADDRESS XX XX XX XX XX MISO PHY_STATUS XX DATA 1 DATA 2 DATA 3 DATA 4 DATA 5

Figure 6-14. Example SPI Sequence – SRAM Write Access of a 5-byte Data Package.

/SEL SCLK MOSI COMMAND ADDRESS DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 MISO PHY_STATUS XX XX XX XX XX

Notes: 1. The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see Section 6.2.2).

1. Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for further details refer to Section 9.3.3.

6.3 Radio Transceiver Status information

Each Atmel AT86RF232 SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO.

The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the first byte send on MISO to the microcontroller is set to zero.

6.3.1 Register Description

Register 0x04 (TRX\_CTRL\_1):

The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver.

Figure 6-15. Register TRX_CTRL_1.

Bit	7	6	5	4
0x04	reserved	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0
Bit	3	2	1	0
0x04	SPI_CMD_MODE		IRQ_MASK_MOD	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0

- Bit 3:2 - SPI\_CMD\_MODE

Each SPI transfer returns bytes back to the SPI master. The content of the first byte (PHY_STATUS) can be configured using register bits SPI_CMD_MODE.

Table 6-4. SPI CMD MODE.

Register Bits	Value	Description
SPI_CMD_MODE	0	Default (empty, all bits zero)
	1	Monitor TRX_STATUS register
	2	Monitor PHY_RSSI register
	3	Monitor IRQ_STATUS register

Note: 1. More information to register TRX_STATUS, see Section 7.1.5, to register PHY_RSSI, see Section 8.3, and to register IRQ_STATUS, see Section 6.6.

6.4 Radio Transceiver Identification

The Atmel AT86RF232 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID.

6.4.1 Register Description

Register 0x1C (PART\_NUM):

The register PART_NUM can be used for the radio transceiver identification and includes the device part number.

Figure 6-16. Register PART_NUM.

- Bit 7:0 - PART\_NUM

Table 6-5. PART_NUM.

Register Bits	Value	Description
PART_NUM	0x0A	AT86RF232 part number

Register 0x1D (VERSION\_NUM):

The register VERSION_NUM can be used for the radio transceiver identification and includes the device version number.

Figure 6-17. Register VERSION_NUM.

- Bit 7:0 - VERSION\_NUM

Table 6-6. VERSION NUM.

Register Bits	Value	Description
VERSION_NUM	0x02	Revision A

Register 0x1E (MAN\_ID\_0):

Part one of the JEDEC manufacturer ID.

Figure 6-18. Register MAN_ID_0.

- Bit 7:0 - MAN\_ID\_0

Table 6-7. MAN ID 0.

Register Bits	Value	Description
MAN_ID_0	0x1F	Atmel JEDEC manufacturer ID, bits[7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The higher 16 bits of the ID are not stored in registers.

Register 0x1F (MAN\_ID\_1):

Part two of the JEDEC manufacturer ID.

Figure 6-19. Register MAN_ID_1.

- Bit 7:0 - MAN\_ID\_1

Table 6-8. MAN ID 1.

Register Bits	Value	Description
MAN_ID_1	0x00	Atmel JEDEC manufacturer ID, bits[15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers.

6.5 Sleep/Wake-up and Transmit Signal (SLP\_TR)

Pin 11 (SLP_TR) is a multi-functional pin. Its function relates to the current state of the Atmel AT86RF232 and is summarized in Table 6-9. The radio transceiver states are explained in detail in Chapter 7.

Table 6-9. SLP_TR Multi-functional Pin.

Transceiver Status	Function	Transition	Description
PLL_ON	TX start	L ⇔ H	Starts frame transmission
TX_ARET_ON	TX start	L ⇔ H	Starts TX_ARET transaction
TRX_OFF	Sleep	L ⇔ H	Takes the radio transceiver into SLEEP state, CLKM disabled
SLEEP	Wakeup	H ⇔ L	Takes the radio transceiver back into TRX_OFF state, level sensitive

In states PLL_ON and TX_ARET_ON, pin 11 (SLP_TR) is used as trigger input to initiate a TX transaction. Here SLP_TR is sensitive on rising edge only.

After initiating a state change by a rising edge at pin 11 (SLP_TR) in radio transceiver state TRX_OFF, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge.

SLEEP state

The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF232 can be powered down to reduce the overall power consumption.

A power-down scenario is shown in Figure 6-20. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF232 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 CLKM cycles. The AT86RF232 awakes when the microcontroller releases pin 11 (SLP_TR).

The CLKM clock frequency setting for 62.5kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering SLEEP state.

Figure 6-20. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer.

SLP_TR CLKM tTR3 (35 CLKM clock cycles) CLKM off tTR1a async timer elapses (microcontroller)

Note: 1. Timing figures t_TR3 and t_TR1a refer to Table 7-1.

6.6 Interrupt Logic

6.6.1 Overview

The Atmel AT86RF232 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ pin). If an interrupt is issued, pin 24 (IRQ) = H, the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ pin, too.

Interrupts are not cleared automatically when the event that caused them vanishes. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the occurrence of one clears the other.

The supported interrupts for the Basic Operating Mode are summarized in Table 6-10.

Table 6-10. Interrupt Description in Basic Operating Mode.

IRQ Name	Description	Section
IRQ_7 (BAT_LOW)	Indicates a supply voltage below the programmed threshold.	9.5.4
IRQ_6 (TRX_UR)	Indicates a Frame Buffer access violation.	9.3.3
IRQ_5 (AMI)	Indicates an address match.	7.2.3.4
IRQ_4 (CCA_ED_DONE)	Multi-functional interrupt:1. AWAKE_END:Indicates finished transition to TRX_OFF state from P_ON, SLEEP, or RESET state.2. CCA_ED_DONE:Indicates the end of a CCA or ED measurement.	7.1.2.38.4.48.5.4
IRQ_3 (TRX_END)	RX: Indicates the completion of a frame reception.TX: Indicates the completion of a frame transmission.	7.1.37.1.3
IRQ_2 (RX_START)	Indicates the start of a PSDU reception. Register bits TRX_STATUS changes to BUSY_RX, the PHR is valid to be read from Frame Buffer.	7.1.3
IRQ_1 (PLL_UNLOCK)	Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately.	9.7.5
IRQ_0 (PLL_LOCK)	Indicates PLL lock.	9.7.5

Note: 1. The IRQ_4 (AWAKE_END) interrupt can usually not be seen when the transceiver enters TRX_OFF state after P_ON, or RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. It is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered.

The interrupt handling in Extended Operating Mode is described in Section 7.2.5.

6.6.2 Interrupt Mask Modes and Pin Polarity

If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided. The Table 6-11, Figure 6-21, and Figure 6-22 describes the function.

Table 6-11. IRQ Mask Configuration.

IRQ_MASK Value	IRQ_MASK_MODE	Description
0	0	IRQ is suppressed entirely and none of interrupt causes are shown in register IRQ_STATUS.
0	1	IRQ is suppressed entirely but all interrupt causes are shown in register IRQ_STATUS.
≠0	0	All enabled interrupts are signaled on IRQ pin and are also shown in register IRQ_STATUS.
≠0	1	All enabled interrupts are signaled on IRQ pin and all interrupt causes are shown in register IRQ_STATUS.

Figure 6-21. IRQ_MASK_MODE = 0.

graph LR
    A["Interrupt Sources"] --> B["IRQ_MASK (register 0x0E)"]
    B --> C["IRQ_STATUS (register 0x0F)"]
    C --> D["OR"]
    D --> E["IRQ"]

Figure 6-22. IRQ_MASK_MODE = 1.

graph LR
    A["Interrupt Sources"] --> B["IRQ_STATUS (register 0x0F)"]
    B --> C["IRQ_MASK (register 0x0E)"]
    C --> D["OR"]
    D --> E["IRQ"]

The Atmel AT86RF232 IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin 24 (IRQ) = H issues an interrupt request.

If "Frame Buffer Empty Indicator" is enabled during Frame Buffer read access the IRQ pin has an alternative functionality, refer to Section 11.5 for details.

6.6.3 Register Description

Register 0x0E (IRQ\_MASK):

The IRQ_MASK register controls the interrupt signaling via pin 24 (IRQ).

Figure 6-23. Register IRQ_MASK.

- Bit 7:0 - IRQ\_MASK

Mask register for interrupts. IRQ_MASK[7] correspondents with IRQ_7_BAT_LOW. IRQ_MASK[0] correspondents with IRQ_0_PLL_LOCK.

Table 6-12. IRQ_MASK.

Register Bits	Value	Description
IRQ_MASK	0x00	The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the corresponding bit is set to one. All interrupts are disabled after power-on sequence (P_ON state) or reset (RESET state).Valid values are [0xFF, 0xFE, ..., 0x00].

Note: 1. If an interrupt is enabled it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history.

Register 0x0F (IRQ\_STATUS):

The IRQ_STATUS register contains the status of the pending interrupt requests.

Figure 6-24. Register IRQ_STATUS.

Bit 0x0F	7	6	5	4	IRQ_STATUS
	IRQ_7_BAT_LOV	IRQ_6_TRX_UR	IRQ_5_AMI	IRQ_4_CCA_ED_DONE
Read/Write	R	R	R	R
Reset value	0	0	0	0
Bit 0x0F	3	2	1	0	IRQ_STATUS
	IRQ_3_TRX_END	IRQ_2_RX_START	IRQ_1_PLL_UNLOCK	IRQ_0_PLL_LOCK
Read/Write	R	R	R	R
Reset value	0	0	0	0

For more information to meanings of interrupts, see Table 6-10 Interrupt Description in Basic Operating Mode.

By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register.

Notes: 1. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However in that case no timing information for this interrupt is provided.
2. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history.

Register 0x04 (TRX\_CTRL\_1):

The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver.

Figure 6-25. Register TRX_CTRL_1.

Bit	7	6	5	4
0x04	reserved	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0
Bit	3	2	1	0
0x04	SPI_CMD_MODE		IRQ_MASK_MOD	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0

- Bit 6 - IRQ\_2\_EXT\_EN

Controls external signaling for time stamping via pin 10 (DIG2).

Table 6-13. IRQ_2_EXT_EN.

Register Bits	Value	Description
IRQ_2_EXT_EN	0	Time stamping over pin 10 (DIG2) is disabled
	1^(1)	Time stamping over pin 10 (DIG2) is enabled

Notes: 1. The pin 10 (DIG2) is also active even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to zero.

1. The pin remains at high level until the end of the frame receive or transmit procedure.

The timing of a received frame can be determined by a separate pin 10 (DIG2). If register bit IRQ_2_EXT_EN is set to one, the reception of a PHR is directly issued on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START).

For further details refer to Section 11.4.

- Bit 1 - IRQ\_MASK\_MODE

The radio transceiver supports polling of interrupt events. Interrupt polling can be enabled by register bit IRQ_MASK_MODE.

Table 6-14. IRQ MASK MODE.

Register Bits	Value	Description
IRQ_MASK_MODE	0	Interrupt polling is disabledMasked off IRQ bits will not appear in IRQ_STATUS register.
	1	Interrupt polling is enabledMasked off IRQ bits will appear in IRQ_STATUS register.

Even if an interrupt request is masked by the corresponding bit in register 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS).

- Bit 0 - IRQ\_POLARITY

The register bit IRQ_POLARITY controls the polarity for pin 24 (IRQ). The default polarity of the pin 24 (IRQ) is active high. The polarity can be configured to active low via register bit IRQ_POLARITY.

Table 6-15. IRQ POLARITY.

Register Bits	Value	Description
IRQ_POLARITY	0	Pin IRQ is high active
	1	Pin IRQ is low active

Note: 1. A modification on IRQ_POLARITY bit has no influence to RX_BL_CTRL behavior.

This setting does not affect the polarity of the “Frame Buffer Empty Indicator”, refer to Section 11.5. The Frame Buffer Empty Indicator is always active high.

7 Operating Modes

7.1 Basic Operating Mode

This section summarizes all states to provide the basic functionality of the Atmel AT86RF232, such as receiving and transmitting frames, the power-on sequence, and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and general ISM band applications; the corresponding radio transceiver states are shown in Figure 7-1.

Figure 7-1. Basic Operating Mode State Diagram (for timing refer to Table 7-1).

graph TD
    A["TRX_OFF (Clock State)"] -->|12/3/5/7/8/9/10/11/12/13| B["RESET"]
    A -->|15/2/3/4/6/8/9/10/11/12/13| C["P_ON (Power-on after V_DD)"]
    A -->|12/3/5/7/8/9/10/11/12/13| D["SLEEP (Sleep State)"]
    A -->|15/2/3/4/6/8/9/10/11/12/13| E["BUSY_RX (Receive State)"]
    A -->|12/3/5/7/8/9/10/11/12/13| F["RX_ON (Rx Listen State)"]
    A -->|12/3/5/7/8/9/10/11/12/13| G["PLL_ON (PLL State)"]
    A -->|12/3/5/7/8/9/10/11/12/13| H["BUSY_TX (Transmit State)"]
    A -->|12/3/5/7/8/9/10/11/12/13| I["BUSY_RX (Receive State)"]
    A -->|12/3/5/7/8/9/10/11/12/13| J["BUSY_TX (Transmit State)"]
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#cfc,stroke:#333
    style E fill:#cfc,stroke:#333
    style F fill:#cfc,stroke:#333
    style G fill:#cfc,stroke:#333
    style H fill:#cfc,stroke:#333
    style I fill:#cfc,stroke:#333
    style J fill:#cfc,stroke:#333

7.1.1 State Control

The radio transceiver states are controlled either by writing commands to register bits TRX_CMD (register 0x02, TRX_STATE), or directly by two signal SLP_TR and /RST pins. A successful state change can be verified by reading the radio transceiver status from register bits TRX_STATUS (register 0x01, TRX_STATUS).

If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the Atmel AT86RF232 is within a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS.

Pin 11 (SLP_TR) is a multifunctional pin, refer to Section 6.5. Depending on the radio transceiver state, a rising edge of pin 11 (SLP_TR) causes the following state transitions:

• TRX_OFF SLEEP (level sensitive)
• PLL_ON BUSY_TX

Whereas the falling edge of pin SLP_TR causes the following state transitions:

- SLEEP TRX_OFF (level sensitive)

A low level on pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details refer to Section 9.6.4) and forces the radio transceiver into TRX_OFF state. However, if the device was in P_ON state it remains in the P_ON state.

For all states except SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states (BUSY_ ^* ), the command FORCE_TRX_OFF interrupts these active processes, and forces an immediate transition to TRX_OFF. In contrast a TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is performed.

For a fast transition from any non sleep states to PLL_ON state, the command FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this command does not disable PLL and analog voltage regulator (AVREG). It is not available in states P_ON, SLEEP, or RESET.

The completion of each requested state change shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS).

Note: 1. If FORCE_TRX_OFF and FORCE_PLL_ON commands are used, it is recommended to set pin 11 (SLP_TR) = L before.

7.1.2 Basic Operating Mode Description

7.1.2.1 P\_ON - Power-On after V_DD

When the external supply voltage ( V_DD ) is firstly applied to the AT86RF232, the radio transceiver goes into the P_ON state performing an on-chip reset. The crystal oscillator is activated and the default 1MHz master clock is provided at pin 17 (CLKM) after the crystal oscillator has stabilized. CLKM can be used as a clock source to the microcontroller. The SPI interface and digital voltage regulator (DVREG) are enabled.

The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal from the microcontroller at pin 8 (/RST) is not necessary, but recommended for hardware / software synchronization reasons.

All digital inputs are pulled-up or pulled-down during P_ON state, refer to Section 1.3.2. This is necessary to support microcontrollers where GPIO signals are floating after power-on or reset. The input pull-up and pull-down circuitry is disabled when the radio transceiver leaves the P_ON state. Output pins DIG1/DIG2 are pulled-down to digital ground, unless their configuration is changed.

Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF232 pins to the default operating values: pin 11 (SLP_TR) = L, pin 8 (/RST) = H and pin 23 (/SEL) = H.

All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, for example enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a locked PLL in PLL_ON state. In P_ON state a first access to the radio transceiver registers is possible after a default 1MHz master clock is provided at pin 17 (CLKM), refer to t_TR1 to Table 7-1.

Once the supply voltage has stabilized and the crystal oscillator has settled (see parameter t_XTAL refer to Table 7-2), a valid SPI write access to register bits TRX_CMD (register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF initiate a state change from P_ON towards TRX_OFF state, which is then indicated by an interrupt IRQ_4 (AWAKE_END) if enabled.

7.1.2.2 SLEEP – Sleep State

In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating beyond the circuitry monitoring pin 11 (SLP_TR) and pin 8 (/RST). This state can only be entered from state TRX_OFF, by setting the SLP_TR = H.

If CLKM is enabled with a clock rates higher than 62.5kHz, the SLEEP state is entered 35 CLKM cycles after the rising edge at pin 11 (SLP_TR). At that time CLKM is turned off. If the CLKM output is already turned off (register bits CLKM_CTRL = 0), the SLEEP state is entered immediately. At clock rate 62.5kHz, the main clock at pin 17 (CLKM) is turned off immediately.

Setting SLP_TR = L returns the radio transceiver to the TRX_OFF state. During SLEEP state the radio transceiver register contents and the AES register contents remain valid while the contents of the Frame Buffer are destroyed.

/RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4.

Note: 1. If during SLEEP state a voltage jump on V_DD occurs of more than 0.8V within 1ms, the internal Power-On logic detects this as a P_ON reset and the AT86RF232 goes into the P_ON state.

7.1.2.3 TRX\_OFF - Clock State

In TRX_OFF the crystal oscillator is running and the master clock is available if enabled. The SPI interface and digital voltage regulator are enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are accessible (see Section 9.3 and Section 11.1).

In contrast to P_ON state the pull-up and pull-down configuration is disabled.

Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control. The analog front-end is disabled during TRX_OFF state.

Entering the TRX_OFF state from P_ON, SLEEP or RESET state is indicated by interrupt IRQ_4 (AWAKE_END) if enabled.

7.1.2.4 PLL\_ON - PLL State

Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage regulator has been settled, the PLL frequency

synthesizer is enabled. When the PLL has been settled at the receive frequency to a channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA), refer to Section 9.7.2, a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK).

If an RX_ON command is issued in PLL_ON state, the receiver is enabled immediately. If the PLL has not been settled before the state change nevertheless takes place. Even if the register bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON, actual frame reception can only start once the PLL has locked.

The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.

7.1.2.5 RX\_ON and BUSY\_RX - RX Listen and Receive State

In RX_ON state the receiver module and the PLL frequency synthesizer are enabled.

The Atmel AT86RF232 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which is always turned on. In both states, the receiver and the PLL frequency synthesizer are enabled.

During RX_ON state, the receiver listens for incoming frames. After detecting a valid synchronization header (SHR), the AT86RF232 automatically enters the BUSY_RX state. The reception of a valid PHY header (PHR) generates an IRQ_2 (RX_START) and starts the PSDU data demodulation.

During PSDU reception, the frame data are stored continuously in the Frame Buffer until the last byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3 (TRX_END) and the radio transceiver reenters the state RX_ON. At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see Section 8.2).

Received frames are passed to the frame filtering unit, refer to Section 7.2.3.4. If the content of the MAC addressing fields (refer to [1] IEEE 802.15.4-2006 Section 7.2.1) of a frame matches to the expected addresses, which is further dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to Section 6.6. The expected address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering is available in Basic Operating Mode and Extended Operating Mode, refer to Section 7.2.3.4.

Leaving state RX_ON is possible by writing a state change command to register bits TRX_CMD in register 0x02 (TRX_STATE).

7.1.2.6 BUSY\_TX - Transmit State

A transmission can be initiated in state PLL_ON. There are two ways to start a transmission:

• Rising edge of pin 11 (SLP_TR)
• TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE).

Either of these takes the radio transceiver into the BUSY_TX state.

During the transition to BUSY_TX state, the PLL frequency shifts to the transmit frequency. The actual transmission of the first data chip of the SHR starts after 16 s to allow PLL settling and PA ramp-up, see Figure 7-6. After transmission of the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame length of zero, the transmission is aborted.

After the frame transmission has completed, the Atmel AT86RF232 automatically turns off the power amplifier, generates an IRQ_3 (TRX_END) interrupt and returns into PLL_ON state.

7.1.2.7 RESET State

The RESET state is to reset all registers and state machines of the AT86RF232 to their default values, exception are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4.

A reset forces the radio transceiver into TRX_OFF state. If the device is still in the P_ON state it remains in the P_ON state though.

A reset is initiated with pin 8 (/RST) = L and the state is left after setting /RST = H. The reset pulse should have a minimum length as specified in Section 12.4 see parameter t_10 .

During reset the microcontroller has to set the radio transceiver control SLP_TR and /SEL pins to their default values.

An overview about the register reset values is provided in Table 14-2.

7.1.3 Interrupt Handling

All interrupts provided by the Atmel AT86RF232 (see Table 6-10) are supported in Basic Operating Mode.

For example, interrupts are provided to observe the status of radio transceiver RX and TX operations.

On reception IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception.

On transmission IRQ_3 (TRX_END) indicates the completion of the frame transmission.

Figure 7-2 shows an example for a transmit/receive transaction between two devices and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame containing a MAC header (in this example of length seven), payload and valid FCS. The frame is received by Device 2 which generates the interrupts during the processing of the incoming frame. The received frame is stored in the Frame Buffer.

The first interrupt IRQ_2 (RX_START) signals the reception of a valid PHR.

If the received frame passes the address filter, refer to Section 7.2.3.4, an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR).

In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of the received frame. In Extended Operating Mode, refer to Section 7.2; the interrupt is only issued if the received frame passes the address filter and the FCS is valid. Further exceptions are explained in Section 7.2.

Processing delay t_IRQ is a typical value, refer to Section 12.4.

Figure 7-2. Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode.

-16 0 128 160 192 192+(9+m)*32 Time [µs] TRX_STATE PLL_ON BUSY_TX PLL_ON SLP_TR IRQ Typ. Processing Delay tTR10 Number of Octets 4 1 1 7 m 2 Frame Content Preamble SFD PHR MHR MSDU FCS TRX_STATE RX_ON BUSY_RX RX_ON IRQ Interrupt latency tIRQ tIRQ IRQ_2 (RX_START) IRQ_5 (AMI) TRX_END tIRQ tIRQ tIRQ Frame on Air RX (Device 2)

7.1.4 Basic Operating Mode Timing

The following paragraphs depict Atmel AT86RF232 state transitions and their timing properties. Timing figures are explained in Table 7-1, Table 7-2, and Section 12.4.

7.1.4.1 Power-on Procedure

The power-on procedure to P_ON state is shown in Figure 7-3.

Figure 7-3. Power-on Procedure to P_ON State.

0 100 400 Time [µs] Event VDD on CLKM on State P_ON Block XOSC, DVREG Time When the external supply voltage ( V_DD ) is first supplied to the AT86RF232, the radio transceiver enables the crystal oscillator (XOSC) and the internal 1.8V voltage regulator for the digital domain (DVREG). After t_TR1 = 330 s (typ.), the master clock signal is available at pin 17 (CLKM) at default rate of 1MHz. As soon as CLKM is available the SPI is enabled and can be used to control the transceiver. As long as no state change towards state TRX\_OFF is performed, the radio transceiver remains in P\_ON state.

7.1.4.2 Wake-up Procedure

The wake-up procedure from SLEEP state is shown in Figure 7-4. Figure 7-4. Wake-up Procedure from SLEEP State. 

0 200 Time [µs] Event SLP_TR = L CLKM on IRQ_4 (AWAKE_END) State SLEEP TRX_OFF Block XOSC, DVREG FTN XOSC, DVREG Time tTR2

The radio transceiver's SLEEP state is left by releasing SLP\_TR pin to logic low. This restarts the XOSC and DVREG. After t_R2=210 s (typ.) the radio transceiver enters TRX\_OFF state. The internal clock signal is available and provided to pin 17 (CLKM), if CLKM was enabled. This procedure is similar to the Power-on Procedure. However the radio transceiver automatically proceeds to the TRX\_OFF state. During this, transition the filter-tuning network (FTN) calibration is performed. Entering TRX\_OFF state is signaled by IRQ\_4 (AWAKE\_END), if this interrupt was enabled by the appropriate mask register bit.

7.1.4.3 PLL\_ON and RX\_ON States

The transition from TRX\_OFF to PLL\_ON or RX\_ON mode is shown in Figure 7-5. Figure 7-5. Transition from TRX\_OFF to PLL\_ON or RX\_ON state. 

Event State TRX_OFF Block Command Time 0 80 Time [µs] IRQ_0 (PLL_LOCK) PLL_ON RX_ON AVREG PLL / RX PLL_ON RX_ON tTR4 tTR8

Notes: 1. If TRX\_CMD = RX\_ON in TRX\_OFF state RX\_ON state is entered immediately, even if the PLL has not settled. 2. Timing figures t_TR4 and t_TR8 refers to Table 7-1. In TRX\_OFF state, entering the commands PLL\_ON or RX\_ON initiates a ramp-up sequence of the internal 1.8V voltage regulator for the analog domain (AVREG). RX\_ON state can be entered any time from PLL\_ON state regardless whether the PLL has already locked, which is indicated by IRQ\_0 (PLL\_LOCK).

7.1.4.4 BUSY\_TX and RX\_ON States

The transition from PLL\_ON to BUSY\_TX state and subsequently to RX\_ON state is shown in Figure 7-6. Figure 7-6. PLL\_ON to BUSY\_TX to RX\_ON Timing. 

0 16 x x + 32 Time [µs] Pin SLP_TR State PLL_ON BUSY_TX RX_ON Block PLL PA PA, TX PLL RX Command or command TX_START RX_ON Time tTR10 tTR11

Starting from PLL\_ON state it is further assumed that the PLL is already locked. A transmission is initiated either by a rising edge of pin 11 (SLP\_TR) or by command TX\_START, the Atmel AT86RF232 changes into BUSY\_TX state. The PLL settles to the transmit frequency and the PA is enabled. T_R10 = 16 s after initiating the transmission starts the internally generated SHR transmission. After that the PSDU data are transmitted from the Frame Buffer. After completing the frame transmission, indicated by IRQ\_3 (TRX\_END), the PLL settles back to the receive frequency within t_TR11 = 32 s in state PLL\_ON. If during TX\_BUSY the radio transmitter is programmed to change to a receive state it automatically proceeds the state change to RX\_ON state after finishing the transmission.

7.1.4.5 Reset Procedure

The radio transceiver reset procedure is shown in Figure 7-7. Figure 7-7. Reset Procedure. 

0 x x + 10 x + 30 Time [µs] Event [IRQ_4 (AWAKE_END)] State various TRX_OFF Block XOSC, DVREG FTN XOSC, DVREG Pin /RST Time >t₁₀ >t₁₁ tᵣ₃₁₃

Note: 1. Timing figure t TR13 refers to Table 7-1, t_10 , t_11 refers to Section 12.4. /RST = L sets all registers to their default values. Exceptions are register bits CLKM\_CTRL (register 0x03, TRX\_CTRL\_0), refer to Section 9.6.4. After releasing the reset pin 8 (/RST) = H the wake-up sequence including an FTN calibration cycle is performed, refer to Section 9.8. After that the TRX\_OFF state is entered. Figure 7-7 illustrates the reset procedure once the P\_ON state was left and the radio transceiver was not in SLEEP state. The reset procedure is identical for all originating radio transceiver states except of state P\_ON, or SLEEP. Instead, here the procedure described in Section 7.1.2.1 must be followed to enter the TRX\_OFF state. If the radio transceiver was in state SLEEP, the XOSC and DVREG are enabled before entering TRX\_OFF state. If register bits TRX\_STATUS indicates STATE\_TRANSITION\_IN\_PROGRESS during system initialization until the Atmel AT86RF232 reaches TRX\_OFF state, do not try to initiate a further state change while the radio transceiver is in this state. Notes: 2. The reset impulse should have a minimum length t_10 = 625ns as specified in Section 12.4. 3. An access to the device should not occur earlier than t 11 ≥ 625ns after releasing the /RST pin; refer to Section 12.4. 4. A reset overrides an SPI command request that might have been queued.

7.1.4.6 State Transition Timing Summary

The Atmel AT86RF232 transition numbers correspond to Figure 7-1 and do not include SPI access time unless otherwise stated. See measurement setup in Figure 5-1. Table 7-1. State Transition Timing.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
t_TR1	P_ON⇒CLKM is available	Depends on crystal oscillator setup ( C_L = 10pF) and external capacitor at DVDD (100nF nom.).		330	1000	μs
t_TR1a	SLEEP⇒CLKM is available	Depends on crystal oscillator setup ( C_L = 10pF) and external capacitor at DVDD (100nF nom.).		180	1000	μs
t_TR2	SLEEP⇒TRX_OFF	Depends on crystal oscillator setup ( C_L = 10pF) and external capacitor at DVDD (100nF nom.).		210	1000	μs
t_TR3	TRX_OFF⇒SLEEP	For f_CLKM>62.5kHz .Otherwise.		350		CLKM cyclesCLKM cycles
t_TR4	TRX_OFF⇒PLL_ON	Depends on external capacitor at AVDD (100nF nom.).		80		μs
t_TR5	PLL_ON⇒TRX_OFF			1		μs
t_TR6	TRX_OFF⇒RX_ON	Depends on external capacitor at AVDD (100nF nom.).		80		μs
t_TR7	RX_ON⇒TRX_OFF			1		μs
t_TR8	PLL_ON⇒RX_ON			1		μs
t_TR9	RX_ON⇒PLL_ON	Transition time is also valid for TX_ARET_ON, RX_AACK_ON.		1		μs
t_TR10	PLL_ON⇒BUSY_TX	When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START first symbol transmission is delayed by one symbol period (PLL settling and PA ramp-up).		16		μs
t_TR11	BUSY_TX⇒PLL_ON	PLL settling time.		32		μs
t_TR12	Various states⇒TRX_OFF	Using TRX_CMD = FORCE_TRX_OFF; not valid for SLEEP.		1		μs
t_TR13	RESET⇒TRX_OFF	Not valid for P_ON or SLEEP.		26		μs
t_TR14	Various states⇒PLL_ON	Using TRX_CMD = FORCE_PLL_ON; not valid for P_ON, SLEEP, or RESET.		1		μs
t_TR15	P_ON⇒TRX_OFF	Using TRX_CMD = TRX_OFF directly after CLKM is available.		360	1000	μs

The state transition timing is calculated based on the timing of the individual blocks shown in Figure 7-3 to Figure 7-7. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations. Table 7-2. Atmel AT86RF232 Block Initialization and Settling Time.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
t_XTAL	Reference oscillator settling time	Start XTAL⇒clock available at pin 17 (CLKM). Depends on crystal Q factor and load capacitor.		330	1000	μs
t_FTN	FTN calibration time				25	μs
t_DVREG	DVREG settling time	Depends on external bypass capacitor at DVDD (CB3 = 100nF nom., 10μF worst case).		50	1000	μs
t_AVREG	AVREG settling time	Depends on external bypass capacitor at AVDD (CB1 = 100nF nom., 10μF worst case).		50	1000	μs
t_PLL\_INIT	Initial PLL settling time	PLL settling time TRX_OFF⇒PLL_ON, including 50μs AVREG settling time.		80	250	μs
t_PLL\_SW	PLL settling time on channel switch	Duration of channel switch within frequency band.		11	100	μs
t_PLL\_CF	PLL CF calibration	PLL center frequency calibration.		8	24	μs
t_PLL\_DCU	PLL DCU calibration	PLL DCU calibration.			6	μs
t_RX\_TX	RX⇒TX	Maximum settling time RX⇒TX.			16	μs
t_TX\_RX	TX⇒RX	Maximum settling time TX⇒RX.			32	μs
t_SHR\_SYNC	SHR, sync	SHR synchronization period.	32	96	160	μs
t_RSSI	RSSI, update	RSSI update period in receive states.		2		μs
t_ED	ED measurement	ED measurement period is eight symbols.		135	180	μs
t_CCA	CCA measurement	CCA measurement period is eight symbols.		135	180	μs
t_RND	Random value, update	Random value update period.		1		μs
t_AES	AES core cycle time			23.4	24	μs

7.1.5 Register Description

Register 0x01 (TRX\_STATUS):

The read-only register TRX\_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Figure 7-8. Register TRX\_STATUS. 

- Bit 4:0 - TRX\_STATUS

The register bits TRX\_STATUS signals the current radio transceiver status. Table 7-3. TRX STATUS.

Register Bits	Value	Description
TRX_STATUS	0x00	P_ON
	0x01	BUSY_RX
	0x02	BUSY_TX
	0x06	RX_ON
	0x08	TRX_OFF (CLK Mode)
	0x09	PLL_ON (TX_ON)
	0x0F^(1)	SLEEP
	0x11^(2)	BUSY_RX_AACK
	0x12^(2)	BUSY_TX_ARET
	0x16^(2)	RX_AACK_ON
	0x19^(2)	TX_ARET_ON
	0x1F^(3)	STATE_TRANSITION_IN_PROGRESS
		All other values are reserved

Notes: 1. In SLEEP state register not accessible. 2. Extended Operating Mode only. 3. Do not try to initiate a further state change while the radio transceiver is in STATE\_TRANSITION\_IN\_PROGRESS state. A read access to register bits TRX\_STATUS reflects the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX\_CMD (register 0x02, TRX\_STATE). Alternatively, some state transitions can be initiated by the rising edge of pin 11 (SLP\_TR) in the appropriate state. These register bits are used for Basic and Extended Operating Mode, see Section 7.2. If the requested state transition is not completed yet, the TRX\_STATUS returns STATE\_TRANSITION\_IN\_PROGRESS. Do not try to initiate a further state change while the radio transceiver is in STATE\_TRANSITION\_IN\_PROGRESS. State transition timings are defined in Table 7-1.

Register 0x02 (TRX\_STATE):

The radio transceiver states are controlled via register TRX\_STATE using register bits TRX\_CMD. The read-only register bits TRAC\_STATUS indicate the status or result of an Extended Operating Mode transaction. Figure 7-9. Register TRX\_STATE. 

- Bit 4:0 - TRX\_CMD

A write access to register bits TRX\_CMD initiates a radio transceiver state transition. Table 7-4. TRX\_CMD.

Register Bits	Value	Description
TRX_CMD	0x00^(1)	NOP
	0x02^(2)	TX_START
	0x03	FORCE_TRX_OFF
	0x04^(3)	FORCE_PLL_ON
	0x06	RX_ON
	0x08	TRX_OFF (CLK Mode)
	0x09	PLL_ON (TX_ON)
	0x16^(4)	RX_AACK_ON
	0x19^(4)	TX_ARET_ON
		All other values are reserved

Notes: 1. TRX\_CMD = "0" after power on reset (POR). 2. The frame transmission starts one symbol after TX\_START command. 3. FORCE\_PLL\_ON is not valid for states P\_ON, SLEEP, and RESET, as well STATE\_TRANSITION\_IN\_PROGRESS towards these states. 4. Extended Operating Mode only. A write access to register bits TRX\_CMD initiates a radio transceiver state transition towards the new state. These register bits are used for Basic and Extended Operating Mode, see Section 7.2.

7.2 Extended Operating Mode

The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks as requested by the IEEE 802.15.4 standard, by hardware, such as automatic acknowledgement, automatic CSMA-CA and retransmission. This results in a more efficient IEEE 802.15.4 software MAC implementation including reduced code size and may allow the use of a smaller microcontroller or to operate at low clock rates. The Extended Operating Mode is designed to support IEEE 802.15.4-2006 and IEEE 802.15.4-2011 compliant frames; the mode is backward compatible to IEEE 802.15.4-2003 and supports non IEEE 802.15.4 compliant frames. This mode comprises the following procedures:

Automatic acknowledgement (RX\_AACK) divides into the tasks:

• Frame reception and automatic FCS check - Configurable addressing fields check - Interrupt indicating address match - Interrupt indicating frame reception, if it passes address filtering and FCS check - Automatic ACK frame transmission (if the received frame passed the address filter and FCS check and if an ACK is required by the frame type and ACK request) - Support of slotted acknowledgment using SLP\_TR pin

Automatic CSMA-CA and Retransmission (TX\_ARET) divides into the tasks:

• CSMA-CA including automatic CCA retry and random back-off • Frame transmission and automatic FCS field generation - Reception of ACK frame (if an ACK was requested) • Automatic frame retry if ACK was expected but not received - Interrupt signaling with transaction status Automatic FCS check and generation, refer to Section 8.2, is used by the RX\_AACK and TX\_ARET modes. In RX\_AACK mode, an automatic FCS check is always performed for incoming frames. In TX\_ARET mode, an ACK, received within the time required by IEEE 802.15.4, is accepted if the FCS is valid, and if the sequence number of the ACK matches the sequence number of the previously transmitted frame. Dependent on the value of the frame pending subfield in the received acknowledgement frame the transaction status is set, see TRAC\_STATUS, Section 7.2.7. An Atmel AT86RF232 state diagram including the Extended Operating Mode states is shown in Figure 7-10. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode. Figure 7-10. Extended Operating Mode State Diagram. 

graph TD
    A["TRX_OFF (Clock State)"] -->|12 13| B["BUSY_RX (Receive State)"]
    A -->|7 5 4| C["PLL_ON (PLL State)"]
    A -->|6 7 5 4| D["TX_ARET_ONRX_AACK_BUSY_TX_ARET"]
    A -->|8 RX_ON 9| C
    A -->|6 RX_ON 6| E["RX_ON (Rx Listen State)"]
    A -->|7 RX_ON 7| F["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| G["BUSY_RX_AACK"]
    A -->|7 RX_ON 8| H["BUSY_TX (Transmit State)"]
    A -->|6 RX_ON 6| I["PULL_ON (PLL State)"]
    A -->|7 RX_ON 7| J["BUSY_RX (Receive State)"]
    A -->|6 RX_ON 6| K["BUSY_TX (Transmit State)"]
    A -->|7 RX_ON 8| L["BUSY_RX (Receive State)"]
    A -->|6 RX_ON 6| M["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| N["BUSY_TX (Transmit State)"]
    A -->|6 RX_ON 6| O["BUSY_RX (Receive State)"]
    A -->|7 RX_ON 8| P["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| Q["BUSY_TX (Receive State)"]
    A -->|7 RX_ON 9| R["BUSY_TX (Transmit State)"]
    A -->|6 RX_ON 6| S["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| T["BUSY_RX (Receive State)"]
    A -->|6 RX_ON 6| U["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| V["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| W["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| X["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| Y["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| Z["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AA["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| AB["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AC["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| AD["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AE["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| AF["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AG["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| AH["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AI["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| AJ["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AK["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| AL["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AM["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| AN["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AO["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| AP["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AQ["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| AR["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AS["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| AT["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AU["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| AV["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AW["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| AX["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| AY["PULL_ON (PLL State)"]
    A -->|7 RX_ON 8| AZ["PULL_ON (PLL State)"]
    A -->|6 RX_ON 6| BA["PULL_ON (PLL State)"]
    A -->|7 RX_ON 9| BB["PULL_ON (PLL State)"]

Legend: Blue: SPI Write to Register TRX\_STATE (0x02) Red: Control signals via IC Pin Green: Event  Basic Operating Mode States  Extended Operating Mode States

7.2.1 State Control

The Extended Operating Mode states RX\_AACK and TX\_ARET are controlled via register bits TRX\_CMD (register 0x02, TRX\_STATE), which receives the state transition commands. The states are usually entered from TRX\_OFF or PLL\_ON state as illustrated by Figure 7-10. The completion of each state change command shall always be confirmed by reading the register bits TRX\_STATUS (register 0x01, TRX\_STATUS).

RX\_AACK - Receive with Automatic ACK

A state transition to RX\_AACK\_ON is initiated by writing the command RX\_AACK\_ON to the register bits TRX\_CMD. The state change should be confirmed by reading register bits TRX\_STATUS (register 0x01, TRX\_STATUS). The RX\_AACK state is left by writing a new command to the register bits TRX\_CMD. If the Atmel AT86RF232 is within a frame receive or acknowledgment procedure (BUSY\_RX\_AACK), the state change is executed after finishing. Alternatively, the commands FORCE\_TRX\_OFF or FORCE\_PLL\_ON can be used to cancel the RX\_AACK transaction and change into radio transceiver state TRX\_OFF or PLL\_ON, respectively.

TX\_ARET - Transmit with Automatic Frame Retransmission and CSMA-CA Retry

A state transition to TX\_ARET\_ON is initiated by writing command TX\_ARET\_ON to register bits TRX\_CMD. The radio transceiver is in the TX\_ARET\_ON state after register bits TRX\_STATUS (register 0x01, TRX\_STATUS) changes to TX\_ARET\_ON. The TX\_ARET transaction is started with a rising edge of pin 11 (SLP\_TR) or writing the command TX\_START to register bits TRX\_CMD. The TX\_ARET state is left by writing a new command to the register bits TRX\_CMD. If the AT86RF232 is within a CSMA-CA transaction, a frame transmission or an acknowledgment procedure (BUSY\_TX\_ARET), the state change is executed after finishing. Alternatively, the command FORCE\_TRX\_OFF or FORCE\_PLL\_ON can be used to instantly terminate the TX\_ARET transaction and change into radio transceiver state TRX\_OFF or PLL\_ON, respectively. Note: 1. A state change request from TRX\_OFF to RX\_AACK\_ON or TX\_ARET\_ON internally passes the state PLL\_ON. Thus the ability to receive or transmit data is delayed accordingly. It is recommended to use interrupt IRQ\_0 (PLL\_LOCK) as an indicator.

7.2.2 Configuration

The use of the Extended Operating Mode is based on Basic Operating Mode functionality. Only features beyond the basic radio transceiver functionality are described in the following sections. For details on the Basic Operating Mode refer to Section 7.1. When using the RX\_AACK or TX\_ARET modes, the following registers needs to be configured.

RX\_AACK configuration steps:

- Short address, PAN-ID and IEEE address registers 0x20 – 0x2B - Configure RX\_AACK properties registers 0x2C, 0x2E ○ Handling of Frame Version Subfield - Handling of Pending Data Indicator ○ Characterize as PAN coordinator - Handling of Slotted Acknowledgement • Additional Frame Filtering Properties registers 0x17, 0x2E - Promiscuous Mode - Enable or disable automatic ACK generation - Handling of reserved frame types The addresses for the address match algorithm are to be stored in the appropriate address registers. Additional control of the RX\_AACK mode is done with register 0x17 (XAH\_CTRL\_1) and register 0x2E (CSMA\_SEED\_1). As long as a short address has not been set, only broadcast frames and frames matching the IEEE address can be received. Configuration examples for different device operating modes and handling of various frame types can be found in Section 7.2.3.1.

TX\_ARET configuration steps:

- Leave register bit TX\_AUTO\_CRC\_ON = 1 register 0x04, TRX\_CTRL\_1 - Configure CSMA-CA - MAX\_FRAME\_RETRIES register 0x2C, XAH\_CTRL\_0 - MAX\_CSMA\_RETRIES register 0x2C, XAH\_CTRL\_0 o CSMA\_SEED registers 0x2D, 0x2E - MAX\_BE, MIN\_BE register 0x2F, CSMA\_BE \- Configure CCA (see Section 8.5) MAX\_FRAME\_RETRIES (register 0x2C, XAH\_CTRL\_0) defines the maximum number of frame retransmissions. The register bits MAX\_CSMA\_RETRIES (register 0x2C, XAH\_CTRL\_0) configure the number of CSMA-CA retries after a busy channel is detected. The register bits CSMA\_SEED (registers 0x2D, 0x2E) define a random seed for the back-off-time random-number generator in the Atmel AT86RF232. The register bits MAX\_BE and MIN\_BE (register 0x2F, CSMA\_BE) set the maximum and minimum CSMA back-off exponent (see [1]), respectively.

7.2.3 RX\_AACK\_ON - Receive with Automatic ACK

The general functionality of the RX\_AACK procedure is shown in Figure 7-11. The gray shaded area is the standard flow of an RX\_AACK transaction for IEEE 802.15.4 compliant frames, refer to Section 7.2.3.2. All other procedures are exceptions for specific operating modes or frame formats, refer to Section 7.2.3.3. The frame filtering operation is described in detail in Section 7.2.3.4. In RX\_AACK\_ON state, the radio transceiver listens for incoming frames. After detecting a valid PHR, the radio transceiver parses the frame content of the MAC header (MHR), refer to Section 8.1.2. If the content of the MAC addressing fields of the received frame (refer to IEEE 802.15.4 Section 7.2.1) matches one of the configured addresses, dependent on the addressing mode, an address match interrupt IRQ\_5 (AMI) is issued, refer to Section 7.2.3.4. The expected address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering as described in Section 7.2.3.4 is also applied in Basic Operating Mode. However, in Basic Operating Mode, the result of frame filtering or FCS check do not affect the generation of an interrupt IRQ\_3 (TRX\_END). By default, only frames that match the address filter and have a valid FCS generate an interrupt IRQ\_3 (TRX\_END). An exception applies if promiscuous mode is enabled; see Section 7.2.3.2, in that case an IRQ\_3 (TRX\_END) interrupt is issued, even if the FCS fails. During reception the Atmel AT86RF232 parses bit[5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an ACK reply is expected. In that case and if the frame passes the third level of filtering, see IEEE 802.15.4-2006, Section 7.5.6.2, the radio transceiver automatically generates and transmits an ACK frame. The sequence number is copied from the received frame. The content of the frame pending subfield of the ACK response is set by register bit AACK\_SET\_PD (register 0x2E, CSMA\_SEED\_1) when the ACK frame is sent in response to a data request MAC command frame, otherwise this subfield is set to zero. Optionally, the start of the transmission of the acknowledgement frame can be influenced by register bit AACK\_ACK\_TIME. Default value (according to standard IEEE 802.15.4) is 12 symbol periods after the reception of the last symbol of a data or MAC command frame. If the register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1) is set, no acknowledgement frame is sent even if an acknowledgment frame was requested. This is useful for operating the MAC hardware accelerator in promiscuous mode, see Section 7.2.3.2. The status of the RX\_AACK operation is indicated by register bits TRAC\_STATUS (register 0x02, TRAC\_STATUS), see Section 7.2.7. During the operations described above, the AT86RF232 remains in BUSY\_RX\_AACK state. Figure 7-11. Flow Diagram of RX\_AACK. 

graph TD
    A["TRX_STATE = RX_AACK_ON"] --> B{SHR detected}
    B -->|Y| C["TRX_STATE = BUSY_RX_AACK"]
    C --> D["Generate IRQ_2 (RX_START)"]
    D --> E["Scanning MHR"]
    E --> F{Frame Filtering}
    F -->|N| G["Generate IRQ_5 (AMI)"]
    F -->|Y| H["FCS valid (see Note 2)"]
    H --> I["Generate IRQ_3 (TRX_END)"]
    I --> J{ACK requested (see Note 3)}
    J -->|N| K{Slotted Operation == 0}
    J -->|Y| L{AACK_ACK_TIME == 0}
    K -->|N| M["Wait 2 symbol periods"]
    K -->|Y| N["Wait 12 symbol periods"]
    L --> O["Wait 2 symbol periods"]
    M --> P{pin 11 (SLP_TR) rising edge}
    N --> P
    O --> P
    P --> Q["Transmit ACK"]
    Q --> R["TRX_STATE = RX_AACK_ON"]
    S["Promiscuous Mode"] --> T["Frame reception"]
    T --> U{AACK_PROM_MODE == 1}
    U -->|N| V["Generate IRQ_3 (TRX_END)"]
    U -->|Y| W["FCF[2:0"] > 3]
    W --> X["AACK_UPLD_RES_FT == 1"]
    X --> Y{FCS valid}
    Y -->|N| Z["Generate IRQ_3 (TRX_END)"]
    Y -->|Y| AA["Reserved Frames"]
    AA --> V
    style A fill:#f9f,stroke:#333
    style V fill:#ccf,stroke:#333

7.2.3.1 Description of RX\_AACK Configuration Bits

Overview

Table 7-5 summarizes all register bits which affect the behavior of an RX\_AACK transaction. For address filtering it is further required to setup address registers to match the expected address. Configuration and address bits are to be set in TRX\_OFF or PLL\_ON state prior to switching to RX\_AACK mode. A graphical representation of various operating modes is illustrated in Figure 7-11. Table 7-5. Overview of RX\_AACK Configuration Bits.

Register Address	Register Bits	Register Name	Description
0x20,0x210x22,0x230x24...0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0...IEEE_ADDR_7	Set node addresses.
0x0C	7	RX_SAFE_MODE	Protect buffer after frame reception.
0x17	1	AACK_PROM_MODE	Support promiscuous mode.
0x17	2	AACK_ACK_TIME	Change auto acknowledge start time.
0x17	4	AACK_UPLD_RES_FT	Enable reserved frame type reception,needed to receive non-standard compliantframes.
0x17	5	AACK_FLTR_RES_FT	Filter reserved frame types like data frametype, needed for filtering of non-standardcompliant frames.
0x2C	0	SLOTTED_OPERATION	If set, acknowledgment transmission hasto be triggered by pin 11 (SLP_TR)
0x2E	3	AACK_I_AM_COORD	If set, the device is a PAN coordinator,that is responds to a null address.
0x2E	4	AACK_DIS_ACK	Disable generation of acknowledgment.
0x2E	5	AACK_SET_PD	Set frame pending subfield in FrameControl Field (FCF), refer toSection 8.1.2.2.
0x2E	7:6	AACK_FVN_MODE	Controls the ACK behavior, depending onFCF frame version number.

The usage of the RX\_AACK configuration bits for various operating modes of a node is explained in the following sections. Configuration bits not mentioned in the following two sections should be set to their reset values according to Table 14-2. All registers mentioned in Table 7-5 are described in Section 7.2.6. The general behavior of the “Atmel AT86RF232 Extended Feature Set”, Chapter 11, settings: - ANT\_DIV (Antenna Diversity) - RX\_PDT\_LEVEL (blocking frame reception of lower power signals) are completely independent from RX\_AACK mode and can be arbitrarily combined.

7.2.3.2 Configuration of IEEE Scenarios

Normal Device

Table 7-6 shows a typical Atmel AT86RF232 RX\_AACK configuration of an IEEE 802.15.4 device operating as a normal device, rather than a PAN coordinator or router. Table 7-6. Configuration of IEEE 802.15.4 Devices.

Register Address	Register Bits	Register Name	Description
0x20,0x210x22,0x230x24...0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0...IEEE_ADDR_7	Set node addresses.
0x0C	7	RX_SAFE_MODE	0: Disable frame protection.1: Enable frame protection.
0x2C	0	SLOTTED_OPERATION	0: Slotted acknowledgment transmissions are not to be used.1: Slotted acknowledgment transmissions are to be used.
0x2E	7:6	AACK_FVN_MODE	Controls the ACK behavior, depending on FCF frame version number.0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames.0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006.0x10: Acknowledges only frames with version number 0 or 1 or 2.0x11: Acknowledges all frames, independent of the FCF frame version number.

Notes: 1. If no short address has been configured, only frames directed to either the broadcast address or the IEEE address are received. 2. In IEEE 802.15.4-2003 standard the frame version subfield did not yet exist but was marked as reserved. According to this standard, reserved fields have to be set to zero. On the other hand, IEEE 802.15.4-2003 standard requires ignoring reserved bits upon reception. Thus, there is a contradiction in the standard which can be interpreted in two ways: a. If a network should only allow access to nodes which use the IEEE 802.15.4-2003, then AACK\_FVN\_MODE should be set to zero. b. If a device should acknowledge all frames independent of its frame version, AACK\_FVN\_MODE should be set to three. However, this can result in conflicts with co-existing IEEE 802.15.4-2006 standard compliant networks. The same holds for PAN coordinators, see below.

PAN-Coordinator

Table 7-7 shows the Atmel AT86RF232 RX\_AACK configuration for a PAN coordinator. Table 7-7. Configuration of a PAN Coordinator.

Register Address	Register Bits	Register Name	Description
0x20,0x210x22,0x230x24...0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0...IEEE_ADDR_7	Set node addresses.
0x0C	7	RX_SAFE_MODE	0: Disable frame protection.1: Enable frame protection.
0x2C	0	SLOTTED_OPERATION	0: Slotted acknowledgment transmissions are not to be used.1: Slotted acknowledgment transmissions are to be used.
0x2E	3	AACK_I_AM_COORD	1: Device is PAN coordinator.
0x2E	5	AACK_SET_PD	0: Frame pending subfield is not set in FCF.1: Frame pending subfield is set in FCF.
0x2E	7:6	AACK_FVN_MODE	Controls the ACK behavior, depends on FCF frame version number.0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames.0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006.0x10: Acknowledges only frames with version number 0 or 1 or 2.0x11: Acknowledges all frames, independent of the FCF frame version number.

Promiscuous Mode

The promiscuous mode is described in IEEE 802.15.4-2006, Section 7.5.6.5. This mode is further illustrated in Figure 7-11. According to IEEE 802.15.4-2006 when in promiscuous mode, the MAC sub layer shall pass received frames with correct FCS to the next higher layer and shall not process them further. That implies that frames should never be acknowledged. Only second level filter rules as defined by IEEE 802.15.4-2006, Section 7.5.6.2, are applied to the received frame. Table 7-8 shows the typical configuration of a device operating promiscuous mode. Table 7-8. Configuration of Promiscuous Mode.

Register Address	Register Bits	Register Name	Description
0x20,0x210x22,0x230x24...0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0...IEEE_ADDR_7	Each address shall be set: 0x00.
0x17	1	AACK_PROM_MODE	1: Enable promiscuous mode.
0x2E	4	AACK_DIS_ACK	1: Disable generation of acknowledgment.
0x2E	7:6	AACK_FVN_MODE	Controls the ACK behavior, depends on FCF frame version number.0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames.0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006.0x10: Acknowledges only frames with version number 0 or 1 or 2.0x11: Acknowledges all frames, independent of the FCF frame version number.

If the Atmel AT86RF232 radio transceiver is in promiscuous mode, second level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, is applied to a received frame. However, an IRQ\_3 (TRX\_END) is issued even if the FCS is invalid. Thus, it is necessary to read register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) after IRQ\_3 (TRX\_END) in order to verify the reception of a frame with a valid FCS. If a device, operating in promiscuous mode, receives a frame with a valid FCS which further passed the third level of filtering according to IEEE 802.15.4-2006, Section 7.5.6.2, an acknowledgement frame would be transmitted. According to the definition of the promiscuous mode a received frame shall not be acknowledged, even if it is requested. Thus register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1) has to be set to one. In all receive modes an IRQ\_5 (AMI) interrupt is issued, when the received frame matches the node's address according to the filter rules described in Section 7.2.3.4. Alternatively, in Basic Operating Mode RX\_ON state, when a valid PHR is detected, an IRQ\_2 (RX\_START) is generated and the frame is received. The end of the frame reception is signalized with an IRQ\_3 (TRX\_END). At the same time the register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is updated with the result of the FCS check (see Section 8.2). According to the promiscuous mode definition the register bit RX\_CRC\_VALID needs to be checked in order to dismiss corrupted frames.

7.2.3.3 Configuration of non IEEE 802.15.4 Compliant Scenarios

Sniffer

Table 7-9 shows an Atmel AT86RF232 RX\_AACK configuration to setup a sniffer device. Other RX\_AACK configuration bits, refer to Table 7-5, should be set to their reset values. All frames received are indicated by an IRQ\_2 (RX\_START) and IRQ\_3 (TRX\_END). After frame reception register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is updated with the result of the FCS check (see Section 8.2). The RX\_CRC\_VALID bit needs to be checked in order to dismiss corrupted frames. Table 7-9. Configuration of a Sniffer Device.

Register Address	Register Bits	Register Name	Description
0x17	1	AACK_PROM_MODE	1: Enable promiscuous mode.
0x2E	4	AACK_DIS_ACK	1: Disable generation of acknowledgment.

This operating mode is similar to the promiscuous mode.

Reception of Reserved Frames

In RX\_AACK mode, frames with reserved frame types, refer to Section 8.1.2.2, can also be handled. This might be required when implementing proprietary, non-standard compliant, protocols. It is an extension of the address filtering in RX\_AACK mode. Received frames are either handled similar to data frames, or may be allowed to completely bypass the address filter. Table 7-10 shows the required configuration for a node to receive reserved frames, Figure 7-11 shows the corresponding flow chart. Table 7-10. RX\_AACK Configuration to Receive Reserved Frame Types.

Register Address	Register Bits	Register Name	Description
0x20,0x210x22,0x230x24...0x2B		SHORT_ADDR_0/1PAN_ADDR_0/1IEEE_ADDR_0...IEEE_ADDR_7	Set node addresses.
0x0C	7	RX_SAFE_MODE	0: Disable frame protection.1: Enable frame protection.
0x17	4	AACK_UPLD_RES_FT	1: Enable reserved frame type reception.
0x17	5	AACK_FLTR_RES_FT	Filter reserved frame types like data frame type, see note below.0: Disable reserved frame types filtering.1: Enable reserved frame types filtering.
0x2C	0	SLOTTED_OPERATION	0: Slotted acknowledgment transmissions are not to be used.1: Slotted acknowledgment transmissions are to be used.
0x2E	3	AACK_I_AM_COORD	0: Device is not PAN coordinator.1: Device is PAN coordinator.
0x2E	4	AACK_DIS_ACK	0: Enable generation of acknowledgment.1: Disable generation of acknowledgment.
0x2E	7:6	AACK_FVN_MODE	Controls the ACK behavior, depends on FCF frame version number.0x00: Acknowledges only frames with version number 0, that is according to IEEE 802.15.4-2003 frames.0x01: Acknowledges only frames with version number 0 or 1, that is frames according to IEEE 802.15.4-2006.0x10: Acknowledges only frames with version number 0 or 1 or 2.0x11: Acknowledges all frames, independent of the FCF frame version number.

There are three different options for handling reserved frame types. 1. AACK\_UPLD\_RES\_FT = 1, AACK\_FLT\_RES\_FT = 0: Any non-corrupted frame with a reserved frame type is indicated by an IRQ\_3 (TRX\_END) interrupt. No further address filtering is applied on those frames. An IRQ\_5 (AMI) interrupt is never generated and the acknowledgment subfield is ignored. 2. AACK\_UPLD\_RES\_FT = 1, AACK\_FLT\_RES\_FT = 1: If AACK\_FLT\_RES\_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. This implies the generation of the IRQ\_5 (AMI) interrupts upon address match. An IRQ\_3 (TRX\_END) interrupt is only generated if the address matched and the frame was not corrupted. An acknowledgment is only send, when the ACK request subfield was set in the received frame and an IRQ\_3 (TRX\_END) interrupt occurred. 3. AACK\_UPLD\_RES\_FT = 0: Any received frame with a reserved frame type is discarded.

Short Acknowledgment Frame (ACK) Start Timing

Register bit AACK\_ACK\_TIME (register 0x17, XAH\_CTRL\_1), see Table 7-11, defines the symbol time between frame reception and transmission of an acknowledgment frame. Table 7-11. Overview of RX\_AACK Configuration Bits.

Register Address	Register Bit	Register Name	Description
0x17	2	AACK_ACK_TIME	0: Standard compliant acknowledgement timing of 12 symbol periods. In slotted acknowledgement operation mode, the acknowledgment frame transmission can be triggered two symbol periods after reception of the frame earliest.1: Reduced acknowledgment timing of two symbol periods (32μs).

This feature can be used in all scenarios, independent of other configurations.

7.2.3.4 Frame Filtering

Frame Filtering is an evaluation whether or not a received frame is addressed to this node. To accept a received frame and to generate an address match interrupt IRQ\_5 (AMI) a filtering procedure as described in IEEE 802.15.4-2006 Section 7.5.6.2. (Third level of filtering) is applied to the frame. The Atmel AT86RF232 RX\_AACK mode accepts only frames that satisfy all of the following requirements (quote from IEEE 802.15.4-2006, Section 7.5.6.2): 1. The Frame Type subfield shall not contain a reserved frame type. 2. The Frame Version subfield shall not contain a reserved value. 3. If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN identifier (0xFFFF). 4. If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise, if an extended destination address is included in the frame, it shall match aExtendedAddress. 5. If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source PAN identifier. 6. If only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId. The AT86RF232 requires satisfying two additional rules: 7. The frame type indicates that the frame is not an ACK frame (refer to Table 8-4). 8. At least one address field must be present. Address match, indicated by interrupt IRQ\_5 (AMI), is further controlled by the content of subfields of the frame control field of a received frame according to the following rule: If (Destination Addressing Mode = 0 OR 1) AND (Source Addressing Mode = 0) no IRQ\_5 (AMI) is generated, refer to Section 8.1.2.2. This effectively causes all acknowledgement frames not to be announced, which would otherwise always pass the filter, regardless of whether they are intended for this device or not. For backward compatibility to IEEE 802.15.4-2003 third level filter rule two (Frame Version) can be disabled by register bits AACK\_FVN\_MODE (register 0x2E, CSMA\_SEED\_1). Frame filtering is available in Extended and Basic Operating Mode, refer to Section 7.1, a frame passing the frame filtering generates an IRQ\_5 (AMI), if enabled. Notes: 1. Filter rule one is affected by register bits AACK\_FLTR\_RES\_FT and AACK\_UPLD\_RES\_FT, Section 7.2.7. 2. Filter rule two is affected by register bits AACK\_FVN\_MODE, Section 7.2.7.

7.2.3.5 RX\_AACK Slotted Operation – Slotted Acknowledgement

Atmel AT86RF232 supports slotted acknowledgement operation, refer to IEEE 802.15.4-2006, Section 7.5.6.4.2, in conjunction with the microcontroller. In RX\_AACK mode with register bit SLOTTED\_OPERATION (register 0x2C, XAH\_CTRL\_0) set, the transmission of an acknowledgement frame has to be controlled by the microcontroller. If an ACK frame has to be transmitted, the radio transceiver expects a rising edge on pin 11 (SLP\_TR) to actually start the transmission. This waiting state is signaled two symbol periods after the reception of the last symbol of a data or MAC command frame by register bits TRAC\_STATUS (register 0x02, XAH\_CTRL\_0), which are set to SUCCESS\_WAIT\_FOR\_ACK in that case. In networks using slotted operation the start of the acknowledgment frame, and thus the exact timing, must be provided by the microcontroller. A timing example of an RX\_AACK transaction with register bit SLOTTED\_OPERATION (register 0x2C, XAH\_CTRL\_0) set is shown in Figure 7-12. The acknowledgement frame is ready to be transmitted two symbol times after the reception of the last symbol of a data or MAC command frame. The transmission of the acknowledgement frame is initiated by the microcontroller with the rising edge of pin 11 (SLP\_TR) and starts t_TR10 = 16 s later. The interrupt latency t_IRQ is specified in Section 12.4. Figure 7-12. Example Timing of an RX\_AACK Transaction for Slotted Operation. 

Frame Type SFD Data Frame (Length = 10, ACK=1) ACK Frame TRX_STATE RX_AACK_ON BUSY_RX_AACK RX_AACK_ON RX/TX RX TX RX IRQ TRX_END Typ. Processing Delay tIRQ 32 µs (2 symbols) ACK transmission initiated by microcontroller SLP_TR waiting period signaled by register bits TRAC_STATUS SLP_TR tTR10

7.2.3.6 RX\_AACK Mode Timing

A timing example of an RX\_AACK transaction is shown in Figure 7-13. In this example a data frame of length 10 with an ACK request is received. The Atmel AT86RF232 changes to state BUSY\_RX\_AACK after SFD detection. The completion of the frame reception is indicated by an IRQ\_3 (TRX\_END) interrupt. Interrupts IRQ\_2 (RX\_START) and IRQ\_5 (AMI) are disabled in this example. The ACK frame is automatically transmitted after a default wait period of 12 symbols (192 s), register bit AACK\_ACK\_TIME = 0 (reset value). The interrupt latency t IRQ is specified in Section 12.4. Figure 7-13. Example Timing of an RX\_AACK Transaction. 

Frame Type SFD Data Frame (Length = 10, ACK=1) ACK Frame TRX_STATE RX_AACK_ON BUSY_RX_AACK RX_AACK_ON RX/TX RX TX IRQ Typ. Processing Delay TRX_END 102 µs (12 symbols) Frame on Air RX/TX

Note: 1. If register bit AACK\_ACK\_TIME (register 0x17, XAH\_CTRL\_1) is set, an acknowledgment frame is sent already two symbol times after the reception of the last symbol of a data or MAC command frame.

7.2.4 TX\_ARET\_ON - Transmit with Automatic Frame Retransmission and CSMA-CA Retry

Figure 7-14. Flow Diagram of TX\_ARET. 

graph TD
    A["TRX_STATE = TX_ARET_ON"] --> B["frame_rctr = 0"]
    B --> C{Start TX}
    C -->|N| D["TRX_STATE = BUSY_TX_ARET_TRAC_STATUS = INVALID"]
    C -->|Y| E["TRX_STATE = BUSY_TX_ARET_TRAC_STATUS = INVALID"]
    E --> F{MAX_CSMA_RETRIES <7}
    F -->|N| G["(see Note 1)"]
    F -->|Y| H["csma_rctr = 0"]
    H --> I["Random Back-Off csma_rctr = csma_rctr + 1 CCA"]
    I --> J{CCA Result}
    J -->|Failure| K{csma_rctr > MAX_CSMA_RETRIES}
    K -->|Y| L["Transmit Frame frame_rctr = frame_rctr + 1"]
    K -->|N| M["ACK requested"]
    M --> N{Receive ACK until timeout}
    N -->|N| O{ACK valid}
    N -->|Y| P{ frame_rctr > MAX_FRAME_RETRIES }
    P -->|N| Q["TRAC_STATUS = NO_ACK"]
    P -->|Y| R["TRAC_STATUS = SUCCESS_DATA_PENDING"]
    R --> S["Issue IRQ_3 (TRX_END) interrupt"]
    S --> T["TRX_STATE = TX_ARET_ON"]
    O -->|N| U["Data Pending"]
    U --> V["TRAC_STATUS = SUCCESS"]
    U --> W["TRAC_STATUS = SUCCESS"]
    V --> X["TRAC_STATUS = CHANNEL_ACCESS_FAILURE"]

Overview

The implemented TX\_ARET algorithm is shown in Figure 7-14. In TX\_ARET mode, the Atmel AT86RF232 first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4–2006, Section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply. The completion of the TX\_ARET transmit transaction is indicated by an IRQ\_3 (TRX\_END) interrupt.

Description

Configuration and address bits are to be set in TRX\_OFF or PLL\_ON state prior to switching to TX\_ARET mode. It is further recommended to transfer the PSDU data to the Frame Buffer in advance. The transaction is started by either using pin 11 (SLP\_TR), refer to Section 6.5, or writing a TX\_START command to register bits TRX\_CMD (register 0x02, TRX\_STATE). If the CSMA-CA detects a busy channel, it is retried as specified by the register bits MAX\_CSMA\_RETRIES (register 0x2C, XAH\_CTRL\_0). In case that CSMA-CA does not detect a clear channel after MAX\_CSMA\_RETRIES, it aborts the TX\_ARET transaction, issues interrupt IRQ\_3 (TRX\_END), and set the value of the register bits TRAC\_STATUS to CHANNEL\_ACCESS\_FAILURE. During transmission of a frame the radio transceiver parses bit 5 (ACK Request) of the MAC header (MHR) frame control field of the PSDU data (PSDU octet #1) to be transmitted to check if an ACK reply is expected. If an ACK is expected, the radio transceiver automatically switches into receive mode to wait for a valid ACK reply. After receiving an ACK frame the Frame Pending subfield of that frame is parsed and the status register bits TRAC\_STATUS are updated accordingly, refer to Table 7-12. This receive procedure does not overwrite the Frame Buffer content. Transmit data in the Frame Buffer is not changed during the entire TX\_ARET transaction. Received frames other than the expected ACK frame are discarded. If no valid ACK is received or after timeout of 54 symbol periods (864 s), the radio transceiver retries the entire transaction, (including CSMA-CA) until the maximum number of retransmissions (as set by the register bits MAX\_FRAME\_RETRIES (register 0x2C, XAH\_CTRL\_0)) is exceeded. The current CSMA-CA and frame retransmission counter values of an ongoing TX\_ARET transaction can be retrieved by the register bits ARET\_FRAME\_RETRIES and ARET\_CSMA\_RETRIES (register 0x19, XAH\_CTRL\_2). Additionally to the RX Frame Time stamping via pin 10 (DIG2), a TX Frame Time stamping within TX\_ARET mode can be activated, if the register bits IRQ\_2\_EXT\_EN (register 0x04, TRX\_CTRL\_1) and ARET\_TX\_TS\_EN (register 0x17, XAH\_CTRL\_1) are set to one, see Section 11.4. After that, the microcontroller may read the value of the register bits TRAC\_STATUS (register 0x02, TRX\_STATE) to verify whether the transaction was successful or not. The register bits are set according to the following cases, additional exit codes are described in Section 7.2.6: Table 7-12. Interpretation of TRAC\_STATUS Register Bits.

Value	Name	Description
0	SUCCESS	The transaction was responded by a valid ACK, or, if no ACK is requested, after a successful frame transmission.
1	SUCCESS_DATA_PENDING	Equivalent to SUCCESS, indicates pending frame data according to the MHR frame control field of the received ACK response.
3	CHANNEL_ACCESS_FAILURE	Channel is still busy after MAX_CSMA_RETRIES of CSMA-CA.
5	NO_ACK	No acknowledgement frames were received during all retry attempts.
7	INVALID	Transaction not yet finished.

If no ACK is expected (according to the content of the received frame in the Frame Buffer), the radio transceiver issues IRQ\_3 (TRX\_END) directly after the frame transmission has been completed. The value of register bits TRAC\_STATUS (register 0x02, TRX\_STATE) is set to SUCCESS. A value of MAX\_CSMA\_RETRIES = 7 initiates an immediate TX\_ARET transaction without performing CSMA-CA. This can be used for example to transmit indirect data to a device. Further the value MAX\_FRAME\_RETRIES is ignored and the TX\_ARET transaction is performed only once. A timing example of a TX\_ARET transaction is shown in Figure 7-15. Figure 7-15. Example Timing of a TX\_ARET Transaction. 

0 128 672 x x+352 time [µs] FrameType Data Frame (Length = 10, ACK=1) ACK Frame TRX_STATE TX_ARET_ON BUSY_TX_ARET TX_ARET_ON RX/TX RX SLP_TR RX IRQ TRX_END Typ. Processing Delay tCSMA-CA tR10 tR11 tRQ Frame on Air RX/TX

Notes: 1. tCSMA-CA defines the random CSMA-CA backoff time. 2. Timing figure t_TR10 and t_TR11 refer to Table 7-1. Here an example data frame of length 10 with an ACK request is transmitted. After that the Atmel AT86RF232 switches to receive mode and expects an acknowledgement response. During the whole transaction including frame transmit, wait for ACK and ACK receive the radio transceiver status register bits TRX\_STATUS (register 0x01, TRX\_STATUS) signals BUSY\_TX\_ARET. A successful reception of the acknowledgment frame is indicated by IRQ\_3 (TRX\_END). The status register bits TRX\_STATUS (register 0x01, TRX\_STATUS) changes back to TX\_ARET\_ON. The register bits TRAC\_STATUS (register 0x02, TRX\_STATE) change to either TRAC\_STATUS = SUCCESS, or TRAC\_STATUS = SUCCESS\_DATA\_PENDING if the frame pending subfield of the received ACK frame was set to one.

7.2.5 Interrupt Handling

The Atmel AT86RF232 interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode, refer to Section 7.1.3. The microcontroller enables interrupts by setting the appropriate bit in register 0x0E (IRQ\_MASK). For RX\_AACK and TX\_ARET modes the following interrupts inform about the status of a frame reception and transmission: Table 7-13. Interrupt Handling in Extended Operating Mode.

Mode	Interrupt	Description
RX_AACK	IRQ_2 (RX_START)	Indicates a PHR reception
	IRQ_5 (AMI)	Issued at address match
	IRQ_3 (TRX_END)	Signals completion of RX_AACK transaction if successful- A received frame must pass the address filter- The FCS is valid
TX_ARET	IRQ_3 (TRX_END)	Signals completion of TX_ARET transaction
Both	IRQ_0 (PLL_LOCK)	Entering RX_AACK_ON or TX_ARET_ON state from TRX_OFF state, the PLL_LOCK interrupt signals that the transaction can be started

RX\_AACK

For RX\_AACK mode, it is recommended to enable IRQ\_3 (TRX\_END). This interrupt is issued only if a frame passes the frame filtering, refer to Section 7.2.3.4, and has a valid FCS. This is in contrast to Basic Operating Mode, refer to Section 7.1.3. The use of the other interrupts is optional. On reception of a valid PHR an IRQ\_2 (RX\_START) is issued. IRQ\_5 (AMI) indicates address match, refer to filter rules in Section 7.2.3.4, and the completion of a frame reception with a valid FCS is indicated by interrupt IRQ\_3 (TRX\_END). Thus, it can happen that an IRQ\_2 (RX\_START) and/or IRQ\_5 (AMI) are issued, but no IRQ\_3 (TRX\_END) interrupt.

TX\_ARET

In TX\_ARET mode, interrupt IRQ\_3 (TRX\_END) is only issued after completing the entire TX\_ARET transaction. Reception of acknowledgement frames does not issue IRQ\_5 (AMI) or IRQ\_3 (TRX\_END) interrupts. All other interrupts as described in Section 6.6, are also available in Extended Operating Mode.

7.2.6 Register Summary

The following Atmel AT86RF232 registers are to be configured to control the Extended Operating Mode: Table 7-14. Register Summary.

Reg.-Addr.	Register Name	Description
0x01	TRX_STATUS	Radio transceiver status, CCA result
0x02	TRX_STATE	Radio transceiver state control, TX_ARET status
0x04	TRX_CTRL_1	TX_AUTO_CRC_ON
0x08	PHY_CC_CCA	CCA mode control, see Section 8.5.6
0x09	CCA_THRES	CCA threshold settings, see Section 8.5.6
0x17	XAH_CTRL_1	TX_ARET and RX_AACK control
0x19	XAH_CTRL_2	TX_ARET control
0x20 – 0x2B		Address filter configuration- Short address, PAN-ID and IEEE address
0x2C	XAH_CTRL_0	TX_ARET control, retries value control
0x2D	CSMA_SEED_0	CSMA-CA seed value
0x2E	CSMA_SEED_1	CSMA-CA seed value, RX_AACK control
0x2F	CSMA_BE	CSMA-CA back-off exponent control

7.2.7 Register Description – Control Registers

Register 0x01 (TRX\_STATUS):

The read-only register TRX\_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Figure 7-16. Register TRX\_STATUS.

Bit	7	6	5	4
0x01	CCA_DONE	CCA_STATUS	reserved	TRX_STATUS	TRX_STATUS
Read/Write	R	R	R	R
Reset value	0	0	0	0
Bit	3	2	1	0
0x01	TRX_STATUS				TRX_STATUS
Read/Write	R	R	R	R
Reset value	0	0	0	0

- Bit 4:0 - TRX\_STATUS

The register bits TRX\_STATUS signals the current radio transceiver status. Table 7-15. TRX\_STATUS.

Register Bits	Value	Description
TRX_STATUS	0x00	P_ON
	0x01	BUSY_RX
	0x02	BUSY_TX
	0x06	RX_ON
	0x08	TRX_OFF (CLK Mode)
	0x09	PLL_ON (TX_ON)
	0x0F^(1)	SLEEP
	0x11^(2)	BUSY_RX_AACK
	0x12^(2)	BUSY_TX_ARET
	0x16^(2)	RX_AACK_ON
	0x19^(2)	TX_ARET_ON
	0x1F^(3)	STATE_TRANSITION_IN_PROGRESS
		All other values are reserved

Notes: 1. In SLEEP state register not accessible. 2. Extended Operating Mode only. 3. Do not try to initiate a further state change while the radio transceiver is in STATE\_TRANSITION\_IN\_PROGRESS state. A read access to TRX\_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX\_CMD (register 0x02, TRX\_STATE). Alternatively, some state transitions can be initiated by the rising edge of pin 11 (SLP\_TR) in the appropriate state.

Register 0x02 (TRX\_STATE):

The radio transceiver states are controlled via register TRX\_STATE using register bits TRX\_CMD. The read-only register bits TRAC\_STATUS indicate the status or result of an Extended Operating Mode transaction. Figure 7-17. Register TRX\_STATE. 

Bit 7 6 5 4 0x02 TRAC_STATUS TRX_CMD TRX_STATE Read/Write R R R R/W Reset value 0 0 0 0 Bit 3 2 1 0 0x02 TRX_CMD TRX_STATE Read/Write R/W R/W R/W R/W Reset value 0 0 0 0

\- Bit 7:5 – TRAC\_STATUS Table 7-16. TRAC\_STATUS.

Register Bits	Value	Description	RX_AACK	TX_ARET
TRAC_STATUS	0^(1)	SUCCESS	X	X
	1	SUCCESS_DATA_PENDING		X
	2	SUCCESS_WAIT_FOR_ACK	X
	3	CHANNEL_ACCESS_FAILURE		X
	5	NO_ACK		X
	7^(1)	INVALID	X	X
		All other values are reserved

Note: 1. Even though the reset value for register bits TRAC\_STATUS is zero, the RX\_AACK and TX\_ARET procedures set the register bits to TRAC\_STATUS = 7 (INVALID) when they are started. The status of the RX\_AACK and TX\_ARET procedure is indicated by register bits TRAC\_STATUS. Details of the algorithm and a description of the status information are given in Section 7.2.3 and Section 7.2.4.

RX\_AACK

SUCCESS\_WAIT\_FOR\_ACK: Indicates an ACK frame is about to be sent in RX\_AACK slotted acknowledgement. Slotted acknowledgement operation must be enabled with register bit SLOTTED\_OPERATION (register 0x2C, XAH\_XTRL\_0). The microcontroller must pulse pin 11 (SLP\_TR) at the next back-off slot boundary in order to initiate a transmission of the ACK frame. For details refer to IEEE 802.15.4-2006, Section 7.5.6.4.2.

TX ARET

SUCCESS\_DATA\_PENDING: Indicates a successful reception of an ACK frame with frame pending bit set to one.

- Bit 4:0 - TRX\_CMD

A write access to register bits TRX\_CMD initiates a radio transceiver state transition. Table 7-17. TRX\_CMD.

Register Bits	Value	Description
TRX_CMD	0x00^(1)	NOP
	0x02^(2)	TX_START
	0x03	FORCE_TRX_OFF
	0x04^(3)	FORCE_PLL_ON
	0x06	RX_ON
	0x08	TRX_OFF (CLK Mode)
	0x09	PLL_ON (TX_ON)
	0x16^(4)	RX_AACK_ON
	0x19^(4)	TX_ARET_ON
		All other values are reserved

Notes: 1. TRX\_CMD = "0" after power on reset (POR). 2. The frame transmission starts one symbol after TX\_START command. 3. FORCE\_PLL\_ON is not valid for states P\_ON, SLEEP, and RESET, as well as STATE\_TRANSITION\_IN\_PROGRESS towards these states. 4. Extended Operating Mode only. A successful state transition shall be confirmed by reading register bits TRX\_STATUS (register 0x01, TRX\_STATUS). The register bits TRX\_CMD are used for Basic and Extended Operating Modes, refer to Section 7.1.

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 7-18. Register TRX\_CTRL\_1.

Bit	7	6	5	4
0x04	reserved	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0
Bit	3	2	1	0
0x04	SPI_CMD_MODE		IRQ_MASK_MOD	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0

- Bit 5 - TX\_AUTO\_CRC\_ON

The register bit TX\_AUTO\_CRC\_ON controls the automatic FCS generation for transmit operations. Table 7-18. TX AUTO CRC ON.

Register Bits	Value	Description
TX_AUTO_CRC_ON	0	Automatic FCS generation is disabled
	1	Automatic FCS generation is enabled

Note: 1. The TX\_AUTO\_CRC\_ON function can be used within Basic and Extended Operating Modes. For further details refer to Section 8.2.

Register 0x17 (XAH\_CTRL\_1):

The XAH\_CTRL\_1 register is a multi-purpose control register for Extended Operating Mode. Figure 7-19. Register XAH\_CTRL\_1. 

- Bit 7 - ARET\_TX\_TS\_EN

If register bit ARET\_TX\_TS\_EN = 1, then any frame transmission within TX\_ARET mode is signaled via pin 10 (DIG2). Table 7-19. ARET\_TX\_TS\_EN.

Register Bits	Value	Description
ARET_TX_TS_EN	0	TX_ARET time stamping via pin 10 (DIG2) is disabled
	1^(1)	TX_ARET time stamping via pin 10 (DIG2) is enabled

Note: 1. It is necessary to set register bit IRQ\_2\_EXT\_EN (register 0x04, TRX\_CTRL\_1).

- Bit 5 - AACK\_FLTR\_RES\_FT

Filter reserved frame types like data frame type. The register bit AACK\_FLTR\_RES\_FT shall only be set if register bit AACK\_UPLD\_RES\_FT = 1. Table 7-20. AACK FLTR RES FT.

Register Bits	Value	Description
AACK_FLTR_RES_FT	0^(1)	Filtering reserved frame types is disabled
	1^(2)	Filtering reserved frame types is enabled

Notes: 1. If AACK\_FLTR\_RES\_FT = 0 the received reserved frame is only checked for valid FCS. 2. If AACK\_FLTR\_RES\_FT = 1 reserved frame types are filtered similar to data frames as specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4, Section 7.2.1.1.1.

- Bit 4 - AACK\_UPLD\_RES\_FT

Upload reserved frame types within RX\_AACK mode. Table 7-21. AACK\_UPLD\_RES\_FT.

Register Bits	Value	Description
AACK_UPLD_RES_FT	0	Upload of reserved frame types is disabled
	1^(1)	Upload of reserved frame types is enabled

Note: 1. If AACK\_UPLD\_RES\_FT = 1 received frames indicated as a reserved frame are further processed. For those frames, an IRQ\_3 (TRX\_END) interrupt is generated if the FCS is valid. In conjunction with the configuration bit AACK\_FLTR\_RES\_FT, these frames are handled like IEEE 802.15.4 compliant data frames during RX\_AACK transaction. An IRQ\_5 (AMI) interrupt is issued, if the addresses in the received frame match the node's addresses. That means, if a reserved frame passes the third level filter rules, an acknowledgement frame is generated and transmitted if it was requested by the received frame. If this is not wanted register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1) has to be set.

- Bit 2 - AACK\_ACK\_TIME

The register bit AACK\_ACK\_TIME controls the acknowledgment frame response time within RX\_AACK mode. Table 7-22. AACK ACK TIME.

Register Bits	Value	Description
AACK_ACK_TIME	0	Acknowledgment time is 12 symbols (aTurnaroundTime)
	1	Acknowledgment time is two symbols

According to IEEE 802.15.4, Section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbols (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK\_ACK\_TIME. Alternatively, if AACK\_ACK\_TIME = 1 an acknowledgment frame is sent already two symbol periods after the reception of the last symbol of a data or MAC command frame.

- Bit 1 - AACK\_PROM\_MODE

The register bit AACK\_PROM\_MODE enables the promiscuous mode, within the RX\_AACK mode. Table 7-23. AACK PROM MODE.

Register Bits	Value	Description
AACK_PROM_MODE	0	Promiscuous mode is disabled
	1	Promiscuous mode is enabled

Refer to IEEE 802.15.4-2006, Section 7.5.6.5. If this register bit is set, every incoming frame with a valid PHR finishes with IRQ\_3 (TRX\_END) interrupt even if the third level filter rules do not match or the FCS is not valid. Register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is set accordingly. In contrast to IEEE 802.15.4-2006, if a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK\_DIS\_ACK (register 0x2E, CSMA\_SEED\_1), or use Basic Operating Mode instead.

Register 0x19 (XAH\_CTRL\_2):

The read-only register XAH\_CTRL\_2 retrieves the current counter values for Extended Operating Mode. Figure 7-20. Register XAH\_CTRL\_2. 

- Bit 7:4 - ARET\_FRAME\_RETRIES

Retrieves current frame retry counter value. Table 7-24. ARET FRAME RETRIES.

Register Bits	Value	Description
ARET_FRAME_RETRIES	0x0	Minimum possible frame retry counter value
	0xF	Maximum possible frame retry counter value

Note: 1. A new CCA\_BACKOFF cycle or new frame transmit cycle changed these value.

- Bit 3:1 - ARET\_CSMA\_RETRIES

Retrieves current CSMA-CA retry counter value. Table 7-25. ARET\_CSMA\_RETRIES.

Register Bits	Value	Description
ARET_CSMA_RETRIES	0	Minimum possible CSMA-CA retry counter value
	5	Maximum possible CSMA-CA retry counter value

Note: 1. A new CCA\_BACKOFF cycle or new frame transmit cycle changed these value.

Register 0x2C (XAH\_CTRL\_0):

The XAH\_CTRL\_0 register is a control register for Extended Operating Mode. Figure 7-21. Register XAH\_CTRL\_0.

Bit	7	6	5	4
0x2C	MAX_FRAME_RETRIES				XAH_CTRL_0
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	1
Bit	3	2	1	0
0x2C	MAX_CSMA_RETRIES			SLOTTED_OPERATION	XAH_CTRL_0
Read/Write	R/W	R/W	R/W	R/W
Reset value	1	0	0	0

- Bit 7:4 - MAX\_FRAME\_RETRIES

Number of retransmission attempts in TX\_ARET mode before the transaction gets cancelled. Table 7-26. MAX FRAME RETRIES.

Register Bits	Value	Description
MAX_FRAME_RETRIES	0x3	The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame, when it was not acknowledged by the recipient, before the transaction gets cancelled. Valid values are [0x7, 0x6, ..., 0x0].

- Bit 3:1 - MAX\_CSMA\_RETRIES

Number of retries in TX\_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. Table 7-27. MAX CSMA RETRIES.

Register Bits	Value	Description
MAX_CSMA_RETRIES	0^(1)	no retries
	1^(1)	One retry
	2^(1)	Two retries
	3^(1)	Three retries
	4^(1)	Four retries
	5^(1)	Five retries
	7^(3)	Immediate frame transmission without performing CSMA-CA

Notes: 1. MAX\_CSMA\_RETRIES specifies the number of retries in TX\_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. According to IEEE 802.15.4 the valid range of MAX\_CSMA\_RETRIES is [5, 4, ..., 0]. 2. MAX\_CSMA\_RETRIES = 6 is reserved. 3. A value of MAX\_CSMA\_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA.

- Bit 0 - SLOTTED\_OPERATION

For RX\_AACK mode, the register bit SLOTTED\_OPERATION determines, if the transceiver will require a time base for slotted operation. Table 7-28. SLOTTED OPERATION.

Register Bits	Value	Description
SLOTTED_OPERATION	0	The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested.
	1	The transmission of an acknowledgement frame has to be controlled by the microcontroller.

Using RX\_AACK mode in networks operating in beacon or slotted mode, refer to IEEE 802.15.4-2006, Section 5.5.1, register bit SLOTTED\_OPERATION indicates that acknowledgement frames are to be sent on back-off slot boundaries (slotted acknowledgement), refer to Section 7.2.3.5. If this register bit is set the acknowledgement frame transmission has to be initiated by the microcontroller using the rising edge of pin 11 (SLP\_TR). This waiting state is signaled in register bits TRAC\_STATUS (register 0x02, TRX\_STATE) with value SUCCESS\_WAIT\_FOR\_ACK.

Register 0x2D (CSMA\_SEED\_0):

The register CSMA\_SEED\_0 contains the lower 8-bit of CSMA\_SEED. Figure 7-22. Register CSMA\_SEED\_0. 

- Bit 7:0 - CSMA\_SEED\_0

Lower 8-bit of CSMA\_SEED, bits[7:0]. Used as seed for random number generation in the CSMA-CA algorithm. Table 7-29. CSMA\_SEED\_0.

Register Bits	Value	Description
CSMA_SEED_0	0xEA	This register contains the lower 8-bit of the CSMA_SEED, bits[7:0]. The higher 3-bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is the seed for the random number generation that determines the length of the back-off period in the CSMA-CA algorithm.

Register 0x2E (CSMA\_SEED\_1):

The CSMA\_SEED\_1 register is a control register for RX\_AACK and contains a part of the CSMA\_SEED for the CSMA-CA algorithm. Figure 7-23. Register CSMA\_SEED\_1. 

- Bit 7:6 - AACK\_FVN\_MODE

Controls the ACK behaviour dependent from FCF frame version number within RX\_AACK mode. Table 7-30. AACK FVN MODE.

Register Bits	Value	Description
AACK_FVN_MODE	0	Accept frames with version number 0
	1	Accept frames with version number 0 or 1
	2	Accept frames with version number 0 or 1 or 2
	3	Accept frames independent of frame version number

Note: 1. AACK\_FVN\_MODE value one indicates frames according to IEEE-802.15.4-2006, a value of three indicates frames according to IEEE-802.15.4-2003 standard. The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of register bits AACK\_FVN\_MODE specifies the frame filtering behavior of the Atmel AT86RF232. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. Thus the register bits AACK\_FVN\_MODE defines the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the address filter and are not acknowledged. The frame version field of the acknowledgment frame is set to zero according to IEEE 802.15.4-2006, Section 7.2.2.3.1 Acknowledgment frame MHR fields.

- Bit 5 - AACK\_SET\_PD

The content of AACK\_SET\_PD bit is copied into the frame pending subfield of the acknowledgment frame if the ACK is the answer to a data request MAC command frame. Table 7-31. AACK\_SET\_PD.

Register Bits	Value	Description
AACK_SET_PD	0	Pending data bit set to zero
	1	Pending data bit set to one

In addition, if register bits AACK\_FVN\_MODE (register 0x2E, CSMA\_SEED\_1) are configured to accept frames with a frame version other than zero or one, the content of register bit AACK\_SET\_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version of two or three that have the security enabled subfield set to one. This is done in the assumption that a future version of the standard [1] might change the length or structure of the auxiliary security header.

- Bit 4 - AACK\_DIS\_ACK

If this bit is set no acknowledgment frames are transmitted in RX\_AACK Extended Operating Mode, even if requested. Table 7-32. AACK DIS ACK.

Register Bits	Value	Description
AACK_DIS_ACK	0	Acknowledgment frames are transmitted
	1	Acknowledgment frames are not transmitted

- Bit 3 - AACK\_I\_AM\_COORD

This register bit has to be set if the node is a PAN coordinator. It is used for frame filtering in RX\_AACK. Table 7-33. AACK I AM COORD.

Register Bits	Value	Description
AACK_I_AM_COORD	0	PAN coordinator addressing is disabled
	1	PAN coordinator addressing is enabled

If AACK\_I\_AM\_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId, for details refer to IEEE 802.15.4, Section 7.5.6.2 (third-level filter rule six).

- Bit 2:0 - CSMA\_SEED\_1

Higher 3-bit of CSMA\_SEED, bits[10:8]. Seed for random number generation in the CSMA-CA algorithm. Table 7-34. CSMA\_SEED\_1.

Register Bits	Value	Description
CSMA_SEED_1	2	These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part is in register 0x2D (CSMA_SEED_0), see register CSMA_SEED_0 for details.

Register 0x2F (CSMA\_BE):

The register CSMA\_BE contains the back-off exponents for the CSMA-CA algorithm. Figure 7-24. Register CSMA\_BE.  Note: 1. If MIN\_BE = 0 and MAX\_BE = 0 the CCA backoff period is always set to zero.

- Bit 7:4 - MAX\_BE

Maximum back-off exponent in the CSMA-CA algorithm. Table 7-35. MAX\_BE.

Register Bits	Value	Description
MAX_BE	0x5	Register bits MAX_BE defines the maximum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for CCA back-off. Valid values are [0x8, 0x7, ..., 0x0].

For details refer to IEEE 802.15.4-2006, Section 7.5.1.4.

- Bit 3:0 - MIN\_BE

Minimum back-off exponent in the CSMA-CA algorithm. Table 7-36. MIN BE.

Register Bits	Value	Description
MIN_BE	0x3	Register bits MIN_BE defines the minimum back-off exponent used in the CSMA-CA algorithm to generate a pseudo random number for CCA back-off. Valid values are [MAX_BE, (MAX_BE - 1), ..., 0].

For details refer to IEEE 802.15.4-2006, Section 7.5.1.4.

7.2.8 Register Description – Address Registers

Register 0x20 (SHORT\_ADDR\_0):

This register contains the lower 8-bit of the MAC short address for Frame Filter address recognition, bits[7:0]. Figure 7-25. Register SHORT\_ADDR\_0. 

Bit 7 6 5 4 0x20 SHORT_ADDR_0 SHORT_ADDR_0 Read/Write R/W R/W R/W R/W Reset value 1 1 1 1 Bit 3 2 1 0 0x20 SHORT_ADDR_0 SHORT_ADDR_0 Read/Write R/W R/W R/W R/W Reset value 1 1 1 1

Register 0x21 (SHORT\_ADDR\_1):

This register contains the higher 8-bit of the MAC short address for Frame Filter address recognition, bits[15:8]. Figure 7-26. Register SHORT\_ADDR\_1. 

Bit 7 6 5 4 0x21 SHORT_ADDR_1 SHORT_ADDR_1 Read/Write R/W R/W R/W R/W Reset value 1 1 1 1 Bit 3 2 1 0 0x21 SHORT_ADDR_1 SHORT_ADDR_1 Read/Write R/W R/W R/W R/W Reset value 1 1 1 1

Register 0x22 (PAN\_ID\_0):

This register contains the lower 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[7:0]. Figure 7-27. Register PAN\_ID\_0. 

Register 0x23 (PAN\_ID\_1):

This register contains the higher 8-bit of the MAC PAN ID for Frame Filter address recognition, bits[15:8]. Figure 7-28. Register PAN\_ID\_1. 

Register 0x24 (IEEE\_ADDR\_0):

This register contains the lower 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[7:0]. Figure 7-29. Register IEEE\_ADDR\_0. 

Register 0x25 (IEEE\_ADDR\_1):

This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[15:8]. Figure 7-30. Register IEEE\_ADDR\_1. 

Register 0x26 (IEEE\_ADDR\_2):

This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[23:16]. Figure 7-31. Register IEEE\_ADDR\_2. 

Bit 7 6 5 4 0x26 IEEE_ADDR_2 IEEE_ADDR_2 Read/Write R/W R/W R/W R/W Reset value 0 0 0 0 Bit 3 2 1 0 0x26 IEEE_ADDR_2 IEEE_ADDR_2 Read/Write R/W R/W R/W R/W Reset value 0 0 0 0

Register 0x27 (IEEE\_ADDR\_3):

This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[31:24]. Figure 7-32. Register IEEE\_ADDR\_3.

Bit	7	6	5	4
0x27	IEEE_ADDR_3				IEEE_ADDR_3
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0
Bit	3	2	1	0
0x27	IEEE_ADDR_3				IEEE_ADDR_3
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0

Register 0x28 (IEEE\_ADDR\_4):

This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[39:32]. Figure 7-33. Register IEEE\_ADDR\_4.

Bit	7	6	5	4
0x28	IEEE_ADDR_4				IEEE_ADDR_4
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0
Bit	3	2	1	0
0x28	IEEE_ADDR_4				IEEE_ADDR_4
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0

Register 0x29 (IEEE\_ADDR\_5):

This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[47:40]. Figure 7-34. Register IEEE\_ADDR\_5. 

Register 0x2A (IEEE\_ADDR\_6):

This register contains 8-bit of the MAC IEEE address for Frame Filter address recognition, bits[55:48]. Figure 7-35. Register IEEE\_ADDR\_6.

Bit	7	6	5	4
0x2A	IEEE_ADDR_6				IEEE_ADDR_6
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0
Bit	3	2	1	0
0x2A	IEEE_ADDR_6				IEEE_ADDR_6
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0

Register 0x2B (IEEE\_ADDR\_7):

This register contains the higher 8-bit of the MAC IEEE Frame Filter address for address recognition, bits[63:56]. Figure 7-36. Register IEEE\_ADDR\_7. 

Bit 7 6 5 4 0x2B IEEE_ADDR_7 IEEE_ADDR_7 Read/Write R/W R/W R/W R/W Reset value 0 0 0 0 Bit 3 2 1 0 0x2B IEEE_ADDR_7 IEEE_ADDR_7 Read/Write R/W R/W R/W R/W Reset value 0 0 0 0

8 Functional Description

8.1 Introduction – IEEE 802.15.4-2006 Frame Format

Figure 8-1 provides an overview of the physical layer (PHY) frame structure as defined by IEEE 802.15.4. Figure 8-2 shows the frame structure of the medium access control (MAC) layer. Figure 8-1. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU).

PHY Protocol Data Unit (PPDU)
Preamble Sequence	SFD	Frame Length	PHY Payload
5 octetsSynchronization Header (SHR)		1 octet(PHR)	Maximum 127 octetsPHY Service Data Unit (PSDU)
			MAC Protocol Data Unit (MPDU)

8.1.1 PHY Protocol Layer Data Unit (PPDU)

8.1.1.1 Synchronization Header (SHR)

The SHR consists of a four-octet preamble field (all zero), followed by a single byte start-of-frame delimiter (SFD, value 0xA7). During transmission, the SHR is automatically generated by the Atmel AT86RF232, thus the Frame Buffer shall contain PHR and PSDU only. The transmission of the SHR requires 160 s (10 symbols). As the SPI data rate is normally higher than the over-air data rate, this allows the microcontroller to initiate a transmission without having transferred the full frame data already. Instead it is possible to subsequently write the frame content. During frame reception, the SHR is used for synchronization purposes. The matching SFD determines the beginning of the PHR and the following PSDU payload data.

8.1.1.2 PHY Header (PHR)

The PHY header is a single octet following the SHR. The least significant seven bits denote the frame length of the following PSDU, while the most significant bit of that octet is reserved, and shall be set to zero for IEEE 802.15.4 compliant frames. On reception, the PHR is returned as the first octet during Frame Buffer read access. While the IEEE 802.15.4-2006 standard declares bit seven of the PHR octet as being reserved, the AT86RF232 preserves this bit upon transmission and reception so it can be used to carry additional information within proprietary networks. Nevertheless, this bit is not considered to be part of the frame length, so only frames between one and 127 octets are possible. For IEEE 802.15.4 compliant operation bit[7] has to be masked by software. The reception of a valid PHR (that is frame length greater than zero) is signaled by an interrupt IRQ\_2 (RX\_START). On transmission the PHR is to be supplied by the microcontroller during Frame Buffer write access as the first octet.

8.1.1.3 PHY Payload (PHY Service Data Unit, PSDU)

The PSDU has a variable length between zero and aMaxPHYPacketSize (127, maximum PSDU size in octets). The length of the PSDU is signaled by the frame length field (PHR), refer to Table 8-1. The PSDU contains the MAC Protocol Layer Data Unit (MPDU). Received frames with a frame length field set to zero (invalid PHR) are not signaled to the microcontroller. Table 8-1 summarizes the type of payload versus the frame length value. Table 8-1. Frame Length Field – PHR.

Frame Length Value	Payload
0 - 4	Reserved
5	MPDU (Acknowledgement)
6 - 8	Reserved
9 - aMaxPHYPacketSize	MPDU

8.1.2 MAC Protocol Layer Data Unit (MPDU)

Figure 8-2 shows the frame structure of the MAC layer. Figure 8-2. IEEE 802.15.4 Frame Format - MAC-Layer Frame Structure (MPDU). 

8.1.2.1 MAC Header (MHR) Fields

The MAC header consists of the Frame Control Field (FCF), a sequence number, and the addressing fields (which are of variable length, and can even be empty in certain situations).

8.1.2.2 Frame Control Field (FCF)

The FCF consists of 16 bits, and occupies the first two octets of the MPDU or PSDU, respectively. Figure 8-3. IEEE 802.15.4-2006 Frame Control Field (FCF).

0 1 2

3 4 5 6 7 8

9 10 11 12

13 14 15

Frame Type

Sec. Enabled

Frame Pending

ACK Request

PAN ID Comp.

Reserved Frame Version

Destination addressing mode

Source addressing mode

Frame Control Field 2 octets

Bit [2:0]: describes the frame type. Table 8-2 summarizes frame types defined by IEEE 802.15.4, Section 7.2.1.1.1. Table 8-2. Frame Control Field – Frame Type Subfield.

Frame Control Field Bit Assignments		Description
Frame Type Value b_2 b_1 b_0	Value
000	0	Beacon
001	1	Data
010	2	Acknowledge
011	3	MAC command
100 – 111	4 – 7	Reserved

This subfield is used for address filtering by the third level filter rules. By default, only frame types 0 – 3 pass the third level filter rules, refer to Section 7.2.3.4. Automatic address filtering by the Atmel AT86RF232 is enabled when using the RX\_AACK mode, refer to Section 7.2.3. However, a reserved frame (frame type value > 3) can be received if register bit AACK\_UPLD\_RES\_FT (register 0x17, XAH\_CTRL\_1) is set, for details refer to Section 7.2.3.3. Address filtering is also provided in Basic Operating Mode, refer to Section 7.1. Bit 3: indicates whether security processing applies to this frame. Bit 4: is the "Frame Pending" subfield. This field can be set in an acknowledgment frame (ACK) in response to a data request MAC command frame. This bit indicates that the node, which transmitted the ACK, might have more data to send to the node receiving the ACK. For acknowledgment frames automatically generated by the AT86RF232, this bit is set according to the content of register bit AACK\_SET\_PD in register 0x2E (CSMA\_SEED\_1) if the received frame was a data request MAC command frame. Bit 5: forms the "Acknowledgment Request" subfield. If this bit is set within a data or MAC command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4 (that is within 192 s for non beacon-enabled networks). The radio transceiver parses this bit during RX\_AACK mode and transmits an acknowledgment frame if necessary. In TX\_ARET mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. If this is the case, the receiver waits for the acknowledgment frame, otherwise the TX\_ARET transaction is finished. Bit 6: the “PAN ID compression” subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address field is omitted. In RX\_AACK mode, this bit is evaluated by the address filter logic of the Atmel AT86RF232. This subfield was previously named "Intra-PAN". Bit [11:10]: the "Destination Addressing Mode" subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 8-3, according to IEEE 802.15.4: Table 8-3. Frame Control Field – Destination and Source Addressing Mode.

Frame Control Field Bit Assignments		Description
Addressing Mode b_11 b_10 b_15 b_14	Value
00	0	PAN identifier and address fields are not present
01	1	Reserved
10	2	Address field contains a 16-bit short address
11	3	Address field contains a 64-bit extended address

If the destination address mode is either two or three (that is if the destination address is present), it always consists of a 16-bit PAN-ID first, followed by either the 16-bit or 64-bit address as described by the mode. Bit [13:12]: the "Frame Version" subfield specifies the version number corresponding to the frame. These register bits are reserved in IEEE 802.15.4-2003. This subfield shall be set to zero to indicate a frame compatible with IEEE 802.15.4-2003 and one to indicate an IEEE 802.15.4-2006 frame. All other subfield values shall be reserved for future use. RX\_AACK register bits AACK\_FVN\_MODE (register 0x2E, CSMA\_SEED\_1) controls the behavior of frame acknowledgements. This register determines if, depending on the Frame Version Number, a frame is acknowledged or not. This is necessary for backward compatibility to IEEE 802.15.4-2003 and for future use. Even if frame version numbers two and three are reserved, it can be handled by the radio transceiver, for details refer to Section 7.2.7. See IEEE 802.15.4-2006, Section 7.2.3 for details on frame compatibility. Table 8-4. Frame Control Field – Frame Version Subfield.

Frame Control Field Bit Assignments		Description
Frame Version b_13 b_12	Value
00	0	Frames are compatible with IEEE 802.15.4-2003
01	1	Frames are compatible with IEEE 802.15.4-2006
10	2	Reserved
11	3	Reserved

Bit [15:14]: the “Source Addressing Mode” subfield, with similar meaning as “Destination Addressing Mode”, see Table 8-3. The subfields of the FCF (Bits 0–2, 3, 6, 10–15) affect the address filter logic of the AT86RF232 while operating in RX\_AACK operation, see Section 7.2.3.

8.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006

All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the "Channel Page" field present (see IEEE 802.15.4-2006, Section 7.3.8) and any frame with a MAC Payload field larger than aMaxMACSafePayloadSize octets. Compatibility for secured frames is shown in Table 8-5, which identifies the security operating modes for IEEE 802.15.4-2006. Table 8-5. Frame Control Field – Security and Frame Version.

Frame Control Field Bit Assignments		Description
Security Enabled b_3	Frame Version b_13 b_12
0	00	No security. Frames are compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006.
0	01	No security. Frames are not compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006.
1	00	Secured frame formatted according to IEEE 802.15.4-2003. This frame type is not supported in IEEE 802.15.4-2006.
1	01	Secured frame formatted according to IEEE 802.15.4-2006

8.1.2.4 Sequence Number

The one-octet sequence number following the FCF identifies a particular frame, so that duplicated frame transmissions can be detected. While operating in RX\_AACK mode, the content of this field is copied from the frame to be acknowledged into the acknowledgment frame.

8.1.2.5 Addressing Fields

The addressing fields of the MPDU are used by the Atmel AT86RF232 for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN-ID and a device address. If both addresses are present, and the “PAN ID compression” subfield in the FCF is set to one, the source PAN-ID is omitted. Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid address combinations for the individual possible MAC frame types. For example, the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. The address filter in the AT86RF232 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame formats and exceptions.

8.1.2.6 Auxiliary Security Header Field

The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB is used (see IEEE 802.15.4-2006, Section 7.6.1). This field shall be present only if the Security Enabled subfield b3, see Section 8.1.2.3, is set to one. For details of its structure, see IEEE 802.15.4-2006, Section 7.6.2 Auxiliary security header.

8.1.2.7 MAC Service Data Unit (MSDU)

This is the actual MAC payload. It is usually structured according to the individual frame type. A description can be found in IEEE 802.15.4-2006, Section 5.5.3.2.

8.1.2.8 MAC Footer (MFR) Fields

The MAC footer consists of a two-octet Frame Checksum (FCS), for details refer to Section 8.2.

8.2 Frame Check Sequence (FCS)

The Frame Check Sequence (FCS) is characterized by: - Indicate bit errors, based on a cyclic redundancy check (CRC) of length 16-bit - Uses International Telecommunication Union (ITU) CRC polynomial • Automatically evaluated during reception - Can be automatically generated during transmission

8.2.1 Overview

The FCS is intended for use at the MAC layer to detect corrupted frames at a first level of filtering. It is computed by applying an ITU CRC polynomial to all transferred bytes following the length field (MHR and MSDU fields). The frame check sequence has a length of 16-bit and is located in the last two bytes of a frame (MAC footer, see Figure 8-2). The Atmel AT86RF232 applies an FCS check on each received frame. The FCS check result is stored in register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI). On transmission the radio transceiver generates and appends the FCS bytes during the frame transmission. This behavior can be disabled by setting register bit TX\_AUTO\_CRC\_ON = 0 (register 0x04, TRX\_CTRL\_1).

8.2.2 CRC calculation

The CRC polynomial used in IEEE 802.15.4 networks is defined by $$ _ {1 6} (\quad) \quad^ {5 1 2 1 6} $$ The FCS shall be calculated for transmission using the following algorithm: Let $$ M (x) = b _ {0} x ^ {k - 1} + b _ {1} x ^ {k - 2} + \dots + b _ {k - 2} x + b _ {k - 1} $$ be the polynomial representing the sequence of bits for which the checksum is to be computed. Multiply M(x) by x^16 , giving the polynomial $$ N (x) = M (x) \cdot x ^ {1 6} $$ Divide N(x) modulo two by the generator polynomial, G_16(x) , to obtain the remainder polynomial, $$ R (x) = r _ {0} x ^ {1 5} + r _ {1} x ^ {1 4} + \dots + r _ {1 4} x + r _ {1 5} $$ The FCS field is given by the coefficients of the remainder polynomial, R(x) .

Example:

Considering a five octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0110. The leftmost bit ( b_0 ) is transmitted first in time. The FCS is in this case 0010 0111 1001 1110. The leftmost bit (r_0) is transmitted first in time.

8.2.3 Automatic FCS generation

The automatic FCS generation is activated with register bit TX\_AUTO\_CRC\_ON = 1 (reset value). This allows the Atmel AT86RF232 to compute the FCS autonomously. For a frame with a frame length specified as N ( 3 ≤ N ≤ 127 ), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer. If the radio transceiver's automatic FCS generation is enabled, the Frame Buffer write access can be stopped right after MAC payload. There is no need to write FCS dummy bytes. In RX\_AACK mode, when a received frame needs to be acknowledged, the FCS of the ACK frame is always automatically generated by the AT86RF232, independent of the TX\_AUTO\_CRC\_ON setting.

Example:

A frame transmission of length five with TX\_AUTO\_CRC\_ON set, is started with a Frame Buffer write access of five bytes (the last two bytes can be omitted). The first three bytes are used for FCS generation; the last two bytes are replaced by the internally calculated FCS.

8.2.4 Automatic FCS check

An automatic FCS check is applied on each received frame with a frame length N ≥ 2 . Register bit RX\_CRC\_VALID (register 0x06, PHY\_RSSI) is set if the FCS of a received frame is valid. The register bit is updated when issuing interrupt IRQ\_3 (TRX\_END) and remains valid until the next TRX\_END interrupt caused by a new frame reception. In RX\_AACK mode, if FCS of the received frame is not valid, the radio transceiver rejects the frame and the TRX\_END interrupt is not issued. In TX\_ARET mode, the FCS and the sequence number of an ACK is automatically checked. If one of these is not correct, the ACK is not accepted.

8.2.5 Register Description

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 8-4. Register TRX\_CTRL\_1.

Bit 0x04	7	6	5	4	TRX_CTRL_1
	reserved	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0
Bit	3	2	1	0
0x04	SPI_CMD_MODE		IRQ_MASK_MOD	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0

- Bit 5 - TX\_AUTO\_CRC\_ON

The register bit TX\_AUTO\_CRC\_ON controls the automatic FCS generation for transmit operations. Table 8-6. TX AUTO CRC ON.

Register Bits	Value	Description
TX_AUTO_CRC_ON	0	Automatic FCS generation is disabled
	1	Automatic FCS generation is enabled

Note: 1. The TX\_AUTO\_CRC\_ON function can be used within Basic and Extended Operating Modes.

Register 0x06 (PHY\_RSSI):

The PHY\_RSSI register is a multi-purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. Figure 8-5. Register PHY\_RSSI. 

- Bit 7 - RX\_CRC\_VALID

The register bit RX\_CRC\_VALID signals the FCS check status for a received frame. Table 8-7. RX CRC VALID.

Register Bits	Value	Description
RX_CRC_VALID	0	FCS is not valid
	1	FCS is valid

Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ\_3 (TRX\_END) and remains valid until the next TRX\_END interrupt is issued, caused by a new frame reception.

8.3 Received Signal Strength Indicator (RSSI)

The Atmel AT86RF232 Received Signal Strength Indicator is characterized by: - Minimum RSSI level is -91dBm (RSSI BASE\_VAL) • Dynamic range is 87dB • Minimum RSSI value is 0 • Maximum RSSI value is 28

8.3.1 Overview

The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3dB. No attempt is made to distinguish IEEE 802.15.4 signals from others, only the received signal strength is evaluated. The RSSI provides the basis for an ED measurement, see Section 8.4.

8.3.2 Reading RSSI

In Basic Operating Mode the RSSI value is valid in any receive state, and is updated every t_RSSI = 2 s to register 0x06 (PHY\_RSSI). It is not recommended to read the RSSI value when using the Extended Operating Mode. The automatically generated ED value should be used alternatively, see Section 8.4.

8.3.3 Data Interpretation

The RSSI value is a 5-bit value indicating the receive power, in steps of 3dB and with a range of zero to 28. An RSSI value of zero indicates a receiver RF input power of r_P ≤ -91dBm . For an RSSI value in the range of one to 28, the RF input power can be calculated as follows: $$ P _ {R F} [ \mathrm{dBm} ] = R S S I _ {\text { BASE\_VAL }} + 3 \times R S S I $$ Figure 8-6. Mapping between RSSI Value and Received Input Power. 

8.3.4 Register Description

Register 0x06 (PHY\_RSSI):

The PHY\_RSSI register is a multi-purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. Figure 8-7. Register PHY\_RSSI. 

- Bit 4:0 - RSSI

Received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3dB. Table 8-8. RSSI.

Register Bits	Value	Description
RSSI	0x00	Minimum RSSI value
	0x1C	Maximum RSSI value

The result of the automated RSSI measurement is stored in register bits RSSI. The value is updated every t_RSSI = 2 s in receive states. The read value is a number between zero and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale with a resolution of 3dB. An RSSI value of zero indicates an RF input power of P_RF ≤ -91dBm (RSSI _BASE\_VAL ), a value of 28 a power of P_RF ≥ -7dBm (see parameter RSSI _MAX specified in Section 12.7).

8.4 Energy Detection (ED)

The Atmel AT86RF232 Energy Detection (ED) module is characterized by: • 84 unique energy levels defined - 1dB resolution

8.4.1 Overview

The receiver ED measurement is used by the network layer as part of a channel selection algorithm. It is an estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128 s).

8.4.2 Measurement Description

There are two ways to initiate an ED measurement: - Manually, by writing an arbitrary value to register 0x07 (PHY\_ED\_LEVEL), or - Automatically, after detection of a valid SHR of an incoming frame. For manually initiated ED measurements the radio transceiver needs to be in one of the states RX\_ON or BUSY\_RX state. The end of the ED measurement is indicated by an interrupt IRQ\_4 (CCA\_ED\_DONE). An automated ED measurement is started if an SHR is detected. The end of the automated measurement is not signaled by an interrupt. Note: 1. The ED result is not updated during the rest of the frame reception, even by requesting an ED measurement manually. The measurement result is stored after t_ED = 180 s (max.) (128 s measurement duration and processing delay) in register 0x07 (PHY\_ED\_LEVEL), refer to Table 7-2. Thus by using Basic Operating Mode, a valid ED value from the currently received frame is accessible 108 s after IRQ\_2 (RX\_START) and remains valid until a new RX\_START interrupt is generated by the next incoming frame or until another ED measurement is initiated. When using the Extended Operating Mode, it is recommended to mask IRQ\_2 (RX\_START), thus the interrupt cannot be used as timing reference. A successful frame reception is signalized by interrupt IRQ\_3 (TRX\_END). The minimum time span between an IRQ\_3 (TRX\_END) interrupt and a following SFD detection is t_SHR\_SYNC = 96 s due to the length of the SHR. Including the ED measurement time, the ED value needs to be read within 224 s after the TRX\_END interrupt; otherwise, it could be overwritten by the result of the next measurement cycle. This is important for time critical applications or if interrupt IRQ\_2 (RX\_START) is not used to indicate the reception of a frame. Note: 2. It is not recommended to manually initiate an ED measurement when using the Extended Operating Mode.

8.4.3 Data Interpretation

The PHY\_ED\_LEVEL is an 8-bit register. The ED\_LEVEL value of the Atmel AT86RF232 has a valid range from 0x00 to 0x53 with a resolution of 1dB. A value of 0xFF indicates the reset value. All other values do not occur. Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED\_LEVEL value has a maximum tolerance of ±5dB , this is to be considered as constant offset over the measurement range. An ED\_LEVEL value of zero indicates an RF input power of P_RF ≤ -91dBm (see parameter RSSI _BASE\_VAL , Section 12.7). For an ED\_LEVEL value in the range of one to 83, the RF input power can be calculated as follows: $$ P _ {R F} [ d B m ] = R S S I _ {B A S E \_ V A L} + E D \_ L E V E L $$ Figure 8-8. Mapping between Received Input Power and ED Value. 

8.4.4 Interrupt Handling

Interrupt IRQ\_4 (CCA\_ED\_DONE) is issued at the end of a manually initiated ED measurement. Note: 1. An ED request should only be initiated in receive states. Otherwise the radio transceiver generates an IRQ\_4 (CCA\_ED\_DONE); however no ED measurement was performed.

8.4.5 Register Description

Register 0x07 (PHY\_ED\_LEVEL):

The PHY\_ED\_LEVEL register contains the result of an ED measurement. Figure 8-9. Register PHY\_ED\_LEVEL. 

- Bit 7:0 - ED\_LEVEL

The register bits ED\_LEVEL signals the ED level for current channel. Table 8-9. ED LEVEL.

Register Bits	Value	Description
ED_LEVEL	0x00	Minimum ED level value
	0x53	Maximum ED level value
	0xFF	Reset value

The minimum ED value zero indicates receiver power less than or equal RSSI BASE\_VAL. The range is 83dB with a resolution of 1dB and an accuracy of ±5dB. A manual ED measurement can be initiated by a write access to the register. A value 0xFF signals that no measurement has been started yet (reset value). The measurement duration is eight symbol periods (128 s) for a data rate of 250kb/s.

8.5 Clear Channel Assessment (CCA)

The main features of the Clear Channel Assessment (CCA) module are: - All four modes are available as defined by IEEE 802.15.4-2006 in Section 6.9.9 - Adjustable threshold for energy detection algorithm

8.5.1 Overview

A CCA measurement is used to detect a clear channel. Four modes are specified by IEEE 802.15.4-2006: Table 8-10. CCA Mode Overview.

CCA Mode	Description
1	Energy above threshold.CCA shall report a busy medium upon detecting any energy above the ED threshold.
2	Carrier sense only.CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an IEEE 802.15.4 compliant signal.The signal strength may be above or below the ED threshold.
0, 3	Carrier sense with energy above threshold.CCA shall report a busy medium using a logical combination of- Detection of a signal with the modulation and spreading characteristics of this standard and- Energy above the ED threshold.Where the logical operator may be configured as either OR (mode 0) or AND (mode 3).

8.5.2 Configuration and Request

The CCA modes are configurable via register 0x08 (PHY\_CC\_CCA). Using the Basic Operating Mode, a CCA request can be initiated manually by setting CCA\_REQUEST = 1 (register 0x08, PHY\_CC\_CCA), if the Atmel AT86RF232 is in any RX state. The current channel status (CCA\_STATUS) and the CCA completion status (CCA\_DONE) are accessible in register 0x01 (TRX\_STATUS). The CCA evaluation is done over eight symbol periods and the result is accessible t_CCA = 180 s (max.) (128 s measurement duration and processing delay) after the request), refer to Table 7-2. The end of a manually initiated CCA measurement is indicated by an interrupt IRQ\_4 (CCA\_ED\_DONE). The register bits CCA\_ED\_THRES of register 0x09 (CCA\_THRES) defines the received power threshold of the "Energy above threshold" algorithm. The threshold is calculated by RSSI _BASE\_VAL + 2 x CCA\_ED\_THRES [dB]. Any received power above this level is interpreted as a busy channel. Note: 1. It is not recommended to manually initiate a CCA measurement when using the Extended Operating Mode.

8.5.3 Data Interpretation

The Atmel AT86RF232 current channel status (CCA\_STATUS) and the CCA completion status (CCA\_DONE) are accessible in register 0x01 (TRX\_STATUS). Note, register bits CCA\_DONE and CCA\_STATUS are cleared in response to a CCA\_REQUEST. The completion of a measurement cycle is indicated by CCA\_DONE = 1. If the radio transceiver detected no signal (idle channel) during the measurement cycle, the CCA\_STATUS bit is set to one. When using the “energy above threshold” algorithm, any received power above CCA\_ED\_THRES level is interpreted as a busy channel. The “carrier sense” algorithm reports a busy channel when detecting an IEEE 802.15.4 signal above the RSSI _BASE\_VAL (see Section 12.7). The radio transceiver is also able to detect signals below this value, but the detection probability decreases with the signal power. It is almost zero at the radio transceiver’s sensitivity level (see parameter P_SENS ).

8.5.4 Interrupt Handling

Interrupt IRQ\_4 (CCA\_ED\_DONE) is issued at the end of a manually initiated CCA measurement. Notes: 1. A CCA request should only be initiated in Basic Operating Mode receive states. Otherwise the radio transceiver generates an IRQ\_4 (CCA\_ED\_DONE) and sets the register bit CCA\_DONE = 1, even though no CCA measurement was performed. 2. Requesting a CCA measurement in BUSY\_RX state and during an ED measurement, an IRQ\_4 (CCA\_ED\_DONE) could be issued immediately after the request. If in this case register bit CCA\_DONE = 0, an additional interrupt CCA\_ED\_DONE is issued after finishing the CCA measurement and register bit CCA\_DONE is set to one.

8.5.5 Measurement Time

The response time for a manually initiated CCA measurement depends on the receiver state. In RX\_ON state the CCA measurement is done over eight symbol periods and the result is accessible t_CCA = 180 s after the request (see above). Table 8-11. CCA Measurement Period and Access in BUSY RX state.

CCA Mode	Request within ED measurement(1)	Request after ED measurement
1	Energy above threshold.
	CCA result is available after finishing automated ED measurement period.	CCA result is immediately available after request.
2	Carrier sense only.
	CCA result is immediately available after request.
3	Carrier sense with Energy above threshold (AND).
	CCA result is available after finishing automated ED measurement period.	CCA result is immediately available after request.
0	Carrier sense with Energy above threshold (OR).
	CCA result is available after finishing automated ED measurement period.	CCA result is immediately available after request.

Note: 1. After receiving the SHR an automated ED measurement is started with a length of eight symbol periods (PSDU rate 250kb/s), refer to Section 8.4. This automated ED measurement must be finished to provide a result for the CCA measurement. Only one automated ED measurement per frame is performed. In BUSY\_RX state the CCA measurement duration depends on the CCA Mode and the CCA request relative to the reception of an SHR. The end of the CCA measurement is indicated by an IRQ\_4 (CCA\_ED\_DONE). The variation of a CCA measurement period in BUSY\_RX state is described in Table 8-11. It is recommended to perform CCA measurements in Atmel AT86RF232 RX\_ON state only. To avoid switching accidentally to BUSY\_RX state the SHR detection can be disabled by setting register bit RX\_PDT\_DIS (register 0x15, RX\_SYN), refer to Section 9.1. The receiver remains in RX\_ON state to perform a CCA measurement until the register bit RX\_PDT\_DIS is set back to continue the frame reception. In this case the CCA measurement duration is eight symbol periods.

8.5.6 Register Description

Register 0x01 (TRX\_STATUS):

The read-only register TRX\_STATUS signals the present state of the radio transceiver as well as the status of a CCA operation. Figure 8-10. Register TRX\_STATUS. 

- Bit 7 - CCA\_DONE

Table 8-12. CCA\_DONE.

Register Bits	Value	Description
CCA_DONE	0	CCA calculation not finished
	1	CCA calculation finished

The register bit CCA\_DONE indicates if a CCA request is completed. This is also indicated by an interrupt IRQ\_4 (CCA\_ED\_DONE). The register bit CCA\_DONE is cleared in response to a CCA\_REQUEST.

- Bit 6 - CCA\_STATUS

Table 8-13. CCA STATUS.

Register Bits	Value	Description
CCA_STATUS	0	Channel indicated as busy
	1	Channel indicated as idle

After a CCA request is completed the result of the CCA measurement is available in register bit CCA\_STATUS. The register bit CCA\_STATUS is cleared in response to a CCA\_REQUEST.

Register 0x08 (PHY\_CC\_CCA):

The PHY\_CC\_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the IEEE 802.15.4 channel setting. Figure 8-11. Register PHY\_CC\_CCA.

Bit	7	6	5	4
0x08	CCA_REQUEST	CCA_MODE		CHANNEL	PHY_CC_CCA
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0
Bit	3	2	1	0
0x08	CHANNEL				PHY_CC_CCA
Read/Write	R/W	R/W	R/W	R/W
Reset value	1	0	1	1

- Bit 7 - CCA\_REQUEST

The register bit CCA\_REQUEST initiates a manual started CCA measurement. Table 8-14. CCA REQUEST.

Register Bits	Value	Description
CCA_REQUEST	0	Reset value
	1	Starts a CCA measurement

Notes: 1. The read value returns always with zero. 2. If a CCA request is initiated in states others than RX\_ON or RX\_BUSY the PHY generates an IRQ\_4 (CCA\_ED\_DONE) and sets the register bit CCA\_DONE, however no CCA was carried out. A manual CCA measurement is initiated with setting CCA\_REQUEST = 1. The end of the CCA measurement is indicated by interrupt IRQ\_4 (CCA\_ED\_DONE). Register bits CCA\_DONE and CCA\_STATUS (register 0x01, TRX\_STATUS) are updated after a CCA\_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA\_REQUEST = 1.

- Bit 6:5 - CCA\_MODE

The CCA mode can be selected using register bits CCA\_MODE. Table 8-15. CCA\_MODE.

Register Bits	Value	Description
CCA_MODE	0	Mode 3a, Carrier sense OR energy above threshold
	1	Mode 1, Energy above threshold
	2	Mode 2, Carrier sense only
	3	Mode 3b, Carrier sense AND energy above threshold

Register 0x09 (CCA\_THRES):

The CCA\_THRES register sets the ED threshold level for CCA. Figure 8-12. Register CCA\_THRES. 

- Bit 3:0 - CCA\_ED\_THRES

An ED value above the threshold signals the channel during a CCA\_ED measurement as busy. Table 8-16. CCA ED THRES.

Register Bits	Value	Description
CCA_ED_THRES	0x7	The CCA Mode 1 request indicates a busy channel if the measured received power is above RSSI_BASE_VAL + 2 x CCA_ED_THRES [dB]. CCA Modes 0 and 3 are logical related to this result.

8.6 Link Quality Indication (LQI)

According to IEEE 802.15.4, the LQI measurement is a characterization of the strength and/or quality of a received packet. The measurement may be implemented using receiver ED, a signal-to-noise ratio estimation, or a combination of these methods. The use of the LQI result by the network or application layers is not specified in this standard. LQI values shall be an integer ranging from 0x00 to 0xFF. The minimum and maximum LQI values (0x00 and 0xFF) should be associated with the lowest and highest quality compliant signals, respectively, and LQI values in between should be uniformly distributed between these two limits.

8.6.1 Overview

The LQI measurement of the Atmel AT86RF232 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error, whereas at a PER of one no frame was received correctly. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value. This is done for each received frame. The minimum frame length for a valid LQI value is two octets PSDU. LQI values are integers ranging from zero to 255. As an example, Figure 8-13 shows the conditional packet error rate (PER) when receiving a certain LQI value. Figure 8-13. Conditional Packet Error Rate versus LQI.  That means that a large number of transmission with an identical LQI value results in a packet error rate shown in the Figure 8-13. Lost packets have been discarded since in this case there is no LQI value available. If, instead, the mean LQI over a large number of transmissions is computed, and the mean LQI is quantized to an LQI value of the figure, the corresponding frame error rate is not strictly equal to the true error rate. The values are taken from received frames of PSDU length of 20 octets on transmission channels with reasonable low multipath delay spreads. If the transmission channel characteristic has higher multipath delay spread than assumed in the example, the PER is slightly higher for a certain LQI value. Since the packet error rate is a statistical value, the PER shown in Figure 8-13 is based on a huge number of transactions. A reliable estimation of the packet error rate cannot be based on a single or a small number of LQI values.

8.6.2 Request an LQI Measurement

The LQI byte can be obtained after a frame has been received by the radio transceiver. One additional byte is automatically attached to the received frame containing the LQI value. This information can also be read via Frame Buffer read access, see Section 6.2.2. The LQI byte can be read after IRQ\_3 (TRX\_END) interrupt.

8.6.3 Data Interpretation

According to IEEE 802.15.4 a low LQI value is associated with low signal strength and/or high signal distortions. Signal distortions are mainly caused by interference signals and/or multipath propagation. High LQI values indicate a sufficient high signal power and low signal distortions. Note: 1. The received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the Atmel AT86RF232 do n characterize the signal quality and the ability to decode a signal. As an example, a received signal with an input power of about 6dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions. For higher signal power the LQI value becomes independent of the actual signal strength. This is because the packet error rate for these scenarios tends towards zero and further increased signal strength, that is increasing the transmission power does not decrease the error rate any further. In this case RSSI or ED can be used to evaluate the signal strength and the link margin. ZigBee networks often require the identification of the “best” routing between two nodes. Both, the LQI and the RSSI/ED can be used for this, dependent on the optimization criteria. If a low packet error rate (corresponding to high throughput) is the optimization criteria then the LQI value should be taken into consideration. If a low transmission power or the link margin is the optimization criteria then the RSSI/ED value is also helpful. Combinations of LQI, RSSI and ED are possible for routing decisions. As a rule of thumb RSSI and ED values are useful to differentiate between links with high LQI values. Transmission links with low LQI values should be discarded for routing decisions even if the RSSI/ED values are high. This is because RSSI/ED does not say anything about the possibility to decode a signal. It is only an information about the received signal strength whereas the source can be an interferer.

9 Module Description

9.1 Receiver (RX)

9.1.1 Overview

The Atmel AT86RF232 receiver is split into an analog radio front-end and a digital base band processor (RX BBP), see Figure 9-1. Figure 9-1. Receiver Block Diagram. 

graph LR
    A["RFP"] --> B["LNA"]
    C["RFN"] --> B
    B --> D["LO"]
    D --> E["×"]
    E --> F["PF Limiter ADC"]
    F --> G["×"]
    G --> H["Square Block"]
    H --> I["AGC"]
    I --> J["RSSI"]
    J --> K["Control, Registers"]
    K --> L["SPIRX"]
    L --> M["SPIX"]
    N["Frame Buffer"] --> O["Square Block"]
    O --> P["SPIRX"]
    Q["μC I/F"] --> R["Control, Registers"]
    R --> S["SPIRX"]
    T["Analog Domain Digital Domain"] --> U["RFN"]
    T --> V["LNA"]

The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band receiver (RX BBP). The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. The receiver is designed to handle frequency and symbol rate deviations f_SRD up to ±120ppm , caused by combined receiver and transmitter deviations. For details refer to Section 12.5 parameter f_SRD . Finally the signal is demodulated and the data are stored in the Frame Buffer. In Basic Operating Mode, refer to Section 7.1, the reception of a frame is indicated by an interrupt IRQ\_2 (RX\_START). Accordingly its end is signalized by an interrupt IRQ\_3 (TRX\_END). Based on the quality of the received signal a link quality indicator (LQI) is calculated and appended to the frame, refer to Section 8.6. Additional signal processing is applied to the frame data to provide further status information like ED value (register 0x07, PHY\_ED\_LEVEL) and FCS correctness (register 0x06, PHY\_RSSI). Beyond these features the Extended Operating Mode of the AT86RF232 supports address filtering and pending data indication. For details refer to Section 7.2.

9.1.2 Frame Receive Procedure

The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in Section 10.1 Frame Receive Procedure.

9.1.3 Configuration

In Basic Operating Mode the receiver is enabled by writing command RX\_ON to register bits TRX\_CMD (register 0x02, TRX\_STATE) in states TRX\_OFF or PLL\_ON. Similarly in Extended Operating Mode, the receiver is enabled for RX\_AACK operation from states TRX\_OFF or PLL\_ON by writing the command RX\_AACK\_ON. There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the Atmel AT86RF232 Extended Operating Mode requires further register configurations, for details refer to Section 7.2. The AT86RF232 receiver has an outstanding sensitivity performance of -100dBm. It may be useful to manually decrease this sensitivity. This is achieved by adjusting the synchronization header detector threshold using register bits RX\_PDT\_LEVEL (register 0x15, RX\_SYN). Received signals with an RSSI value below the threshold do not activate the demodulation process. Furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. A Dynamic Frame Buffer Protection is enabled with register bit RX\_SAFE\_MODE (register 0x0C, TRX\_CTRL\_2) set, see Section 11.6. The receiver remains in RX\_ON or RX\_AACK\_ON state until the whole frame is read by the microcontroller, indicated by pin 23 (/SEL) = H during the SPI Frame Receive Mode. The Frame Buffer content is only protected if the FCS is valid. A Static Frame Buffer Protection is enabled with register bit RX\_PDT\_DIS (register 0x15, RX\_SYN) set. The receiver remains in RX\_ON or RX\_AACK\_ON state and no further SHR is detected until the register bit RX\_PDT\_DIS is set back.

9.1.4 Register Description

Register 0x15 (RX\_SYN):

The register RX\_SYN controls the blocking of receiver path and the sensitivity threshold of the receiver. Figure 9-2. Register RX\_SYN. 

- Bit 7 - RX\_PDT\_DIS

The register bit RX\_PDT\_DIS prevents the reception of a frame during RX phase. Table 9-1. RX\_PDT\_DIS.

Register Bits	Value	Description
RX_PDT_DIS	0	RX path is enabled
	1	RX path is disabled

RX\_PDT\_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing frame reception is not affected. This operation mode is independent of the setting of register bits RX\_PDT\_LEVEL.

- Bit 3:0 - RX\_PDT\_LEVEL

The register bits RX\_PDT\_LEVEL desensitize the receiver in steps of 3dB. Table 9-2. RX PDT LEVEL.

Register Bits	Value	Description
RX_PDT_LEVEL	0x00	Maximum RX sensitivity
	0x0F	RX input level > RSSI_BASE_VAL + 3 x 14

These register bits desensitize the receiver such that frames with an RSSI level below the RX\_PDT\_LEVEL threshold level (if RX\_PDT\_LEVEL > 0) are not received. For a RX\_PDT\_LEVEL > 0 value the threshold level can be calculated according to the following formula: $$ P _ {R F} [ \mathrm{dBm} ] > R S S I _ {\text { BASE\_VAL }} + 3 \times (R X \_ P D T \_ L E V E L - 1) $$ Examples for certain register settings are given in Table 9-3. Table 9-3. Receiver Desensitization Threshold Level – RX PDT LEVEL.

Register Value	RX Input Threshold Level	Value [dBm]
0x0	disabled, maximum RX sensitivity	RSSI value not considered
0x1	> RSSI_BASE_VAL + 3 x 0	>-91
...
0xE	> RSSI_BASE_VAL + 3 x 13	>-52
0xF	> RSSI_BASE_VAL + 3 x 14	>-49

If register bits RX\_PDT\_LEVEL = 0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. If register bits RX\_PDT\_LEVEL > 0, the current consumption of the receiver in states RX\_ON and RX\_AACK\_ON is reduced to I RX\_ON\_L0 = 11.3mA (typ.), refer to Section 12.8.

9.2 Transmitter (TX)

9.2.1 Overview

The Atmel AT86RF232 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-3. Figure 9-3. Transmitter Block Diagram. 

graph LR
    A["RF"] --> B["Amplifier"]
    C["RFN"] --> B
    B --> D["Buf"]
    D --> E["PLL - TX Modulation PA"]
    E --> F["TX Data"]
    F --> G["Control, Registers"]
    G --> H["μC I/F"]
    G --> I["SPI I/F"]
    G --> J["TX BBP"]
    J --> K["Frame Buffer"]
    K --> L["SPI"]
    style A fill:#f9f,stroke:#333
    style C fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style D fill:#ccf,stroke:#333
    style E fill:#ccf,stroke:#333
    style F fill:#ccf,stroke:#333
    style G fill:#ccf,stroke:#333
    style H fill:#ccf,stroke:#333
    style I fill:#ccf,stroke:#333
    style J fill:#ccf,stroke:#333
    style K fill:#ccf,stroke:#333
    style L fill:#ccf,stroke:#333
    style_M["Ext. RF front-end and Output Power Control"] --> N["Control, Registers"]
    O["PLL - TX Modulation PA"] --> N
    P["Frame Buffer"] --> N

The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in Section 6.5.2. The O-QPSK modulation signal is generated and fed into the analog radio front end. The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF signal, which is amplified by the power amplifier (PA). The PA output is internally connected to bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed.

9.2.2 Frame Transmit Procedure

The frame transmit procedure including writing PSDU data in the Frame Buffer and initiating a transmission is described in Section 10.2 Frame Transmit Procedure.

9.2.3 Configuration

The maximum output power of the transmitter is typically +3dBm. The output power can be configured via register bits TX\_PWR (register 0x05, PHY\_TX\_PWR). The output power of the transmitter can be controlled over a range of 20dB. A transmission can be started from PLL\_ON or TX\_ARET\_ON state by a rising edge of pin 11 (SLP\_TR) or by writing TX\_START command to register bits TRX\_CMD (register 0x02, TRX\_STATE). Figure 9-4. TX Power Ramping for maximum TX Power. 

9.2.4 TX Power Ramping

To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequentially, see in Figure 9-4. In this example the transmission is initiated with the rising edge of pin 11 (SLP\_TR). The radio transceiver state changes from PLL\_ON to BUSY\_TX. The modulation of the frame starts 16 s after SLP\_TR rising edge.

9.2.5 Register Description

Register 0x05 (PHY\_TX\_PWR):

The PHY\_TX\_PWR register controls the output power of the transmitter. Figure 9-5. Register PHY\_TX\_PWR. 

- Bit 3:0 - TX\_PWR

The register bits TX\_PWR determine the TX output power of the radio transceiver. Table 9-4. TX Output Power.

Register Bits	Value	TX Output Power [dBm]
TX_PWR	0x0	+3.0
	0x1	+2.8
	0x2	+2.3
	0x3	+1.8
	0x4	+1.3
	0x5	+0.7
	0x6	0.0
	0x7	-1
	0x8	-2
	0x9	-3
	0xA	-4
	0xB	-5
	0xC	-7
	0xD	-9
	0xE	-12
	0xF	-17

9.3 Frame Buffer

The Atmel AT86RF232 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep one IEEE 802.15.4 RX or one TX frame of maximum length at a time. Frame Buffer access modes are described in Section 6.2.2. Frame Buffer access conflicts are indicated by an under run interrupt IRQ\_6 (TRX\_UR). Note: 1. The IRQ\_6 (TRX\_UR) interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame Buffer. In that case the content of the Frame Buffer cannot be guaranteed. Frame Buffer access is only possible if the digital voltage regulator (DVREG) is turned on. This is valid in all device states except in SLEEP state. An access in P\_ON state is possible if pin 17 (CLKM) provides the 1MHz master clock.

9.3.1 Data Management

Data in Frame Buffer (received data or data to be transmitted) remains valid as long as: - No new frame or other data are written into the buffer over SPI - No new frame is received (in any BUSY\_RX state) - No state change into SLEEP state is made - No RESET took place By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is received during Frame Buffer read access of a previously received frame, interrupt IRQ\_6 (TRX\_UR) is issued and the stored data might be overwritten. Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air data rate. For a data rate of 250kb/s a minimum SPI clock rate of 1MHz is recommended. Finally the microcontroller should check the transferred frame data integrity by an FCS check. To protect the Frame Buffer content against being overwritten by newly incoming frames the radio transceiver state should be changed to PLL\_ON state after reception. This can be achieved by writing immediately the command PLL\_ON to register bits TRX\_CMD (register 0x02, TRX\_STATE) after receiving the frame, indicated by IRQ\_3 (TRX\_END). Alternatively, Dynamic Frame Buffer Protection can be used to protect received frames against overwriting, for details refer to Section 11.6. Both procedures do not protect the Frame Buffer from overwriting by the microcontroller. In Extended Operating Mode during TX\_ARET operation, see Section 7.2.4, the radio transceiver switches to receive, if an acknowledgement of a previously transmitted frame was requested. During this period received frames are evaluated, but not stored in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission without writing them again. A radio transceiver state change, except a transition to SLEEP, or RESET state, does not affect the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the Frame Buffer is powered off and the stored data gets lost.

9.3.2 User accessible Frame Content

The Atmel AT86RF232 supports an IEEE 802.15.4 compliant frame format as shown in Figure 9-6. Figure 9-6. AT86RF232 Frame Structure. 

0 Length [octets] 4 5 6 n + 3 n + 5 n + 6 n + 7 n + 8 Frame Preamble Sequence SFD PHR Payload LQI FCS (1) ED(1) RX_STATUS(1) Duration 4 octets 1 n octets (n <= 128) 3 octets Access SHR not accessible PHY generated TX: Frame Buffer content RX: Frame Buffer content

Note: 1. Stored into Frame Buffer during frame reception. A frame comprises two sections, the radio transceiver internally generated SHR field and the user accessible part stored in the Frame Buffer. The SHR contains the preamble and the SFD field. The variable frame section contains the PHR and the PSDU including the FCS, see Section 8.2. To access the data follow the procedures described in Section 6.2.2. The frame length information (PHR field) and the PSDU are stored in the Frame Buffer. During frame reception, the link quality indicator (LQI) value, the energy detection (ED) value, and the status information (RX\_STATUS) of a received frame are additionally stored, see Section 8.6, Section 8.4, and Section 6.2.2, respectively. The radio transceiver appends these values to the frame data during Frame Buffer read access. If the SRAM read access is used to read an RX frame, the frame length field (PHR) can be accessed at address zero. The SHR cannot be read by the microcontroller. For frame transmission, the PHR and the PSDU needs to be stored in the Frame Buffer. The maximum frame size supported by the radio transceiver is 128 bytes. If the register bit TX\_AUTO\_CRC\_ON is set in register 0x05 (PHY\_TX\_PWR), the FCS field of the PSDU is replaced by the automatically calculated FCS during frame transmission. There is no need to write the FCS field when using the automatic FCS generation. To manipulate individual bytes of the Frame Buffer a SRAM write access can be used instead. For non IEEE 802.15.4 compliant frames, the minimum frame length supported by the radio transceiver is one byte (Frame Length Field + one byte of data).

9.3.3 Interrupt Handling

Access conflicts may occur when reading and writing data simultaneously at the two independent ports of the Frame Buffer, TX/RX BBP and SPI. These ports have their own address counter that points to the Frame Buffer's current address. Access violations occurs during concurrent Frame Buffer read or write accesses, when the SPI port's address counter value becomes higher than or equal to that of TX/RX BBP port. While receiving a frame, primarily the data needs to be stored in the Atmel AT86RF232 Frame Buffer before reading it. This can be ensured by accessing the Frame Buffer 32 s after IRQ\_2 (RX\_START) at the earliest. When reading the frame data continuously the SPI data rate shall be lower than 250kb/s to ensure no under run interrupt occurs. To avoid access conflicts and to simplify the Frame Buffer read access Frame Buffer Empty indication may be used, for details refer to Section 11.5. During transmission, an access violation occurs on Frame Buffer write access, when the SPI port's address counter value becomes less than or equal to that of TX BBP port. Both these access violations may cause data corruption and are indicated by IRQ\_6 (TRX\_UR) interrupt when using the Frame Buffer access mode. Access violations are not indicated when using the SRAM access mode. Notes: 1. Interrupt IRQ\_6 (TRX\_UR) is valid 64μs after IRQ\_2 (RX\_START). The occurrence of the interrupt can be disregarded when reading the first byte of the Frame Buffer between 32μs and 64μs after the RX\_START interrupt. 2. If a Frame Buffer read access is not finished until a new frame is received, an IRQ\_6 (TRX\_UR) interrupt occurs. Nevertheless the old frame data can be read, if the SPI data rate is higher than the effective PHY data rate. A minimum SPI clock rate of 1MHz is recommended in this case. Finally, the microcontroller should check the integrity of the transferred frame data by calculating the FCS. 3. When writing data to the Frame Buffer during frame transmission, the SPI data rate shall be higher than the PHY data rate to ensure no under run interrupt. The first byte of the PSDU data must be available in the Frame Buffer before SFD transmission is complete, which takes 176 s (16 s PA ramp-up + 160 s SHR) from the rising edge of pin 11 (SLP\_TR) (see Figure 7-2).

9.4 Voltage Regulators (AVREG, DVREG)

The main features of the Voltage Regulator blocks are: - Bandgap stabilized 1.8V supply for analog and digital domain - Low dropout (LDO) voltage regulator - Configurable for usage of external voltage regulator

9.4.1 Overview

The internal voltage regulators supply a stabilized voltage to the Atmel AT86RF232. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. A simplified schematic of the internal voltage regulator is shown in Figure 9-7. Figure 9-7. Simplified Schematic of AVREG/DVREG. 

Bandgap voltage reference 1.25V (D)EVDD AVDD, DVDD

The voltage regulators require bypass capacitors for stable operation. The value of the bypass capacitors determine the settling time of the voltage regulators. The bypass capacitors shall be placed as close as possible to the pins and shall be connected to ground with the shortest possible traces.

9.4.2 Configuration

The voltage regulators can be configured by the register 0x10 (VREG\_CTRL). It is recommended to use the internal regulators, but it is also possible to supply the low voltage domains by an external voltage supply. For this configuration, the internal regulators need to be switched off by setting the register bits to the values AVREG\_EXT = 1 and DVREG\_EXT = 1. A regulated external supply voltage of 1.8V needs to be connected to the pins 13, 14 (DVDD) and pin 29 (AVDD). When turning on the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF232.

9.4.3 Data Interpretation

The status bits AVDD\_OK = 1 and DVDD\_OK = 1 of register 0x10 (VREG\_CTRL) indicate an enabled and stable internal supply voltage. Reading value zero indicates a disabled or internal supply voltage not settled to the final value.

9.4.4 Register Description

Register 0x10 (VREG\_CTRL):

The VREG\_CTRL register controls the use of the voltage regulators and indicates the status of these. Figure 9-8. Register VREG\_CTRL. 

- Bit 7 - AVREG\_EXT

If set this register bit disables the internal analog voltage regulator to apply an external regulated 1.8V supply for the analog building blocks. Table 9-5. AVREG\_EXT.

Register Bits	Value	Description
AVREG_EXT	0	Internal voltage regulator enabled, analog section
	1	Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the analog section

- Bit 6 - AVDD\_OK

This register bit indicates if the internal 1.8V regulated voltage supply AVDD has settled. The bit is set to logic high, if AVREG\_EXT = 1. Table 9-6. AVDD OK.

Register Bits	Value	Description
AVDD_OK	0	Analog voltage regulator is disabled or supply voltage not stable
	1	Analog supply voltage has been settled

- Bit 3 - DVREG\_EXT

If set this register bit disables the internal digital voltage regulator to apply an external regulated 1.8V supply for the digital building blocks. Table 9-7. DVREG EXT.

Register Bits	Value	Description
DVREG_EXT	0	Internal voltage regulator enabled, digital section
	1	Internal voltage regulator disabled, use external regulated 1.8V supply voltage for the digital section

- Bit 2 - DVDD\_OK

This register bit indicates if the internal 1.8V regulated voltage supply DVDD has settled. The bit is set to logic high, if DVREG\_EXT = 1. Table 9-8. DVDD OK.

Register Bits	Value	Description
DVDD_OK	0	Digital voltage regulator is disabled or supply voltage not stable
	1	Digital supply voltage has settled

Note: 1. While the reset value of this bit is zero, any practical access to the register is only possible when DVREG is active. So this bit is normally always read out as one.

9.5 Battery Monitor (BATMON)

The main features of the battery monitor are: - Configurable voltage threshold range: 1.7V to 3.675V - Generates an interrupt when supply voltage drops below a threshold

9.5.1 Overview

The Atmel AT86RF232 battery monitor (BATMON) detects and indicates a low supply voltage of the external supply voltage at pin 28 (EVDD). This is done by comparing the voltage on the external supply pin 28 (EVDD) with a configurable internal threshold voltage. A simplified schematic of the BATMON with the most important input and output signals is shown in Figure 9-9. Figure 9-9. Simplified Schematic of BATMON. 

graph LR
    A["BATMON_HR"] --> B["DAC"]
    C["BATMON_VTH"] --> B
    B --> D["Threshold Voltage"]
    D --> E["+"]
    E --> F["BATMON_OK"]
    G["For input-to-output mapping see control register 0x11 (BATMON)"] --> B
    H["1"] --> I["d"]
    I --> J["clear"]
    J --> K["Q"]
    K --> L["BATMON_IRQ"]
    M["EVDD"] --> N["+"]
    N --> E

9.5.2 Configuration

The BATMON can be configured using the register 0x11 (BATMON). Register bits BATMON\_VTH sets the threshold voltage. It is configurable with a resolution of 75mV in the upper voltage range (BATMON\_HR = 1) and with a resolution of 50mV in the lower voltage range (BATMON\_HR = 0), for details refer to register 0x11 (BATMON).

9.5.3 Data Interpretation

The signal register bit BATMON\_OK of register 0x11 (BATMON) monitors the current value of the battery voltage: - If BATMON\_OK = 0, the battery voltage is lower than the threshold voltage - If BATMON\_OK = 1, the battery voltage is higher than the threshold voltage After setting a new threshold, the value BATMON\_OK should be read out to verify the current supply voltage value. Note: 1. The battery monitor is inactive during P\_ON, and SLEEP states, see register bits TRX\_STATUS (register 0x01, TRX\_STATUS).

9.5.4 Interrupt Handling

A supply voltage drop below the configured threshold value is indicated by an interrupt IRQ\_7 (BAT\_LOW), see Section 6.6. Note: 1. The Atmel AT86RF232 IRQ\_7 (BAT\_LOW) interrupt is issued only if BATMON\_OK changes from one to zero. No interrupt is generated when: - The battery voltage is under the default 1.8V threshold at power-on (BATMON\_OK was never one), or - A new threshold is set, which is still above the current supply voltage (BATMON\_OK remains zero). When the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops may generate unwanted interrupts. To avoid this: - Disable the IRQ\_7 (BAT\_LOW) in register 0x0E (IRQ\_MASK) and treat the battery as empty, or - Set a lower threshold value.

9.5.5 Register Description

Register 0x11 (BATMON):

The BATMON register signals and configures the battery monitor to observe the supply voltage at pin 28 (EVDD). Figure 9-10. Register BATMON. 

- Bit 5 - BATMON\_OK

The register bit BATMON\_OK indicates the level of the external supply voltage with respect to the programmed threshold BATMON\_VTH. Table 9-9. BATMON\_OK.

Register Bits	Value	Description
BATMON_OK	0	The battery voltage is below the threshold
	1	The battery voltage is above the threshold

- Bit 4 - BATMON\_HR

The register bit BATMON\_HR sets the range and resolution of the battery monitor. Table 9-10. BATMON HR.

Register Bits	Value	Description
BATMON_HR	0	Enables the low range, see BATMON_VTH
	1	Enables the high range, see BATMON_VTH

- Bit 3:0 - BATMON\_VTH

The threshold values for the battery monitor are set by register bits BATMON\_VTH. Table 9-11. Battery Monitor Threshold Voltages.

ValueBATMON_VTH	Voltage [V]BATMON_HR = 1	Voltage [V]BATMON_HR = 0
0x0	2.550	1.70
0x1	2.625	1.75
0x2	2.700	1.80
0x3	2.775	1.85
0x4	2.850	1.90
0x5	2.925	1.95
0x6	3.000	2.00
0x7	3.075	2.05
0x8	3.150	2.10
0x9	3.225	2.15
0xA	3.300	2.20
0xB	3.375	2.25
0xC	3.450	2.30
0xD	3.525	2.35
0xE	3.600	2.40
0xF	3.675	2.45

9.6 Crystal Oscillator (XOSC)

The main crystal oscillator features are: • 16MHz amplitude controlled crystal oscillator • 180 s typical settling time after leaving SLEEP state - Configurable trimming capacitance array - Configurable clock output (CLKM)

9.6.1 Overview

The crystal oscillator generates the reference frequency for the Atmel AT86RF232. All other internally generated frequencies of the radio transceiver are derived from this unique frequency. Therefore, the overall system performance is mainly determined by the accuracy of crystal reference frequency. The external components of the crystal oscillator should be selected carefully and the related board layout should be done with caution (see Chapter 5). The register 0x12 (XOSC\_CTRL) provides access to the control signals of the oscillator. Two operating modes are supported. It is recommended to use the integrated oscillator setup as described in Figure 9-11; nevertheless a reference frequency can be fed to the internal circuitry by using an external clock reference as shown in Figure 9-12.

9.6.2 Integrated Oscillator Setup

Using the internal oscillator, the oscillation frequency depends on the load capacitance between the crystal pin 26 (XTAL1) and pin 25 (XTAL2). The total load capacitance C_L must be equal to the specified load capacitance of the crystal itself. It consists of the external capacitors CX and parasitic capacitances connected to the XTAL nodes. Figure 9-11 shows all parasitic capacitances, such as PCB stray capacitances and the pin input capacitance, summarized to C_PAR . Figure 9-11. Simplified XOSC Schematic with External Components. 

VDD EVDD XTAL1 16MHz XTAL2 PCB AT86RF232 CTRIM XTAL_TRIM[3:0] XTAL_TRIM[3:0] CTRIM EVDD

Additional internal trimming capacitors C_TRIM are available. Any value in the range from 0pF to 4.5pF with a 0.3pF resolution is selectable using XTAL\_TRIM of register 0x12 (XOSC\_CTRL). To calculate the total load capacitance, the following formula can be used $$ C _ {L} [ p F ] = 0. 5 \times (C X + C _ {T R I M} + C _ {P A R}). $$ The Atmel AT86RF232 trimming capacitors provide the possibility of reducing frequency deviations caused by production process variations or by external components tolerances. Note that the oscillation frequency can only be reduced by increasing the trimming capacitance. The frequency deviation caused by one step of C_TRIM decreases with increasing crystal load capacitor values. An amplitude control circuit is included to ensure stable operation under different operating conditions and for different crystal types. Enabling the crystal oscillator in P\_ON state and after leaving SLEEP state causes a slightly higher current during the amplitude build-up phase to guarantee a short start-up time. At stable operation, the current is reduced to the amount necessary for a robust operation. This also keeps the drive level of the crystal low. Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects caused by external component variations or by variations of board and circuit parasitic. On the other hand, a larger crystal load capacitance results in a longer start-up time and a higher steady state current consumption.

9.6.3 External Reference Frequency Setup

When using an external reference frequency, the signal must be connected to pin 26 (XTAL1) as indicated in Figure 9-12 and the register bits XTAL\_MODE (register 0x12, XOSC\_CTRL) need to be set to the external oscillator mode for power saving reasons. The oscillation peak-to-peak amplitude shall be between 100mV and 500mV, the optimum range is between 400mV and 500mV. Pin 25 (XTAL2) should not be wired. It is possible, among other waveforms, to use sine and square wave signals. Note: 1. The quality of the external reference (that is phase noise) determines the system performance. Figure 9-12. Setup for Using an External Frequency Reference. 

16MHz XTAL1 XTAL2 PCB AT86RF232

9.6.4 Master Clock Signal Output (CLKM)

The generated reference clock signal can be fed to a microcontroller using pin 17 (CLKM). The internal 16MHz raw clock can be divided by an internal prescaler. Thus, clock frequencies of 1MHz or 62.5kHz can be supplied by pin 17 (CLKM). The CLKM frequency is configurable using register 0x03 (TRX\_CTRL\_0). There are two possibilities to change the CLKM frequency. If CLKM\_SHA\_SEL = 0, changing the register bits CLKM\_CTRL (register 0x03, TRX\_CTRL\_0) immediately affects a glitch free CLKM clock rate change. Otherwise (CLKM\_SHA\_SEL = 1) the new clock rate is supplied when leaving the SLEEP state the next time. To reduce power consumption and spurious emissions, it is recommended to turn off the Atmel AT86RF232 CLKM clock when not in use. Note: 1. During reset procedure, see Section 7.1.2.7, register bits CLKM\_CTRL are shadowed. Although the clock setting of CLKM remains after reset, a read access to register bits CLKM\_CTRL delivers the reset value one. For that reason it is recommended to write the previous configuratic (before reset) to register bits CLKM\_CTRL to align the radio transceiver behavior and register configuration. Otherwise the CLKM clock rate set back to the reset value (1MHz) after the next SLEEP cycle.

9.6.5 Register Description

Register 0x03 (TRX\_CTRL\_0):

The TRX\_CTRL\_0 register controls the CLKM clock rate. Figure 9-13. Register TRX\_CTRL\_0. 

- Bit 3 - CLKM\_SHA\_SEL

The register bit CLKM\_SHA\_SEL defines if a new clock rate, defined by CLKM\_CTRL, is set immediately or after the next SLEEP cycle. Table 9-12. CLKM SHA SEL.

Register Bits	Value	Description
CLKM_SHA_SEL	0	CLKM clock rate change appears immediately
	1	CLKM clock rate change appears after SLEEP cycle

- Bit 2:0 - CLKM\_CTRL

The register bits CLKM\_CTRL sets the clock rate of pin 17 (CLKM). Table 9-13. CLKM CTRL.

Register Bits	Value	Description
CLKM_CTRL	0	No clock at pin CLKM, pin set to logic low
	1	1MHz
	7	62.5kHz (IEEE 802.15.4 symbol rate)
		All other values are reserved

Register 0x12 (XOSC\_CTRL):

The XOSC\_CTRL register controls the operation of the crystal oscillator. Figure 9-14. Register XOSC\_CTRL. 

- Bit 7:4 - XTAL\_MODE

The register bits XTAL\_MODE sets the operating mode of the crystal oscillator. Table 9-14. XTAL\_MODE.

Register Bits	Value	Description
XTAL_MODE	0x5	Internal crystal oscillator disabled, use external reference frequency
	0xF	Internal crystal oscillator enabled and XOSC voltage regulator enabled
		All other values are reserved

For normal operation the default value is set to XTAL\_MODE = 0xF after reset. Using an external clock source it is recommended to set XTAL\_MODE = 0x5.

- Bit 3:0 - XTAL\_TRIM

The register bits XTAL\_TRIM controls internal capacitance arrays connected to pin 26 (XTAL1) and pin 25 (XTAL2). Table 9-15. XTAL\_TRIM.

Register Bits	Value	Description
XTAL_TRIM	0x0	A capacitance value in the range from 0pF to 4.5pF is selectable with a resolution of 0.3pF. Valid values are [0xF, 0xE, ..., 0x0].

9.7 Frequency Synthesizer (PLL)

The main PLL features are: - Generate RX/TX frequencies for all IEEE 802.15.4 – 2.4GHz channels - Autonomous calibration loops for stable operation within the operating range - Two PLL-interrupts for status indication - Fast PLL settling to support frequency hopping

9.7.1 Overview

The PLL generates the RF frequencies for the Atmel AT86RF232. During receive operation the frequency synthesizer works as a local oscillator on the radio transceiver receive frequency, during transmit operation the voltage-controlled oscillator (VCO) is directly modulated to generate the RF transmit signal. The frequency synthesizer is implemented as a fractional-N PLL. Two calibration loops ensure correct PLL functionality within the specified operating limits.

9.7.2 RF Channel Selection

The PLL is designed to support 16 channels in the 2.4GHz ISM band with channel spacing of 5MHz according to IEEE 802.15.4. The center frequency of these channels is defined as follows: $$ \mathrm{Fc} [ \mathrm{MHz} ] = 2 4 0 5 + 5 \times (k - 1 1), \text { for } k = 1 1, 1 2, \dots , 2 6 $$ where k is the channel number. The channel k is selected by register bits CHANNEL (register 0x08, PHY\_CC\_CA).

9.7.3 Frequency Agility

When the PLL is enabled during state transition from TRX\_OFF to PLL\_ON, the settling time is typically t_TR4 = 80 s , including settling of the analog voltage regulator (AVREG) and PLL self calibration, refer to Table 7-2 and Figure 13-12. A lock of the PLL is indicated with an interrupt IRQ\_0 (PLL\_LOCK). Switching between 2.4GHz ISM band channels in PLL\_ON or RX\_ON states is typically done within t_PLL\_SW = 11 s . This makes the radio transceiver highly suitable for frequency hopping applications. When starting the transmit procedure the PLL frequency is changed to the transmit frequency within a period of _RX\_TX = 16 s before starting the transmission. After the transmission the PLL settles back to the receive frequency within a period of t_TX\_RX = 32 s . This frequency step does not generate an interrupt IRQ\_0 (PLL\_LOCK) or IRQ\_1 (PLL\_UNLOCK) within these periods.

9.7.4 Calibration Loops

Due to variation of temperature, supply voltage and part-to-part variations of the radio transceiver the VCO characteristics may vary. To ensure a stable operation, two automated control loops are implemented, center frequency (CF) tuning and delay cell (DCU) calibration. Both calibration loops are initiated automatically when the PLL is enabled during state transition from TRX\_OFF to PLL\_ON state. Additionally, center frequency calibration is initiated when the PLL changes to a different channel center frequency. If the Atmel AT86RF232 PLL operates for a long time on the same channel, for example more than five minutes, or the operating temperature changes significantly, it is recommended to initiate the calibration loops manually. Both calibration loops can be initiated manually by setting PLL\_CF\_START = 1 (register 0x1A, PLL\_CF) and register bit PLL\_DCU\_START = 1 (register 0x1B, PLL\_DCU). To start the calibration the device must be in PLL\_ON or RX\_ON state. The completion of the center frequency tuning is indicated by a PLL\_LOCK interrupt. Both calibration loops may be run simultaneously.

9.7.5 Interrupt Handling

Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ\_0 (PLL\_LOCK) indicates that the PLL has locked. IRQ\_1 (PLL\_UNLOCK) interrupt indicates an unexpected unlock condition. A PLL\_LOCK interrupt clears any preceding PLL\_UNLOCK interrupt automatically and vice versa. An IRQ\_0 (PLL\_LOCK) interrupt is supposed to occur in the following situations: - State change from TRX\_OFF to PLL\_ON / RX\_ON / TX\_ARET\_ON / RX\_AACK\_ON - Channel change in states PLL\_ON / RX\_ON / TX\_ARET\_ON / RX\_AACK\_ON Any other occurrences of PLL interrupts indicate erroneous behavior and require checking of the actual device status. The state transition from BUSY\_TX to PLL\_ON after successful transmission does not generate an IRQ\_0 (PLL\_LOCK) within the settling period.

9.7.6 Register Description

Register 0x08 (PHY\_CC\_CCA):

The PHY\_CC\_CCA register is a multi-purpose register that controls CCA configuration, CCA measurement, and the IEEE 802.15.4 channel setting. Figure 9-15. Register PHY\_CC\_CCA. 

- Bit 4:0 – CHANNEL

The register bits CHANNEL define the RX/TX channel. The channel assignment is according to IEEE 802.15.4. Table 9-16. Channel Assignment for IEEE 802.15.4 – 2.4GHz Band.

Register Bits	Value	IEEE 802.15.4 Channel Number k	Center Frequency [MHz]
CHANNEL	0x0B	11	2405
	0x0C	12	2410
	0x0D	13	2415
	0x0E	14	2420
	0x0F	15	2425
	0x10	16	2430
	0x11	17	2435
	0x12	18	2440
	0x13	19	2445
	0x14	20	2450
	0x15	21	2455
	0x16	22	2460
	0x17	23	2465
	0x18	24	2470
	0x19	25	2475
	0x1A	26	2480
		All other values are reserved

Register 0x1A (PLL\_CF):

The PLL\_CF register controls the operation of the center frequency calibration loop. Figure 9-16. Register PLL\_CF. 

- Bit 7 - PLL\_CF\_START

Manual start of center frequency calibration cycle. Table 9-17. PLL\_CF\_START.

Register Bits	Value	Description
PLL_CF_START	0	Center frequency calibration cycle is finished
	1	Initiates center frequency calibration cycle

PLL\_CF\_START = 1 initiates the center frequency calibration. The calibration cycle has finished after t_PLL\_CF = 8 s (typ.). The register bit is cleared immediately after finishing the calibration.

- Bit 3:0 - PLL\_CF

VCO center frequency control word. Table 9-18. PLL\_CF.

Register Bits	Value	Description
PLL_CF	0x7	Initial CF start wordValid values are [0xF, 0xE, ..., 0x0]

Register 0x1B (PLL\_DCU):

The PLL\_DCU register controls the operation of the delay cell calibration loop. Figure 9-17. Register PLL\_DCU.

Bit	7	6	5	4
0x1B	PLL_DCU_STAR'	reserved
Read/Write	R/W	R	R/W	R/W
Reset value	0	0	1	0
Bit	3	2	1	0
0x1B	reserved
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0

- Bit 7 - PLL\_DCU\_START

Manual start of delay cell calibration cycle. Table 9-19. PLL\_DCU\_START.

Register Bits	Value	Description
PLL_DCU_START	0	Delay cell calibration cycle is finished
	1	Initiates delay cell calibration cycle

PLL\_DCU\_START = 1 initiates the delay cell calibration. The calibration cycle has finished after p_PLL\_DCU = 6 s . The register bit is cleared immediately after finishing the calibration.

9.8 Automatic Filter Tuning (FTN)

9.8.1 Overview

The Atmel AT86RF232 FTN is incorporated to compensate device tolerances for temperature, supply voltage variations as well as part-to-part variations of the radio transceiver. The filter-tuning result is used to correct the analog baseband filter transfer function and the PLL loop-filter time constant, refer to Chapter 4. An FTN calibration cycle is initiated automatically when entering the TRX\_OFF state from the P\_ON, SLEEP, or RESET state. Although receiver and transmitter are very robust against these variations, it is recommended to initiate the FTN manually if the radio transceiver does not use the SLEEP state. If necessary, a calibration cycle is to be initiated in states TRX\_OFF, PLL\_ON or RX\_ON. The recommended calibration interval is five minutes or less.

9.8.2 Register Description

Register 0x18 (FTN\_CTRL):

The FTN\_CTRL register controls the operation of the filter tuning network calibration loop. Figure 9-18. Register FTN\_CTRL. 

- Bit 7 - FTN\_START

Manual start of a filter calibration cycle. Table 9-20. FTN\_START.

Register Bits	Value	Description
FTN_START	0	Filter calibration is finished
	1	Initiates filter calibration cycle

FTN\_START = 1 initiates the filter tuning network calibration. When the calibration cycle has finished after t_FTN = 25 s (typ.). The register bit is cleared immediately after finishing the calibration.

10 Radio Transceiver Usage

This section describes basic procedures to receive and transmit frames using the Atmel AT86RF232. For a detailed programming description refer to reference [6].

10.1 Frame Receive Procedure

A frame reception comprises of two actions: The PHY listens for, receives and demodulates the frame to the Frame Buffer and signalizes the reception to the microcontroller. After or while that the microcontroller read the available frame data from the Frame Buffer via the SPI interface. While in state RX\_ON or RX\_AACK\_ON the radio transceiver searches for incoming frames on the selected channel. Assuming the appropriate interrupts are enabled, a detection of an IEEE 802.15.4 compliant frame is indicated by interrupt IRQ\_2 (RX\_START) first. The frame reception is completed when issuing interrupt IRQ\_3 (TRX\_END). Different Frame Buffer read access scenarios are recommended for: - Non-time critical applications read access starts after IRQ\_3 (TRX\_END) - Time-critical applications read access starts after IRQ\_2 (RX\_START) Waiting for IRQ\_3 (TRX\_END) interrupt before starting a Frame Buffer read access is recommended for operations considered to be none time critical. Figure 10-1 illustrates the frame receive procedure using IRQ\_3 (TRX\_END). Figure 10-1. Transactions between AT86RF232 and Microcontroller during Receive. 

graph TD
    A["AT86RF232"] --> B["IRQ issued (IRQ_2)"]
    B --> C["Read IRQ status, pin 24 (IRQ) deasserted"]
    C --> D["IRQ issued (IRQ_3)"]
    D --> E["Read IRQ status, pin 24 (IRQ) deasserted"]
    E --> F["Read frame data (Frame Buffer access)"]
    style A fill:#f9f,stroke:#333
    style B fill:#ccf,stroke:#333
    style C fill:#cfc,stroke:#333
    style D fill:#fcc,stroke:#333
    style E fill:#cff,stroke:#333
    style F fill:#ffc,stroke:#333

Critical protocol timing could require starting the Frame Buffer read access after interrupt IRQ\_2 (RX\_START). The first byte of the frame data can be read 32 s after the IRQ\_2 (RX\_START) interrupt. The microcontroller must ensure to read slower than the frame is received. Otherwise a Frame Buffer under run occurs, IRQ\_6 (TRX\_UR) is issued, and the frame data may be not valid. To avoid this, the Frame Buffer read access can be controlled by using a Frame Buffer Empty indicator, refer to Section 11.5.

10.2 Frame Transmit Procedure

A frame transmission comprises of two actions, a Frame Buffer write access and the transmission of the Frame Buffer content. Both actions can be run in parallel if required by critical protocol timing. Figure 10-2 illustrates the Atmel AT86RF232 frame transmit procedure, when writing and transmitting the frame consecutively. After a Frame Buffer write access, the frame transmission is initiated by asserting pin 11 (SLP\_TR) or writing command TX\_START to register bits TRX\_CMD (register 0x02, TRX\_STATE), while the radio transceiver is in state PLL\_ON or TX\_ARET\_ON. The completion of the transaction is indicated by interrupt IRQ\_3 (TRX\_END). Figure 10-2. Transaction between AT86RF232 and Microcontroller during Transmit. 

graph TD
    A["AT86RF232"] --> B["Write frame data (Frame Buffer access)"]
    B --> C["Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)"]
    C --> D["IRQ_3 (TRX_END) issued"]
    D --> E["Read IRQ_STATUS register, pin 24 (IRQ) deasserted"]
    E --> F["Microcontroller"]

Alternatively, a frame transmission can be started first, followed by the Frame Buffer write access (PSDU data); refer to Figure 10-3. This is applicable for time critical applications. Initiating a transmission, either by asserting pin 11 (SLP\_TR) or command TX\_START to register bits TRX\_CMD (register 0x02, TRX\_STATE), the radio transceiver starts transmitting the SHR, which is internally generated. This first phase requires 16 s for PLL settling and 160 s for SHR transmission. The PHR must be available in the Frame Buffer before this time elapses. Furthermore the SPI data rate must be higher than the PHY data rate to ensure that no Frame Buffer under run occurs. Figure 10-3. Time Optimized Frame Transmit Procedure. 

graph TD
    A["Write TRX_CMD = TX_START, or assert pin 11 (SLP_TR)"] --> B["Write frame data (Frame Buffer access)"]
    B --> C["IRQ_3 (TRX_END) issued"]
    C --> D["Read IRQ_STATUS register, pin 24 (IRQ) deasserted"]
    D --> E["Microcontroller"]

11 AT86RF232 Extended Feature Set

11.1 Security Module (AES)

The security module (AES) is characterized by: - Hardware accelerated encryption and decryption - Compatible with AES-128 standard (128-bit key and data block size) - ECB (encryption/decryption) mode and CBC (encryption) mode support - Stand-alone operation, independent of other blocks

11.1.1 Overview

The security module is based on an AES-128 core according to FIPS197 standard, refer to [5]. The security module works independent of other building blocks of the Atmel AT86RF232, encryption and decryption can be performed in parallel to a frame transmission or reception. Controlling the security block is implemented as an SRAM access to address space 0x82 to 0x94. A Fast SRAM access mode allows simultaneously writing new data and reading data from previously processed data within the same SPI transfer. This access procedure is used to reduce the turnaround time for ECB and CBC modes, see Section 11.1.5. In addition, the security module contains another 128-bit register to store the initial key used for security operations. This initial key is not modified by the security module.

11.1.2 Security Module Preparation

The use of the security module requires a configuration of the security engine before starting a security operation. The following steps are required: Table 11-1. AES Engine Configuration Steps.

Step	Description	Description	Section
1	Key Setup	Write encryption or decryption key to SRAM	11.1.3
2	AES mode	Select AES mode: ECB or CBCSelect encryption or decryption	11.1.4.111.1.4.2
3	Write Data	Write plaintext or cipher text to SRAM	11.1.5
4	Start operation	Start AES operation
5	Read Data	Read cipher text or plaintext from SRAM	11.1.5

Before starting any security operation a key must be written to the security engine, refer to Section 11.1.3. The key set up requires the configuration of the AES engine KEY mode using register bits AES\_MODE (SRAM address 0x83, AES\_CTRL). The following step selects the AES mode, either electronic code book (ECB) or cipher block chaining (CBC). These modes are explained more in detail in Section 11.1.4. Further, encryption or decryption must be selected with register bit AES\_DIR (SRAM address 0x83, AES\_CTRL). As next the 128-bit plain text or ciphertext data has to be provided to the AES hardware engine. The data uses the SRAM address range 0x84 - 0x93. The encryption or decryption is initiated with register bit AES\_REQUEST = 1 (SRAM address 0x83, AES\_CTRL or the mirrored version with SRAM address 0x94, AES\_CTRL\_MIRROR). The AES module control registers are only accessible using SRAM read and write accesses on address space 0x82 to 0x94. A configuration of the AES mode, providing the data and the start of the operation can be combined within one SRAM access. Notes: 1. No additional register access is required to operate the security block. 2. Access to the security block is not possible while the radio transceiver is in SLEEP, or RESET state. 3. All configurations of the security module, the SRAM content and keys are reset during RESET state.

11.1.3 Security Key Setup

The setup of the key is prepared by setting register bits AES\_MODE = 1 (SRAM address 0x83, AES\_CTRL). Afterwards the 128-bit key must be written to SRAM addresses 0x84 through 0x93 (registers AES\_KEY). It is recommended to combine the setting of control register 0x83 (AES\_CTRL) and the 128-bit key transfer using only one SRAM access starting from address 0x83. The address space for the 128-bit key and 128-bit data is identical from programming point of view. However, both use different pages which are selected by register bit AES\_MODE before storing the data. A read access to registers AES\_KEY (0x84 - 0x93) returns the last round key of the preceding security operation. After an ECB encryption operation, this is the key that is required for the corresponding ECB decryption operation. However, the initial AES key, written to the security module in advance of an AES run, see step one in Table 11-1, is not modified during an AES operation. This initial key is used for the next AES run even it cannot be read from AES\_KEY. Note: 1. ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The Atmel AT86RF232 provides this functionality as an additional feature.

11.1.4 Security Operation Modes

11.1.4.1 Electronic Code Book (ECB)

ECB is the basic operating mode of the security module. After setting up the initial AES key, register bits AES\_MODE = 0 (SRAM address 0x83, AES\_CTRL) sets up ECB mode. Register bit AES\_DIR (SRAM address 0x83, AES\_CTRL) selects the direction, either encryption or decryption. The data to be processed has to be written to SRAM addresses 0x84 through 0x93 (registers AES\_STATE). An example for a programming sequence is shown in Figure 11-1. This example assumes a suitable key has been loaded before. A security operation can be started within one SRAM access by appending the start command AES\_REQUEST = 1 (register 0x94, AES\_CTRL\_MIRROR) to the SPI sequence. Register AES\_CTRL\_MIRROR is a mirrored version of register 0x83 (AES\_CTRL). Figure 11-1. ECB Programming SPI Sequence – Encryption. 

byte 0 (cmd.) byte 1 (address) byte 3 byte 18 byte 19 (AES cmd)byte 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 data_007609 0 0 .... 1 0 0 0 0 0 0 0 data_15[7:0] SRAM write □ 0x83 □ ECB, encryption □ AES start □

Summarizing, the following steps are required to perform a security operation using only one Atmel AT86RF232 SPI access: 1. Configure SPI access a) SRAM write, refer to Section 6.2.3 2. Configure AES operation b) Start address 0x83 3. Write 128-bit data block address 0x83: select ECB mode, direction 4. Start AES operation addresses 0x84 - 0x93: either plain or ciphertext address 0x94: start AES operation, ECB mode This sequence is recommended because the security operation is configured and started within one SPI transaction. The ECB encryption operation is illustrated in Figure 11-2. Figure 11-3 shows the ECB decryption mode, which is supported in a similar way. Figure 11-2. ECB Mode – Encryption. 

graph TD
    A["Plaintext"] --> B["Block Cipher Encryption"]
    C["Encryption Key"] --> B
    B --> D["Ciphertext"]
    E["Plaintext"] --> F["Block Cipher Encryption"]
    G["Encryption Key"] --> F
    F --> H["Ciphertext"]

Figure 11-3. ECB Mode – Decryption. 

graph TD
    A["Ciphertext"] --> B["Block Cipher Decryption"]
    B --> C["Plaintext"]
    D["Ciphertext"] --> E["Block Cipher Decryption"]
    E --> F["Plaintext"]
    B -->|Decryption Key| G
    E -->|Decryption Key| H

When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same as the one used for encryption, but rather the last round key instead. This last round key is the content of the key address space stored after running one full encryption cycle, and must be saved for decryption. If the decryption key has not been saved, it has to be recomputed by first running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then fetching the resulting round key from the key memory, and writing it back into the key memory as the decryption key. ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of these standards do not directly encrypt the payload, but rather a nonce instead, and protect the payload by applying an XOR operation between the resulting (AES-) cipher text and the original payload. As the nonce is the same for encryption and decryption only ECB encryption is required. Decryption is performed by XORing the received cipher text with its own encryption result respectively, which results in the original plaintext payload upon success.

11.1.4.2 Cipher Block Chaining (CBC)

In CBC mode, the result of a previous AES operation is XORed with the new incoming vector, forming the new plaintext to encrypt, see Figure 11-4. This mode is used for the computation of a cryptographic checksum (message integrity code, MIC). Figure 11-4. CBC Mode – Encryption. 

graph TD
    A["Plaintext Initialization Vector (IV)"] --> B["Block Cipher Encryption"]
    B --> C["Ciphertext"]
    D["Plaintext"] --> E["Block Cipher Encryption"]
    E --> F["Ciphertext"]
    B -->|Encryption Key| G["ECB mode"]
    E -->|Encryption Key| H["CBC mode"]

After preparing the AES key and defining the AES operation direction using Atmel AT86RF232 SRAM register bit AES\_DIR, the data has to be provided to the AES engine and the CBC operation can be started. The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with an initialization vector provided by the microcontroller). All succeeding AES runs are to be configured as CBC by setting register bits AES\_MODE = 2 (register 0x83, AES\_CTRL). Register bit AES\_DIR (register 0x83, AES\_CTRL) must be set to AES\_DIR = 0 to enable AES encryption. The data to be processed has to be transferred to the SRAM starting with address 0x84 to 0x93 (register AES\_STATE). Setting register bit AES\_REQUEST = 1 (register 0x94, AES\_CTRL\_MIRROR) as described in Section 11.1.4 starts the first encryption within one SRAM access. This causes the next 128 bits of plaintext data to be XORed with the previous cipher text data, see Figure 11-4. According to IEEE 802.15.4 the input for the very first CBC operation has to be prepared by a XORing a plaintext with an initialization vector (IV). The value of the initialization vector is zero. However, for non-compliant usage any other initialization vector can be used. This operation has to be prepared by the microcontroller. Note: 1. The IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode encryption only, as it implements a one-way hash function.

11.1.5 Data Transfer – Fast SRAM Access

The ECB and CBC modules including the AES core are clocked with 16MHz. One AES operation takes t_AES = 23.4 s to execute, refer to Table 7-2. That means that the processing of the data is usually faster than the transfer of the data via the SPI interface. To reduce the overall processing time the Atmel AT86RF232 provides a Fast SRAM access for the address space 0x82 to 0x94. Figure 11-5. Packet Structure – Fast SRAM Access Mode. 

graph TD
    subgraph_AES_run_0["AES run #0"]
        direction LR
        A["cmd add cfg P0 P1 ... P14 P15 start"] --> B["stat xx xx xx xx ... xx xx xx"]
    end
    subgraph_AES_run_n["AES run #n"]
        direction LR
        C["cmd add cfg P0 P1 ... P14 P15 start"] --> D["stat xx xx xx C0 ... C13 C14 C15"]
    end
    E["byte 0 (cmd) byte 1 (addr.) byte 2 (cfg) byte 3 byte byte 18 byte 19 (start)"] --> F["SRAM write MOS Address 0x83 <AES_CTRL> P0[7:0"] P1["7:0"] ... P15["7:0"] <AES_CTRL^(1)]
    G["PHY_STATUS MISO XX XX C0[7:0"] ... C14["7:0"] C15["7:0"]] --> H["Address 0x83 0x84 0x85 0x93 0x94"]
    I["Address"] --> J["..."]
    style AES_run_0 fill:#f9f,stroke:#333
    style AES_run_n fill:#f9f,stroke:#333

Note: 1. Byte 19 is the mirrored version of register AES\_CTRL on SRAM address 0x94, see register description AES\_CTRL\_MIRROR for details. In contrast to a standard SRAM access, refer to Section 6.2.3, the Fast SRAM access allows writing and reading of data simultaneously during one SPI access for consecutive AES operations (AES run). For each byte P0 transferred to pin 22 (MOSI) for example in "AES access #1", see Figure 11-5 (lower part), the previous content of the respective AES register C0 is clocked out at pin 20 (MISO) with an offset of one byte. In the example shown in Figure 11-5 the initial plaintext P0 – P15 is written to the SRAM within “AES access #0”. The last command on address 0x94 (AES\_CTRL\_MIRROR) starts the AES operation (“AES run #0”). In the next “AES access #1” new plaintext data P0 – P15 is written to the SRAM for the second AES run, in parallel the ciphertext C0 – C15 from the first AES run is clocked out at pin MISO. To read the ciphertext from the last “AES run #(n)” one dummy “AES access #(n+1)” is needed. Note: 2. The SRAM write access always overwrites the previous processing result. The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94.

11.1.6 Start of Security Operation and Status

A security operation is started within one Atmel AT86RF232 SRAM access by appending the start command AES\_REQUEST = 1 (register 0x94, AES\_CTRL\_MIRROR) to the SPI sequence. Register AES\_CTRL\_MIRROR is a mirrored version of register 0x83 (AES\_CTRL). The status of the security processing is indicated by register 0x82 (AES\_STATUS). After t_AES = 24 s (max.) AES processing time register bit AES\_DONE changes to 1 (register 0x82, AES\_STATUS) indicating that the security operation has finished.

11.1.7 SRAM Register Summary

The following registers are required to control the security module: Table 11-2. SRAM Security Module Address Space Overview.

SRAM-Addr.	Register Name	Description
0x82	AES_STATUS	AES status
0x83	AES_CTRL	Security module control, AES mode
0x84 – 0x93	AES_KEYAES_STATE	Depends on AES_MODE setting:AES_MODE = 1:- Contains AES_KEY (key)AES_MODE = 0 | 2:- Contains AES_STATE (128 bit data block)
0x94	AES_CTRL_MIRROR	Mirror of register 0x83 (AES_CTRL)

These registers are only accessible using SRAM write and read accesses, for details refer to Section 6.2.3.

11.1.8 AES SRAM Configuration Register

Register 0x82 (AES\_STATUS):

The read-only register AES\_STATUS signals the status of the security module and operation. Figure 11-6. Register AES\_STATUS. 

- Bit 7 - AES\_ER

This SRAM register bit indicates an error of the AES module. An error may occur for instance after an access to SRAM register 0x83 (AES\_CTRL) while an AES operation is running or after reading less than 128-bits from SRAM register space 0x84 - 0x93 (AES\_STATE). Table 11-3. AES\_ER.

Register Bits	Value	Description
AES_ER	0	No error of the AES module
	1	AES module error

- Bit 0 - AES\_DONE

The bit AES\_DONE signals the status of AES operation. Table 11-4. AES\_DONE.

Register Bits	Value	Description
AES_DONE	0	AES module is not finished
	1	AES module has finished

Register 0x83 (AES\_CTRL):

The AES\_CTRL register controls the operation of the security module. Figure 11-7. Register AES\_CTRL.

Bit	7	6	5	4
0x83	AES_REQUEST		AES_MODE		AES_CTRL
Read/Write	W	R/W	R/W	R/W
Reset value	0	0	0	0
Bit	3	2	1	0
0x83	AES_DIR		reserved		AES_CTRL
Read/Write	R/W	R	R	R
Reset value	0	0	0	0

Notes: 1. Do not access this register during AES operation to read the AES core status. A read or write access during AES operation stops the actual processing. 2. To read the AES status use register bit AES\_DONE (register 0x82, AES\_STATUS).

- Bit 7 - AES\_REQUEST

A write access with AES\_REQUEST = 1 initiates the AES operation. Table 11-5. AES\_REQUEST.

Register Bits	Value	Description
AES_REQUEST	0	Security module, AES core idle
	1	A write access starts the AES operation

- Bit 6:4 - AES\_MODE

This register bit sets the AES operation mode. Table 11-6. AES\_MODE.

Register Bits	Value	Description
AES_MODE	0	ECB mode
	1	KEY mode
	2	CBC mode
		All other values are reserved

- Bit 3 - AES\_DIR

The register bit AES\_DIR sets the AES operation direction, either encryption or decryption. Table 11-7. AES\_DIR.

Register Bits	Value	Description
AES_DIR	0	AES encryption (ECB, CBC)
	1	AES decryption (ECB)

Register 0x94 (AES\_CTRL\_MIRROR):

Register 0x94 is a mirrored version of register 0x83 (AES\_CTRL), for details refer to register 0x83 (AES\_CTRL). This register could be used to start a security operation within a single SRAM access by appending it to the data stream and setting register bit AES\_REQUEST = 1.

11.2 Random Number Generator

11.2.1 Overview

The Atmel AT86RF232 incorporates a two bit truly random number generator by observation of noise. This random number can be used to: - Generate random seeds for CSMA-CA algorithm see Section 7.2 - Generate random values for AES key generation see Section 11.1 The random number is updated every t_RND = 1 s in Basic Operation Mode receive states. The values are stored in register bits RND\_VALUE (register 0x06, PHY\_RSSI).

11.2.2 Register Description

Register 0x06 (PHY\_RSSI):

The PHY\_RSSI register is a multi-purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. Figure 11-8. Register PHY\_RSSI. 

- Bit 6:5 - RND\_VALUE

The 2-bit random value can be retrieved by reading register bits RND\_VALUE. Table 11-8. RND VALUE.

Register Bits	Value	Description
RND_VALUE	3	Deliver two bit noise value within receive state. Valid values are [3, 2, ..., 0].

Note: 1. The radio transceiver shall be in Basic Operating Mode receive state.

11.3 Antenna Diversity

The Antenna Diversity implementation is characterized by: - Improves signal path robustness between nodes - Atmel AT86RF232 self-contained antenna diversity algorithm - Direct register based antenna selection

11.3.1 Overview

Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small changes of the antenna location. These fading effects can result in an increased error floor or loss of the connection between devices. To improve the reliability of an RF connection between network nodes Antenna Diversity can be applied to reduce effects of multipath propagation and fading. Antenna Diversity uses two antennas to select the most reliable RF signal path. To ensure highly independent receive signals on both antennas, the antennas should be carefully separated from each other. If a valid IEEE 802.15.4 frame is detected on one antenna, this antenna is selected for reception. Otherwise the search is continued on the other antenna and vice versa. Antenna Diversity can be used in Basic and Extended Operating Modes and can also be combined with other features and operating modes.

11.3.2 Antenna Diversity Application Example

A block diagram for an application using an antenna switch is shown in Figure 11-9. Figure 11-9. Antenna Diversity – Block Diagram. 

graph TD
    ANT0["Ant0"] --> RF_Switch["RF-Switch"]
    RF_Switch --> Balun["Balun"]
    Balun --> AVSS1["AVSS"]
    Balun --> AVSS2["AVSS"]
    Balun --> AVSS3["AVSS"]
    Balun --> RFP["RFP"]
    Balun --> RFN["RFN"]
    Balun --> AVSS4["AVSS"]
    AVSS1 --> AT86RF232["AT86RF232"]
    AVSS2 --> AT86RF232
    AVSS3 --> AT86RF232
    AVSS4 --> AT86RF232
    AVSS5["AVSS"] --> AT86RF232
    AVSS6["AVSS"] --> AT86RF232
    AVSS7["AVSS"] --> AT86RF232
    AVSS8["AVSS"] --> AT86RF232
    AVSS9["AVSS"] --> AT86RF232
    AVSS10["AVSS"] --> AT86RF232
    AT86RF232 --> DIG1["DIG1"]
    AT86RF232 --> DIG2["DIG2"]
    AT86RF232 --> ...[...]
    AT86RF232 --> 9["9"]
    AT86RF232 --> 10["10"]

Generally, if the antenna diversity used the control of an antenna diversity switch must be enabled by register bit ANT\_EXT\_SW\_EN (register 0x0D, ANT\_DIV). The internal connection to digital ground of the control pins pin 9 (DIG1) and pin 10 (DIG2) is disabled (refer to Section 1.3), and they feed the antenna switch signal and its inverse to the differential inputs of the RF Switch (SW1). If the Atmel AT86RF232 is not in a receive or transmit state, it is recommended to disable register bit ANT\_EXT\_SW\_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT\_EXT\_SW\_EN = 0, output pins DIG1/DIG2 are pulled-down to digital ground.

User Defined Antenna Selection

A microcontroller defined selection of a certain antenna can be done by disabling the automated Antenna Diversity algorithm (ANT\_DIV\_EN = 0) and selecting one antenna using register bits ANT\_CTRL = 1 / 2. The antenna defined by register bits ANT\_CTRL (register 0x0D, ANT\_DIV) is used for transmission and reception.

Autonomous Antenna Selection

The autonomous Antenna Diversity algorithm is enabled with register bits ANT\_DIV\_EN = 1 and ANT\_CTRL = 0 / 3 (register 0x0D, ANT\_DIV). It allows the use of Antenna Diversity even if the microcontroller does currently not control the radio transceiver, for instance in Extended Operating Mode. Upon reception of a frame the AT86RF232 selects one antenna. The selected antenna is then indicated by register bit ANT\_SEL (register 0x0D, ANT\_DIV). If required, it is recommended to read register bit ANT\_SEL after IRQ\_2 (RX\_START). After the frame reception is completed, the antenna selection continues searching for new frames on both antennas. However, the register bit ANT\_SEL maintains its previous value (from the last received frame) until a new IEEE 802.15.4 frame has been detected, and the selection algorithm locked into one antenna again. At this time the register bit ANT\_SEL is updated again. If a device is in RX\_AACK mode, receiving a frame containing an ACK request, the ACK frame is transmitted using the same antenna as used during receive. If a device performs a transaction in TX\_ARET mode, it starts to listen for an ACK on the transmit antenna. If no ACK was received, the next transmission attempt is done on the other transmit antenna. This will be repeated with each retry.

11.3.3 Antenna Diversity Sensitivity Control

Due to a different receive algorithm used by the Antenna Diversity algorithm, the correlator threshold of the receiver has to be adjusted. It is recommended to set register bits PDT\_THRES (register 0x0A, RX\_CTRL) to three.

11.3.4 Register Description

Register 0x0A (RX\_CTRL):

The RX\_CTRL register controls the sensitivity of the Antenna Diversity mode. Figure 11-10. Register RX\_CTRL. 

- Bit 3:0 - PDT\_THRES

The register bits PDT\_THRES controls the sensitivity of the receiver correlation unit. Table 11-9. PDT THRES.

Register Bits	Value	Description
PDT_THRES	0x3^(1)	Recommended correlator threshold for Antenna Diversity operation
	0x7	To be used if Antenna Diversity algorithm is disabled
		All other values are reserved

Note: 1. If the Antenna Diversity algorithm is enabled (ANT\_DIV\_EN = 1), the value shall be set to PDT\_THRES = 3, otherwise it shall be set back to the reset value. This is not automatically done by the hardware.

Register 0x0D (ANT\_DIV):

The ANT\_DIV register controls Antenna Diversity. Figure 11-11. Register ANT\_DIV. 

- Bit 7 - ANT\_SEL

Signals selected antenna, related to the last received frame. Table 11-10. ANT SEL.

Register Bits	Value	Description
ANT_SEL	0	Antenna 0
	1	Antenna 1

Note: 1. If the autonomous Antenna Diversity algorithm is enabled, the register bit ANT\_SEL maintains its previous value (from the last received frame) until a new SHR has been found. This register bit signals the currently selected antenna path. The selection may be based either on the last antenna diversity cycle (ANT\_DIV\_EN = 1) or on the content of register bits ANT\_CTRL, for details refer to Section 11.3.2.

- Bit 3 - ANT\_DIV\_EN

The register bit ANT\_DIV\_EN activates the autonomous Antenna Diversity algorithm. Table 11-11. ANT DIV EN.

Register Bits	Value	Description
ANT_DIV_EN	0	Antenna Diversity algorithm is disabled
	1	Antenna Diversity algorithm is enabled

Note: 1. If ANT\_DIV\_EN = 1 register bit ANT\_EXT\_SW\_EN shall be set to one, too. This is not automatically done by the hardware. If register bit ANT\_DIV\_EN is set the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm selects an antenna autonomously during SHR search. This selection is kept until: • A new SHR search starts • Leaving receive states - Register bits ANT\_CTRL are manually programmed

- Bit 2 - ANT\_EXT\_SW\_EN

The register bit ANT\_EXT\_SW\_EN controls the external antenna switch. Table 11-12. ANT EXT SW EN.

Register Bits	Value	Description
ANT_EXT_SW_EN	0	Antenna Diversity RF switch control is disabled
	1	Antenna Diversity RF switch control is enabled

If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential control signal for an Antenna Diversity switch. The selection of a specific antenna is done either by the automated Antenna Diversity algorithm (ANT\_DIV\_EN = 1), or according to register bits ANT\_CTRL if Antenna Diversity algorithm is disabled. If the Atmel AT86RF232 is not in a receive or transmit state, it is recommended to disable register bit ANT\_EXT\_SW\_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT\_EXT\_SW\_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital ground. Pin 10 (DIG2) is overloaded with RX and TX Frame Time Stamping, see Section 11.4, if IRQ\_2\_EXT\_EN is set.

- Bit 1:0 - ANT\_CTRL

These register bits provide a static control of an Antenna Diversity switch. Table 11-13. ANT\_CTRL.

Register Bits	Value	Description
ANT_CTRL	0	Mandatory setting for applications not using Antenna Diversity and if autonomous antenna selection is enabled
	1	Antenna 0DIG1 = LDIG2 = H
	2	Antenna 1DIG1 = HDIG2 = L
	3	Same behaviour as value zero

11.4 RX and TX Frame Time Stamping (TX\_ARET)

11.4.1 Overview

An exact timing of received and transmitted frames is signaled by Atmel AT86RF232 pin 10 (DIG2). A valid PHR reception or start of frame transmission is indicated by a DIG2 posedge. The pin remains high during frame reception or transmission. TX Frame Time Stamping is limited to TX\_ARET, whereas the RX Frame Time Stamping is available for all receive modes. Exemplary, Figure 11-12 illustrates a frame reception example. Figure 11-12. Timing of RX\_START and DIG2 for RX Frame Time Stamping.  Note: 1. Timing figures t_IRQ refer to Section 12.4. If pin 10 (DIG2) is not used for RX and/or TX Frame Time Stamping, or Antenna Diversity, it is pulled-down to digital ground.

11.4.2 Register Description

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 11-13. Register TRX\_CTRL\_1.

Bit 0x04	7	6	5	4	TRX_CTRL_1
	reserved	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL
Read/Write Reset value	R/W 0	R/W 0	R/W 1	R/W 0
Bit 0x04	3	2	1	0	TRX_CTRL_1
	SPI_CMD_MODE		IRQ_MASK_MODE	IRQ_POLARITY
Read/Write Reset value	R/W 0	R/W 0	R/W 1	R/W 0

- Bit 6 - IRQ\_2\_EXT\_EN

Controls external signaling for time stamping via pin 10 (DIG2). Table 11-14. IRQ 2 EXT EN.

Register Bits	Value	Description
IRQ_2_EXT_EN	0	Time stamping over pin 10 (DIG2) is disabled
	1^(1)	Time stamping over pin 10 (DIG2) is enabled

Notes: 1. The pin 10 (DIG2) is also active even if the corresponding interrupt event IRQ\_2 (RX\_START) mask bit in register 0x0E (IRQ\_MASK) is set to zero. 2. The pin remains at high level until the end of the frame receive or transmit procedure.

Register 0x17 (XAH\_CTRL\_1):

The XAH\_CTRL\_1 register is a multi-purpose control register for Extended Operating Mode. Figure 11-14. Register XAH\_CTRL\_1.

Bit	7	6	5	4
0x17	ARET_TX_TS_EI	reserved	AACK_FLTR_RES FT	AACK_UPLD_RES FT	XAH_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	0	0
Bit	3	2	1	0
0x17	reserved	AACK_ACK_TIME	AACK_PROM MODE	reserved	XAH_CTRL_1
Read/Write	R	R/W	R/W	R/W
Reset value	0	0	0	0

- Bit 7 - ARET\_TX\_TS\_EN

If register bit ARET\_TX\_TS\_EN = 1, then any frame transmission within TX\_ARET mode is signaled via pin 10 (DIG2). Table 11-15. ARET\_TX\_TS\_EN.

Register Bits	Value	Description
ARET_TX_TS_EN	0	TX_ARET time stamping via pin 10 (DIG2) is disabled
	1^(1)	TX_ARET time stamping via pin 10 (DIG2) is enabled

Note: 1. It is necessary to set register bit IRQ\_2\_EXT\_EN (register 0x04, TRX\_CTRL\_1).

11.5 Frame Buffer Empty Indicator

11.5.1 Overview

For time critical applications that want to start reading the frame data as early as possible, the Atmel AT86RF232 Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing. Pin 24 (IRQ) can be configured as a Frame Buffer Empty Indicator during a Frame Buffer read access. This mode is enabled by register bit RX\_BL\_CTRL (register 0x04, TRX\_CTRL\_1). The IRQ pin turns into Frame Buffer Empty Indicator after the Frame Buffer read access command, see note (1) in Figure 11-15, has been transferred on the SPI bus until the Frame Buffer read procedure has finished indicated by /SEL = H, see note (4). Figure 11-15. Timing Diagram of Frame Buffer Empty Indicator. 

/SEL SCLK MOSI Command XX Command XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX X MISO PHY_STATUS IRQ_STATUS TRX_STATUS PHR[7:0] PSDU[7:0] PSDU[7:0] PSDU[7:0] LQI[7:0] ED[7:0] RX_STATUS TRX_STATUS IRQ_STATUS IRQ IRQ_2 (RX_START) Frame Buffer Empty Indicator IRQ_3 (TRX_END) (1) (4)(3)Notes (2)

Notes: 1. Timing figure t_12 refer to Section 12.4. 2. A Frame Buffer read access can proceed as long as pin 24 (IRQ) = L. 3. Pin IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle. 4. The Frame Buffer read procedure has finished indicated by /SEL = H. The microcontroller has to observe the IRQ pin during the Frame Buffer read procedure. A Frame Buffer read access can proceed as long as pin 24 (IRQ) = L, see note (2). Pin IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle, note (3), and thus the Frame Buffer read procedure has to wait for valid data accordingly. The access indicator pin 24 (IRQ) shows a valid access signal (either access is allowed or denied) not before t_12 = 750ns after the rising edge of last SCLK clock of the Frame Buffer read command byte. After finishing the SPI frame receive procedure, and the SPI has been released by /SEL = H, note (4), pending interrupts are indicated immediately by pin 24 (IRQ). During all other SPI accesses, except during a SPI frame receive procedure with RX\_BL\_CTRL = 1, pin IRQ only indicates interrupts. If a receive error occurs during the Frame Buffer read access the Frame Buffer Empty Indicator locks on 'empty' (pin 24 (IRQ) = H), too. To prevent possible deadlocks, the microcontroller should impose a timeout counter that checks whether the Frame Buffer Empty Indicator remains logic high for more than 64 s. Presuming a PHY data rate of 250kb/s a new byte must have been arrived at the frame buffer during that period. If not, the Frame Buffer read access should be aborted.

11.5.2 Register Description

Register 0x04 (TRX\_CTRL\_1):

The TRX\_CTRL\_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. Figure 11-16. Register TRX\_CTRL\_1.

Bit	7	6	5	4
0x04	reserved	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0
Bit	3	2	1	0
0x04	SPI_CMD_MODE		IRQ_MASK_MOD	IRQ_POLARITY	TRX_CTRL_1
Read/Write	R/W	R/W	R/W	R/W
Reset value	0	0	1	0

- Bit 4 - RX\_BL\_CTRL

The register bit RX\_BL\_CTRL controls the Frame Buffer Empty Indicator. Table 11-16. RX\_BL\_CTRL.

Register Bits	Value	Description
RX_BL_CTRL	0	Frame Buffer Empty Indicator disabled
	1	Frame Buffer Empty Indicator enabled

Note: 1. A modification on IRQ\_POLARITY bit has no influence to RX\_BL\_CTRL behavior. If this register bit is set the Frame Buffer Empty Indicator is enabled. After sending a Frame Buffer read command, refer to Section 6.2, pin 24 (IRQ) indicates to the microcontroller that an access to the Frame Buffer is not possible as long as valid PSDU data are missing. The pin 24 (IRQ) does not indicate any interrupts during this time.

11.6 Dynamic Frame Buffer Protection

11.6.1 Overview

The Atmel AT86RF232 continues the reception of incoming frames as long as it is in any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Protection prevents that a new valid frame passes to the Frame Buffer until a Frame Buffer read access has ended (indicated by /SEL = H, refer to Section 6.2). A received frame is automatically protected against overwriting: - in Basic Operating Mode, if its FCS is valid - in Extended Operating Mode, if an IRQ\_3 (TRX\_END) is generated The Dynamic Frame Buffer Protection is enabled with RX\_SAFE\_MODE set and applicable transceiver states RX\_ON and RX\_AACK\_ON. Note: 1. The Dynamic Frame Buffer Protection only prevents write accesses from the air interface – not from the SPI interface.

11.6.2 Register Description

Register 0x0C (TRX\_CTRL\_2):

The TRX\_CTRL\_2 register is a multi-purpose control register to control various settings of the radio transceiver. Figure 11-17. Register TRX\_CTRL\_2. 

- Bit 7 - RX\_SAFE\_MODE

Protect Frame Buffer after frame receive with valid FCF check. Table 11-17. RX\_SAFE\_MODE.

Register Bits	Value	Description
RX_SAFE_MODE	0	Disable Dynamic Frame Buffer protection
	1^(1)	Enable Dynamic Frame Buffer protection

Note: 1. Dynamic Frame Buffer Protection is released with the rising edge of /SEL pin of a Frame Buffer read access, or radio transceiver state changes from RX\_ON o RX\_AACK\_ON to another state. This operation mode is independent of the setting of register bits RX\_PDT\_LEVEL, (register 0x15, RX\_SYN), refer to Section 9.1.3.

12 Electrical Characteristics

12.1 Absolute Maximum Ratings

Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
T_STOR	Storage temperature		-50		150	°C
T_LEAD	Lead temperature	T = 10s(soldering profile compliant with IPC/JEDEC J STD 020B)			260	°C
V_ESD	ESD robustness	Compl. to [3], Compl. to [4]	2500			kVV
P_RF	Input RF level				+10	dBm
V_DIG	Voltage on all pins(except pins 4, 5, 13, 14, 29)		-0.3		V_DD+0.3	V
V_ANA	Voltage on pins 4, 5, 13, 14, 29		-0.3		2.0	V

 Caution! ESD sensitive device. Precaution should be used when handling the device in order to preve permanent damage.

12.2 Recommended Operating Range

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
T_OP	Operating temperature range		0	+25	+70	°C
V_DD	Supply voltage	Voltage on pins 15, 28(1)	1.8	3.0	3.6	V
V_DD1.8	Supply voltage (on pins 13, 14, 29)	External voltage supply(2)	1.7	1.8	1.9	V

Notes: 1. Even if an implementation uses the external 1.8V voltage supply V_DD1.8 it is required to connect V_DD . 2. Register 0x10 (VREG\_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to Section 9.4.

12.3 Digital Pin Characteristics

Test Conditions: T_OP = +25^ (unless otherwise stated).

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
V_IH	High level input voltage^(1)		V_DD-0.4			V
V_IL	Low level input voltage^(1)				0.4	V
V_OH	High level output voltage^(1)		V_DD-0.4			V
V_OL	Low level output voltage^(1)				0.4	V
C_Load	Capacitive load^(1)			50		pF

Note: 1. The capacitive load C_Load should not be larger than 50pF for all I/Os. Generally, large load capacitances increase the overall current consumption.

12.4 Digital Interface Timing Characteristics

Test Conditions: T_OP = +25^ , V_DD = 3.0V , C_Load = 50pF (unless otherwise stated).

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
f_async	SCLK frequency	Asynchronous operation			7.5	MHz
t_1	/SEL falling edge to MISO active				180	ns
t_2	SCLK falling edge to MISO out	Data hold time	25			ns
t_3	MOSI setup time		10			ns
t_4	MOSI hold time		10			ns
t_5	LSB last byte to MSB next byte	SPI read/write, standard SRAM and frame access modes	250^(1)			ns
t_6a	LSB last byte to MSB next byte	Fast SRAM read/write access mode	500^(1)			ns
t_6	/SEL rising edge to MISO tri state				10	ns
t_7	SLP_TR pulse width	TX start trigger	62.5		Note ^(2)	ns
t_8	SPI idle time: SEL rising to falling edge	SPI read/write, standard SRAM and frame access modesIdle time between consecutive SPI accesses	250^(1)			ns
t_8a	SPI idle time: SEL rising to falling edge	Fast SRAM read/write access modeIdle time between consecutive SPI accesses	500^(1)			ns
t_9	Last SCLK rising edge to /SEL rising edge			250		ns
t_10	Reset pulse width	≥ 10 clock cycles at 16MHz	625			ns
t_11	SPI access latency after reset	≥ 10 clock cycles at 16MHz	625			ns
t_12	Frame buffer empty indicator latency	rising edge of last SCLK clock of the Frame Buffer read command byte to rising edge of IRQ		750		ns
t_IRQ	IRQ_2, IRQ_3, IRQ_4 latency	Relative to the event to be indicated		9		μs
f_CLKM	Output clock frequency at pin 17 (CLKM)	Configurable in register 0x03		0162.5		MHzMHzkHz

Notes: 1. For Fast SRAM read/write accesses on address space 0x82 - 0x94 the time t_5 (Min.) and t_8 (Min.) increases to 500ns. 2. Maximum pulse width less than (TX frame length + 16 s).

12.5 General RF Specifications

Test Conditions (unless otherwise stated): $$ V _ {D D} = 3. 0 \mathrm{V}, f _ {R F} = 2 4 4 5 \mathrm{MHz}, T _ {O P} = + 2 5 ^ {\circ} \mathrm{C}, \text { Measurement setup see Figure 5 - 1 }. $$

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
f_RF	Frequency range	As specified in [1], [2]	2405	2445	2480	MHz
f_CH	Channel spacing	As specified in [1], [2]		5		MHz
f_HDR	Header bit rate (SHR, PHR)	As specified in [1], [2]		250		kb/s
f_PSDU	PSDU bit rate	As specified in [1], [2]		250		kb/s
f_CHIP	Chip rate	As specified in [1], [2]		2000		kchip/s
f_CLK	Crystal oscillator frequency	Reference oscillator		16		MHz
f_SRD	Symbol rate deviationReference frequency accuracy for correct functionality	PSDU bit rate250kb/s	-60(1)		+60	ppm
f_20dB	20dB bandwidth			2.8		MHz

Note: 1. A reference frequency accuracy of ±40ppm is required by [1], [2].

12.6 Transmitter Characteristics

Test Conditions (unless otherwise stated): $$ V _ {D D} = 3. 0 \mathrm{V}, f _ {R F} = 2 4 4 5 \mathrm{MHz}, T _ {O P} = + 2 5 ^ {\circ} \mathrm{C}, \text { Measurement setup see Figure 5 - 1 }. $$

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
P_TX\_MAX	TX Output power	Maximum configurable TX output power valueRegister bit TX_PWR = 0		+3		dBm
P_RANGE	Output power range	16 steps, configurable in register 0x05 (PHY_TX_PWR)		20		dB
P_ACC	Output power tolerance				±5	dB
EVM	EVM				30	%rms
P_HARM	Harmonics	2^nd harmonic 3^rd harmonic		-45	-40	dBmdBm
P_SPUR\_TX	Spurious Emissions(1)	30 – ≤ 1000MHz>1 – 12.75GHz1.8 – 1.9GHz5.15 – 5.3GHz		-36-30-47-47		dBmdBmdBmdBm

Note: 1. Complies with EN 300 328/440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210.

12.7 Receiver Characteristics

Test Conditions (unless otherwise stated): V_DD = 3.0V, f_RF = 2445MHz, T_OP = +25^ , Measurement setup see Figure 5-1.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
P_SENS	Receiver sensitivity	250kb/s ^(1) Antenna Diversity250kb/s ^(1)		-100-99		dBmdBm
RL_RX	RX Return loss	100Ω differential impedance		10		dB
NF	Noise figure			6		dB
P_RX\_MAX	Maximum RX input level	250kb/s ^(1)		8		dBm
P_ACRN	Adjacent channel rejection:-5MHz	250kb/s ^(1) , P_RF = -82dBm		32		dB
P_ACRP	Adjacent channel rejection:+5MHz	250kb/s ^(1) , P_RF = -82dBm		35		dB
P_AACRN	Adjacent channel rejection:-10MHz	250kb/s ^(1) , P_RF = -82dBm		48		dB
P_AACRP	Adjacent channel rejection:+10MHz	250kb/s ^(1) , P_RF = -82dBm		48		dB
P_AACR2N	2ndalternate channel rejection:-15MHz	250kb/s ^(1) , P_RF = -82dBm		54		dB
P_AACR2P	2ndalternate channel rejection:+15MHz	250kb/s ^(1) , P_RF = -82dBm		54		dB
P_SPUR\_RX	Spurious emissions	LO leakage30 – ≤ 1000MHz>1 – 12.75GHz		-70-47		dBmdBmdBm
f_CAR\_OFFS	TX/RX carrier frequency offset	Sensitivity loss ≤ 2dB	-300 ^(2)		+300	kHz
RSSI_TOL	RSSI tolerance	Tolerance within gain step			±5	dB
RSSI_RANGE	RSSI dynamic range			87		dB
RSSI_RES	RSSI resolution			3		dB
RSSI_BASE\_VAL	RSSI sensitivity	Defined as RSSI_BASE_VAL		-91		dBm
RSSI_MIN	Minimum RSSI value	P_RF ≤ RSSI\_BASE\_VAL		0
RSSI_MAX	Maximum RSSI value	P_RF ≥ RSSI\_BASE\_VAL + 84dB		28

Notes: 1. AWGN channel, PER ≤ 1%, PSDU length 20 octets. 2. Offset equals ±120 ppm.

12.8 Current Consumption Specifications

Test Conditions (unless otherwise stated): V_DD = 3.0V, f_RF = 2445MHz, T_OP = +25^ , Measurement setup see Figure 5-1.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
I_BUSY\_TX	Supply current transmit state	P_TX=+3dBm P_TX=+0dBm P_TX=-17dBm		13.811.87.2		mA mA mA
I_RX\_ON	Supply current RX_ON state	high sensitivity RX PDT_LEVEL = [0x0]		11.8		mA
I_RX\_ON\_L0	Supply current RX_ON state with active receiver desensitize	receiver desensitize RX PDT_LEVEL = [0x1, ..., 0xE, 0xF] ^(1)		11.3		mA
I_PLL\_ON	Supply current PLL_ON state			5.2		mA
I_TRX\_OFF	Supply current TRX_OFF state			330		μA
I_SLEEP	Supply current SLEEP state			0.4		μA

Notes: 1. Refer to Section 9.1. 2. All power consumption measurements are performed with CLKM disabled.

12.9 Crystal Parameter Requirements

Symbol	Parameter	Condition	Min.	Typ.	Max.	Unit
f_0	Crystal frequency			16		MHz
C_L	Load capacitance		8		14	pF
C_0	Static capacitance				7	pF
R_1	Series resistance				100	Ω

13 Typical Characteristics

13.1 Active Supply Current

The following charts showing each a typical behavior of the Atmel AT86RF232. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement setup used for the measurements is shown in Figure 5-1. The power consumption of the microcontroller, which is required to program the radio transceiver, is not included in the measurement results. The power consumption in SLEEP state is independent from CLKM master clock rate selection. The current consumption depends on several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, and ambient temperature. The dominating factors are operating voltage and ambient temperature. If possible the measurement results are not affected by current drawn from I/O pins. Register, SRAM or Frame Buffer read or write accesses are not performed during current consumption measurements.

13.1.1 P\_ON and TRX\_OFF states

Figure 13-1. Current Consumption in P\_ON State.  Figure 13-2. Current Consumption in TRX\_OFF State. 

13.1.2 PLL\_ON state

Figure 13-3. Current Consumption in PLL\_ON State. 

13.1.3 RX\_ON state

Figure 13-4. Current Consumption in RX\_ON State – High Sensitivity.  Figure 13-5. Current Consumption in RX\_ON State – Reduced Sensitivity. 

13.1.4 TX\_BUSY state

Figure 13-6. Current Consumption in TX\_BUSY State – Minimum Output Power.  Figure 13-7. Current Consumption in TX\_BUSY State – Output Power 0dBm.  Figure 13-8. Current Consumption in TX\_BUSY State – Maximum Output Power. 

13.1.5 SLEEP

Figure 13-9. Current Consumption in SLEEP. 

13.2 State Transition Timing

Figure 13-10. Transition Time from EVDD to P\_ON (CLKM available).  Figure 13-11. Transition Time from SLEEP to TRX\_OFF (IRQ\_4 (AWAKE\_END)).  Figure 13-12. Transition Time from TRX\_OFF to PLL\_ON. 

14 Register Reference

The Atmel AT86RF232 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value. Table 14-1. Register Summary.

Addr	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0	Page
0x01	TRX_STATUS	CCA_DONE	CCA_STATUS	reserved	TRX_STATUS					41,62,95
0x02	TRX_STATE	TRAC_STATUS			TRX_CMD					42,63
0x03	TRX_CTRL_0	reserved	reserved	reserved	reserved	CLKM_SHA_SEL	CLKM_CTRL			116
0x04	TRX_CTRL_1	reserved	IRQ_2_EXT_EN	TX_AUTO_CRC_ON	RX_BL_CTRL	SPI_CMD_MODE		IRQ_MASK_MODE	IRQ_POLARITY	21,28,65,86,138,142
0x05	PHY_TX_PWR	reserved	reserved	reserved		TX_PWR				104
0x06	PHY_RSSI	RX_CRC_VALID	RND_VALUE		RSSI					86,89,133
0x07	PHY_ED_LEVEL	ED_LEVEL								92
0x08	PHY_CC_CCA	CCA_REQUEST	CCA_MODE		CHANNEL					96,119
0x09	CCA_THRES	reserved				CCA_ED_THRES				97
0x0A	RX_CTRL	reserved		reserved	reserved	PDT_THRES				136
0x0C	TRX_CTRL_2	RX_SAFE_MODE	reserved	reserved	reserved		reserved			143
0x0D	ANT_DIV	ANT_SEL	reserved			ANT_DIV_EN	ANT_EXT_SW_EN	ANT_CTRL		136
0x0E	IRQ_MASK	IRQ_MASK								27
0x0F	IRQ_STATUS	IRQ_7_BAT_LOW	IRQ_6_TRX_UR	IRQ_5_AMI	IRQ_4_CCA_ED_DON	IRQ_3_TRX_END	IRQ_2_RX_START	IRQ_1_PLL_UNLOCK	IRQ_0_PLL_LOCK	27
0x10	VREG_CTRL	AVREG_EXT	AVDD_OK	reserved		DVREG_EXT	DVDD_OK	reserved		109
0x11	BATMON	reserved	reserved	BATMON_OK	BATMON_HR	BATMON_VTH				112
0x12	XOSC_CTRL	XTAL_MODE				XTAL_TRIM				117
0x15	RX_SYN	RX_PDT_DIS	reserved			RX_PDT_LEVEL				101
0x17	XAH_CTRL_1	ARET_TX_TS_EN	reserved	AACK_FLTR_RES_F	AACK_UPLD_RES_F	reserved	AACK_ACK_TIME	AACK_PROM_MODE	reserved	66,140
0x18	FTN_CTRL	FTN_START	reserved	reserved						122
0x19	XAH_CTRL_2	ARET_FRAME_RETRIES				ARET_CSMA_RETRIES			reserved	68
0x1A	PLL_CF	PLL_CF_START	reserved	reserved		PLL_CF				120
0x1B	PLL_DCJ	PLL_DCJ_START	reserved	reserved						121
0x1C	PART_NUM	PART_NUM								22
0x1D	VERSION_NUM	VERSION_NUM								22
0x1E	MAN_ID_0	MAN_ID_0								23
0x1F	MAN_ID_1	MAN_ID_1								23
0x20	SHORT_ADDR	SHORT_ADDR_0								75
0x21	SHORT_ADDR	SHORT_ADDR_1								75
0x22	PAN_ID_0	PAN_ID_0								75
0x23	PAN_ID_1	PAN_ID_1								76
0x24	IEEE_ADDR_0	IEEE_ADDR_0								76
0x25	IEEE_ADDR_1	IEEE_ADDR_1								76
0x26	IEEE_ADDR_2	IEEE_ADDR_2								77
0x27	IEEE_ADDR_3	IEEE_ADDR_3								77
0x28	IEEE_ADDR_4	IEEE_ADDR_4								77
0x29	IEEE_ADDR_5	IEEE_ADDR_5								78
0x2A	IEEE_ADDR_6	IEEE_ADDR_6								78
0x2B	IEEE_ADDR_7	IEEE_ADDR_7								78
0x2C	XAH_CTRL_0	MAX_FRAME_RETRIES				MAX_CSMA_RETRIES			SLOTTED_OPERATIC	69
0x2D	CSMA_SEED_0	CSMA_SEED_0								71
0x2E	CSMA_SEED_1	AACK_FVN_MODE		AACK_SET_PD	AACK_DIS_ACK	AACK_I_AM_COORI	CSMA_SEED_1			71
0x2F	CSMA_BE	MAX_BE				MIN_BE				73
0x36	TST_CTRL_DIO	reserved	reserved	reserved	reserved	TST_CTRL_DIG				166

The reset values of the Atmel AT86RF232 registers in state P\_ON (1, 2, 3) are shown in Table 14-2. Note: All reset values in Table 14-2 are only valid after a power on reset. After a reset procedure (/RST = L) as described in Section 7.1.4.5 the reset values of selected registers (for example registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 14-2. Table 14-2. Register Summary – Reset Values.

Address	Reset Value
0x00	0x00
0x01	0x00
0x02	0x00
0x03	0x09
0x04	0x22
0x05	0x00
0x06	0x60
0x07	0xFF
0x08	0x2B
0x09	0xC7
0x0A	0x37
0x0B	0xA7
0x0C	0x20
0x0D	0x00
0x0E	0x00
0x0F	0x00

Address	Reset Value
0x10	0x00
0x11	0x02
0x12	0xF0
0x13	0x00
0x14	0x00
0x15	0x00
0x16	0xC1
0x17	0x00
0x18	0x58
0x19	0x00
0x1A	0x57
0x1B	0x20
0x1C	0x0A
0x1D	0x02
0x1E	0x1F
0x1F	0x00

Address	Reset Value
0x20	0xFF
0x21	0xFF
0x22	0xFF
0x23	0xFF
0x24	0x00
0x25	0x00
0x26	0x00
0x27	0x00
0x28	0x00
0x29	0x00
0x2A	0x00
0x2B	0x00
0x2C	0x38
0x2D	0xEA
0x2E	0x42
0x2F	0x53

Address	Reset Value
0x30	0x00
0x31	0x00
0x32	0x00
0x33	0x00
0x34	0x00
0x35	0x00
0x36	0x00
0x37	0x00
0x38	0x00
0x39	0x40
0x3A	0x00
0x3B	0x00
0x3C	0x00
0x3D	0x00
0x3E	0x00
0x3F	0x00

15 Abbreviations

AACK - Automatic acknowledgement ACK - Acknowledgement ADC - Analog-to-digital converter AD - Antenna diversity AGC - Automated gain control AES - Advanced encryption standard ARET - Automatic retransmission AVREG - Voltage regulator for analog building blocks AWGN - Additive White Gaussian Noise BATMON - Battery monitor BBP - Base band processor BPF - Band pass filter CBC - Cipher block chaining CRC - Cyclic redundancy check CCA - Clear channel assessment CSMA-CA - Carrier sense multiple access/Collision avoidance CW - Continuous wave DFBP - Dynamic Frame Buffer Protection DVREG - Voltage regulator for digital building blocks ECB - Electronic code book ED - Energy detection ESD - Electrostatic discharge EVM - Error vector magnitude FCF - Frame control field FCS - Frame check sequence FIFO - First in first out FTN - Filter tuning network GPIO - General purpose input output ISM - Industrial, scientific, and medical LDO - Low-drop output LNA - Low-noise amplifier LO - Local oscillator LQI - Link quality indicator LSB - Least significant bit MAC - Medium access control MFR - MAC footer MHR - MAC header MISO - SPI Interface: Master input slave output MOSI - SPI Interface: Master output slave input MSB - Most significant bit MSDU - MAC service data unit MPDU - MAC protocol data unit MSK - Minimum shift keying O-QPSK - Offset - quadrature phase shift keying PA - Power amplifier PAN - Personal area network PCB - Printed circuit board PER - Packet error rate PHR - PHY header PHY - Physical layer PLL - Phase locked loop POR - Power-on reset PPF - Poly-phase filter PRBS - Pseudo random bit sequence PSDU - PHY service data unit PSD - Power spectral mask QFN - Quad flat no-lead package RF - Radio frequency RSSI - Received signal strength indicator RX - Receiver SCLK - SPI Interface: SPI clock /SEL - SPI Interface: SPI select SFD - Start-of-frame delimiter SHR - Synchronization header SPI - Serial peripheral interface SRAM - Static random access memory SSBF - Single side band filter TX - Transmitter VCO - Voltage controlled oscillator VREG - Voltage regulator XOSC - Crystal oscillator 16 Ordering Information

Ordering Code	Packaging	Package	Voltage Range	Temperature Range
AT86RF232-ZX	Tray	QN	1.8V – 3.6V	Commercial (0°C to +70°C) Lead-free/Halogen-free
AT86RF232-ZXR	Tape & Reel	QN	1.8V – 3.6V	Commercial (0°C to +70°C) Lead-free/Halogen-free

Package Type	Description
QN	32QN2, 32-lead 5.0 x 5.0mm Body, 0.50mm Pitch, Quad Flat No-lead Package (QFN) Sawn

Note: T&R quantity 5,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities.

17 Soldering Information

Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C. 18 Package Thermal Properties

Thermal Resistance
Velocity [m/s]	Theta ja [K/W]
0	40.9
1	35.7
2.5	32.0

19 Package Drawing - 32QN2 

D E Pin 1 Corner

Top View 

A A3 A1 A2

Side View 

Pin 1 Corner D2 E2 + e L b

Bottom View COMMON DIMENSIONS (Unit of Measure = mm)

SYMBOL	MIN.	NOM. MAX. NOTE
D	5.00 BSC
E	5.00 BSC
D2	3.20	3.30	3.40
E2	3.20	3.30	3.40
A	0.80	0.90	1.00
A1	0.0	0.02	0.05
A2	0.0	0.65	1.00
A3	0.20 REF
L	0.30	0.40	0.50
e	0.50 BSC
b	0.18	0.23	0.30	2

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VHHD-6, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 11/26/07

Package Drawing Contact:[e-mail]

TITLE32QN2, 32-lead 5.0 x 5.0 mm Body, 0.50 mm Pitch,Quad Flat No Lead Package (QFN) Sawn

GPCZJZ

DRAWING NO.32QN2

REV.A

Appendix A - Continuous Transmission Test Mode

A.1 - Overview

The Atmel AT86RF232 offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode). In CW mode two different signal frequencies per channel can be transmitted: - f_1 = Fc + 0.5MHz - f_2 = Fc - 0.5MHz Here Fc is the channel center frequency, refer to Section 9.7.2. Note: 1. In CW mode it is not possible to transmit a RF signal directly on the channel center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR (see Section 8.1). It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated continuously.

A.2 - Configuration

Before enabling Continuous Transmission Test Mode all register configurations shall be done as follow: • TX channel setting (optional) • TX output power setting (optional) - Mode selection (PRBS / CW) A register access to register 0x36 and 0x1C enables the Continuous Transmission Test Mode. The transmission is started by enabling the PLL (TRX\_CMD = PLL\_ON) and writing the TX\_START command to register 0x02. Even for CW signal transmission it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is recommended to write a frame of maximum length. The detailed programming sequence is shown in Table A-0-1. The column R/W informs about writing (W) or reading (R) a register or the Frame Buffer. Table A-0-1. Continuous Transmission Programming Sequence.

Step	Action	Register	R/W	Value	Description
1	RESET				Reset AT86RF232
2	Register Access	0x0E	W	0x01	Set IRQ mask register, enable IRQ_0 (PLL_LOCK)
3	Register Access	0x04	W	0x00	Disable TX_AUTO_CRC_ON
4	Register Access	0x02	W	0x03	Set radio transceiver state TRX_OFF
5	Register Access	0x03	W	0x01	Set clock at pin 17 (CLKM)
6	Register Access	0x08	W	0x33	Set IEEE 802.15.4 CHANNEL, for example channel 19
7	Register Access	0x05	W	0x00	Set TX output power, for example to P_TX\_MAX
8	Register Access	0x01	R	0x08	Verify TRX_OFF state
9	Register Access	0x36	W	0x0F	Enable Continuous Transmission Test Mode – step # 1
10^(1)	Register Access	0x0C	W	0x03	Enable raw data mode
11^(1)	Register Access	0x0A	W	0x37	Enable raw data mode
12^(2)	Frame Buffer Write Access		W		Write PSDU data (even for CW mode), refer to Table A-0-2
13	Register Access	0x1C	W	0x54	Enable Continuous Transmission Test Mode – step # 2
14	Register Access	0x1C	W	0x46	Enable Continuous Transmission Test Mode – step # 3
15	Register Access	0x02	W	0x09	Enable PLL_ON state
16	Interrupt event	0x0F	R	0x01	Wait for IRQ_0 (PLL_LOCK)
17	Register Access	0x02	W	0x02	Initiate Transmission, enter BUSY_TX state
18	Measurement				Perform measurement
19	Register Access	0x1C	W	0x00	Disable Continuous Transmission Test Mode
20	RESET				Reset AT86RF232

Notes: 1. Only required for CW mode, do not configure for PRBS mode. 2. Frame Buffer content varies for different modulation schemes. The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum length for the PSDU data. To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table A-0-2. Table A-0-2. Frame Buffer Content for various Continuous Transmission Modulation Schemes.

Step	Action	Frame Content	Comment
12	Frame Buffer Access	Random Sequence	Modulated RF signal
		0x00 (each byte of PSDU)	Fc – 0.5MHz, CW signal
		0xFF (each byte of PSDU)	Fc + 0.5MHz, CW signal

Note: 1. It is recommended to use a frame of maximum length (127 bytes).

A.3 – Register Description

Register 0x36 (TST\_CTRL\_DIGI): The TST\_CTRL\_DIG register enables the continuous transmission test mode. Figure 0-1. Register TST\_CTRL\_DIGI. 

- Bit 3:0 - TST\_CTRL\_DIG

The register bits TST\_CTRL\_DIG with value 0xF enables continuous transmission. Table 0-3. TST\_CTRL\_DIG.

Register Bits	Value	Description
TST_CTRL_DIG	0x0	No mode is active
	0xF	Continuous Transmission enabled
		All other values are reserved

Appendix B - Errata

AT86RF232 Rev. A

Potential current peak in radio transceiver state SLEEP

When leaving active states like receive or transmit immediately towards SLEEP state, a transient current peak of a few A at DEVDD may occur for a short period of time. Occurance depends on operational parameters as well as load capacitance at pin 29 (AVDD).

Problem Fix/Workaround

Place an external resistor (for example 220kΩ) between AVDD and AVSS, in parallel to the AVDD load capacitor.

Potential long PLL settling duration

In very rare cases a PLL\_LOCK interrupt is not generated within the specified maximum t_PLL\_INIT = 250 s PLL lock duration.

Problem Fix/Workaround

In such a case perform the following action: - read the register bits PLL\_CF (register 0x1A, PLL\_CF) - invert the LSB bit - write the value back to the PLL\_CF register; keep upper four bits as read before - wait a additional typical t PLL\_INIT = 80μs duration or until interrupt is generated

References

[1] IEEE Std 802.15.4 ^™ -2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [2] IEEE Std 802.15.4™-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) [3] ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Human Body Model (HBM). [4] ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Charged Device Model (CDM). [5] NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 [6] AT86RF232 Software Programming Model [7] IEEE Std 802.15.4 ^™ -2011: Low-Rate Wireless Personal Area Networks (WPANs)

Data Sheet Revision History

Rev. 8321A-MCU Wireless-10/11 1. Initial release

Table of Contents

1 Pin-out Diagram 2

1.1 Pin Descriptions.... 3 1.2 Analog and RF Pins .... 4 1.2.1 Supply and Ground Pins 4 1.2.2 RF Pins....4 1.2.3 Crystal Oscillator Pins .... 5 1.2.4 Analog Pin Summary....5 1.3 Digital Pins....6 1.3.1 Driver Strength Settings 6 1.3.2 Pull-up and Pull-down Configuration 6

2 Disclaimer....7

3 Overview....7

4 General Circuit Description....8

5 Application Circuits....10

5.1 Basic Application Schematic.... 10 5.2 Extended Feature Set Application Schematic.... 12

6 Microcontroller Interface....14

6.1 SPI Timing Description.... 15 6.2 SPI Protocol.... 16 6.2.1 Register Access Mode.... 16 6.2.2 Frame Buffer Access Mode....17 6.2.3 SRAM Access Mode....19 6.3 Radio Transceiver Status information 21 6.3.1 Register Description 21 6.4 Radio Transceiver Identification 22 6.4.1 Register Description 22 6.5 Sleep/Wake-up and Transmit Signal (SLP\_TR).... 24 6.6 Interrupt Logic.... 25 6.6.1 Overview 25 6.6.2 Interrupt Mask Modes and Pin Polarity....26 6.6.3 Register Description 27

7 Operating Modes....30

7.1 Basic Operating Mode 30 7.1.1 State Control .... 30 7.1.2 Basic Operating Mode Description 31 7.1.3 Interrupt Handling 35 7.1.4 Basic Operating Mode Timing 36 7.1.5 Register Description 41 7.2 Extended Operating Mode 43 7.2.1 State Control 45 7.2.2 Configuration 46 7.2.3 RX\_AACK\_ON - Receive with Automatic ACK 47 7.2.4 TX\_ARET\_ON – Transmit with Automatic Frame Retransmission and CSMA-CA Retry 58 7.2.5 Interrupt Handling....61 7.2.6 Register Summary....62 7.2.7 Register Description – Control Registers....62 7.2.8 Register Description – Address Registers 75

8 Functional Description 79

8.1 Introduction – IEEE 802.15.4-2006 Frame Format ...... 79 8.1.1 PHY Protocol Layer Data Unit (PPDU)....79 8.1.2 MAC Protocol Layer Data Unit (MPDU)....80 8.2 Frame Check Sequence (FCS) 84 8.2.1 Overview 84 8.2.2 CRC calculation....84 8.2.3 Automatic FCS generation 85 8.2.4 Automatic FCS check....85 8.2.5 Register Description 86 8.3 Received Signal Strength Indicator (RSSI) 88 8.3.1 Overview 88 8.3.2 Reading RSSI....88 8.3.3 Data Interpretation....88 8.3.4 Register Description....89 8.4 Energy Detection (ED) 90 8.4.1 Overview 90 8.4.2 Measurement Description....90 8.4.3 Data Interpretation....91 8.4.4 Interrupt Handling....91 8.4.5 Register Description....92 8.5 Clear Channel Assessment (CCA)....93 8.5.1 Overview 93 8.5.2 Configuration and Request....93 8.5.3 Data Interpretation....94 8.5.4 Interrupt Handling....94 8.5.5 Measurement Time 94 8.5.6 Register Description 95 8.6 Link Quality Indication (LQI) 98 8.6.1 Overview 98 8.6.2 Request an LQI Measurement 99 8.6.3 Data Interpretation....99

9 Module Description....100

9.1 Receiver (RX) 100 9.1.1 Overview 100 9.1.2 Frame Receive Procedure....100 9.1.3 Configuration 100 9.1.4 Register Description.... 101 9.2 Transmitter (TX) 103 9.2.1 Overview 103 9.2.2 Frame Transmit Procedure....103 9.2.3 Configuration 103 9.2.4 TX Power Ramping 104 9.2.5 Register Description....104 9.3 Frame Buffer.... 105 9.3.1 Data Management.... 105 9.3.2 User accessible Frame Content 106 9.3.3 Interrupt Handling....106 9.4 Voltage Regulators (AVREG, DVREG) 108 9.4.1 Overview 108 9.4.2 Configuration 108 9.4.3 Data Interpretation....108 9.4.4 Register Description....109 9.5 Battery Monitor (BATMON) 111 9.5.1 Overview 111 9.5.2 Configuration....111 9.5.3 Data Interpretation....111 9.5.4 Interrupt Handling....112 9.5.5 Register Description 112 9.6 Crystal Oscillator (XOSC).... 114 9.6.1 Overview 114 9.6.2 Integrated Oscillator Setup 114 9.6.3 External Reference Frequency Setup 115 9.6.4 Master Clock Signal Output (CLKM)....115 9.6.5 Register Description 116 9.7 Frequency Synthesizer (PLL).... 118 9.7.1 Overview 118 9.7.2 RF Channel Selection....118 9.7.3 Frequency Agility 118 9.7.4 Calibration Loops 118 9.7.5 Interrupt Handling....119 9.7.6 Register Description....119 9.8 Automatic Filter Tuning (FTN).... 122 9.8.1 Overview 122 9.8.2 Register Description....122

10 Radio Transceiver Usage 123

10.1 Frame Receive Procedure 123 10.2 Frame Transmit Procedure 124

11 AT86RF232 Extended Feature Set.... 125

11.1 Security Module (AES) 125 11.1.1 Overview 125 11.1.2 Security Module Preparation 125 11.1.3 Security Key Setup 126 11.1.4 Security Operation Modes....126 11.1.5 Data Transfer – Fast SRAM Access.... 129 11.1.6 Start of Security Operation and Status 130 11.1.7 SRAM Register Summary 130 11.1.8 AES SRAM Configuration Register 130 11.2 Random Number Generator.... 133 11.2.1 Overview 133 11.2.2 Register Description 133 11.3 Antenna Diversity 134 11.3.1 Overview 134 11.3.2 Antenna Diversity Application Example.... 134 11.3.3 Antenna Diversity Sensitivity Control.... 135 11.3.4 Register Description 136 11.4 RX and TX Frame Time Stamping (TX\_ARET) 139 11.4.1 Overview 139 11.4.2 Register Description 139 11.5 Frame Buffer Empty Indicator 141 11.5.1 Overview 141 11.5.2 Register Description 142 11.6 Dynamic Frame Buffer Protection 143 11.6.1 Overview 143 11.6.2 Register Description 143

12 Electrical Characteristics.... 144

12.1 Absolute Maximum Ratings.... 144 12.2 Recommended Operating Range.... 144 12.3 Digital Pin Characteristics ...... 144 12.4 Digital Interface Timing Characteristics.... 145 12.5 General RF Specifications.... 146 12.6 Transmitter Characteristics ...... 146 12.7 Receiver Characteristics ...... 147 12.8 Current Consumption Specifications.... 148 12.9 Crystal Parameter Requirements 148

13 Typical Characteristics.... 149

13.1 Active Supply Current.... 149 13.1.1 P\_ON and TRX\_OFF states....149 13.1.2 PLL\_ON state 150 13.1.3 RX\_ON state 151 13.1.4 TX BUSY state 152 13.1.5 SLEEP 153 13.2 State Transition Timing 154

14 Register Reference 156

15 Abbreviations.... 159

16 Ordering Information 162

17 Soldering Information.... 162

18 Package Thermal Properties.... 162

19 Package Drawing - 32QN2.... 163

Appendix A - Continuous Transmission Test Mode....164

A.1 - Overview 164 A.2 - Configuration.... 164 A.3 – Register Description.... 166 Appendix B - Errata 167 AT86RF232 Rev. A 167 References.... 168 Data Sheet Revision History 169 8321A-MCU Wireless-10/11 169 Table of Contents.... 170 

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