ATSAMA5D28C-LD1G - Electronic component Microchip - Free user manual and instructions

USER MANUAL ATSAMA5D28C-LD1G Microchip

SAMA5D2-PTC-EK User's Guide

Scope

This user's guide describes how to use the SAMA5D2 PTC Evaluation Kit (SAMA5D2-PTC-EK).

The SAMA5D2-PTC-EK is used to evaluate the capabilities of the Peripheral Touch Controller (PTC) designed for the SAMA5D2 series of embedded MPUs. Refer to the Configuration Summary table in the SAMA5D2 Series Datasheet for the list of MPUs featuring PTC.

Blue printed circuit board with various electronic components and connectors (no readable text or symbols)

Table of Contents

Scope....1

1. Introduction......3

1.1. Document Layout....3
1.2. Recommended Reading....3

1. Product Overview....4

2.1. SAMA5D2-PTC-EK Features....4
2.2. SAMA5D2-PTC-EK Content....5
2.3. Evaluation Kit Specifications....5
2.4. Power Sources....5

1. Board Components....6

3.1. Board Overview....6
3.2. Function Blocks....9
3.3. External Interfaces.... 30
3.4. Debugging Capabilities.... 34
3.5. PIO Usage on Expansion Connectors....39

1. Installation and Operation....47

4.1. System and Configuration Requirements....47
4.2. Board Setup.... 47

1. Appendix A. Schematics and Layouts....48
2. Revision History....61

6.1. DS50002709B - 09/2019....61
6.2. DS50002709A - 12/2017....61

The Microchip Website....62

Product Change Notification Service....62

Customer Support....62

Microchip Devices Code Protection Feature....62

Legal Notice....62

Trademarks....63

Quality Management System....63

Worldwide Sales and Service....64

1. Introduction

1.1 Document Layout

The document is organized as follows:

• Chapter 1. "Introduction"
- Chapter 2. "Product Overview" – Important information about the SAMA5D2-PTC-EK board
- Chapter 3. "Board Components" – Specifications of the SAMA5D2-PTC-EK and high-level description of the major components and interfaces
- Chapter 4. "Installation and Operation" – Instructions on how to get started with the SAMA5D2-PTC-EK
- Appendix A. "Schematics and Layouts" – SAMA5D2-PTC-EK schematics and layout diagrams

1.2 Recommended Reading

The following Microchip document is available and recommended as a supplemental reference resource:

• SAMA5D2 Series Datasheet. Lit. Number DS60001476

2. Product Overview

2.1 SAMA5D2-PTC-EK Features

The SAMA5D2-PTC-EK follows the Microchip MPU strategy for low cost evaluation kits with maximum reuse capability, and is built on the SAMA5D2 Xplained Ultra (XULT) hardware and software ecosystem. This board is mainly dedicated to evaluating the Peripheral Touch Controller capabilities.

Table 2-1. SAMA5D2-PTC-EK Features

Characteristics Specifications Components
Processor	SAMA5D27-CU (289-ball BGA) 14x14mm body, 0.8mm pitch	-
Clock speed	MPU: 24 MHz, 32.768 KHzPHY: Crystal 25 MHz	-
Memory	Two 16-bit, 2-Gbit DDR2One 4-Gbit Nand FlashOne QSPI FlashOne Serial Data Flash (optional)One EEPROM	Winbond W972GG6KB-25Micron MT29F4G08Microchip SST26VF064BMicrochip SST26VF032BMicrochip 24AA02E48
Display One LCD interface connector RGB, 18 bits
SD/MMC	One standard SD card interfaceOne microSD card interface	With 3.3V/1.8V power switch-
USB	One USB host type AOne USB device type Micro-ABOne USB HSIC	With 5V power switch-Connector not mounted
Ethernet One ETH PHY Micrel KSZ8081RN
Debug port	One J-Link-OB/J-Link-CDCOne JTAG interface	Embedded J-Link-OB and J-Link-CDC (ATSAM3U4C TFBGA100)
Board monitor	One RGB (Red, Green, Blue) LEDFour push button switches	-DisableBoot, Reset, WakeUp, User Free
Expansion	One set of XPRO WINGS connectorsOne ITO FLEX connectorOne Port B connectorOne PIOBU connectorOne mikroBUSTMconnector	Dedicated PTC QTouch®OptionalOptionalOptional-
Board supply From USB A and USB J-Link-OB 5VDC
Backup power supply SuperCap ELNA DSK-3R3H204T614-H2L

2.2 SAMA5D2-PTC-EK Content

The SAMA5D2-PTC-EK evaluation kit includes the following:

• The SAMA5D2-PTC-EK board
- A USB cable

2.3 Evaluation Kit Specifications

Table 2-2. Evaluation Kit Specifications

Characteristic Specification
Board SAMA5D2-PTC-EK
Board supply voltage USB-powered
Temperature Operating: 0°C to +70°CStorage: -40°C to +85°C
Relative humidity 0 to 90% (non-condensing)
Main board dimensions 135 × 90 × 20 mm
RoHS status Compliant
Board identification SAMA5D2 Peripheral Touch Controller Evaluation Kit

2.4 Power Sources

Several options are available to power up the SAMA5D2-PTC-EK board:

• USB powering through the USB Micro-AB connector (J4 - default configuration)
• Powering through the USB Micro-AB connector on the J-Link-OB Embedded Debugger interface (J9)

Table 2-3. Electrical Characteristics

Electrical Parameter Value
Input voltage 5VCC
Maximum input voltage 6VCC
Maximum 3.3VDC current available 1.2A
I/O voltage 3.3V only

3. Board Components

This section covers the specifications of the SAMA5D2-PTC-EK and provides a high-level description of the board's major components and interfaces. This document is not intended to provide detailed documentation about the processor or about any other component used on the board. It is expected that the user will refer to the appropriate documents of these devices to access detailed information.

3.1 Board Overview

The fully-featured SAMA5D2-PTC-EK board integrates multiple peripherals and interface connectors, as shown in the figure below.

JPLIN Technology www.sagger.com JLINK C158 J10 JTAG RST DBOOT U3 C7 TP7 R242 U14 R168 U15 R174 R180 R190 R200 R210 R220 R230 R240 R250 R260 R270 R280 R290 R300 R310 R320 R330 R340 R350 R360 R370 R380 R390 R400 R410 R420 R430 R440 R450 R460 R470 R480 R490 R500 R510 R520 R530 R540 R550 R560 R570 R580 R590 R600 R610 R620 R630 R640 R650 R660 R670 R680 R690 R700 R710 R720 R730 R740 R750 R760 R770 R780 R790 R800 R810 R820 R830 R840 R850 R860 R870 R880 R890 R900 R910 R920 R930 R940 R950 R960 R970 R980 R990 R1000 SAMS1B2-PTC-EK Microchip www.microchip.com LCD J15A J15B J15C J15D J15E J15F J15G J15H J15I J15J J15K J15L J15M J15N J15O J15P J15Q J15R J15S J15T J15U J15V J15W J15X J15Y J15Z J15A J15C J15D J15E J15F J15G J15H J15I J15J J15K J15L J15M J15N J15O J15P J15Q J15W J15X J15Y J15Z J15A J15C J15D J15E J15F J15G J15H J15I J15J J15K J15L J15M J15N J15O J15P J15O J15W J15X J15Y J15Z

3.1.1 Default Jumper Settings

The figure below shows the default jumper settings. Jumpers in red are configuration items and current measurement points. Jumpers in blue are not populated.

Figure 3-1. Default Jumper Settings

J-Link Technology www.segger.com J9 L20 JLINK JP1 MBUS PMM INT RX TX SCL SDA SV GND J15B AN RST CS SCK MISO MOS1 3V3 GND J15A JP12 x7 L18 ED3 R190 C123 J8 1 2 7 8 ETH R189 LCD R234 Microchip www.microchip.com R230 R231 SAMA5D2-PTC-EK Rev B J12 EXT2 XPRO J11 EXT1 PTC P146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DP3 R146 DPT JP222 JP223 JP224 JP225 JP226 JP227 JP228 JP229 JP230 JP231 JP232 JP233 JP234 JP235 JP236 JP237 JP238 JP239 JP240 JP241 JP242 JP243 JP244 JP245 JP246 JP247 JP248 JP249 JP250 JP251 JP252 JP253 JP254 JP255 JP256 JP257 JP258 JP259 JP260 JP261 JP262 JP263 JP264 JP265 JP266 JP267 JP268 JP269 JP270 JP271 JP272 JP273 JP274 JP275 JP276 JP277 JP278 JP279 JP280 JP281 JP282 JP283 JP284 JP285 JP286 JP287 JP288 JP289 JP290 JP291 JP292 JP293 JP294 JP295 JP296 JP297 JP298 JP299 JP300 JP301 JP302 JP303 JP304 JP305 JP306 JP307 JP308 JP309 JP310 JP311 JP312 JP313 JP314 JP315 JP316 JP317 JP318 JP319 JP320 JP321 JP322 JP323 JP324 JP325 JP326 JP327 JP328 JP329 JP330

The following table describes the functionality of the jumpers.

Table 3-1. SAMA5D2-PTC-EK Jumper Settings

Jumper Default Function
JP1 Closed VDD_MAIN_5V current measurement
JP2 Closed VDDOSC, VDDUTMII, VDDANA, VDDAUDIOPLL current measurement
JP3 Closed VDDISC + VDDIOP0/1/2 current measurement
JP4 Closed VDDIODDR_MPU current measurement
JP5 Closed VDDCORE current measurement
JP6 Closed VDDBU current measurement
JP7 Open PIOBU1, PIOBU7
JP8 Closed Disables NAND_CS (open=disable)
JP9 Open Enables JTAG-CDC (closed=disable)
JP10 Open Enables JTAG-OB (closed=disable)
......continued
Jumper	Default Function
JP11 Open		Erases SAM3U Flash Code (closed = erase)
		⚠ WARNING This jumper is reserved for factory configuration and should never be used by the end user.
JP12 Closed Powers mikroBUS extension (3.3V)
JP13 Open Disables QSPI
JP14	1-2 Enables 3.3V J-Link-OB, connected to shutdown circuitry
	2-3 Enables 3.3V J-Link-OB, always ON

3.1.2 Connectors on Board

The following table describes the interface connectors on the SAMA5D2-PTC-EK.

Table 3-2. SAMA5D2-PTC-EK Board Interface Connectors

Connector Interfaces to
J1 PIOBU, tamper and analog comparator connector (not populated)
J2 JTAG, 10-pin IDC connector
J3 USB Host B. Supports USB host using a type A connector
J4 USB A Device. Supports USB device using a type Micro-AB connector
J5 USB-C	^TM HSIC header (not populated)
J6 Standard SDMMC connector
J7 microSD connector
J8 Ethernet 10/100 RJ45
J9 USB-A Micro-AB, J-Link-OB port
J10 PCB connector for factory-programming the J-Link-OB/SAM3U
J11, J12 Xplained Pro expansion connectors (PTC-dedicated add-on boards)
J13 PIOs PortB connector
J14 ITO connector
J15 A&B mikroBUS connector
J16 Expansion TFT LCD connector for display module

3.2 Function Blocks

Figure 3-2. SAMA5D2-PTC-EK Block Diagram

graph TD
    A["USB-B Connector"] -->|USB A&B| B["POWER REGULATORS"]
    C["USB-A Connector"] -->|USB Detection| D["USB Detection"]
    E["USB Connector"] -->|J-Link Power 5V/3.3V| F["J-Link-OB J-Link-CDC"]
    G["Push Button"] -->|Reset, Wkup DisBoot, User| H["J-Link-OB JTAG Interface"]
    I["LEDs"] --> F
    J["Power Monitor"] --> F
    K["Power Cap"] --> L["DEBUG Interface"]
    M["TRi State"] --> F
    N["Function Select"] --> F
    O["GPIO"] -.-> P["GPIO"]
    Q["SD Card Connector"] --> R["MikroBUS Interface"]
    S["uSD Connector"] --> T["SDHC01"]
    U["XPRO (1&2) PTC Interface"] --> V["ITO Connector"]
    W["SAMA5D27"] --> X["DDR2 SDRAM"]
    W --> Y["QSPI Flash"]
    W --> Z["NAND Flash"]
    W --> AA["Serial EEPROM"]
    AB["DDR2 SDRAM"] --> AC["SHDN"]
    AD["GPIO"] --> AE["JTAG"]
    AF["RGB LEDs"] --> AG["JTAG Switch"]
    AH["UART"] --> AI["JTAG"]
    AJ["RAM"] --> AK["CPU"]
    AL["LED"] --> AM["J-Link-OB J-Link-CDC"]
    AN["GPIO"] --> AO["GPIO"]
    AP["GPIO"] --> AQ["GPIO"]
    AR["GPIO"] --> AS["GPIO"]
    AT["GPIO"] --> AU["GPIO"]
    AV["GPIO"] --> AW["GPIO"]
    AX["GPIO"] --> AY["GPIO"]
    AZ["GPIO"] --> BA["GPIO"]
    BB["GPIO"] --> BC["GPIO"]
    BD["GPIO"] --> BE["GPIO"]
    BF["GPIO"] --> BG["GPIO"]
    BH["GPIO"] --> BI["GPIO"]
    BJ["GPIO"] --> BK["GPIO"]
    BL["GPIO"] --> BLA["GPIO"]
    BN["SAMA5D2-PTC-EK"] --> BO["PortB(0-7)"]
    BN --> BP["PIOBU Connector"]
    BN --> BQ["ETH PHY"]
    BN --> BR["RJ45"]
    BN --> BS["LCD (18 bits)"]
    BN --> BT["TW/SPI"]
    BN --> BU["FPC Connector"]
    BN --> BV["PTC"]

3.2.1 Processor

The SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the ARM® Cortex®-A5 processor.

Please refer to the SAMA5D2 Series datasheet for more information.

3.2.2 Power Supply Topology and Power Distribution

3.2.2.1 Input Power Options

Two options are available to power the SAMA5D2-PTC-EK board. The USB-powered operation is the default configuration and comes from the USB device ports (J4-J9) connected to a PC or a 5VDC supply. Such USB power source is sufficient to supply the board in most applications. It is important to note that when the USB-powered operation is used, the USB port down the way has a limited powering capability. If the USB-B Host port (J3) is required to provide full powering capabilities to the target application, it is recommended to use an external DC supply instead of a USB power source.

The following figure is a schematic of the power options.

Figure 3-3. Input Powering

V_BUS_LINK C1 100nF C0402 R1 10K R0402 GND_POWER V_BUS_USBA C2 100nF C0402 R2 100K R0402 GND_POWER U1A DMP2160UFD 1 7 6 7 6 1 U4A DMP2160UFD R5-100K R0402 GND_POWER U1B DMP2160UFD 4 8 3 8 3 4 U4B DMP2160UFD R5_DNF R0402 GND_POWER JPR1 Jumper JP1 Header 1X2 VDD_MAIN_5V C12 100nF C0402 GND_POWER

Note: USB-powered operation eliminates additional wires and batteries. It is the preferred mode of operation for any project that requires only a 5V source at up to 500 mA.
Jumper JP1 is used to perform MAIN_5V current measurements on the SAMA5D2-PTC-EK board.

3.2.2.2 Power Supply Requirements and Restrictions

Detailed information on the device power supplies is provided in tables "SAMA5D2 Power Supplies" and "Power Supply Connections" in the SAMA5D2 Series datasheet.

3.2.2.3 Power-up and Power-down Considerations

Power-up and power-down considerations are described in section "Power Considerations" of the SAMA5D2 Series datasheet.

The power-up and power-down sequences provided in the SAMA5D2 Series datasheet must be respected for reliable operation of the device.

3.2.2.4 Power Management

The board power management uses three types of regulators:

• One dual synchronous step-down DC-DC regulator (U2 MIC2230) generates the 3.3V/800mA and 1.8V/800mA power lines and utilizes a high-efficiency, fixed-frequency (2.5 MHz), current-mode PWM control architecture that requires a minimum number of external components.
  • One ultra low-dropout linear regulator (U3 MIC47053) generates the 1.25V/500mA from the 1.8V source.
  • One high-performance single 2.5V/150mA is used as a VDDFUSE generator (U5 MIC5366).

The main regulators are enabled through a Field Effect Transistor (FET) scheme. The processor can assert SHDN (a VDDBU-powered I/O) to shut down the regulators to enter Backup mode. All regulators on the board are also shut down by the action of the SHDN signal.

A 3.3V battery (supercap) is implemented to permanently maintain VDDBU voltage (note: jumper JP6 must be in place). The board can be woken up by action on the PB4 button, which drives the WKUP signal (also a VDDBU-powered I/O).

The figure below shows the power management scheme.

Figure 3-4. Board Power Management

VDD_MAIN_5V C3 10uF C0603 C5 1uF C0603 GND POWER U2 AVIN VIN EN1 EN2 FPWMN 7 FPWM# PGOOD SW1 SW2 OUT1 OUT2 AGND PGND EPAD 13 MIC2250-GSYML MLF3x3mm R8100K R0402 C1039G0F C0402 VDD_3V3 L2LQH45ON2R2M03L L1812 C11 10uF C0603 C13 4.7nF C0402 VDD_MAIN_5V R9 100K R0402 FPWMN R10 DNP R0402 GND_POWER VDD_MAIN_5V C7 100nF C0402 U3 B/AS EN 8 EN_VDD_1V25 GND FGOOD 7 IN1 ADJ 6 R248 7K R0402 VDD_1V25 IN2 OUT 5 R251 10K R0402 GND_POWER C9 1uF C0603 GND_POWERGND_POWER GND_POWER GND_POWER GND_POWERGND_POWER VDD_3V3 R248 20K R0402 EN_VDD_1V25 VDD_3V3 R11 100K R0402 NRST VDD_MAIN_5V R3 100K R0402 STARTB Q1 BSS138 SOT23_123 SHDN 1 GND_POWER GND_POWER Q2 BSS136 SOT23_123 STARTB 1 Q3 BSS138 SOT23_123 C14 2.2uF C0603 GND_POWER Q4 SOT.23 BC847C D1 PMEG6010CEGWX sod123 R13 39K R0402

3.2.2.5 Supply Group Configuration

The main regulators provide all power supplies required by the SAMA5D2 device:

• 1.25V VDDCORE, VDDPLLA, VDDUTMIC, VDDHSIC
• 1.8V VDDIODDR, VDDSDHC1V8
• 2.5V VDDFUSE
• 3.3V VDDIOP0, VDDIOP1, VDDIOP2, VDDISC
• 3.3V VDDOSC, VDDUTMI, VDDANA, VDDAUDIOPLL
• 3.3V VDDBU

Figure 3-5. Power Lines Distribution

VDD_3V3 JP3 Header 1X2 VDDIOP2 L3 1 2 BLM16PG181SN1DVDDIOP1 R0603 L4 1 2 BLM16PG181SN1DVDDIOP0 R0603 L5 1 2 BLM18PG181SN1DVDDISC R0603 L6 1 2 BLM18PG181SN1D R0603 VDDOSC JP2 Header 1X2 R18 L8 VDDOSC 2R7 R0603 MLZ160EN-10CL VDDOUTMI R17 L12.1 2 OK R0603 R0603 VDDANA R18 R0603 L13.1 2 OK R0603 R0603 BLM18PG181SN1D R19 R0603 L8 VDDAUDIOPLL 2R7 R0603 MLZ160EN-10CL L5603

JP4 Header 1X2 VDD 1V8 VDD50H0R For DDR2 For MPU L14 1 2 BLM18PG181SN1D JP5 Header 1X2 VDD 1V25 VDDCORE R15 2R2 R0603 L7 MI 7 (ACM100) L0603 L16 1 2 BLM18PG181SN1D R0603 L11 1 2 BLM18PG181SN1D R0603 VDDPLLA VDDUTMIC VDDHSIC

Figure 3-6. Processor Power Lines Supplies

VDDCORE C19 10nF C0603 C27 10nF C0603 C31 100nF C0402 C33 100nF C0402 C35 100nF C0402 C43 100nF C0402 C47 100nF C0402 C49 100nF C0402 C51 1nF C0402 C58 1nF C0402 VDDCORE C80 1nF C0402 GND_POWER VDDBU (3V3) VDDBU C21 100nF C0402 VDDANA (3V3) VDDANA C37 100nF C0402 C45 100nF C0402 GND_POWER VDDIOP0 (3V3) VDDIOP0 C22 100nF C0402 VDDIOP1 (3V3) VDDIOP1 C36 100nF C0402 C48 100nF C0402 VDDIOP2 (3V3) VDDIOP2 C53 100nF C0402 GND_POWER VDDHSIC (1V2) VDDHSIC C23 100nF C0402 VDDFUSE (2V5) VDDFUSE C39 100nF C0402 VDDAUDIOPLL (3V3) VDDAUDIOPLL C54 4.7uF C0805 C57 100nF C0402 GND_POWER VDDUTMIC (1V2) VDDUTMIC C24 4.7uF C0605 C30 100nF C0402 VDDUTMII (3V3) VDDUTMII C40 100nF C0402 VDDSDHC (3V3 or 1V8) VDDSDHC GND_POWER VDDPLLA (1V2) VDDPLLA R20 1R-1% R3603 C26 100nF C0402 VDDOSC VDDISC (3V3) R21 1R-1% R8603 C42 100nF C0402 GND_POWER GND_POWER GND_POWER GND_POWER

VDDCORE (1V2) D7 D0 H3 K13 N5 N9 VDDDDR (1V8) G11 D12 D15 E15 H15 J15 L15 VDDBU (3V3) N7 VDDANA (3V3) K3 L5 VDDIOP0 (3V3) E8 F7 VDDIOP1 (3V3) N13 R14 VDDIOP2 (3V3) F10 VDDHSIC (1V2) R9 VDDFUSE (2V6) M12 VDDAUDIOPLL (3V3) T3 VDDUTMIC (1V2) P7 VDDUTMII (3V3) P8 VDDSDHC (3V3 or 1V8) P11 VDDPLLA (1V2) U4 VDDOSC (3V3) T7 VDDISC (3V3) F4 VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 VDDCORE_6 GNDCORE_1 GNDCORE_2 GNDCORE_3 GNDCORE_4 GNDCORE_5 GNDCORE_6 D14 E12 E12 E12 H14 J14 L14 N6 L3 K5 F6 G7 M13 P74 F9 T5 T4 R7 P9 R11 U5 T6 G4 ATSAMA5D27C-CN bga26@p8 GND_POWER

3.2.2.6 VDDFUSE

The SAMA5D2-PTC-EK board embeds a 2.5V regulator for fuse box programming.

Figure 3-7. VDDFUSE Regulator

VDD_3V3 U5 VIN VOUT 1 4 2 GND EPAD EN 3 EN_1 12 C15 1uF C2603 MICSS8A-2.5V/NT MLF1x1mn GND_POWER VDDFUSE C16 1uF C3603

3.2.2.7 Backup Power Supply

The SAMA5D2-PTC-EK board requires a power source in order to permanently power the backup part of the SAMA5D2 device (refer to SAMA5D2 Series datasheet). The super capacitor C17 sustains such permanent power to VDDBU when all system power sources are off.

Figure 3-8. VDDBU Powering Options

VDD_3V3 D2 7 R14 100R-15 PME6010CEGWX sod123 R0402 C17 0.2F/3.3V c117x08 GND_POWER (Subert) Capacitor energy storage D3 BAT54C 1 2 3 SOT25_125 JPS Header 1X2 C18 100nF C0402 GND_POWER VDOSL

3.2.3 Reset Circuitry

The reset sources for the SAMA5D2-PTC-EK board are:

• Power-on Reset from the power management unit,
• Push button reset BP3,
• JTAG or J-Link-OB reset from an in-circuit emulator.

Figure 3-9. Main Reset Control

PowerGood VDD_1V25 STARTB 1 GND POWER Q3 BSS138 SOT25_125 C14 2.7μF C0603 Q4 SOT-23 BC547C R11 100K R0402 VDD_3V3 R12 220K R0402 VDD MAIN 5V D1 PMEG6010CEGWX SOD123 R13 39K R0402 NRST

3.2.4 Shutdown Circuitry

The SHDN signal, output of Shutdown Controller (SHDN), drives the shutdown request to the power supply. This output signal is supplied by VDDBU, which is present in Backup mode.

The Shutdown Controller manages the main power supply and is connected to the ENABLE input pin of the DC/DC converter providing the main power supplies of the system.

Figure 3-10. Shutdown Controller

VDD MAIN 5V R3 100K R3402 STARTS Q1 BSS138 SOT23_123 GND POWER GND POWER SHDN 1 2 3 1 2 VDD 3V3 R4 10K R402 EN_1 C8 100fF C0402 GND POWER Q2 BSS138 SOT23_123

3.2.5 Push Button Switches

The SAMA5D2-PTC-EK features four push buttons:

• One board reset push button (BP3). When pressed and released, it causes a power-on reset of the board.
• One wakeup push button (BP4) connected to the SAMA5D2 WKUP pin, used to exit the processor from Low-Power mode.
  • One disable boot push button (BP2) used to devalidate the boot memories (refer to 3.2.8.3 CS Disable).

Figure 3-11. System Push Buttons

DIS BOOT DISABLE_BOOT → R145 100R-1% r0402 BP2 Tad Switch FSM2JISML RESET NRST → R146 100R-1% r0402 BP3 Tad Switch FSM2JISML WAKE UP WKUP → R147 100R-1% r0402 BP4 Tad Switch FSM2JISML VDDBU R238 10K R0402 GND_POWER

- One user push button (BP1) connected to PIO PB10.

Figure 3-12. User Push Button

PA10_USER_BT USER BUTTON R142.0K R0402 BPI TestSwitch FSM2J5ML OND_POWER

3.2.6 Clock Circuitry

The embedded microcontroller generates its necessary clocks based on two crystal oscillators: one slow clock (SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 24 MHz.

The SAMA5D2-PTC-EK board includes four clock sources:

• The two clocks mentioned above are alternatives for the SAMA5D2 processor (24 MHz, 32.768 kHz)
• One crystal oscillator for the Ethernet RMII chip (25 MHz)
• One crystal oscillator for the J-Link-OB microcontroller (12 MHz)

Figure 3-13. MPU Clock Circuitry

XIN R123 DNP R0402 XOUT Y1 24V/Hz CL=10pF x4s32x25 C96 20pF C0402 GND_POWER GND_POWER XOLT32 R122 DNP R0402 32.768KHz CL=12.5pF 4 1 3 2 C97 20pF C0402 X2 X4S70X15 C09 22pF C0402 GND_POWERGND

3.2.7 Memory

3.2.7.1 Memory Organization

The SAMA5D2 features a DDR/SDR memory interface and an External Bus Interface (EBI) to enable interfacing to a wide range of external memories and to almost any kind of parallel peripheral.

This section describes the memory devices mounted on the SAMA5D2-PTC-EK board:

• Two DDR2 SDRAMs
• One NAND Flash
  • One QSPI Flash
  • One SPI Flash (optional)
  • One serial EEPROM

Additional memory can be added to the board by:

• Installing an SD or MMC card in the SD/MMC0 or SD/MMC1 slot,
  • Using the USB-B port.

Support is dependent upon driver support in the OS.

3.2.7.2 DDR2/SDRAMs

Two DDR2/SDRAMs (W972GG6KB-25-2 Gbits = 16 Mbits x 16 x 8 banks) are used as main system memory, totalling 4 Gbits of SDRAM on the board. The memory bus is 32 bits wide and operates with a frequency of up to 166 MHz.

The figure below illustrates the implementation for the DDR2 memories.

Figure 3-14. DDR2 SDRAMs

One specific analog input, DDR_CAL, is used to calibrate all DDR I/Os.

Table 3-3. Calibration Cell DDR_CAL Value

Memory Resistor value
LPDDR2/LPDDR3 24K
DDR3L 23K
DDR3 22K
DDR2/LPDDR1 21K

Figure 3-15. DDR Signals and CAL Analog Input

DDR_A0 F12 DDR_A1 C17 DDR_A0 DDR_D6 DDR_A2 B17 DDR_A1 DDR_D1 DDR_A3 B16 DDR_A2 DDR_D2 DDR_A4 C16 DDR_A3 DDR_D3 DDR_A5 G14 DDR_A4 DDR_D4 DDR_A6 F14 DDR_A5 DDR_D5 DDR_A7 F11 DDR_A6 DDR_D6 DDR_A8 C54 DDR_A7 DDR_D7 DDR_A9 D13 DDR_A8 DDR_D8 DDR_A10 C55 DDR_A9 DDR_D9 DDR_A11 A16 DDR_A10 DDR_D10 DDR_A12 A17 DDR_A11 DDR_D11 DDR_A13 G11 DDR_A12 DDR_D12 DDR_BA0 H12 DDR_BA0 DDR_D13 DDR_BA1 H3 DDR_BA1 DDR_D14 DDR_BA2 F17 DDR_BA2 DDR_D14 DDR_CAS F13 DDR_CAS DDR_D15 DDR_CLK+ E17 DDR_CLKD DDR_D21 DDR_D22 DDR_CLK D17 DDR_CLKD DDR_D23 DDR_CKE F16 DDR_CKE DDR_D24 R25 100K DDR_CKE DDR_D25 R0402 GND_POWER DDR_CKE DDR_CKE DDR_D26 DDR_CS G13 DDR_CS DDR_D27 DDR_WE F15 DDR_WE DDR_D28 DDR_CAL E13 DDR_CAL DDR_D29 VDDIODDR 21K-1% R24 R3402 C64 C6402 22pF DDR_CSD DDR_DQM0 R23 100K R0402 C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C64C GND_POWER DDR_RESETN E16 DDR_RESETN DDR_RESETN DDR_VREFB0 DDR_VREFCOM DDR_DQS0 DDR_DQS0 DDR_DQS0 DDR_VREF C62 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63 C63

3.2.7.4 NAND Flash

The SAMA5D2-PTC-EK has native support for NAND Flash memory through its NAND Flash Controller. The board implements one MT29F4G08ABA 4Gb x 16 NAND Flash connected to Chip Select three (NCS3) of the microcontroller.

The NAND Flash interface is shared with the SDMMC1 and QSPI interfaces.

The figure below illustrates the NAND Flash memory implementation.

Figure 3-16. NAND Flash

On-board jumper JP8 controls the selection (CS#) of the NAND Flash memory.

3.2.8 Additional Memories

3.2.8.1 Serial Flash

The SAMA5D2 includes two high-speed Serial Peripheral Interface (SPI) controllers. The SPI is a full duplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists of the following items:

• a serial clock line (generated by the master)
• a data output line from the master
• a data input line to the master
• one or more active low Chip Select signals (output from the master)

One SPI port is used to interface with the on-board serial Flash.

The following figure illustrates the implementation of an SPI Flash memory.

Figure 3-17. Serial Flash

SPI0_MOSI_PA15 SPI0_MISO_PA16 SPI0_SPCK_PA14 SPI0_CS0_PA17 U16 5 2 6 1 SI SO BCK CS VCC TP HOLD GND SST26VF032B-T04USM soo8g 8 3 7 4 VDD_3V3 C119 100mF CD402 GND_POWER

Note: The serial Flash is optional and not mounted on board.

3.2.8.2 QSPI Serial Flash

The SAMA5D2 provides two Quad Serial Peripheral Interfaces (QSPI).

A QSPI is a synchronous serial data link that provides communication with external devices in Master mode.

The QSPI can be used in SPI mode to interface with serial peripherals (such as ADCs, DACs, LCD controllers, CAN controllers and sensors), or in Serial Memory mode to interface with serial Flash memories.

The QSPI allows the system to execute code directly from a serial Flash memory (XIP, or Execute In place, technology) without code shadowing to RAM. The serial Flash memory mapping is seen in the system as other memories (ROM, SRAM, DRAM, etc.).

With the support of the Quad SPI protocol, the QSPI allows the system to use high-performance serial Flash memories which are small and inexpensive, instead of larger and more expensive parallel Flash memories.

The figure below illustrates the implementation of a QSPI Flash memory.

Figure 3-18. QSPI Serial Flash

VDD_3V3 R186 10K R0402 R187 10K R0402 QSPI0_IO0_PA24 QSPI0_IO1_PA25 QSPI0_IO2_PA26 QSPI0_IO3_PA27 QSPI0_SCK_PA28 U14 Si/SiO0 VCC SO/SiO1 GND SiO2 CSW SiO3 SCLK SST26VF564B-104/SM soo8g VDD_3V3 R242 10K JP13 Header 1X2 QSPI0_CS_PA23 VDD_3V3 C120 100nF CD4E2 GND_POWER

A jumper (JP13) is used to disable the QSPI Flash.

Table 3-5. SPI and QSPI Signal Descriptions

PIO Signal Name Shared PIO Signal Description
PA14 SPI0_SPCK – SPI clock
PA15 SPI0_MOSI – Master out - Slave in
PA16 SPI0_MISO – Master in - Slave out
PA17 SPI0_NPCS0 – Chip Select
----
PA22 QSPI0_SCK SDMMC1-NAND Flash QSPI clock
PA23 QSPI0_CS	NAND Flash	Chip Select
......continued
PIO Signal Name Shared PIO Signal Description
PA24 QSPI0_IO0 NAND Flash Data0
PA25 QSPI0_IO1 NAND Flash Data1
PA26 QSPI0_IO2 NAND Flash Data2
PA27 QSPI0_IO3 NAND Flash Data3

3.2.8.3 CS Disable

On-board push button PB2 controls the selection (CS#) of the bootable memory components (QSPI and serial Flash) using a non-inverting 3-state buffer.

Figure 3-19. CS Disable

VDD_3V3 R178 10K C117 100nF R184 10K QSPI0_NPCS_PA23 U11 5 VCC 4 QSPI Flash CS GND GND_POWER GND_Power QSPI0_CS_PA23 BOOT_DIS DISABLE_BOOT U12 5 VCC 4 R185 10K SPi0_CS0_PA17 SPi0_NPCS0_PA17 GND_Power GND NL17SZ126DFT2G C116 100nF U12 5 VCC 4 SPi0_CS0_PA17 GND_Power

The rule of operation is:

- PB2 (DISABLE_BOOT) and PB3 (RESET) pressed = booting from QSPI or optional serial Flash is disabled.

Refer to the SAMA5D2 Series datasheet for more information on standard boot strategies and sequencing.

3.2.8.4 Serial EEPROM with Unique MAC Address

The SAMA5D2-PTC-EK board embeds one Microchip 24AA02E48 I²C serial EEPROM connected on the TWI1 interface.

The TWI interface is I²C-compatible and similarly uses only two lines, namely serial data (SDA) and serial clock (SCL). According to the standard, the TWI clock rate is limited to 400 kHz in Fast mode and 100 kHz in Normal mode, but configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. The TWI is used in Master mode.

The 24AA02E48 features 2048 bits of Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM) organized as 256 words of eight bits each and is accessed via an I²C-compatible (2-wire) serial interface. In addition, the 24AA02E48 incorporates an easy and inexpensive method to obtain a globally unique MAC or EUI address (EUI-48™).

The EUI-48 addresses can be assigned as the actual physical address of a system hardware device or node, or it can be assigned to a software instance. These addresses are factory-programmed by Microchip and guaranteed unique. They are permanently write-protected in an extended memory block located outside the standard 2-Kbit memory array.

The EEPROM device is used as a “software label” to store board information such as chip type, manufacturer name and production date, using the last two 16-byte blocks in memory. The information contained in these blocks should not be modified.

Table 3-6. EEPROM PIOs Signal Descriptions

PIO Signal Name Shared Signal Description
PC6 TWD1 XPRO TWI Data
PC7 TWCL1 XPRO TWI Clock

The figure below illustrates the implementation for the EEPROM.

Figure 3-20. EEPROM 24AA02E48

TWDI PC8 TWCK1_PCT GND POWER R16A 10K RD402 GND POWER U15 1 A0 2 A1 3 A2 5 SDA 6 BCL 7 WP VCC 8 GND 4 VDD_3V3 C11B 120uF CD452 24AA02E38 BMA2

3.2.9 Secure Digital Multimedia Card (SDMMC) Interface

The SD (Secure Digital) Card is a non-volatile memory card format used as a mass storage memory in mobile devices.

3.2.9.1 Secure Digital Multimedia Card (SDMMC) Controller

The SAMA5D2-PTC-EK board has two Secure Digital Multimedia Card (SDMMC) interfaces that support the MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 Specification.

• The SDMMC0 interface is connected to a standard SD card interface.
• The SDMMC1 interface is connected to a microSD card interface.

3.2.9.2 SDMMC0 Card Connector

A standard MMC/SD card connector, connected to SDMMC0, is mounted on the top side of the board. The SDMMC0 communication is based on a 12-pin interface (clock, command, data (8) and power lines (2)). A card detection switch is included.

The figure below illustrates the implementation for the SDMMC0 interface.

Figure 3-21. SDMMC0 Standard SD Socket

VDDSDHC R154 OR R0402 R155 68k R0603 R157 68k R0603 R158 68k R0603 R159 68k R0603 R161 68k R0603 R163 68k R0603 R165 68k R0603 R167 68k R0603 R169 10k R0402 R172 10k R0402 R173 10k R0402 C115 10uF D0003 C111 10nF D0402 GND_POWER SDMMC0_WP_PA12 (MCIO_WP) SDMMC0_CO_PA13 (MCIO_CD) SDMMC2_DAT1_PA3 (MCIO_DA1) SDMMC0_DAT0_PA2 (MCIO_DA0) SDMMC0_CK_PA9 (MCIO_CK) SDMMC0_CMD_PA1 (MCIO_CDA) SDMMC2_DAT3_PA5 (MCIO_DA3) SDMMC2_DAT2_PA4 (MCIO_DA2) SDMMC3_DAT4_PA6 (MCIO_DA4) SDMMC2_DAT5_PA7 (MCIO_DA5) SDMMC0_DAT6_PA8 (MCIO_DA6) SDMMC2_DAT7_PA9 (MCIO_DA7) VDDSDHC VDDSDHC VDDSDHC J6 8 7 6 5 4 3 2 1 9 7SDMM-SC-2211 con_kingscomm_7sdmm_2211 GND_POWER 16 15 14 13 12 11 10

Figure 3-22. Standard SD Socket J6 Location

J-Link Technology www.segger.com J9 L20 JLINK C156 U1 C1 JP1 MBUS PMM INT R X T S D SA SY GN J15B RST CS SCK MISO 3V3 GND J15A MICROBUS AN RST C5 SCK MISO 3V3 GND J15A C123 J8 C127 C125 R195 ETH R189 LCD J13 T3 C126 R195 C128 R182 U5 C15 C11 R244 U8 R243 U6 R244 U7 R243 U6 R242 U7 R241 U6 R240 U7 R239 U6 R238 U6 R237 U6 R236 U6 R235 U6 R234 U6 R233 U6 R232 U6 R231 U6 R230 U6 R229 L1 C4 L14 U20 R229 L1 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C4 C3 C3 A B C D E F G H I J K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K L K M K N L K l k k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k l k t a d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t a d o n t e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i v e r i j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j j jj x y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y z y

The table below describes the pin assignment of SD/MMC connector J6.

Table 3-7. Standard SD Socket J6 Pin Assignment

Pin No Signal Name Signal Description
1 MCI0_DA3 SDMMC0_DAT3_PA5
2 MCI0_CDA SDMMC0_CMD_PA1
3 GND GND
4 VCC VDDSDHC (3.3V or 1.8V)
5 MCI0_CK SDMMC0_CK_PA0
6 MCI0_CD SDMMC0_CD_PA13 (card detect)
7 MCI0_DA0 SDMMC0_DAT0_PA2
8 MCI0_DA1 SDMMC0_DAT1_PA3
9 MCI0_DA2 SDMMC0_DAT2_PA4
10 MCI0_DA4 SDMMC0_DAT4_PA6
11 MCI0_DA5 SDMMC0_DAT5_PA7
12 MCI0_DA6 SDMMC0_DAT6_PA8
13 MCI0_DA7 SDMMC0_DAT7_PA9
14 MCI0_WP SDMMC0_WP_PA12

......continued
Pin No Signal Name Signal Description
15 GND GND
16 GND GND

3.2.9.3 SDMMC0 VDDHC Voltage Switching

The board uses an ADG849 to switch the power line VDDSDHC_3V3 or VDDSDHC_1V8 through the command line SDMMC0_VDDSEL_PA11.

Figure 3-23. SDMMC0 VDDSDHC Voltage Switching

VDD_SV3 VDOSDHC1V8 R151 DNP R152 DNP R0402 R0402 VDD_3V3 U9 6 S2 4 S1 1 IN GND 3 ADGR40YKSZ-REEL SC73 GND_POWER 5 C107 100nF CS402 VDDSDHC SOMAC0_VDDSEL_PA11 R150 10k R0402 GND_POWER

Table 3-8. SDMMC1 Power Command

PIO Signal Name Signal Description
PA11 SDMMC0_VDDSEL Selects 3.3V or 1.8V

3.2.9.4 SDMMC1 Card Connector

A microSD card connector, connected to SDMMC1, is mounted on the top side of the board. The SDMMC1 communication is based on a 9-pin interface (clock, command, card detect, four data and power lines). A card detection switch is included. The microSD connector can be used to connect any microSD card for mass storage.

Figure 3-24. SDMMC1 microSD Socket

VDD_SV3 R160 10k R0422 R162 68k R0503 R164 68k R0503 R166 68k R0503 R168 68k R0503 R170 10k R0422 SDMMC1_CD_PA30 (MC11 CD) SDMMC1_DAT1_PA15 (MC11 DA1) SDMMC1_DAT0_PA18 (MC11 DA3) SDMMC1_CK_PA22 (MC11 CK) SDMMC1_CMD_PA28 (MC11 CDA) SDMMC1_DAT3_PA21 (MC11 GA3) SDMMC1_DAT2_PA26 (MC11 GA2) C109 10uF C3603 C108 T00uF CD422 GND_POWER J7 5.5V 6 7 8 9 PJS006-2123-0 GND_POWER Micro_SD_PJS006

Figure 3-25. microSD Socket J7 Location

J-Link Technology www.segger.com J9 L20 JLINK JP1 MBUS PKM INT RX TX SCL SDA 5V GND J15B AN RST CS SCK MOS1 3V3 GND J15A JP12 L18 R190 C123 JB C127 C126 R195 C124 C125 C126 C127 C128 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U38 U39 U40 U41 U42 U43 U44 U45 U46 U47 U48 U49 U50 U51 U52 U53 U54 U55 U56 U57 U58 U59 U60 U61 U62 U63 U64 U65 U66 U67 U68 U69 U70 U71 U72 U73 U74 U75 U76 U77 U78 U79 U80 U81 U82 U83 U84 U85 U86 U87 U88 U89 U90 U91 U92 U93 U94 U95 U96 U97 U98 U99 U100 U101 U102 U103 U104 U105 U106 U107 U108 U109 U110 U111 U112 U113 U114 U115 U116 U117 U118 U119 U120 U121 U122 U123 U124 U125 U126 U127 U128 U129 U130 U131 U132 U133 U134 U135 U136 U137 U138 U139 U140 U141 U142 U143 U144 U145 U146 U147 U148 U149 U150

The table below describes the pin assignment of microSD connector J7.

Table 3-9. microSD Socket J7 Pin Assignment

Pin No	Signal Name	PIO Shared Signal	Description
1	SDMMC1_DAT2	PA20 – Data bit 2
2	SDMMC1_DAT3	PA21 – Data bit 3
3	SDMMC1_CDA	PA28 – Command
4	VCC – - 3.3V supply voltage
5	SDMMC1_CK	PA22 – Clock
6	GND – – Common ground
7	SDMMC1_DAT0	PA18 – Data bit 0
8	SDMMC1_DAT1	PA19 – Data bit 1
9	SW1	GND – Not used
10	SDMMC1_CD	PA30 – Card detection switch
11	GND – – Common ground

Pin No Signal Name PIO Shared Signal Description
12 GND	-- Common ground
13 GND	-- Common ground
14 GND	-- Common ground

3.2.10 Communication Interfaces

The SAMA5D2-PTC-EK board is equipped with Ethernet and USB host/device communication interfaces. This section describes the signals and connectors related to the ETH and USB communication interfaces.

3.2.10.1 Ethernet 10/100 (GMAC) Port

The SAMA5D2-PTC-EK board features a Micrel PHY device (KSZ8081) operating at 10/100 Mb/s. The board supports RMII interface modes. The Ethernet interface consists of two pairs of low-voltage differential pair signals designated from GRX± and GTX± plus control signals for link activity indicators. These signals can be used to connect to a 10/100 Base-T RJ45 connector integrated on the SAMA5D2-PTC-EK board.

An individual 48-bit MAC address (Ethernet hardware address) is allocated to each product. This number is stored in the Microchip 24AA02E48 I2C serial EEPROM (refer to Serial EEPROM with Unique MAC Address).

Additionally, for monitoring and control purposes, a LED functionality is carried on the RJ45 connectors to indicate activity, link, and speed status.

For more information about the Ethernet controller device, refer to the Micrel KSZ8081RN controller manufacturer's datasheet.

Figure 3-26. Ethernet Interface

VDD_3V3 R197 R198 R199 R200 R203 1K 1K 10K 10K 10K R0402 R0402 R0402 R0402 TX+ top/bot 7 TX- top/bot 6 TXM RX+ top/bot 5 RX- top/bot 4 RXM C123 2uF C0803 C124 100uF C0492 VDD_1V2 GND PADDLE TXC TXD2 TXD3 REXT R194 6.49K 1% R0402 VDD_3V3/GND_POWER ETH_XO ETH_XI ETH_LED0 ETH_LED1 ETH_LED2 ETH_CMDIC_PB23 ETH_INT_PB24 ETH_GMX_PB19 ETH_GMX_PB18 ETH_GMX_PB17 ETH_GMX_PB16 ETH_GMX_PB15 ETH_GMX_PB14 ETH GTX1_PB21 ETH GTX_PB20 ETH GTXER_PB16 ETH GRX1_PB19 ETH GRX0_PB18 ETH GRX0_PB17 ETH GMDC_PB22 ETH INT_PB24 ETH GMDC_PB23 ETH INT_PB25 RXD/PHYAD0 RXD/PHYAD1 RXD/PHYAD2 RXD/DUPLEX RXDV/CONFIG2 RXER/ISO CRS/CONFIG1 COL/CONFIG0 VDD_3V3 L19 BLM16PG181SN1D VDD_3V3 VDDA_3V3 C127 C129 C129 10uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF 100uF C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402 C0503 C0402

Table 3-10. Ethernet PHY 10/100 Signal Descriptions

PIO Signal Name		Shared	Signal Description
PB14	ETH_GTXCK	-	Transmit clock
PB15	ETH_GTXEN	-	Transmit enable
PB16	ETH_GRXDV	-	Receive data valid

......continued
PIO Signal Name Shared Signal Description
PB17 ETH_GRXER _Receive error
PB18 ETH_GRX0 _Receive data 0
PB19 ETH_GRX1 _Receive data 1
PB20 ETH_GTX0 _Transmit data 0
PB21 ETH_GTX1 _Transmit data 1
PB22 ETH_GMDC _Management data clock
PB23 ETH_GMDIO _Management data in/out
PB24 ETH_GTX_INT _Interrupt (open drain)

Figure 3-27. Ethernet PHY Connector J8

JB 134-R43GYJ2/PL/NI 1 TX- 2 TX- 3 RX- 4 RX- 5 RX- 6 RX- 7 C121 C122 100uF 100uF C9402 C3402 GND_ETH EARTH_ETH 13 14 15 16 Right yellow LED Left Screen LED 8 FART-ETH VDD 3V0 R189 51C3 RD402 R190 51C3 RD402 10 Q45_13-64gy_P12_4 ACI ETH_LED1 LSPY ETH_LED0

Figure 3-28. Ethernet RJ45 Connector J8 Location

J-Link Technology www.segger.com J9 L20 JLINK C156 JP1 U1 C1 Q1 D0 D1 R217 R216 R229 L1 C4 C14 U20 R220 R221 R222 R223 R224 R225 R226 R227 R228 R229 R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R257 R258 R259 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R280 R281 R282 R283 R284 R285 R286 R287 R288 R289 R290 R291 R292 R293 R294 R295 R296 R297 R298 R299 R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 R310 SAMS1D0-PTC-EK Microchip.com/ microchip.com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. com/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. COM/ microchip. CONC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

The table below describes the pin assignment of Ethernet connector J8.

Table 3-11. Ethernet RJ45 Connector J8 Pin Assignment

Pin No Signal Name Signal Description
1 TX+ Transmit
2 TX- Transmit
3 RX+ Receive
4 Decoupling capacitor –
5 Decoupling capacitor –
6 RX- Receive
7 NC –
8 EARTH / GND Common ground
9 ACT LED LED activity
10 ACT LED LED activity
11 LINK LED LED link connection
12 LINK LED LED link connection
13 EARTH / GND Common ground
14 EARTH / GND Common ground

......continued
Pin No Signal Name Signal Description
15 NC –
16 NC –

3.2.10.2 USB Host/Device A, B

The USB (Universal Serial Bus) is a hot-pluggable general-purpose high-speed I/O standard for computer peripherals. The standard defines connector types, cabling, and communication protocols for interconnecting a wide variety of electronic devices. The USB 2.0 Specification defines data transfer rates as high as 480 Mbps (also known as High Speed USB). A USB host bus connector uses 4 pins: a power supply pin (5V), a differential pair (D+ and D-pins) and a ground pin.

The SAMA5D2-PTC-EK board features three USB communication ports named USB-A to USB-C:

- USB-A device interface

– One USB device standard micro-AB connector.
- This port has a VBUS detection function made through the R148-R149 resistor bridge.
- The USB-A port is used as a primary power source and as a communication link for the board, and derives power from the PC over the USB cable. In most cases, this port is limited to 500mA .

- USB-B (host port B high- and full-speed interface)

– One USB host type A connector.
- The USB-B host port is equipped with a 500mA high-side power switch to enable powering devices connected to it.

• UBC-C (High-Speed Inter-Chip/HSIC port)

– One USB high-speed host port with an HSIC interface.
- The port is connected to a single 2-pin jumper.

3.2.10.3 USB-A Interface

Figure 3-29. USB-A Type Micro-AB Connector J4 Location

J-Link Technology www.segger.com J9 L20 JLINK JP1 C12 U1 C1 Q1 D3 R217 D6 R216 R229 L1 C3 12 7 U2 6 C50 L18 JP12 L18 C123 J8 C127 U17 C126 R193 C125 R13 ETH R234 LCD J16 SAMA5D2-PTC-EK Rev B Microchip www.microchip.com J12 EXT2 XPRO J11 EXT1 PTC C17 J1 RST D6OOTT RST R1460 BP3 R248 TP3 JP5 R222 R251 U3 C6 TP7 C31 JP8 JP4 JP3 JP2 JP13 JP14 JP13 JP12 R242 U14 R186 U16 R184 U15 R17 L12 C40 R16 Le R44 X50 R44 R38 R35 R33 R31 R29 R27 R25 R23 R20 R18 R16 R14 R12 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R1 A R44 X50 U3 C6 TP7 C31 R248 TP3 JP5 R222 TIP7 C31 JP8 JP4 JP3 JP2 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 JP13 JP14 J10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

3.2.10.4 USB-A VBUS Detection

The USB-A port (J4) features a VBUS detection function provided by the R148-R149 resistor bridge.

The figure below shows the USB implementation on the USBA port.

Figure 3-30. USB-A Power and VBUS Detection

VBUS USBA R148 100K C103 20pF C0402 R0402 R149 200K R0402 GND_POWER USBDA DV USBDA DP GND_POWER USSB/MICRO5 6A MicroUSB AB Connector EARTH_USB_A

Table 3-12. USB-A PIO Signal Descriptions

PIO Signal Name Shared Signal Description
PB11 USBA_VBUS_5V – VBUS insertion detection

3.2.10.5 USB-B Interface

The figure below shows the USB implementation on the USB-B port.

Figure 3-31. USB-B Interface

5 SH1 VBUS DM DP GND SH2 1 2 3 4 USBB VBUS 5V USBS DM USBS DF GND_POWER J3 Single USB Type A USB4_2AL 6 EARTH USB_R

Figure 3-32. USB-B Type A Connector J3 Location

J-Link Technology www.segger.com J9 L20 JLINK C156 R245 R245 R224 R224 R222 R222 R221 R217 R216 R215 R214 R213 R212 R211 R210 R209 R208 R207 R206 R205 R204 R203 R202 R201 R200 R15B U15B JP1 MBUS PMM INT RX TX SCL SOA SV GND J15A AN RST C5 SCK MISO MOSI 3V3 GND J15A C3 C4 L14 U7 C5 C6 6 7 8 9 U20 R229 L1 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 U35 U36 U37 U38 U39 U40 U41 U42 U43 U44 U45 U46 U47 U48 U49 U50 U51 U52 U53 U54 U55 U56 U57 U58 U59 U60 U61 U62 U63 U64 U65 U66 U67 U68 U69 U70 U71 U72 U73 U74 U75 U76 U77 U78 U79 U80 U81 U82 U83 U84 U85 U86 U87 U88 U89 U90 U91 U92 U93 U94 U95 U96 U97 U98 U99 U100 U101 U102 U103 U104 U105 U106 U107 U108 U109 U110 U111 U112 U113 U114 U115 U116 U117 U118 U119 U120 U121 U122 U123 U124 U125 U126 U127 U128 U129 U130 U131 U132 U133 U134 U135 U136 U137 U138 U139 U140

Table 3-13. USB-B PIO Signal Descriptions

PIO Signal Name Shared Signal Description

PB12 USBB_EN_5V – Power switch enable (active high)

PB13 USBB_OVCUR – Indicates overcurrent (open drain)

3.2.10.5.1 USB-B Power Switch

The USB-B Host port is equipped with a 500 mA high-side power switch for self-powered and bus-powered applications. If the client device is bus-powered, the carrier can supply a 5V, 500mA power to the client device. The USBB_EN_5V_PB12 signal controls the power switch and current limiter, the Micrel MIC2025, which in turn supplies power to a bus-powered client device. Per the USB specification, bus-powered USB 2.0 devices are limited to a

maximum of 500 mA. The MIC2025 limits the current and indicates an overcurrent with the USBB_OVCUR_PB13 signal.

The table below describes the pin assignment of the USB-A and USB-B connectors.

Table 3-14. USB-A and USB-B Connector Signal Descriptions

Pin No Signal	Name Signal Description
1 VBUS 5V	power
2 DM Data	minus
3 DP Data	plus
4 ID On-the-go identification
5 GND	Common ground

3.2.10.6 HSIC

High-Speed Inter-Chip (HSIC) is a standard for USB chip-to-chip interconnect with a 2-signal (strobe, data) source synchronous serial interface using 240 MHz DDR signaling to provide only high-speed 480 Mbps data rate.

The interface operates at high speed, 480 Mbps, and is fully compatible with existing USB software stacks. It meets all data transfer needs through a single unified USB software stack.

The HSIC interface is not used on the board and is connected to two-point jumper J5 (not mounted).

Figure 3-33. HSIC Interface

3.3 External Interfaces

3.3.1 LCD TFT Interface

This section describes the signals and connectors related to the LCD interface.

3.3.1.1 LCD Interface

The SAMA5D2-PTC-EK board provides a connector with 18 bits of data and control signals to the LCD interface. Other signals are used to control the LCD and are available on connector J16: TWI, SPI, two GPIOs for interrupt, 1-wire and power supply lines.

This connector is used to connect LCD display series 43xx or 70xx from PDA.

3.3.1.2 LCD Expansion Header

J16 is a 1.27-mm pitch, 50-pin header. It gives access to the LCD signals.

Figure 3-34. LCD Expansion Header Interface

SPI_CS_PB31 R234 100R-1% R5422 J6 ID GND1 D0 D1 D2 D3 GND2 D4 D5 D6 D7 GND3 D8 D9 D10 D11 GND4 D12 D13 D14 D15 GND5 D16 D17 GND6 D18 D19 GND7 PCLK/CMD VSYNC/CS HSYNC/WE DCRE SPI_SCK SPI_MOSI SPI_MISO SPI_CS ENABLE TWI_SDA TWI_SCL IRQ1 IRQ2 PWM RESET VCC1 VCC2 GND6 XF2M-5015-1A FPC50-0p5mm R230 DNP R0803 R231 JR R0803 VDD_3V3VDD_MAIN-LCD_PWM_PC26 NRST GND_POWER

3.3.1.3 LCD Power

In order to operate correctly with various LCD modules, two voltage lines are available: 3.3V and 5VCC (default). The selection is made with 0R resistors R230 and R231.

3.3.1.4 LCD Connector JX

Figure 3-35. LCD Connector J16 Location

-Link Technology www.segger.com J9 L20 JLINK JP1 C12 U4 PWM INT RX TX SCL SDA 5V GND J1SB AN RST CS SCK MISO MS1 3V3 GND J15A J16 LCD ETH MICROCHIP R230 Rev B J12 EXT2 J11 EXT1 XPRO SAMA5D2-PTC-EK Microchip R234 L3 L6 Y3 J13 U17 R197 C16 R244 R183 U8 R243 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R244 R24 J10 JP11 D5 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R22 R23 R186 U16 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 U15 VSD C156 C70 C74 K E A J07 C69 C80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R80 R69 C69 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 C80 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 D37 AUSBB R146BP3 BP3 BP2 BP1 BP1 BP0 BP9 BP8 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 BP9 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 BP9 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 BP9 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 BP9 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 BP9 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 BP9 BP7 BP6 BP5 BP4 BP4BP3BP2BP1BP0BP9BP7BP6BP5BP4BP3BP2BP1BP0BP9BP7BP6BP5BP4BP3BP2BP1BP0BP9BP7BP6BP5BP4BP3BP2BP1BP1BP0BP9BP7BP6BP5BP4BP3BP2BP1BP1BP0BP9BP7BP6BP5BP4BP3BP2BP1BP1BP0BP9BP7BP6BP5BP4BP3BP2BP1BP1BP0BP9BP7BP6BP5BP4BP3BP2BP1BP1BP0BP9BP7BP6BP5BP4BP3BP2BP JTAG RST DBOOT U13 JP6 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C65 C 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. 6. U18 R197 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 U19 C70 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T C74 K E A J07 C69 K E A J07 C80 K E A J07 C89 K E A J07 C90 K E A J07 C91 K E A J07 C92 K E A J07 C93 K E A J07 C94 K E A J07 C95 K E A J07 C96 K E A J07 C97 K E A J07 C98 K E A J07 C99 K E A J07 C100 K E A J07 C101 K E A J07 C102 K E A J07 C103 K E A J07 C104 K E A J07 C105 K E A J07 C106 K E A J07 C107 K E A J07 C108 K E A J07 C109 K E A J07 C110 K E A J07 C111 K E A J07 C112 K E A J07 C113 K E A J07 C114 K E A J07 C115 K E A J07 C116 K E A J07 C117 K E A J07 C118 K E A J07 C119 K E A J07 C120 K E A J07 C121 K E A J07 C122 K E A J07 C123 K E A J07 C124 K E A J07 C125 K E A J07 C126 K E A J07 C127 K E A J07 C128 K E A J07 C129 K E A J07 C130 K E A J07 C131 K E A J07 C132 K E A J07 C133 K E A J07 C134 K E A J07 C135 K E A J07 C136 K E A J07 C137 K E A J07 C138 K E A J07 C139 K E A J07 C140 K E A J07 C141 K E A J07 C142 K E A J07 C143 K E A J07 C144 K E A J07 C145 K E A J07 C146 K E A J07 C147 K E A J07 C148 K E A J07 C149 K E A J07 C150 K E A J07 C151 K E A J07

The table below describes the pin assignment of LCD FPC connector J16.

Table 3-15. LCD Connector J16 Signal Descriptions

Pin No	Signal PIO Signal RGB Interface Function
1	ID PB31_ID LCD module
2	GND – GND GND
3	LCDDAT0 – D0 –
4	LCDDAT1 – D1 –
5	LCDDAT2 PC10 D2 Data line
6	LCDDAT3 PC11 D3 Data line
7	GND – GND GND
8	LCDDAT4 PC12 D4 Data line
9	LCDDAT5 PC13 D5 Data line
10	LCDDAT6 PC14 D6 Data line
11	LCDDAT7 PC15 D7 Data line
12	GND – GND GND
Pin No Signal PIO Signal RGB Interface Function
13 LCDDAT8 – D8 –
14 LCDDAT9 – D9 –
15 LCDDAT10 PC16 D10 Data line
16 LCDDAT11 PC17 D11 Data line
17 GND GND GND		GND
18 LCDDAT12 PC18 D12 Data line
19 LCDDAT13 PC19 D13 Data line
20 LCDDAT14 PC20 D14 Data line
21 LCDDAT15 PC21 D15 Data line
22 GND – GND	GND
23 LCDDAT16 – D16 –
24 LCDDAT17 – D17 –
25 LCDDAT18 PC22 D18 Data line
26 LCDDAT19 PC23 D19 Data line
27 GND – GND	GND
28 LCDDAT20 PC24 D20 Data line
29 LCDDAT21 PC25 D21 Data line
30 LCDDAT22 PC26 D22 Data line
31 LCDDAT23 PC27 D23 Data line
32 GND – GND	GND
33 LCDPCK	PD0 PCLK	Pixel clock
34 LCDVSYNC	PC30 VSYNC/CS	Vertical sync
35 LCDHSYNC	PC31 HSYNC/WE	Horizontal sync
36 LCDDEN	PD1 DATA_ENABLE	Data enable
37 SPI_SPCK	PB30 SPI_SCK	-
38	SPI_MOSI	PB28	SPI_MOSI	(Shared with TWI)
39	SPI_MISO	PB29	SPI_MISO	(Shared with TWI)
40 SPI_NPCS0	PB31 SPI_CS	-
41 LCDDISP	PC29 ENABLE	Display enable signal
42	TWD	PB28	TWI_SDA	I2C data line (maXTouch)
43	TWCK	PB29	TWI_SCL	I2C clock line (maXTouch)
44	GPIO	PC9	IRQ1	maXTouch interrupt line
45	GPIO	PD2	IRQ2	Interrupt line for other I2C devices
46 LCDPWM	PC28 PWM	Backlight control
47	RESET	-	RESET	Reset for both display and maXTouch

......continued
Pin No Signal PIO Signal RGB Interface Function
48 Main_5V/3.3V VCC VCC	3.3V or 5V supply (0R)
49 Main_5V/3.3V VCC VCC	3.3V or 5V supply (0R)
50 GND – GND GND

3.3.2 RGB LED

The SAMA5D2-PTC-EK board features one RGB LED which can be controlled by the user. The three LED cathodes are controlled via GPIO PWM or timer/counter pins.

Figure 3-36. RGB LED Indicators

LED LED RED PS10 > R181 100R-1% V R0402 1 3 Q5 BSS136 SOT25_123 2 GND_POWER 3 Q7 BSS138 SOT23_123 1 2 GND_POWER 3 Q9 BSS136 SOT23_123 1 2 GND_POWER 3 R239 2.2K-1% R0402 1 R240 1K R0402 4 Blue R241 1K R0402 3 CLV1A-FKB-CJTM1F1BB7RAS3 2 VDD_3V3 LED GREEN PS8 > R182 100R-1% V R0402 1 3 Q7 BSS138 SOT23_123 1 2 GND_POWER 3 Q9 BSS136 SOT23_123 1 2 GND_POWER 3 R243 10K GND_POWER LED BLUE PS6 > R183 100R-1% V R0402 1 3 Q9 BSS136 SOT23_123 1 2 GND_POWER

Table 3-16. RGB LED PIOS

Signal PIO	Function
LED_RED	PB10	TIOB3
LED_GREEN	PB8	PWML3
LED_BLUE	PB6	PWML2

3.4 Debugging Capabilities

The SAMA5D2-PTC-EK includes two main debugging interfaces to provide debug-level access to the SAMA5D2:

• One UART through USB J-Link-CDC
- Two JTAG interfaces, one connected directly to the MPU using connector J2 and one through the J-Link-OB interface USB port J9

3.4.1 Debug JTAG

This section describes the signals and connectors related to the JTAG interface.

A 10-pin JTAG header is provided on the SAMA5D2-PTC-EK board to facilitate software development and debugging using various JTAG emulators. The interface signals have a voltage level of 3.3V.

Figure 3-37. JTAG Interface

VDD 3V3 R140 R141 R142 100K 100K 100K R0402 R0402 R0402 R138_DWR R236 10K R0402 GND_POWER GND_POWER J2 1 2 3 4 5 6 7 8 9 10 Header 2X5 FTSH-105.01-F.DV-P.TR R143 J09K-1% R0402 CON _ITAG_Pn2 CON _ITAG_Pn4 CON _ITAG_Pn6 CON _ITAG_Pn8RTCH NRST

Figure 3-38. JTAG Connector J2 Location

J-Link Technology www.segger.com J9 L20 JLINK C156 U1 C1 Q17 R213 D1 R216 R229 L1 C3 12 7 U5 6 C510 L18 R190 C123 J6 U17 C127 C125 C126 R195 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 C164 C165 C166 C167 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 C184 C185 C186 C187 C188 C189 C190 C191 C192 C193 C194 C195 C196 C197 C198 C199 C200 C201 C202 C203 C204 C205 C206 C207 C208 C209 C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 C222 C223 C224 C225 C226 C227 C228 C229 C230 C231 SAMA5D2-PTC-EK Microchip www.microchip.com/Rev B LCD LCD Microchip EXT2 EXT1 XPRO LCD LCD Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip Microchip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip MicroChip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro Chip Micro

The table below describes the pin assignment of JTAG connector J2.

Table 3-17. JTAG/ICE Connector J2 Pin Assignment

Pin No	Signal Name Signal Description
1	VTref. 3.3V power This is the target reference voltage (main 3.3V).
2	TMS TEST MODE SELECT JTAG mode set input into target CPU
3	GND Common ground
......continued
Pin No	Signal Name Signal Description
4	TCK TEST CLOCK - Output timing signal, for synchronizing test logic and control register access	JTAG clock signal into target CPU
5 GND Common ground
6	TDO JTAG TEST DATA OUTPUT - Serial data input from the target	JTAG data output from target CPU
7	RTCK - Input return test clock signal from the target	Some targets with a slow system clock must synchronize the JTAG inputs to internal clocks. In the present case, such synchronization is unneeded and TCK is merely looped back into RTCK.
8	TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal	JTAG data input into target CPU
9 GND Common ground
10 nRST RESET Active-low reset signal. Target CPU reset signal.

3.4.2 Embedded Debugger (J-Link-OB) Interface

The SAMA5D2-PTC-EK includes a built-in SEGGER J-Link-On-Board device. The functionality is implemented with an ATSAM3U4C microcontroller in an LFBGA100 package. The ATSAM3U4C provides the functions of JTAG and a bridge USB/Serial debug port (CDC). One two-colored LED (D6) mounted near the SAM3 chip (U20) shows the status of the J-Link-On-Board device.

J-Link-OB-ATSAM3U4C was designed in order to provide an efficient, low-cost, on-board alternative to the standard J-Link.

The USB J-Link-OB port is used as a secondary power source and as a communication link for the board, and derives power from the PC over the USB cable. This port is limited in most cases to 500 mA. A single PC USB port is sufficient to power the board.

Figure 3-39. J-Link-OB Interface

VDD_3V3_3U R206 19K R402 D5 PME C6010CECAX xo1123 GND_POWER C132 10F C0402 VDD_3V3_3U C156 100F C0402 GND_POWER VCC Out 3 GND NC ASC-12.00MHz-Cc-T VDD_3V3_3U VRUS_JLINK VBRIS DM -3 DP -4 GND -5 MicroUSB AB Connector USDMICRO5_6A EARTH_USB_EDBC VDD_3V3_3U JP11 Header_D2 ERASE 3U TDI 3U B3 TDO 3U B8 TCK 3U A7 TNS 3U C7 ERASE 3U D6 VDD_3V3_3U J3 K2 NRST 3U R209 100R-1% R402 GND_POWER C136 10F C0402 R213 DNP R214 R402 R215 R402 C107 10F C0402 R215 10K R402 R21LJR R402 R21LJR R402 D7 C9 A1 A10 B10 HDHG_XIN A2 A3 D8 VDD_3V3_3U R215 10K R402 D2 D1 C1 D1 DHSDM DFSDM DFSDP D1SOP VDDENI VDDUTM A8 A9 A10 VDDOUT L VDDCORE 1 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 4 VDDCORE 5 VDDENI VDDUTM C10 R2 B3 A8 A9 A10 VDDIN I VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN OUT VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN IN VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN In VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN VDDIN IN GND_POWER VINCE 3U R215 150R-1% R217 150R-1% R0432 R0432 D6 LED1_3U R215 150R-1% RED KPT8-1815 LED2_3U R217 150R-1% Gross KPT8-1815 VINCE 3U TDI/TRACE/SWG TOK/SWCLK TMSS/WNDG ERIASE ADVREF AD126VREF NRST NRST TST JTAGSH VBG XINT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT XOUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X Out X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUT X OUTX PAINPCAMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PA5PGMMK PA6PGMMK PA7PGMMK PA8PGMMK PA9PGMMK PA10PGMDI PA10PGMDI PA11PGMDI PA11PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PAINPCAMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PA5PGMMK PA6PGMMK PA7PGMMK PA8PGMMK PA9PGMMK PA10PGMDI PA10PGMDI PA11PGMDI PA11PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PA2P/GMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PA5PGMMK PA6PGMMK PA7PGMMK PA8PGMMK PA9PGMMK PA10PGMDI PA10PGMDI PA11PGMDI PA11PGMDI PA12PGMDI PA12PGMDI PA12PGMDI PAINPCAMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PA5PGMMK PA6PGMMK PA7PGMMK PA8PGMMK PA9PGMMK PAINPCAMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PA5PGMMK PA6PGMMK PA7PGMMK PA8PGMMK PAINPCAMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PA5PGMMK PA6PGMMK PA7PGMMK PAINPCAMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PA5PGMMK PA6PGMMK PAINPCAMNCMD PA1P-GMNDY PA2P-GMNOE PA3P-GPMNVID PA4PGMMO PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPCAMNCMD PAINPC AMCUA CPU TA SANBUCA/CU TFGGA/DCG GND_POWER

Jumper JP10 disables the J-Link-OB-ATSAM3U4C JTAG functionality. When the jumper is installed, it grounds pin 26 of the ATSAM3U4C that is normally pulled high. A quad analog switch is used to select the JTAG interface.

• Jumper JP10 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.
• Jumper JP10 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG controller can be used through the 10-pin JTAG port J2.

Jumper JP10 disables only the J-Link functionality. The debug serial com port that is emulated through a Communication Device Class (CDC) of the same USB connector remains operational (if JP9 is open).

Figure 3-40. Enabling/Disabling J-Link-OB and J-Link-CDC

JP9 Header 1X2 N GND_POWER PA25_3U JTAG-CD3_disable JP10 Header 1X2 N GND_POWER PA26_3U JTAG-OS_disable VDD_3V3_3U R224 10K H0402 VDD_3V3_3U R225 10K H0402

Figure 3-41. JTAG Switch

VDD 3VS 3U TDIOUT R218_150R-1% TDIIN 15 VCC JTAG_TDI_PD28 16 COMA NCA CON_JTAG_Pin8 1 NCA PA26_3U 2 ABIN CDIN TDOIN 3 NOB NCC CON JTAG Pin4 JTAG_TDO_PD29 4 COMB COMD R222_150R-1% CON_JTAG_Pin5 5 NOB COMC R3402 TCKOUT NLA53898MNTWG TMSOUT WQFN-16 R3402 TMSIN GND_POWER 14 13 12 11 10 9 8 7 VCC NCA COMA NCA ABIN NCB COMB NCB GND OND_POWER

3.4.3 Hardware UART via CDC

In addition to the J-Link-OB functionality, the ATSAM3U4C microcontroller provides a bridge to a debug serial port (UART DBGU) of the SOM's processor. The port is made accessible over the same USB connection used by JTAG by implementing Communication Device Class (CDC), which allows terminal communication with the target device.

This feature is enabled only if the SAM3U/PA25 (pin K10) is not grounded. The pin is normally pulled high and controlled by jumper JP9.

• Jumper JP9 not installed: the J-Link-CDC is enabled and fully functional.
• Jumper JP9 installed: the J-Link-CDC device is disabled.

The USB Communications Device Class (CDC) enables conversion of the USB device into a serial communication device. The target device running USB-Device CDC is recognized by the host as a serial interface (USB2COM, virtual COM port) without the need to install a special host driver (since the CDC is standard). All PC software using a COM port work without modifications with this virtual COM port. Under Windows, the device shows up as a COM port; under Linux®, as a /dev/ACMx device. This enables the user to use host software which was not designed to be used with USB, such as a terminal program.

Table 3-18. Debug COM Port PIOs Signal Descriptions

PIO Signal Name Shared Signal Description
PB26 URXD0 – Receive data
PB27 UTXD0 – Transmit data

Figure 3-42. J-Link-OB and CDC USB Connector J9 Location

J-Link Technology www.segger.com J9 JLINK C156 JP1 C12 U4 R245 R217 R216 R229 L1 C3 12 7 U2 6 C5 L2 C15 C11 U5 R197 R202 R204 C128 C123 J8 C127 U17 R195 C125 J13 T3 ETH R189 LCD J16 SAMA5D2-PTC-EK Microchip www.microchip.com R230 R231 J12 EXT2 XPRO J11 EXT1 PTC J14 PIOBU C17 J1 PPOB C97 R134 R133 R147 R238 R233 R56 R59 R57 R90 R91 R244 R183 R243 R182 R181 R244 R180 R243 R182 R243 R180 R244 R180 R244 R180 R244 R180 R244 R180 R244 R180 R244 R180 R244 R180 R244 R180 R244 R180 R244 R180 R245 U7 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C69 C68

The table below describes the pin assignment of USB connector J9.

Table 3-19. USB Connector J9 Pin Assignment

Pin No Signal	Name Signal Description
1 VBUS 5V	power
2 DM Data minus
3 DP Data plus
4 ID Not used
5 GND Common ground

3.4.3.1 Board Edge Connector

This connector is used to upgrade or download code to the ATSAM3U4C microcontroller J-Link-OB.

3.5 PIO Usage on Expansion Connectors

3.5.1 PIOBU Interface

The SAMA5D2-PTC-EK board features eight tamper pins for static or dynamic intrusion detection, UART reception, and two analog pins for comparison.

For a description of intrusion detection, refer to the SAMA5D2 datasheet, chapter "Security Module".

Figure 3-43. PIOBU Connector

FIOBUS R124 330R R5402 R129 330R R402 FIOBUS R126 330R R402 FIOBUS R126 330R R5402 ACP R126 330R R402 FTSH-10501-FDV-P-TR GND_POWER I1 DNP 2 4 5 6 7 8 9 10 R132 330R R402 R131 330R R5402 R132 330R R5402R127 330R R5402 FIOBUS FIOBUS R124 330R R5402 R129 330R R402 FIOBUS R126 330R R402 FIOBUS R126 330R R5402 ACP R126 330R R402 FTSH-10501-FDV-P-TR GND_POWER

Figure 3-44. PIOBU Connector J1 Location

J-Link Technology www.segger.com J0 L20 JLINK C156 JP1 C12 U4 R217 D1 +D3 +D6 +D9 +D10 +D11 +D12 +D13 +D14 +D15 +D16 +D17 +D18 +D19 +D20 +D21 +D22 +D23 +D24 +D25 +D26 +D27 +D28 +D29 +D30 +D31 +D32 +D33 +D34 +D35 +D36 +D37 +D38 +D39 +D40 +D41 +D42 +D43 +D44 +D45 +D46 +D47 +D48 +D49 +D50 +D51 +D52 +D53 +D54 +D55 +D56 +D57 +D58 +D59 +D60 +D61 +D62 +D63 +D64 +D65 +D66 +D67 +D68 +D69 +D70 +D71 +D72 +D73 +D74 +D75 +D76 +D77 +D78 +D79 +D80 +D81 +D82 +D83 +D84 +D85 +D86 +D87 +D88 +D89 +D90 +D91 +D92 +D93 +D94 +D95 +D96 +D97 +D98 +D99 +D100 + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Microchip www.microchip.com/

The table below describes the pin assignment of PIOBU connector J1.

Table 3-20. PIOBU Connector J1 Pin Assignment

Signal Pin No. Signal
PIOBU0 1 2 PIOBU3
PIOBU2 3 4 PIOBU5
PIOBU4 5 6 RXD
PIOBU6 7 8 ACN
ACP 9 10	GND

3.5.2 mikroBUS Interface

The SAMA5D2-PTC-EK hosts a pair of 8-pin female headers as mikroBus interface. The mikroBUS interface defines the main board sockets and add-on boards used for interfacing microprocessors with integrated modules with proprietary pin configuration and silkscreen markings. The pinout consists of three groups of communication pins (SPI, UART and TWI), four additional pins (PWM, interrupt, analog input and reset) and two power groups (+3.3V and GND on the left, and 5V and GND on the right 1x8 header).

Figure 3-45. mikroBUS Interface

AN-AD6 MBUS_RST-PC05 NPCSO-PC04 SPCK-PC01 MISO-PC03 MOSS-PC02 VDD_3V3 SD23 SD22 SDC20 SDC21 SDC28 SDC29 SDC30 SDC31 SDC32 SDC33 SDC34 SDC35 SDC36 SDC37 SDC38 SDC39 SDC40 SDC41 SDC42 SDC43 SDC44 SDC45 SDC46 SDC47 SDC48 SDC49 SDC50 SDC51 SDC52 SDC53 SDC54 SDC55 SDC56 SDC57 SDC58 SDC59 SDC60 SDC61 SDC62 SDC63 SDC64 SDC65 SDC66 SDC67 SDC68 SDC69 SDC70 SDC71 SDC72 SDC73 SDC74 SDC75 SDC76 SDC77 SDC78 SDC79 SDC80 SDC81 SDC82 SDC83 SDC84 SDC85 SDC86 SDC87 SDC88 SDC89 SDC90 SDC91 SDC92 SDC93 SDC94 SDC95 SDC96 SDC97 SDC98 SDC99 SDC100 J16A J16B J16B_PDW_PD20 INT_PD19 RX_PD23 TX_PD24 TWCK0_PD22 TVD0_PD21 VDD_MAIN_5V

Figure 3-46. mikroBUS Connector J15 Location

J-Link Technology www.segger.com J0 L20 JLINK C156 U1 C1 R21203 R217 U20 R216 R29 L1 U7 C4 L14 S U5 R182 U6 Q6 R244 U8 C15 C11 R243 U7 C15 C18 R181 R182 R244 U6 C69 R239 R240 R241 R243 R239 R232 R232 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R239 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R238 R237 R14660000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 JSTAG JP11 10 15 18 21 24 27 31 34 37 41 44 47 51 54 57 61 64 67 71 74 77 81 84 87 91 94 97 101 104 107 111 114 117 121 124 127 131 134 137 141 144 147 151 154 157 161 164 167 171 174 177 181 184 187 191 194 197 199 203 206 211 214 217 221 224 227 231 234 237 241 244 247 251 254 257 261 264 267 271 274 277 281 284 287 291 294 297 301 304 307 311 314 317 321 324 327 331 334 337 341 344 347 351 354 357 361 364 367 371 374 377 381 384 387 391 394 397 401 404 407 411 414 417 421 424 427 431 434 437 441 444 447 451 454 457 461 464 467 471 474 477 481

The table below describes the pin assignment of mikroBUS1 connector J15.

Table 3-21. mikroBUS Connector J15 Pin Assignment

SAMA5D27						SAMA5D27
Function PIO PIO Function MBUS Signal Pin No MBUS Signal
Analog input PD25 AN 1 1 PWM PD20 PWM
Reset PC05 RST 2 2 INT PD19 Interrupt
SPI Chip Select	PC04	SPI_NPCS	3	3	UART_RX	PD23	UART receive
SPI clock	PC01	SPI_SPCK	4	4	UART_TX	PD24	UART transmit
SPI MISO	PC03	SPI_MISO	5	5	TWI_SCL	PD22	TWI clock
SPI MOSI	PC02	SPI_MOSI	6	6	TWI_SDA	PD21	TWI data
3.3VCC	-	3.3V Supply	7	7	5V Supply	-	5VDD
......continued
SAMA5D27						SAMA5D27
Function PIO PIO Function MBUS Signal Pin No MBUS Signal
GROUND – GND 8 8 GND _ GROUND

The SAMA5D2-PTC-EK board hosts two connectors to interface XPRO QT boards. The QTouch Xplained Pro are extension boards that enable evaluation of Self-capacitance and Mutual capacitance modes using the Peripheral Touch Controller (PTC). The boards show how easy it is to design a capacitive touch board solution using the PTC without the need for any external components.

Nevertheless, the PTC IO pins available on XPRO connectors can be used as GPIO pins. Each of these can be configured as an input or output pin according to the PIO peripheral functions.

The GPIO voltage levels depend on the VDDIOP level supported by the SAMA5D2, 3.3V in this case.

Figure 3-47. XPRO EXT1 Connector

PTC_YLINE0 PTC_YLINE2 XPRO1_GPIO_PB9 PTC_YLINE4 XPRO_P08 PTC_YLINES R226 0R PD11 PD13 PD15 PD17 PD26 J11 3 2 4 PD12 5 PD14 6 PD16 7 7 8 PC0 9 PD18 10 12 7CP6CP 11 14 13 16 PD18 14 18 PD17 15 20 VDD_3V3 16 22 DNP 17 24 R227 18 26 R235 0R XPRO2_GPIO_PD31 GND_POWER Header 2X10

Figure 3-48. XPRO EXT1 Connector J11 Location

J-Link Technology www.segger.com J9 L20 JLINK JP1 MBUS PWM INT RX TX SCL SDA 5V GND J15B AN RST CS SK MT50 MOS1 3V3 GND J15A JP12 L18 R190 ETH C123 J0 C127 U17 C126 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R19 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C12B U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17 C125 R190 C128 U17

The following table describes the pin assignment of XPRO EXT1 connector J11.

Table 3-22. XPRO EXT1 Connector J11 Pin Assignment

SAMA5D27						SAMA5D27
Function PIO	PIO Function	XPRO Signal Pin No XPRO Signal
- Not used ID 1 2 GND - GROUND
PTC_YLINE0	PD11	ADC(+)	3	4	ADC(-)	PD12	PTC_YLINE1
PTC_YLINE2	PD13	GPIO	5	6	GPIO	PD14	PTC_YLINE3
GPIO	PA10	PWM(+)	7	8	PWM(-)	PC0	GPIO
PTC_YLINE4	PD15	IRQ/GPIO	9	10	SPI_SS_B/GPIO	PD16	PTC_YLINE5
XPRO_TWD	PC6	TWI_SDA	11	12	TWI_SCL	PC7	XPRO_TWCK
-	-	UART_RX	13	14	UART_TX	-	-
PTC_YLINE6	PD17	SPI_SS_A	15	16	SPI_MOSI	PD18	PTC_YLINE7
GPIO	PD26	SPI_MISO	17	18	SPI_SCK	PD31 or PD17	PTC_YLINE6
GROUND	-	GND	19	20	3.3VCC	-	3.3V Supply

Figure 3-49. XPRO EXT2 Connector

PTC_XLINE0 PTC_XLINE1 PTC_XLINE2 PTC_XLINE3 PTC_XLINE4 PTC_XLINE5 PTC_XLINE6 XPRO2_GPIO_PB25 GND_POWER Header 2X10 J12 1 3 5 7 9 11 13 15 17 19 20 2 4 6 8 10 12 14 16 18 20 XPROI R235 OR PTC_XLINE1 PTC_XLINE2 PTC_XLINE3 PTC_XLINE4 PTC_XLINE5 PTC_XLINE6 PTC_XLINE7 PTC_XLINE8 PTC_XLINE9 PTC_XLINE10 XPRO2_GPIO_PD31 VDD_3V3

Figure 3-50. XPRO EXT2 Connector J12 Location

J-Link Technology www. segger.com J0 L20 JLINK JP1 MBUS PWM INT RX TX SCL SDA SV GND J15B AN RST CS SOX MISO MOS1 3V3 GND J15A C3 C4 L14 U7 C20 C28 R K E A U6 R44 R46 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105 C106 L15 4 CI03 USBA ETH MICROCHIP WWW.microchip.com LCD SAMA5D2-PTC-EK Rev B EXT2 XPRO J11 EXT1 PTOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPOBU PPO BU XPRO

The table below describes the pin assignment of XPRO EXT2 connector J12.

Table 3-23. XPRO EXT2 Connector J12 Pin Assignment

SAMA5D27						SAMA5D27
Function PIO PIO Function		XPRO Signal	Pin No XPRO Signal
- Not used ID 1 2 GND - GROUND
PTC_XLINE0	PD3 ADC(+) 3	4 ADC(-) PD4	PTC_XLINE1
PTC_XLINE2	PD5 GPIO 5 6	GPIO PD6	PTC_XLINE3
PTC_XLINE4	PD7 PWM(+) 7 8	PWM(-)		PD8 PTC_XLINE5
PTC_XLINE6	PD9	IRQ/GPIO	9	10	SPI_SS_B/GPIO	PD10	PTC_XLINE7
-	-	TWI_SDA	11	12	TWI_SCL	PD31	GPIO
-	-	UART_RX	13	14	UART_TX	-	-
GPIO	PB25	SPI_SS_A	15	16	SPI_MOSI	-	-
-	-	SPI_MISO	17	18	SPI_SCK	-	-
GROUND - GND		19	20 3.3VCC	- 3.3V	Supply

3.5.4 Miscellaneous PIOB[0-7]

PIOs PB00 to PB07 are available on connector J13 and can be used as GPIO pins. Each of these can be configured as an input or output pin according to the PIO peripheral functions.

Figure 3-51. PIOs PB[0-7] Connector

VDD 3VS J13 1 2 3 4 5 6 7 8 9 10 GND_POWER PLOB[0-7] connector

Figure 3-52. PIOB[0-7] Connector J13 Location

J-Link Technology www.segger.com J9 L20 JLINK JP1 MBUS PMM INT RX TX SCL SDA 5V GND J15B AN RST C5 SCK MI5D MOSI 3V3 GND J15A C123 C127 C126 R195 R189 ETH R244 U8 R183 Q6 U5 C11 C123 C127 C128 U17 R197 C16 R204 C128 U17 R182 Q7 R181 Q5 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R257 R258 R259 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R280 R281 R282 R283 R284 R285 R286 R287 R288 R289 R290 R291 R292 R293 R294 R295 R296 R297 R298 R299 R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 R310 R311 R312 R313 R314 R315 R316 R317 R318 R319 R320 R321 R322 R323 R324 R325 R326 R327 R328 R329 R330 SAMA5D2-PTC-EK Rev B PTC C17 PIOBU XPRO J11 EXT1 J12 EXT2 J13 EXT3 J14 EXT4 J15 EXT5 J16 EXT6 J17 EXT7 J18 EXT8 J19 EXT9 J20 EXT10 J21 EXT11 J22 EXT12 J23 EXT13 J24 EXT14 J25 EXT15 J26 EXT16 J27 EXT17 J28 EXT18 J29 EXT19 J30 EXT20 J31 EXT21 J32 EXT22 J33 EXT23 J34 EXT24 J35 EXT25 J36 EXT26 J37 EXT27 J38 EXT28 J39 EXT29 J40 EXT30 J41 EXT31 J42 EXT32 J43 EXT33 J44 EXT34 J45 EXT35 J46 EXT36 J47 EXT37 J48 EXT38 J49 EXT39 J50 EXT40 J51 EXT41 J52 EXT42 J53 EXT43 J54 EXT44 J55 EXT45 J56 EXT46 J57 EXT47 J58 EXT48 J59 EXT49 J60 EXT50 J61 EXT51 J62 EXT52 J63 EXT53 J64 EXT54 J65 EXT55 J66 EXT56 J67 EXT57 J68 EXT58 J69 EXT59 J70 EXT60 J71 EXT61 J72 EXT62 J73 EXT63 J74 EXT64 J75 EXT65 J76 EXT66 J77 EXT67 J78 EXT68 J79 EXT69 J80 EXT70 J81 EXT71 J82 EXT72 J83 EXT73 J84 EXT74 J85 EXT75 J86 EXT76 J87 EXT77 J88 EXT78 J89 EXT79 J90 EXT80 J91 EXT82 J93 EXT84 J95 EXT86 J97 EXT88 J99 EXT90 J100 EXT91 EXT92 EXT93 EXT94 EXT95 EXT96 EXT97 EXT98 EXT99 EXT100

The table below describes the pin assignment of PIOs PB[0-7] connector J13.

Table 3-24. PIOs PB[0-7] Connector J13 Pin Assignment

Pin No PIO Signal Name Shared Signal Description
1 – VDD_3V3 – Main 3.3V
2 PB0 GPIO NAND Flash PIO port B
3 PB1 GPIO NAND Flash PIO port B
4 PB2 GPIO NAND Flash PIO port B
5 PB3 GPIO – PIO port B
6 PB4 GPIO – PIO port B
7 PB5 GPIO – PIO port B
8 PB6 GPIO LED BLUE PIO port B

......continued
Pin No PIO Signal Name Shared Signal Description
9 PB7 GPIO – PIO port B
10 – GND – Common ground

4. Installation and Operation

4.1 System and Configuration Requirements

The SAMA5D2-PTC-EK requires the following:

• Personal Computer
• USB cable

4.2 Board Setup

Follow these steps before using the SAMA5D2-PTC-EK:

1. Unpack the board, taking care to avoid electrostatic discharge.
2. Check the default jumper settings.
3. Connect the USB Micro-AB cable to connector J9.
4. Connect the other end of the cable to a free port of your PC.
5. Open a terminal (console 115200, N, 8, 1) on your Personal Computer.
6. Reset the board. A startup message appears on the console.

5. Appendix A. Schematics and Layouts

This appendix contains the following schematics and layouts for the SAMA5D2-PTC-EK board:

• Title and Revision History
- Block Diagram
- Power Domains
- MPU Power
- DDR2-SDRAM
- PIOA & PIOB
- PIOC & PIOD
- System
- USB & TF
- Memories & RGB LED
- Ethernet 10/100M
- JLINK-OB
- EXT Connectors

Figure 5-1. Title and Revision History
Schematic: A5D2-PTC-EK

	SHEET NAMESHEET
01	Title & Revision Tabercy
02	Block Diagram
03	Power domains
04	MOV_POWER
05	DDR2-STDAN
06	PDCAPIOD
07	JDCAPIOD
08	SYSTEM
09	USB&TF
10	REXORISFAROBLED
11	Ethernet 10/100V
12	JT/TNK-07
13	EXL_CONNECTORS

Revision History

DATE		NOITPIRCSEDNOISIVER
06 Jan 2017	RevA-20160107	Init edit
07-MAR-17	RevA	RevA release
03-OCT-17	RevB	RevB release
6-DEC-17 RevB	Cosmetic changes
5-jun-19	RevB	Removed erroneous comment in sheet 4

Figure 5-2. Block Diagram

graph TD
    A["Push Buttons"] -->|Reset Force PwrOn| B["POWER Sheet 3"]
    B -->|5V & 3V3| C["XPRO Connectors"]
    C -->|ANALOG Reference| D["Atmel SAMA5D27 Cortex(R)-A5 Processor"]
    D -->|USB A,B,C| E["USB Device"]
    D -->|USB A OTG| F["USB Device"]
    D -->|USB B Host| G["USB Device"]
    D -->|USB C HSIC| H["USB Device"]
    D -->|JTAG JLINK-CB| I["USB Device"]
    D -->|JTAG Connector| J["USB Device"]
    D -->|EBI| K["USB Device"]
    D -->|PIO A,B,C,D| L["QSPI Flash"]
    D -->|PIO A,B,C,D| M["SPI Data Flash"]
    D --> N["Ethernet 10/100M bps"]
    D --> O["24AA02E48"]
    D --> P["LCD CON"]
    D --> Q["PTC PORT"]
    D --> R["SDCARD CON"]
    D --> S["Sheet 13"]
    D --> T["Sheet 09"]

Figure 5-3. Power Domains

Switching Power lines POWER SUPPLY VDDBU Power Supply Fixed output 1V8, 3v3, Fixed output 1V25

Figure 5-4. MPU Power

POWER TEST POINTS VCCDC12 C10 C21 C31 C41 C51 C61 C71 C81 C91 C101 C111 C121 C131 VCCDC12 C10 C21 C31 C41 C51 C61 C71 C81 C91 C101 C111 C121 C131 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCD-PCB VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDO-PCB VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12 VCCDC12

Figure 5-5. DDR2-SDRAM

2 x W972GG6KB-25, DDR2-800, 16 Meg x 16 x 8 MICROCHIP 14 VCC 1.0 VCC 1.1 VCC 1.2 VCC 1.3 VCC 1.4 VCC 1.5 VCC 1.6 VCC 1.7 VCC 1.8 VCC 1.9 VCC 2.0 VCC 2.1 VCC 2.2 VCC 2.3 VCC 2.4 VCC 2.5 VCC 2.6 VCC 2.7 VCC 2.8 VCC 2.9 VCC 3.0 VCC 3.1 VCC 3.2 VCC 3.3 VCC 3.4 VCC 3.5 VCC 3.6 VCC 3.7 VCC 3.8 VCC 3.9 VCC 4.0 VCC 4.1 VCC 4.2 VCC 4.3 VCC 4.4 VCC 4.5 VCC 4.6 VCC 4.7 VCC 4.8 VCC 4.9 VCC 5.0 VCC 5.1 VCC 5.2 VCC 5.3 VCC 5.4 VCC 5.5 VCC 5.6 VCC 5.7 VCC 5.8 VCC 5.9 VCC 6.0 VCC 6.1 VCC 6.2 VCC 6.3 VCC 6.4 VCC 6.5 VCC 6.6 VCC 6.7 VCC 6.8 VCC 6.9 VCC 7.0 VCC 7.1 VCC 7.2 VCC 7.3 VCC 7.4 VCC 7.5 VCC 7.6 VCC 7.7 VCC 7.8 VCC 7.9 VCC 8.0 VCC 8.1 VCC 8.2 VCC 8.3 VCC 8.4 VCC 8.5 VCC 8.6 VCC 8.7 VCC 8.8 VCC 8.9 VCC 9.0 VCC 9.1 VCC 9.2 VCC 9.3 VCC 9.4 VCC 9.5 VCC 9.6 VCC 9.7 VCC 9.8 VCC 9.9 VCC 10.0 VCC 10.1 VCC 10.2 VCC 10.3 VCC 10.4 VCC 10.5 VCC 10.6 VCC 10.7 VCC 10.8 VCC 10.9 VCC 11.0 VCC 11.1 VCC 11.2 VCC 11.3 VCC 11.4 VCC 11.5 VCC 11.6 VCC 11.7 VCC 11.8 VCC 11.9 VCC 12.0 VCC 12.1 VCC 12.2 VCC 12.3 VCC 12.4 VCC 12.5 VCC 12.6 VCC 12.7 VCC 12.8 VCC 12.9 VCC 13.0 VCC 13.1 VCC 13.2 VCC 13.3 VCC 13.4 VCC 13.5 VCC 13.6 VCC 13.7 VCC 13.8 VCC 13.9 VCC 14.0 VCC 14.1 VCC 14.2 VCC 14.3 VCC 14.4 VCC 14.5 VCC 14.6 VCC 14.7 VCC 14.8 VCC 14.9 VCC 15.0 VCC 15.1 VCC 15.2 VCC 15.3 VCC 15.4 VCC 15.5 VCC 15.6 VCC 15.7 VCC 15.8 VCC 15.9 VCC 16.0 VCC 16.1 VCC 16.2 VCC 16.3 VCC 16.4 VCC 16.5 VCC 16.6 VCC 16.7 VCC 16.8 VCC 16.9 VCC 17.0 VCC 17.1 VCC 17.2 VCC 17.3 VCC 17.4 VCC 17.5 VCC 17.6 VCC 17.7 VCC 17.8 VCC 17.9 VCC 18.0 VCC 18.1 VCC 18.2 VCC 18.3 VCC 18.4 VCC 18.5 VCC 18.6 VCC 18.7 VCC 18.8 VCC 18.9 VCC 19.0 VCC 19.1 VCC 19.2 VCC 19.3 VCC 19.4 VCC 19.5 VCC 19.6 VCC 19.7 VCC 19.8 VCC 19.9 VCC 20.0

Figure 5-6. PIOA & PIOB

SNX SNX1 SNX2 SNX3 SNX4 SNX5 SNX6 SNX7 SNX8 SNX9 SNX10 SNX11 SNX12 SNX13 SNX14 SNX15 SNX16 SNX17 SNX18 SNX19 SNX20 SNX21 SNX22 SNX23 SNX24 SNX25 SNX26 SNX27 SNX28 SNX29 SNX30 SNX31 SNX32 SNX33 SNX34 SNX35 SNX36 SNX37 SNX38 SNX39 SNX40 SNX41 SNX42 SNX43 SNX44 SNX45 SNX46 SNX47 SNX48 SNX49 SNX50 SNX51 SNX52 SNX53 SNX54 SNX55 SNX56 SNX57 SNX58 SNX59 SNX60 SNX61 SNX62 SNX63 SNX64 SNX65 SNX66 SNX67 SNX68 SNX69 SNX70 SNX71 SNX72 SNX73 SNX74 SNX75 SNX76 SNX77 SNX78 SNX79 SNX80 SNX81 SNX82 SNX83 SNX84 SNX85 SNX86 SNX87 SNX88 SNX89 SNX90 SNX91 SNX92 SNX93 SNX94 SNX95 SNX96 SNX97 SNX98 SNX99 SNX100

741	742	743	744	H_ZEN(1, 1)
743	744	745	746	H_ZEN(1, 1)
744	745	746	747	H_ZEN(1, 1)
745	746	747	748	H_ZEN(1, 1)
746	747	748	749	H_ZEN(1, 1)
747	748	749	750	H_ZEN(1, 1)
748	749	750	751	H_ZEN(1, 1)
749	750	751	752	H_ZEN(1, 1)
750	751	752	753	H_ZEN(1, 1)
751	752	753	754	H_ZEN(1, 1)
752	753	754	755	H_ZEN(1, 1)
753	754	755	756	H_ZEN(1, 1)
754	755	756	757	H_ZEN(1, 1)
755	756	757	758	H_ZEN(1, 1)
756	757	758	759	H_ZEN(1, 1)
757	758	759	760	H_ZEN(1, 1)
758	759	760	761	H_ZEN(1, 1)
759	760	761	762	H_ZEN(1, 1)
760	761	762	763	H_ZEN(1, 1)
761	762	763	764	H_ZEN(1, 1)
762	763	764	765	H_ZEN(1, 1)

7423	7424	7425	7426
	7427	7428	7429
	7429	7430	7431
	7431	7432	7433
7423	7424	7425	7426
	7427	7428	7429
	7429	7430	7431
	7431	7432	7433
7423	7424	7425	7426
	7427	7428	7429
	7431	7432	7433
	7432	7433	7434
	7433	7434	7435
	7434	7435	7436
	7435	7436	7437
	7436	7437	7438
	7437	7438	7439
	7438	7439	7440
	7439	7440	7441
	7440	7441	7442

All resistors on this page connected to PIOs populated close to MPU

100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200

7501	1293	24.5	28.50	LTRSTOCK 7614 1
7501	817	12.9	25.40	LTRSTOCK 7613 1
7502	1042	24.1	28.50	LTRSTOCK 7611 1
7507	916	27.4	28.50	LTRSTOCK 7611 1
7509	834	22.5	28.60	LTRSTOCK 7610 1
7511	916	27.4	28.50	LTRSTOCK 7610 1
7523	936	22.5	28.60	LTRSTOCK 7602 1
7527	1017	27.4	28.50	LTRSTOCK 7601 1
7532	930	22.5	28.60	LTRSTOCK 7602 1
7533	1024	27.4	28.50	LTRSTOCK 7602 1
7536	930	22.5	28.60	LTRSTOCK 7601 1

192	+2%	150KΩ 3.247	60V
	-2%	25%	70V
193	+2%	150KΩ 3.247	60V
	-2%	25%	70V
194	+2%	150KΩ 3.247	60V
	-2%	25%	70V
195	+2%	150KΩ 3.247	60V
	-2%	25%	70V
196	+2%	150KΩ 3.247	60V
	-2%	25%	70V
197	+2%	150KΩ 3.247	60V
	-2%	25%	70V
198	+2%	150KΩ 3.247	60V
	-2%	25%	70V
199	+2%	150KΩ 3.247	60V
	-2%	25%	70V
200	+2%	150KΩ 3.247	60V
	-2%	25%	70V
201	+2%	150KΩ 3.247	60V
	-2%	25%	70V
202	+2%	150KΩ 3.247	60V
	-2%	25%	70V
203	+2%	150KΩ 3.247	60V
	-2%	25%	70V
204	+2%	150KΩ 3.247	60V
	-2%	25%	70V
205	+2%	150KΩ 3.247	60V
	-2%	25%	70V
206	+2%	150KΩ 3.247	60V
	-2%	25%	70V
207	+2%	150KΩ 3.247	60V
	-2%	25%	70V
208	+2%	150KΩ 3.247	60V
	-2%	25%	70V
209	+2%	150KΩ 3.247	60V
	-2%	25%	70V
210	+2%	150KΩ 3.247	60V
	-2%	25%	70V
211	+2%	150KΩ 3.247	60V
	-2%	25%	70V
212	+2%	150KΩ 3.247	60V
	-2%	25%	70V
213	+2%	150KΩ 3.247	60V
	-2%	25%	70V
214	+2%	150KΩ 3.247	60V
	-2%	25%	70V

Figure 5-7. PIOC & PIOD
All resistors on this page connected to PIOs populated close to MPU

R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100

Figure 5-8. System

Clock sources SAMA5D2 System Pins Routing top or bottom HACDC HACDC HACDC HACDC HACDC HACDC HACDC HACDC HACDC HACDC USER BUTTON DIS BOOT RESET WAVE UP JTAG Microchip 1/1 B 477 13

Figure 5-9. USB & TF

Figure 5-10. Memories & RGB LED

QSPI Flash & SPI Flash CS QSPI Flash LED SPI Flash NAND Flash EEPROM+MAC

Figure 5-11. Ethernet 10/100M

Ethernet 10Base-T/100Base-TX 100 pins differential base impedance Racing output DCB-265 DCB-264 DCB-263 DCB-262 DCB-261 DCB-260 DCB-259 DCB-258 DCB-257 DCB-256 DCB-255 DCB-254 DCB-253 DCB-252 DCB-251 DCB-250 DCB-249 DCB-248 DCB-247 DCB-246 DCB-245 DCB-244 DCB-243 DCB-242 DCB-241 DCB-240 DCB-239 DCB-238 DCB-237 DCB-236 DCB-235 DCB-234 DCB-233 DCB-232 DCB-231 DCB-230 DCB-229 DCB-228 DCB-227 DCB-226 DCB-225 DCB-224 DCB-223 DCB-222 DCB-221 DCB-220 DCB-219 DCB-218 DCB-217 DCB-216 DCB-215 DCB-214 DCB-213 DCB-212 DCB-211 DCB-210 DCB-209 DCB-208 DCB-207 DCB-206 DCB-205 DCB-204 DCB-203 DCB-202 DCB-201 DCB-200 DCB-199 DCB-198 DCB-197 DCB-196 DCB-195 DCB-194 DCB-193 DCB-192 DCB-191 DCB-190 DCB-189 DCB-188 DCB-187 DCB-186 DCB-185 DCB-184 DCB-183 DCB-182 DCB-181 DCB-180 DCB-179 DCB-178 DCB-177 DCB-176 DCB-175 DCB-174 DCB-173 DCB-172 DCB-171 DCB-170 DCB-169 DCB-168 DCB-167 DCB-166 DCB-165 DCB-164 DCB-163 DCB-162 DCB-161 DCB-160 DCB-159 DCB-158 DCB-157 DCB-156 DCB-155 DCB-154 DCB-153 DCB-152 DCB-151 DCB-150 DCB-149 DCB-148 DCB-147 DCB-146 DCB-145 DCB-144 DCB-143 DCB-142 DCB-141 DCB-140 DCB-139 DCB-138 DCB-137 DCB-136 DCB-135 DCB-134 DCB-133 DCB-132 DCB-131 DCB-130 DCB-129 DCB-128 DCB-127 DCB-126 DCB-125 DCB-124 DCB-123 DCB-122 DCB-121 DCB-120 DCB-119 DCB-118 DCB-117 DCB-116 DCB-115 DCB-114 DCB-113 DCB-112 DCB-111 DCB-110 DCB-109 DCB-108 DCB-107 DCB-106 DCB-105 DCB-104 DCB-103 DCB-102 DCB-101 DCB-100

Figure 5-12. J-Link-OB

DBGU function switches JLINK-OB PCB connector for SAMTEC MEC1-108-02

Figure 5-13. EXT Connectors

PIOB[0-7] Connector MikroBUS LCD-50PIN XPRO EXT1 XPRO EXT2 XPRO Connectors PTC Connector Microchip 1/1 13/13

6. Revision History

6.1 DS50002709B - 09/2019

Changes

1. Appendix A. Schematics and Layouts: updated all schematics and layouts

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Tel: [phone]			Sweden - Stockholm
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Tel: [phone]			UK - Wokingham
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Canada - Toronto			Fax: [phone]
Tel: [phone]
Fax: [phone]