MCP1801 - Electronic component Microchip - Free user manual and instructions

USER MANUAL MCP1801 Microchip

150 mA, High PSRR, Low Quiescent Current LDO

Features:

• 150 mA Maximum Output Current
- Low Dropout Voltage, 200 mV typical @ 100 mA
• 25 μA Typical Quiescent Current
• 0.01 μA Typical Shutdown Current
- Input Operating Voltage Range: 2.0V to 10.0V
- Standard Output Voltage Options:
- 0.9V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V, 6.0V
- Output Voltage Accuracy:
- ± 2 %R (N5V), ±30 mV (VR ≤ 1.5V)
• Stable with Ceramic Output Capacitors
- Current Limit Protection
- Shutdown Pin
• High PSRR: 70 dB typical @ 10 kHz

Applications:

• Battery-powered Devices
• Battery-powered Alarm Circuits
• Smoke Detectors
• CO^2 Detectors
• Pagers and Cellular Phones
  • Wireless Communications Equipment
• Smart Battery Packs
• Low Quiescent Current Voltage Reference
  • P D A s
  • Digital Cameras
• Microcontroller Power
  • Solar-Powered Instruments
• Consumer Products
• Battery Powered Data Loggers

Related Literature:

• AN765, "Using Microchip's Micropower LDOs", DS00765, Microchip Technology Inc., 2002
• AN766, "Pin-Compatible CMOS Upgrades to BiPolar LDOs", DS00766, Microchip Technology Inc., 2002
• AN792, "A Method to Determine How Much Power a SOT23 Can Dissipate in an Application", DS00792, Microchip Technology Inc., 2001

Description:

The MCP1801 is a family of CMOS low dropout (LDO) voltage regulators that can deliver up to 150 mA of current while consuming only 25 A of quiescent current (typical). The input operating range is specified from 2.0V to 10.0V, making it an ideal choice for two to six primary cell battery-powered applications, 9V alkaline and one or two cell Li-Ion-powered applications.

The MCP1801 is capable of delivering 100 mA with only 200 mV (typical) of input to output voltage differential ( V_OUT = 3.3V ). The output voltage tolerance of the MCP1801 at +25°C is typically ±0.4% with a maximum of ±2%. Line regulation is ±0.01% typical at +25°C.

The LDO output is stable with a minimum of 1 F of output capacitance. Ceramic, tantalum, or aluminum electrolytic capacitors can all be used for input and output. Overcurrent limit with current foldback provides short-circuit protection. A shutdown (SHDN) function allows the output to be enabled or disabled. When disabled, the MCP1801 draws only 0.01 A of current (typical).

The MCP1801 is available in a SOT-23-5 package.

Package Types

SOT-23-5 VOUT NC 5 4 1 2 3 VIN SS SHDNV

Functional Block Diagram

graph TD
    A["SHDN"] --> B["Shutdown Control"]
    C["VIN"] --> B
    D["GND"] --> B
    B --> E["Voltage Reference"]
    E --> F["Current Limiter"]
    F --> G["Error Amplifier"]
    G --> H["+VIN"]
    H --> I["VOUT"]
    J["+VIN"] --> K["Diode"]
    L["VOUT"] --> M["Diode"]
    N["VOUT"] --> O["Diode"]
    P["VOUT"] --> Q["Diode"]
    R["VOUT"] --> S["Diode"]
    T["VOUT"] --> U["Diode"]
    V["VOUT"] --> W["Diode"]
    X["VOUT"] --> Y["Diode"]
    Z["VOUT"] --> AA["Diode"]

Typical Application Circuit

MCP1801 V_IN 1 V_IN V_OUT 5 2 G_ND 3 SHDN NC 4 9V Battery + C_IN 1 µF Ceramic V_OUT 3.3V @ 40 mA C_OUT 1 µF Ceramic

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Input Voltage ....+12V

Output Current (Continuous) P D /(V IN -V _OUT )mA

Output Current (Peak) 500 mA

Output Voltage (V SS -0.3V) to (V IN +0.3V)

Voltage (V_SS - 0.3V) to (V_IN + 0.3V)

Continuous Power Dissipation:

SOT-23-5 250 mW

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise specified, all limits are established for V_IN=V_R+1.0V , Note 1, C_OUT=1μF(X7R) , C_IN=1μF(X7R) , V_SHDN=V_IN , T_A=+25°C .
Parameters Sym Min Typ Max Units Conditions
Input / Output Characteristics
Input Operating Voltage V	IN	2.0	—	10.0	V	Note 1
Input Quiescent Current	I_q	—	25	50		μA 0 mA
Shutdown Current	I_SHDN	—	0.01	0.10	μA	=0V
Maximum Output Current	I_OUT\_mA	150	—	—	mA
Current Limiter	LIMIT	—	300	—	mA	if V_R≤1.75V , then V_IN=V_R+2.0V
Output Short Circuit Current	I_OUT\_SC	—	50	—	mA	if V_R≤1.75V , then V_IN=V_R+2.0V
Output Voltage Regulation	V_OUT	V_R-2.0%	V_R	V_R+2.0%	V	V_R≥1.45V , I_OUT=30mA , Note 2
		V_R-30mV	V_R	V_R+30mV		V_R<1.45V , I_OUT=30mA
V_OUT Temperature Coefficient	TCV_OUT	—	100	— ppm	°C I	OUT=30mA,-40°C≤T_A≤+85°C , Note 3
Line Regulation	V_OUT/(V_OUTX V_IN)	-0.2	±0.01	+0.2	%/V	(V_R+1V)≤V_IN≤10V , Note 1 V_R>1.75V , I_OUT=30mA V_R≤1.75V , I_OUT=10mA
Load Regulation	V_OUT/V_OUT	—	15	50		mV/1.0 mA to 100 mA, Note 4
Dropout Voltage, Note 5	V_DROPOUT	—	60	90		mV/30 mA, 3.1V ≤ V_R≤6.0V
		—	200	250		I_L=100mA, 3.1V≤V_R≤6.0V
		—	80	120		I_L=30mA, 2.0V≤V_R<3.1V
		—	240	350		I_L=100mA, 2.0V≤V_R<3.1V
		—	2.07 - V_R	2.10 - V_R	V	I_L=30mA, V_R<2.0V
		—	2.23 - V_R	2.33 - V_R		I_L=100mA, V_R<2.0V
Power Supply Ripple Rejection Ratio	PSRR	—	70	—	dB	f = 10 kHz, I_L=50mA , V_INAC=1Vpk-pk , C_IN=0μF ,if V_R<1.5V , then V_IN=2.5V
Output Noise	e_N	—	0.6	—	μV/√Hz	I_OUT=100mA, f=1kHz , C_OUT=1μF(X7R Ceramic) , V_OUT=3.3V

Note 1: The minimum V_IN must meet two conditions: V_IN ≥ 2.0V and V_IN ≥ (V_R + 1.0V) .
2: V_R is the nominal regulator output voltage. For example: V_R = 1.8V, 2.5V, 3.0V, 3.3V , or 5.0V. The input voltage V_IN = V_R + 1.0V or V_IN = 2.0V (whichever is greater); I_OUT = 100 A .
3: TCV_OUT = (V_OUT-HIGH - V_OUT-LOW) * 10^6 / (V_R * Temperature) , V_OUT-HIGH = highest voltage measured over the temperature range . V_OUT-LOW = lowest voltage measured over the temperature range .
4: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Changes in output voltage due to heating effects are determined using thermal regulation specification TCV_OUT .
5: Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its measured value with an applied input voltage of V_R + 1.0V or 2.0V, whichever is greater.

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all limits are established for V_IN = V_R + 1.0V , Note 1, C_OUT = 1 μF (X7R), C_IN = 1 μF (X7R), V_ = V_IN , T_A = +25°C .
Parameters Sym Min	Typ Max Units	Conditions
Shutdown Input
Logic High Input V	SHDN-HIGH	1.6 — — V
Logic Low Input V	SHDN-LOW	— — 0.25 V

Note 1: The minimum V_IN must meet two conditions: V_IN ≥ 2.0V and V_IN ≥ (V_R + 1.0V) .
2: V_R is the nominal regulator output voltage. For example: V_R = 1.8V , 2.5V, 3.0V, 3.3V, or 5.0V. The input voltage V_IN = V_R + 1.0V or V_IN = 2.0V (whichever is greater); I_OUT = 100 A .
3: TCV_OUT = (V_OUT-HIGH - V_OUT-LOW) * 10^6 / (V_R * Temperature) , V_OUT-HIGH = highest voltage measured over the temperature range . V_OUT-LOW = lowest voltage measured over the temperature range .
4: Load regulation is measured at a constant junction temperature using low duty cycle pulse testing. Changes in output voltage due to heating effects are determined using thermal regulation specification TCV_OUT .
5: Dropout voltage is defined as the input to output differential at which the output voltage drops 2% below its measured value with an applied input voltage of V_R + 1.0V or 2.0V, whichever is greater.

TEMPERATURE SPECIFICATIONS

Parameters	Sym	Min	Typ	Max	Units	Conditions
Temperature Ranges
Operating Temperature Range	T_A	-40	—	+85	°C
Storage Temperature Range	Tstg	-55	—	+125	°C
Thermal Package Resistance
Thermal Resistance, 5LD SOT-23	_JA	—	256	—	°C/W	EIA/JEDEC JESD51-7
	_JC	—	81	—		FR-4 0.063 4-Layer Board

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated: V_R = 3.3V , C_OUT = 1 F Ceramic (X7R), C_IN = 1 F Ceramic (X7R), I_L = 100 A , T_A = +25^ , V_IN = V_R + 1.0V , SOT-23-5.

Note: Junction Temperature ( T_J ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant.

FIGURE 2-1: Quiescent Current vs. Input Voltage.

FIGURE 2-4: Ground Current vs. Load Current.

FIGURE 2-2: Quiescent Current vs. Input Voltage.

FIGURE 2-5: Ground Current vs. Load Current.

FIGURE 2-3: Quiescent Current vs. Input Voltage.

FIGURE 2-6: Quiescent Current vs. Junction Temperature.

Note: Unless otherwise indicated: V_R = 3.3V , C_OUT = 1 F Ceramic (X7R), C_IN = 1 F Ceramic (X7R), I_L = 100 A , T_A = +25^ , V_IN = V_R + 1.0V , SOT-23-5.

FIGURE 2-7: Output Voltage vs. Input Voltage.

FIGURE 2-10: Output Voltage vs. Load Current.

FIGURE 2-8: Output Voltage vs. Input Voltage.

FIGURE 2-11: Output Voltage vs. Load Current.

FIGURE 2-9: Output Voltage vs. Input Voltage.

FIGURE 2-12: Output Voltage vs. Load Current.

Note: Unless otherwise indicated: V_R = 3.3V , C_OUT = 1 F Ceramic (X7R), C_IN = 1 F Ceramic (X7R), I_L = 100 A , T_A = +25^ , V_IN = V_R + 1.0V , SOT-23-5.

FIGURE 2-13: Dropout Voltage vs. Load Current.

FIGURE 2-16: Dynamic Line Response.

FIGURE 2-14: Dropout Voltage vs. Load Current.

FIGURE 2-17: Short Circuit Current vs. Input Voltage.

FIGURE 2-15: Dynamic Line Response.

FIGURE 2-18: Load Regulation vs. Temperature.

Note: Unless otherwise indicated: V_R = 3.3V , C_OUT = 1 F Ceramic (X7R), C_IN = 1 F Ceramic (X7R), I_L = 100 A , T_A = +25^ , V_IN = V_R + 1.0V , SOT-23-5.

FIGURE 2-19: Load Regulation vs. Temperature.

FIGURE 2-22: Line Regulation vs. Temperature.

FIGURE 2-20: Load Regulation vs. Temperature.

FIGURE 2-23: Line Regulation vs. Temperature.

FIGURE 2-21: Line Regulation vs. Temperature.

FIGURE 2-24: PSRR vs. Frequency.

Note: Unless otherwise indicated: V_R = 3.3V , C_OUT = 1 F Ceramic (X7R), C_IN = 1 F Ceramic (X7R), I_L = 100 A , T_A = +25^ , V_IN = V_R + 1.0V , SOT-23-5.

FIGURE 2-25: PSRR vs. Frequency.

FIGURE 2-28: Dynamic Load Response.

FIGURE 2-26: Power-Up Timing.

FIGURE 2-29: Power-Up Timing From SHDN.

FIGURE 2-27: Dynamic Load Response.

FIGURE 2-30: Output Noise

NOTES:

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table3-1.

TABLE 3-1: MCP1801 PIN FUNCTION TABLE

Pin No.SOT-23-5	Name Function
1	V_IN	Unregulated Supply Voltage
2 GND Ground Terminal
3 SHDN	——	Shutdown Input
4	NC	No Connection
5	V_OUT	Regulated Voltage Output

3.1 Unregulated Input Voltage (V IN)

Connect V_IN to the input unregulated source voltage. Like all low dropout linear regulators, low source impedance is necessary for the stable operation of the LDO. The amount of capacitance required to ensure low source impedance will depend on the proximity of the input source capacitors or battery type. For most applications, 0.1 F of capacitance will ensure stable operation of the LDO circuit. The type of capacitor used can be ceramic, tantalum, or aluminum electrolytic. The low ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency.

3.2 Ground Terminal (GND)

Regulator ground. Tie GND to the negative side of the output and the negative side of the input capacitor. Only the LDO bias current (25 A typical) flows out of this pin; there is no high current. The LDO output regulation is referenced to this pin. Minimize voltage drops between this pin and the negative side of the load.

3.3 Shutdown Input (SHDN)

The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.01 μA. The SHDN pin does not have an internal pull-up or pull-down resistor. The SHDN pin must be connected to either V_IN or GND to prevent the device from becoming unstable.

3.4 Regulated Output Voltage (V OUT)

Connect V_OUT to the positive side of the load and the positive terminal of the output capacitor. The positive side of the output capacitor should be physically located as close to the LDO V_OUT pin as is practical. The current flowing out of this pin is equal to the DC load current.

NOTES:

4.0 DETAILED DESCRIPTION

4.1 Output Regulation

A portion of the LDO output voltage is fed back to the internal error amplifier and compared with the precision internal bandgap reference. The error amplifier output will adjust the amount of current that flows through the P-Channel pass transistor, thus regulating the output voltage to the desired value. Any changes in input voltage or output current will cause the error amplifier to respond and adjust the output voltage to the target voltage (refer to Figure 4-1).

4.2 Overcurrent

The MCP1801 internal circuitry monitors the amount of current flowing through the P-Channel pass transistor. In the event that the load current reaches the current limiter level of 300 mA (typical), the current limiter circuit will operate and the output voltage will drop. As the output voltage drops, the internal current foldback circuit will further reduce the output voltage causing the output current to decrease. When the output is shorted, a typical output current of 50 mA flows.

4.3 Shutdown

The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.01 μA. The SHDN pin does not have an internal pull-up or pull-down resistor. Therefore, the SHDN pin must be pulled either high or low to prevent the device from becoming unstable. The internal device current will increase when the device is operational and current flows through the pull-up or pull-down resistor to the SHDN pin internal logic. The SHDN pin internal logic is equivalent to an inverter input.

4.4 Output Capacitor

The MCP1801 requires a minimum output capacitance of 1 F for output voltage stability. Ceramic capacitors are recommended because of their size, cost, and environmental robustness qualities.

Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 F X7R 0805 capacitor has an ESR of 50 milli-ohms.

Larger LDO output capacitors can be used with the MCP1801 to improve dynamic performance and power supply ripple rejection performance. Aluminum-electrolytic capacitors are not recommended for low temperature applications of ≤25^ .

4.5 Input Capacitor

Low input source impedance is necessary for the LDO output to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 0.1 F to 4.7 F is recommended for most applications.

For applications that have output step load requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. For good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO.

graph TD
    A["SHDN"] --> B["Shutdown Control"]
    C["VIN"] --> B
    D["GND"] --> B
    B --> E["Voltage Reference"]
    E --> F["Current Limiter"]
    F --> G["Error Amplifier"]
    G --> H["+VIN"]
    H --> I["VOUT"]
    J["+VIN"] --> K["Diode"]
    L["VOUT"] --> M["Diode"]
    N["VOUT"] --> O["Diode"]
    P["VOUT"] --> Q["Diode"]
    R["VOUT"] --> S["Diode"]
    T["VOUT"] --> U["Diode"]
    V["VOUT"] --> W["Diode"]
    X["VOUT"] --> Y["Diode"]
    Z["VOUT"] --> AA["Diode"]

FIGURE 4-1: Block Diagram.

5.0 FUNCTIONAL DESCRIPTION

The MCP1801 CMOS low dropout linear regulator is intended for applications that need the low current consumption while maintaining output voltage regulation. The operating continuous load range of the MCP1801 is from 0 mA to 150 mA. The input operating voltage range is from 2.0V to 10.0V, making it capable of operating from three or more alkaline cells or single and multiple Li-Ion cell batteries.

5.1 Input

The input of the MCP1801 is connected to the source of the P-Channel PMOS pass transistor. As with all LDO circuits, a relatively low source impedance (10Ω) is needed to prevent the input impedance from causing the LDO to become unstable. The size and type of the capacitor needed depends heavily on the input source type (battery, power supply) and the output current range of the application. For most applications a 0.1 μF ceramic capacitor will be sufficient to ensure circuit stability. Larger values can be used to improve circuit AC performance.

5.2 Output

The maximum rated continuous output current for the MCP1801 is 150 mA.

A minimum output capacitance of 1.0 F is required for small signal stability in applications that have up to 150 mA output current capability. The capacitor type can be ceramic, tantalum, or aluminum electrolytic.

NOTES:

6.0 APPLICATION CIRCUITS AND ISSUES

6.1 Typical Application

The MCP1801 is most commonly used as a voltage regulator. Its low quiescent current and low dropout voltage make it ideal for many battery-powered applications.

MCP1801 VOUT 1.8V IOUT 50 mA COUT 1 μF Ceramic NC SHDN GND VIN VIN 2.4V to 5.0V CIN 1 μF Ceramic

FIGURE 6-1: Typical Application Circuit.

6.1.1 APPLICATION INPUT CONDITIONS

$$ \text { Package Type } = \text { SOT - 23 - 5 } $$

$$ \text { Input Voltage Range } = 2. 4 \mathrm{V} \text { to } 5. 0 \mathrm{V} $$

$$ V _ {I N} \text { maximum } = 5. 0 V $$

$$ V _ {O U T} \text { typical } = 1. 8 V $$

$$ I _ {O U T} = 5 0 \mathrm{mA} \text { maximum } $$

6.2 Power Calculations

6.2.1 POWER DISSIPATION

The internal power dissipation of the MCP1801 is a function of input voltage, output voltage, and output current. The power dissipation, as a result of the quiescent current draw, is so low, it is insignificant (25.0 A x V_IN ). The following equation can be used to calculate the internal power dissipation of the LDO.

EQUATION 6-1:

$$ P _ {L D O} = (V _ {I N (M A X)}) - V _ {O U T (M I N)}) \times I _ {O U T (M A X))} $$

Where:

$$ \begin{array}{r c l} P _ {L D O} & = & L D O \text { Pass device internal power } \ & & \text { dissipation } \end{array} $$

$$ V _ {I N (M A X)} = \text { Maximum input voltage } $$

$$ V _ {\text { OUT(MIN) }} = \text { LDO minimum output voltage } $$

The maximum continuous operating temperature specified for the MCP1801 is +85°C. To estimate the internal junction temperature of the MCP1801, the total internal power dissipation is multiplied by the thermal

resistance from junction to ambient (R0JA). The thermal resistance from junction to ambient for the SOT-23-5 pin package is estimated at 256°C/W.

EQUATION 6-2:

$$ T _ {J (M A X)} = P _ {T O T A L} \times R \theta_ {J A} + T _ {A M A X} $$

Where:

$$ \begin{array}{l} \begin{array}{r l r} {T _ {\mathrm{J(MAX)}}} & = & {\text { Maximum continuous junction }} \ & & {\text { temperature }} \end{array} \ P _ {\text { TOTAL }} = \text { Total device power dissipation } \ \begin{array}{r l r} {R \theta_ {\mathrm{JA}}} & = & {\text { Thermal resistance from }} \ & & {\text { junction to ambient }} \end{array} \ T _ {\text { AMAX }} = \text { Maximum ambient temperature } \ \end{array} $$

The maximum power dissipation capability for a package can be calculated given the junction-to-ambient thermal resistance and the maximum ambient temperature for the application. The following equation can be used to determine the package maximum internal power dissipation.

EQUATION 6-3:

$$ P _ {D (M A X)} = \frac {\left(T _ {J (M A X)} - T _ {A (M A X)}\right)}{R \theta_ {J A}} $$

Where:

$$ \begin{array}{l} \begin{array}{r l r} {P _ {\mathrm{D(MAX)}}} & {=} & {\mathrm{Maximum~device~power}} \ & & {\mathrm{dissipation}} \end{array} \ \begin{array}{r c l} T _ {J (M A X)} & = & \text { Maximum continuous junction } \ & & \text { temperature } \end{array} \ T _ {A (M A X)} = \text { Maximum ambient temperature } \ \begin{array}{r l r} {R \theta_ {\mathrm{JA}}} & = & {\text { Thermal resistance from }} \ & & {\text { junction to ambient }} \end{array} \ \end{array} $$

EQUATION 6-4:

$$ T _ {J R I S E} = P _ {D (M A X)} \times R 0 _ {J A} $$

Where:

$$ \begin{array}{r c l} T _ {J (R I S E)} & = & \text { Rise in device junction } \ & & \text { temperature over the ambient } \ & & \text { temperature } \end{array} $$

$$ \begin{array}{r l r} {P _ {\mathrm{TOTAL}}} & {=} & {\mathrm{Maximum~device~power}} \ & & {\mathrm{dissipation}} \end{array} $$

$$ \begin{array}{r l r} {R \theta_ {\mathrm{JA}}} & = & {\text { Thermal resistance from }} \ & & {\text { junction to ambient }} \end{array} $$

EQUATION 6-5:

$$ T _ {J} = T _ {J R I S \vec {E}} (T _ {A}) $$

Where:

$$ T _ {J} = \text { Junction Temperature } $$

$$ \begin{array}{r l} T _ {J (R I S E)} & = \text { Rise in device junction } \ & \text { temperature over the ambient } \ & \text { temperature } \end{array} $$

$$ T _ {A} = \text { Ambient temperature } $$

6.3 Voltage Regulator

Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. The power dissipation, as a result of ground current, is small enough to be neglected.

6.3.1 POWER DISSIPATION EXAMPLE

Package

Package Type: SOT-23-5

Input Voltage

$$ V _ {I N} = 2. 4 V \text { to } 5. 0 V $$

LDO Output Voltages and Currents

$$ V _ {O U T} = 1. 8 \mathrm{V} $$

$$ I _ {O U T} = 5 0 \mathrm{mA} $$

Maximum Ambient Temperature

$$ T _ {A (M A X)} = + 4 0 ^ {\circ} \mathrm{C} $$

Internal Power Dissipation

Internal Power dissipation is the product of the LDO output current times the voltage across the LDO ( V_IN to V_OUT ).

$$ P _ {L D O (M A X)} = \left(V _ {I N (M A X)} - V _ {O U T (M I N)}\right) \times I _ {O U T (M A X)} $$

$$ P _ {L D O} = (5. 0 \mathrm{V} - (0. 9 8 \times 1. 8 \mathrm{V})) \times 5 0 \mathrm{mA} $$

$$ P _ {L D O} = 1 6 1. 8 \text { milli - Watts } $$

Device Junction Temperature Rise

The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. The thermal resistance from junction to ambient ( R_ JA ) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface mount packages. The EIA/JEDEC specification is JESD51-7, “High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages”. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT-23 Can Dissipate in an Application”, (DS00792), for more information regarding this subject.

$$ T _ {J (R I S E)} = P _ {T O T A L} \times R q _ {U A} $$

$$ T _ {J R I S E} = 1 6 1. 8 \text { milli - Watts } \times 2 5 6. 0 ^ {\circ} \mathrm{C} / \text { Watt } $$

$$ T _ {J R I S E} = 4 1. 4 2 ^ {\circ} C $$

Junction Temperature Estimate

To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated in the following table.

$$ T _ {J} = T _ {J R I S E} + T _ {A (M A X)} $$

$$ T _ {J} = 8 1. 4 2 ^ {\circ} \mathrm{C} $$

Maximum Package Power Dissipation at +25°C Ambient Temperature

$$ \mathrm{SOT-23-5} (2 5 6 ^ {\circ} \mathrm{C} / \text { Watt } = R \theta_ {\mathrm{JA}}) $$

$$ P _ {D (M A X)} = (8 5 ^ {\circ} \mathrm{C} - 2 5 ^ {\circ} \mathrm{C}) / 2 5 6 ^ {\circ} \mathrm{C} / \mathrm{W} $$

$$ P _ {D (M A X)} = 2 3 4 \text { milli - Watts } $$

6.4 Voltage Reference

The MCP1801 can be used not only as a regulator, but also as a low quiescent current voltage reference. In many microcontroller applications, the initial accuracy of the reference can be calibrated using production test equipment or by using a ratio measurement. When the initial accuracy is calibrated, the thermal stability and line regulation tolerance are the only errors introduced by the MCP1801 LDO. The low cost, low quiescent current, and small ceramic output capacitor are all advantages when using the MCP1801 as a voltage reference.

Ratio Metric Reference MCP1801 25 µA Bias CIN 1 µF VIN VOUT GND COUT 1 µF Bridge Sensor PIC® Microcontroller VREF ADO AD1

FIGURE 6-2: Using the MCP1801 as a Voltage Reference.

6.5 Pulsed Load Applications

For some applications, there are pulsed load current events that may exceed the specified 150 mA maximum specification of the MCP1801. The internal current limit of the MCP1801 will prevent high peak load demands from causing non-recoverable damage. The 150 mA rating is a maximum average continuous rating. As long as the average current does not exceed 150 mA nor the maximum power dissipation of the packaged device, pulsed higher load currents can be applied to the MCP1801. The typical current limit for the MCP1801 is 300 mA ( T_A + 25^ ).

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

5-Lead SOT-23

XXNN 1

Standard Options for SOT-23
Extended Temp
Symbol Voltage * Symbol Voltage *
9X8# 0.9	9XZ#	3.0
9XB#	1.2	9B2#	3.3
9XK#	1.8	9BM#	5.0
9XT#	2.5	9BZ#	6.0

* Custom output voltages available upon request. Contact your local Microchip sales office for more information.

Example:

9XNN 1

Legend: XX...X Customer-specific information
	Y Year code (last digit of calendar year)
	YY Year code (last 2 digits of calendar year)
	WW Week code (week of January 1 is week '01')
	NNN Alphanumeric traceability code
	eBb-free JEDEC designator for Matte Tin (Sn)
*	This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

5-Lead Plastic Small Outline Transistor (OT) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

N b E E1 1 2 3 e e1 D

Isometric line drawing of an integrated circuit chip with four leads (no text or symbols)

A A1 A2

c L L1 φ

Units		MILLIMETERS
Dimension Limits		MIN NOM MAX
Number of Pins	N	5
Lead Pitch e 0.95 BSC
Outside Lead Pitch e1	1.90 BSC
Overall Height	A	0.90	-	1.45
Molded Package Thickness	A2	0.89	-	1.30
Standoff	A1	0.00	-	0.15
Overall Width	E	2.20	-	3.20
Molded Package Width	E1	1.30	-	1.80
Overall Length	D	2.70	-	3.10
Foot Length	L	0.10	-	0.60
Footprint	L1	0.35	-	0.80
Foot Angle		0°	-	30°
Lead Thickness c 0.08	-	0.26
Lead Width	b	0.20	-	0.51

Notes:

1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-091B

5-Lead Plastic Small Outline Transistor (OT) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

X Y Z C G SILK SCREEN E GX

RECOMMENDED LAND PATTERN

Units		MILLIMETERS
Dimension Limits		MIN	NOM	MAX
Contact Pitch	E	0.95 BSC
Contact Pad Spacing	C		2.80
Contact Pad Width (X5)	X			0.60
Contact Pad Length (X5)	Y			1.10
Distance Between Pads	G	1.70
Distance Between Pads	GX	0.35
Overall Width	Z			3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091A

APPENDIX A: REVISION HISTORY

Revision D (October 2010)

The following is the list of modifications:

1. Removed Note 1 from the Dropout Voltage parameter in the Electrical Characteristics table.
2. Added Land Pattern package outline drawing C04-2091A.

Revision C (January 2009)

The following is the list of modifications:

1. Added Shutdown Input information to the Electrical Characteristics table.

Revision B (February 2008)

The following is the list of modifications:

1. Updated the Electrical Characteristics table.
2. Added Figure 2-30.

Revision A (June 2007)

• Original Release of this Document.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. Device X- Tape and Reel XX Output Voltage X Feature Code X Tolerance X/ Temp. Package

Device: MCP1801: 150 mA, Low Quiescent Current LDO

Tape and Reel: T = Tape and Reel

Output Voltage*: 09 = 0.9V "Standard"

12 = 1.2V "Standard"

18 = 1.8V "Standard"

25 = 2.5V "Standard"

30 = 3.0V "Standard"

33 = 3.3V "Standard"

50 = 5.0V "Standard"

60 = 6.0V "Standard"

*Contact factory for other output voltage options.

Extra Feature Code: 0 = Fixed

Tolerance: 2 = 2.0% (Standard)

Temperature: I = -40°C to +85°C

Package Type: OT = Plastic Small Outline Transistor (SOT-23) 5-lead,

Examples:

a) MCP1801T-0902I/OT: Tape and Reel, 0.9V

b) MCP1801T-1202I/OT: Tape and Reel, 1.2V

c) MCP1801T-1802I/OT: Tape and Reel, 1.8V

d) MCP1801T-2502I/OT: Tape and Reel, 2.5V

e) MCP1801T-3002I/OT: Tape and Reel, 3.0V

f) MCP1801T-3302I/OT: Tape and Reel, 3.3V

g) MCP1801T-5002I/OT: Tape and Reel, 5.0V

h) MCP1801T-6002I/OT: Tape and Reel, 6.0V

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
- Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

=ISO/TS 16949:2002=

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC ^32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-60932-574-9

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC® MCUs and dsPIÖ® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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