ATF1500AL - Electronic component Microchip - Free user manual and instructions

USER MANUAL ATF1500AL Microchip

This user guide describes how to use the Microchip ATF15XX and ATF1500 device fitters with the ProChip Designer® and WinCUPL PLD development software tools. The ATF15XX family of Complex Programmable Logic Devices (CPLDs) includes the ATF1502, ATF1504 and ATF1508 devices, while the ATF1500 family includes the ATF1500A and ATF1500AL devices. The device fitters are used to place and route designs into ATF15XX or ATF1500 CPLDs and to generate JEDEC® files. This guide introduces the macrocell (MC) and device features of these CPLDs and provides a detailed description of the fitting process and available fitter options. Design examples are included to illustrate the features of the ATF15XX and ATF1500 families and the various fitter command options. Please note that the device fitter options for the ATF1500 (FIT1500) differ slightly from those available for the ATF15XX device fitters (FIT15XX).

Table of Contents

Introduction....1

1. Architectural Features....3

1.1. Macrocell (MC) Features....5
1.2. Foldback Logic....7
1.3. Cascade Logic....7
1.4. Power-Down Control....7
1.5. Slew Rate Control....7
1.6. Logic Doubling....8
1.7. Pin/Node Maps....8

1. Using the ATF15XX Fitter....17

2.1. Operation....17

1. FIT1500 and FIT15XX Options and Strategies 20

3.1. Basic Options....20
3.2. Advanced Options and Strategies....21

1. The Fitting Process Flow.... 31

4.1. Design Passes....31
4.2. Design Rule Check 34
4.3. Assign Global Input Pins.... 34
4.4. Logic Optimization....34
4.5. Control Signal Patching....36
4.6. Signal/Design Placement 36
4.7. Fuse mapping....36

1. Interpreting the Fitter Report.... 37

2. Fitter Hints....43

6.1. Hint 1 - Do Not Assign Pins....43
6.2. Hint 2 - Use Default Properties and Strategies.... 43
6.3. Hint 3 - Using Cascade Logic for Design Performance....43
6.4. Hint 4 - Using Foldback Logic.... 43
6.5. Hint 5 - Use XOR Synthesis.... 44
6.6. Hint 6 - Prevent Certain Nodes from Collapsing....44
6.7. Hint 7- Using Slew Rate Control....44
6.8. Hint 8 - Using the Power-Down Pin....44

1. Revision History......45

Microchip Information....46

Trademarks....46
Legal Notice....46
Microchip Devices Code Protection Feature....46

Product Page Links....47

1. Architectural Features

The ATF1500A/AL and ATF1502 devices are offered in 44-lead PLCC/TQFP packages. The ATF1504 is offered in 44-lead PLCC/TQFP, 84-lead PLCC and 100-lead TQFP packages. The ATF1508 is offered in 84-lead PLCC, 100-lead TQFP/PQFP and 128-lead LQFP packages.

Table 1-1. ATF1500 and ATF15XX Families of CPLDs

Device # of Macrocells ISP Description
ATF1500A 32 No 5V Standard Power Device
ATF1500AL 32 No 5V Low-Power Device
ATF1502AS 32		Yes 5V Standard Power DeviceATF1504AS 64
ATF1508AS 128
ATF1502ASL 32		Yes 5V Low-Power DeviceATF1504ASL 64
ATF1508ASL 128
ATF1502ASV	32	Yes 3.3V Standard Power Device
ATF1504ASV	64
ATF1508ASV	128
ATF1504ASVL	64	Yes 3.3V Low-Power Device
ATF1508ASVL	128

The macrocell architecture of the ATF1502, ATF1504 and ATF1508 devices is identical, with slight differences compared to the ATF1500A/AL.

The ATF1500A/AL devices (non-ISP) use a globally connected architecture, in which any pin can be routed to any other pin. In contrast, the ATF1502/1504/1508 devices have a defined number of pins and feedback signals that are routed to Logic Array Blocks (LABs) through a Universal Interconnect Matrix (UIM). Each LAB contains 16 macrocells.

Figure 1-1. ATF1508 Block Diagram

graph TD
    subgraph I/O_Pins["6 to 12"]
        A["Macrocells 1 to 16"] -->|16| B["Regional Fodbacks"]
        B --> C["Switch Matrix"]
        C --> D["Global BUS (INPUTS AND FEEDBACKS BUS)"]
    end

    subgraph_Logic_Pins["Logic Block B"]
        E["Logic Block C"]
        F["Logic Block D"]
        G["Logic Block E"]
    end

    subgraph_Logic_Flops["Logic Block F"]
        H["Logic Block G"]
        I["Logic Block H"]
    end

    subgraph I/O_Pins["IO Pins"]
        J["IO Pins"]
        K["IO Pins"]
        L["IO Pins"]
        M["IO Pins"]
        N["IO Pins"]
        O["I/O (MC128)/GCLK3"]
        P["INPUT/GCLK1"]
        Q["INPUT/OE2/GCLK2"]
        R["INPUT/GCLR"]
    end

    subgraph_Global_BUS["GLOBAL BUS (INPUTS AND FEEDBACKS BUS)"]
        S["GOE[0:5"]]
        T["GCK[0:2"]]
        U["GCLEAR"]
        V["Output Enable Switch Matrix"]
        W["GCK[0:2"]]
        X["GCLEAR"]
    end

    I/O_Pins --> A
    I/O_Pins --> E
    I/O_Pins --> F
    I/O_Pins --> M
    I/O_Pins --> O
    I/O_Pins --> R
    I/O_Pins --> S
    I/O_Pins --> T
    I/O_Pins --> U
    I/O_Pins --> V
    I/O_Pins --> W
    I/O_Pins --> X
    I/O_Pins --> Y
    I/O_Pins --> Z
    I/O_Pins --> AA
    I/O_Pins --> AB
    I/O_Pins --> AC
    I/O_Pins --> AD
    I/O_Pins --> AE
    I/O_Pins --> AF
    I/O_Pins --> AG
    I/O_Pins --> AH
    I/O_Pins --> AI
    I/O_Pins --> AJ
    I/O_Pins --> AK
    I/O_Pins --> AL
    I/O_Pins --> AM
    I/O_Pins --> AN
    I/O_Pins --> AO
    I/O_Pins --> AP
    I/O_Pins --> AQ
    I/O_Pins --> AR
    I/O_Pins --> AS
    I/O_Pins --> AT
    I/O_Pins --> AU
    I/O_Pins --> AV
    I/O_Pins --> AW
    I/O_Pins --> AX
    I/O_Pins --> AY
    I/O_Pins --> AZ
    I/O_Pins --> BA
    I/O_Pins --> BB
    I/O_Pins --> BC
    I/O_Pins --> BD
    I/O_Pins --> BE
    I/O_Pins --> BF
    I/O_Pins --> BG
    I/O_Pins --> BH
    I/O_Pins --> BI
    I/O_Pins --> BJ
    I/O_Pins --> BK
    I/O_Pins --> BL
    I/O_Pins --> BM
    I/O_Pins --> BN
    I/O_Pins --> BO
    I/O_Pins --> BP
    I/O_Pins --> BPB
    I/O_Pins --> BPK
    I/O_Pins --> BPL
    I/O_Pins --> BPM
    I/O_Pins --> BPN
    I/O_Pins --> BPO
    I/O_Pins --> BPQ
    I/O_Pins --> BPR
    I/O_Pins --> BPS
    I/O_Pins --> BPT
    I/O_Pins --> BPU
    I/O_Pins --> BPV
    I/O_Pins --> BPW
    I/O_Pins --> BPX
    I/O_Pins --> BPY
    I/O_Pins --> BPZ
    I/O_Pins --> BPYB
    I/O_Pins --> BPZB
    I/O_Pins --> BPZC
    I/O_Pins --> BPZD
    I/O_Pins --> BPZE
    I/O_Pins --> BPZF
    I/O_Pins --> BPZG
    I/O_Pins --> BPZH
    I/O_Pins --> BPZI
    I/O_Pins --> BPZJ
    I/O_Pins --> BPZK
    I/O_Pins --> BPZL
    I/O_Pins --> BPZM
    I/O_Pins --> BPZM'
    I/O_Pins --> BPZM'

Figure 1-2. ATF1500A Block Diagram

graph TD
    subgraph_Global_BUS["Global Bus"]
        A1["(44, 38) INPUT/OE1"] --> B1["MACROCELL 1"]
        A2["(2, 40) INPUT/OE2"] --> B2["MACROCELL 2"]
        A3["INPUT/CLK (43, 37)"] --> B3["MACROCELL 17"]
        A4["INPUT/GCLR (1, 39)"] --> B4["MACROCELL 18"]
        A5["VO / PD (4, 42)"] --> B5["MACROCELL 1"]
        A6["VO (5, 43)"] --> B6["MACROCELL 2"]
        A7["IO (12, 6)"] --> B7["MACROCELL 8"]
        A8["IO (13, 7)"] --> B8["MACROCELL 9"]
        A9["IO (21, 15)"] --> B9["MACROCELL 16"]
    end

    subgraph_Regional_FoldBack_Bus["Regional Foldback Bus"]
        B1 --> C1["MACROCELL 16"]
        B2 --> C2["MACROCELL 16"]
        B3 --> C3["MACROCELL 16"]
        B4 --> C4["MACROCELL 16"]
        B5 --> C5["MACROCELL 16"]
        B6 --> C6["MACROCELL 16"]
        B7 --> C7["MACROCELL 16"]
        B8 --> C8["MACROCELL 16"]
        B9 --> C9["MACROCELL 16"]
    end

    subgraph Regional_FoldBack_Bus
        C1 --> D1["MACROCELL 16"]
        C2 --> D2["MACROCELL 16"]
        C3 --> D3["MACROCELL 16"]
        C4 --> D4["MACROCELL 16"]
        C5 --> D5["MACROCELL 16"]
        C6 --> D6["MACROCELL 16"]
        C7 --> D7["MACROCELL 16"]
        C8 --> D8["MACROCELL 16"]
    end

    subgraph PIN_FoldBack_Bus
        D1 --> E1["IPIN # PLCC TQFP"]
        D2 --> E2["Vcc: (3, 41) (15, 9) (23, 17) (35, 29)"]
        D3 --> E3["GND: (10, 4) (22, 16) (30, 24) (42, 36)"]
    end

    style Global_BUS fill:#f9f,stroke:#333
    style Regional_FoldBack_Bus fill:#ccf,stroke:#333

1.1. Macrocell (MC) Features

The ATF1500 and ATF15XX devices have distinct features for each macrocell, as detailed in Table 1-2.

Table 1-2. ATF1500 and ATF15XX Macrocell Features

ATF1500 Macrocell ATF15XX Macrocell
Global or product-term controlled Output Enable originate from the Input pins	Global (GOE0-GOE5) or product-term controlled Output Enable originate from the switch matrix
Global or product-term controlled Reset inputs Global or product-term controlled Reset inputs
Global or product-term controlled clock inputs 3 global clocks or product-term clock input
Product-term controlled Clock Enable and Preset inputs Product-term controlled Clock Enable and Preset inputs
5 product terms per MC 5 product terms per MC
Foldback and cascade logic Foldback and cascade logic
Independently configurable D/T/L flip-flop	Independently configurable D/T/L flip-flop
Combinatorial Output with a Buried Register option	Combinatorial Output with a Buried Register option or Buried Combinatorial Output with Registered Output
Pin-controlled or Automatic Power-Down Control options Pin-controlled or Automatic Power-Down Control options
Slew rate control on each output Slew rate control on each output
Programmable pin-keeper circuits Programmable pin-keeper circuits
The ATF1500A is a non-ISP device 4 JTAG port pins that allow for In-System Programming (ISP)
	Open collector outputs
	Fast input from the I/O pin

Figure 1-3 and Figure 1-4 illustrate the MC architectures for the ATF15xx and ATF1500 devices. The MC architecture is the same for the ATF1502, ATF1504 and ATF1508 devices, and it differs slightly from that of the ATF1500.

Figure 1-3. ATF15XX Macrocell

graph TD
    A["Global Bus"] --> B["Switch Matrix"]
    B --> C["40 Inputs for Better Connectivity"]
    C --> D["Switch Matrix Outputs"]
    D --> E["Regional Foldback Bus"]
    E --> F["CASIN"]
    F --> G["Product Term MUX"]
    G --> H["PT1 PT2 PT3"]
    H --> I["Logic Foldback"]
    I --> J["GOE[0:5"] 6]
    J --> K["Individual Output Enables for Full I/O Control"]
    K --> L["AP D/T*L Q CK/CK/LE CE AR"]
    L --> M["I/O Pin"]
    M --> N["Open Collector"]
    N --> O["I/O Pin"]
    O --> P["Slew Rate"]
    P --> Q["Individual Feedbacks for Extra Latches"]
    Q --> R["GCLEAR"]
    R --> S["PT4 PT5"]
    S --> T["Local Logic Block"]
    T --> U["PT1 PT2 PT3"]
    U --> V["Local Logic Block"]
    V --> W["PT4 PT5"]
    W --> X["Local Logic Block"]
    X --> Y["TOU Logic Block"]
    Y --> Z["TOU Logic Block"]
    Z --> AA["TOU Logic Block"]
    AA --> AB["TOU Logic Block"]
    AB --> AC["TOU Logic Block"]
    AC --> AD["TOU Logic Block"]
    AD --> AE["TOU Logic Block"]
    AE --> AF["TOU Logic Block"]
    AF --> AG["TOU Logic Block"]
    AG --> AH["TOU Logic Block"]
    AH --> AI["TOU Logic Block"]
    AI --> AJ["TOU Logic Block"]
    AJ --> AK["TOU Logic Block"]
    AK --> AL["TOU Logic Block"]
    AL --> AM["TOU Logic Block"]
    AM --> AN["TOU Logic Block"]
    AN --> AO["TOU Logic Block"]
    AO --> AP["TOU Logic Block"]
    AP --> AQ["TOU Logic Block"]
    AQ --> AR["TOU Logic Block"]
    AR --> AS["TOU Logic Block"]
    AS --> AT["TOU Logic Block"]
    AT --> AU["TOU Logic Block"]
    AU --> AV["TOU Logic Block"]
    AV --> AW["TOU Logic Block"]
    AW --> AX["TOU Logic Block"]
    AX --> AY["TOU Logic Block"]
    AY --> AZ["TOU Logic Block"]
    AZ --> BA["TOU Logic Block"]
    BA --> BB["TOU Logic Block"]
    BB --> BC["TOU Logic Block"]
    BC --> BD["TOU Logic Block"]
    BD --> BE["TOU Logic Block"]
    BE --> BF["TOU Logic Block"]
    BF --> BG["TOU Logic Block"]
    BG --> BH["TOU Logic Block"]
    BH --> BI["TOU Logic Block"]
    BI --> BJ["TOU Logic Block"]
    BJ --> BK["TOU Logic Block"]
    BK --> BL["TOU Logic Block"]
    BL --> BM["TOU Logic Block"]
    BM --> BN["TOU Logic Block"]
    BN --> BO["TOU Logic Block"]
    BO --> BP["TOU Logic Block"]
    BP --> BQ["TOU Logic Block"]
    BQ --> BR["TOU Logic Block"]
    BR --> BS["TOU Logic Block"]
    BS --> BT["TOU Logic Block"]
    BT --> BU["TOU Logic Block"]
    BU --> BV["TOU Logic Block"]
    BV --> BW["TOU Logic Block"]
    BW --> BX["TOU Logic Block"]
    BX --> BY["TOU Logic Block"]
    BY --> BZ["TOU Logic Block"]

Figure 1-4. ATF1500A Macrocell

graph TD
    A["AND Logic Array"] --> B["Global Feedback BUS"]
    A --> C["FOLDBACK BUS"]
    B --> D["PTMU"]
    C --> D
    D --> E["Foldback Logic"]
    E --> F["CASIN (Cascade Logic - Borrowed from Previous Macrocell)"]
    F --> G["Product Term OE Option"]
    G --> H["SLEW RATE"]
    H --> I["IO"]
    D --> J["GCLR"]
    D --> K["Buried Macrocell Feedback"]
    D --> L["Pin Feedback"]
    J --> M["SCL"]
    K --> N["EN CLR"]
    L --> O["PR D/T/L Q"]
    M --> P["OE1 OE2"]
    N --> Q["OE2"]
    O --> R["OE1 OE2"]

1.2. Foldback Logic

Each ATF15XX/ATF1500 MC contains foldback logic nodes. These nodes enable the implementation of complex functions that require additional logic. All foldback logic nodes are connected to the foldback bus. The ATF15XX/ATF1500 devices contain multiple foldback buses, each allocated to a group of 16 MCs. The foldback logic nodes for the first group (MC1 through MC16) are connected to one foldback bus, while the nodes for the second group (MC17 through MC32) are connected to the other foldback bus.

1.3. Cascade Logic

Cascade logic allows a macrocell (MC) to borrow from an adjacent MC. This feature is available on all macrocells except the corner macrocells (MC1, MC9, MC17 and MC25). It is particularly useful for designs that require large product-term fan-in, such as state machines or high-performance designs where speed is important. Each macrocell can borrow up to five product terms from an adjacent macrocell, and multiple macrocells can be cascaded to provide up to 40 product terms for a single macrocell.

1.4. Power-Down Control

The ATF15XX devices support a pin-controlled power-down option which, when enabled, allows the user to place the device into a Zero-Power mode with standby current in the microampere range. In addition, the ATF15XXASL/ASVL low-power devices include an automatic power-down feature that powers down the device when no transitions occur on any inputs, internal feedbacks or I/O pins. The ATF15XX fitter provides a command option to enable the pin-controlled power-down feature.

1.5. Slew Rate Control

Each macrocell output in the ATF15XX family includes a programmable slew-rate control bit. This feature can be used to reduce system noise by slowing outputs that do not require maximum switching speed. By default, all outputs are set to the slower switching rate unless explicitly configured for fast switching through the ATF15XX fitter's slew rate control option.

1.6. Logic Doubling

"Logic Doubling" refers to the efficient and flexible CPLD architecture implemented across all ATF15XX devices. The ATF15XX family incorporates several features designed to improve connectivity and logic reusability, including:

• Increased availability of crosspoint multiplexers (MUXs) to support higher input node fan-in
• Wider MUX channels feeding the Logic Array Blocks (LABs)
• Dual, independent feedback paths for each macrocell. The buried and pin-driver paths are split, allowing a register output to be buried while independently driving a combinatorial pin, or vice versa.
• Independent product-term controlled output enable for every macrocell
• Selectable global clock polarity, supporting either rising or falling edge operation
• Global RESET functionality that can be logically combined (ORed) with a local product term

1.7. Pin/Node Maps

The pin and node assignments for the ATF1500 device in both PLCC and TQFP packages are shown in Table 1-3. This table also shows the node assignments for Foldback logic and Buried registers (feedback nodes) available in each macrocell (MC).

Table 1-3. ATF1500 Pin/Node List

MC	Foldback Node Number	Feedback Node Number	Pinout 44-Pin PLCC Pinout 44-Pin TQFP
1 45 77 4 42
2 46 78 5 43
3 47 79 6 44
4 48 80 7 1
5 49 81 8 2
6 50 82 9 3
7 51 83 11 5
8 52 84 12 6
9 53 85 13 7
10 54 86 14 8
11 55 87 16 10
12 56 88 17 11
13 57 89 18 12
14 58 90 19 13
15 59 91 20 14
16 60 92 21 15
17 61 93 41 35
18 62 94 40 34
19 63 95 39 33
20 64 96 38 32
21 65 97 37 31
22 66 98 36 30
23 67 99 34 28
24 68 100 33 27
25 69 101 32 26
26 70 102 31 25
27 71 103 29 23
28 72 104 28 22
29 73 105 27 21
30 74 106 26 20
31 75 107 25 19
32 76 108 24 18

Table 1-4 shows the pin and node assignments for the ATF1502 device in both PLCC and TQFP packages. While the feedback and foldback node numbers are provided for reference, it is recommended that Pinnode numbers not be pre-assigned, allowing the fitter to determine the most optimal resource allocation.

Table 1-4. ATF1502 Pin/Node List

MC LAB		Feedback Node Number	Foldback Node Number	Signal Name	Pinout 44-Pin PLCC	Pinout 44-Pin TQFP
INPUT none none (OE2/GCLK2) 2 40
INPUT none none (GCLK1) 43 37
INPUT none none (GCLR) 1 39
INPUT none none (OE1) 44 38
1	A	601 301		4 42
2		602 302		5 43
3		603 303		6 44
4		604 304		7 (TDI)	1 (TDI)
5		605 305		8	2
6		606 306		9	3
7		607 307		11 5
8		No Casout 608	308		12 6
9		609 309		13 (TMS)	7 (TMS)
10		610 310		14 8
11		611 311		16 10
12		612 312		17 11
13		613 313		18 12
14		614 314		19 13
15		615 315		20 14
16		No Casout 616	316		21 15
17		617 317 41	35
18 618 318 40 34
19 619 319 39 33
20 620 320 38 (TDO) 32 (TDO)
21 621 321 37 31
22 622 322 36 30
23 623 323 34 28
24 No Casout 624 324 B	33 27
25 625 325 32 (TCK) 26 (TCK)
26 626 326 31 25
27 627 327 29 23
28 628 328 28 22
29 629 329 27 21
30 630 330 26 20
31 631 331 25 19
32 No Casout 632 332 24 18

Table 1-5 lists the pin and node numbers for the ATF1504 device across the supported package options. To enable optimal resource utilization, it is recommended that Foldback and Buried Feedback node numbers not be pre-assigned in the source files, allowing the fitter to place the design in the most efficient manner.

Table 1-5. ATF1504 Pin/Node List

MC LAB		Feedback Node Number	Foldback Node Number	Signal Name	Pinout for ATF1504
					44-Pin PLCC	44-Pin TQPF	68-Pin PLCC	84-Pin PLCC	100-Pin PQFP	100-Pin TQFP
INPUT none none				(OE2/ GCLK2)	2	40	2	2	92	90
INPUT		none	none	(GCLK1)	43	37	67	83	89	87
INPUT		none	none	(GCLR)	1	39	1	1	91	89
INPUT none none (OE1)			44 38	68 84 90 88
1		601 301	12 6 18 22 16 14
2 602	302 —	— — 21 15 13
3 603	303 11	5 17 20 14 12
4 604	304 9 3	15 18 12 10
5 605	305 8 2	14 17 11 9
6 606	306 —	— 13 16 10 8
7 607	307 —	— — 15 8 6
8	A	No Casout 608 308 7 1 12 14 6 4
9 609	309 —	— 10 12 4 100
10 610	310 —	— — 11 3 99
11 611	311 6 4	4 9 10 100 98
12 612	312 —	— 8 9 99 97
13 613	313 —	— 7 8 98 96
14 614	314 5 4	3 5 6 96 94
15 615	315 —	— — 5 95 93
16		No Casout 616 316 4 42 4 4 94 92
17		617 317 21 15 33 41 39 37
18 618	318 —	— — 40 38 36
19 619	319 20	14 32 39 37 35
20 620	320 19	13 30 37 35 33
21 621	321 18	12 29 36 34 32
22 622	322 —	— 28 35 33 31
23 623	323 —	— — 34 32 30
24	B	No Casout 624 324 17 11 27 33 31 29
25 625	325 16	10 25 31 27 25
26 626	326 —	— — 30 25 23
27 627	327 —	— 24 29 23 21
28 628	328 —	— 23 28 22 20
29 629	329 —	— 22 27 21 19
30 630	330 14	8 20 25 19 17
31 631	331 —	— — 24 18 16
32		No Casout 632 332 13 7 19 23 17 15
33		633 333 24 18 36 44 42 40
34 634	334 —	— — 45 43 41
35 635	335 25	19 37 46 44 42
36 636	336 26	20 39 48 46 44
37 637	337 27	21 40 49 47 45
38 638	338 —	— 41 50 48 46
39 639	339 —	— — 51 49 47
40		No Casout 640 340 28 22 42 52 50 48
41 641	341 29	23 44 54 54 52
42 642	342 —	— — 55 56 54
43 643	343 —	— 45 56 58 56
44 644	344 —	— 46 57 59 57
45 645	345 —	— 47 58 60 58
46 646	346 31	25 49 60 62 60
47 647	237 —	— — 61 63 61
48		No Casout 648 348 32 26 50 62 64 62
49		649 349 33 27 51 63 65 63
50 650	350 —	— — 64 66 64
51 651	351 34	28 52 65 67 65
52 652	352 36	30 54 57 69 67
53 653	353 37	31 55 58 70 68
54 654	354 —	— 56 59 71 69
55 655	355 —	— — 70 73 71
56		No Casout 656 356 38 32 57 71 75 73
57 657	357 39	33 59 73 77 75
58 658	358 —	— — 74 78 76
59 659	359 —	— 60 75 81 79
60 660	360 —	— 61 76 82 80
61 661	361 —	— 62 77 83 81
62 662	362 40	34 64 79 85 83
63 663	363 —	— — 80 86 84
64		No Casout 664 364 41 35 65 81 87 85

Table 1-6 lists the pin and node numbers for the ATF1508 device across the supported package options. To ensure efficient fitting, it is recommended that Foldback and Buried Feedback node numbers not be pre-assigned in the source files.

Table 1-6. ATF1508Pin/Node List

MC LAB		Feedback Node Number	Foldback Node Number	Signal Name	Pinout for ATF1508
					84-Pin PLCC	100-Pin PQPF	100-Pin TQFP	128-Pin LQFP	160-Pin PQFP
INPUT none none				(OE2/ GCLK2) 2 92 90 117 142
INPUT none none (GCLK1) 83 89 87 114 139
INPUT none none (GCLR) 1 91 89 116 141
INPUT none none (OE1) 84 90 88 115 140
1	A	601 301		—	4 2 3 160
2		602	302		—	—	—	—	—
3		603 303		12 3 1 2 159
4		604	304		—	—	—	1	158
5		605 305		11 2 100 128 153
6		606 306		10 1 99 127 152
7		607	307		—	—	—	—	—
8		No Casout 608	308		9 100 98 126 151
9		609 309		—	99 97 125 150
10		610	310		—	—	—	—	—
11		611 311		8 98 96 124 149
12		612	312		—	—	—	122	147
13		613 313		6 96 94 121 146
14		614 314		5 95 93 120 145
15		615	315		—	—	—	—	—
16		No Casout 616	316		4 94 92 119 144
17	B	617 317		22 16 14 20 21
18		618	318		—	—	—	—	—
19		619 319		21 15 13 19 20
20		620	320		—	—	—	18	19
21		621 321		20 14 12 17 18
22		622 322		—	12 10 15 16
23		623	323		—	—	—	—	—
24		No Casout 624	324		18 11 9 14 15
25		625 325		17 10 8 13 14
26		626	326		—	—	—	—	—
27		627 327		16 9 7 12 13
28		628	328		—	—	—	11	12
29		629 329		15 8 6 10 11
30		630 330		—	7 5 9 10
31		631	331		—	—	—	—	—
32		No Casout 632	332		14 6 4 8 9
MC LAB		Feedback Node Number	Foldback Node Number	Signal Name	Pinout for ATF1508
					84-Pin PLCC	100-Pin PQPF	100-Pin TQFP	128-Pin LQFP	160-Pin PQFP
33		633 333 —	27 25 36 41
34 634	334 — — — —
35 635	335 31 26 24 32 33
36 636	336 — — — 31 32
37 637	337 30 25 23 30 31
38 638	338 29 24 22 29 30
39 639	339 — — — —
40 No Casout C	640 340 28 23 21 28 29
41 641	341 — 22 20 27 28
42 642	342 — — — —
43 643	343 27 21 19 26 27
44 644	344 — — — 24 25
45 645	345 25 19 17 23 24
46 646	346 24 18 16 22 23
47 647	237 — — — —
48 No Casout D	648 348 23 17 15 21 22
49		649 349 41 39 37 50 59
50 650	350 — — — —
51 651	351 40 38 36 49 58
52 652	352 — — — 48 57
53 653	353 39 37 35 47 56
54 654	354 — 35 33 45 54
55 655	355 — — — —
56 No Casout D	656 356 37 34 32 44 53
57 657	357 36 33 31 43 52
58 658	358 — — — —
59 659	359 35 32 30 42 51
60 660	360 — — — 41 50
61 661	361 34 32 29 40 49
62 662	362 — 30 28 39 48
63 663	363 — — — —
64 No Casout D	664 364 33 29 27 38 43
		728 428 81 87 85 112
127 727	427 —	— — — —
126 726	426 80	86 84 111 136
125 725	425 79	85 83 110 135
124 724	424 —	— — 109 134
123 723	423 77	83 81 107 132
122 722	422 —	— — — —
121 No	Casout H	721 421 — 82 80 106 131
120 720	420 76	81 79 105 130
119 719	419 —	— — — —
118 718	418 75	80 78 104 129
117 717	417 74	79 77 103 128
116 716	416 —	— — 102 123
115 715	415 73	78 76 101 122
114 714	414 —	— — — —
113 No	Casout	713 413 — 77 75 100 121
112		712 412 71 75 73 95 112
111 711	411 —	— — — —
110 710	410 —	74 72 94 111
109 709	409 70	73 71 93 110
108 708	408 —	— — 92 109
107 707	407 69	72 70 91 108
106 706	406 —	— — — —
105 No	Casout G	705 405 68 71 69 90 107
104 704	404 67	70 68 89 106
103 703	403 —	— — — —
102 702	402 —	69 67 88 105
101 701	401 65	67 65 86 103
100 700	400 —	— — 85 102
99		699 399 64 66 64 84 101
98		698 398 — — — — —
97		No Casout 697 397 63 65 63 83 100
96		696 396 62 64 62 82 99
95 695	395 — — — —
94 694	394 61 63 61 81 98
93 693	393 60 62 60 80 97
92 692	392 — — — 79 96
91 691	391 58 60 58 77 94
90 690	390 — — — —
89 No Casout F	689 389 — 59 57 76 93
88 688	388 57 58 56 75 92
87 687	387 — — — —
86 686	386 56 57 55 74 91
85 685	385 55 56 54 73 90
84 684	384 — — — 72 89
83 683	383 54 55 53 71 88
82 682	382 — — — —
81 No Casout	681 381 — 54 52 67 80
80		680 380 52 52 50 65 78
79 679	379 — — — —
78 678	378 — 51 49 64 73
77 677	377 51 50 48 63 72
76 676	376 — — — 62 71
75 675	375 50 49 47 61 70
74 674	374 — — — —
73 No Casout E	673 373 49 48 46 60 69
72 672	372 48 47 45 59 68
71 671	371 — — — —
70 670	370 — 46 44 58 67
69 669	369 46 44 42 56 65
68 668	368 — — — 55 64
67 667	367 45 43 41 54 63
66 666	366 — — — —
65 No Casout	665 365 44 42 40 53 62

2. Using the ATF15XX Fitter

This section explains how to use the fitter tools available in the ProChip Designer® and WinCUPL PLD development software.

2.1. Operation

The fitters are designed to run automatically in ProChip Designer® and WinCUPL. By specifying the device type in the project file, the appropriate compiler automatically executes the fitter software. For CUPL designs, fitter operation can be customized using DOS command-line options, PROPERTY statements, or macros defined in the source file. These customization methods are described in detail later in this user guide.

2.1.1. VHDL or Verilog Designs Using ProChip Designer ^®

For VHDL and Verilog designs, source files are compiled in ProChip Designer® to generate an EDIF netlist. After the EDIF file is created, users can access the Device Fitter properties window within ProChip Designer and configure settings under the Global Device, MC & I/O or Pins tab to define global, macrocell or pin-specific properties. To execute the fitter, users select the RunFitter button (as shown in Figure 2-1). This process generates both the Fitter Report file (.FIT) and the JEDEC programming file (.JED).

Figure 2-1. ProChip Designer® Device Pin/Node Options Window

Fitter options Global Configuration JTAG ✓ JTAG Port ✓ TDI Pullup ✓ TMS Pullup Power Reset ○ Large Hysteresis ● Small Hysteresis Pin Fit Control ○ Ignore ● Keep ○ Try Power Save □ Pin Power Down 1 □ Pin Power Down 2 □ GCLK Auto Wake ○ GCLK1 Auto Wake ○ GCLK2 Auto Wake ○ GCLK3 Auto Wake Device Logic Options ✓ Optimize □ Latch Synthesis ✓ Not Gate Push Back Logic Doubling ○ always ● if necessary Simulation ✓ Generate Sim Files Security □ Secure Device Files Global Device MC & I/O Pins Close RunFitter Default Help

2.1.2. CUPL Designs via WinCUPL

For CUPL designs developed using WinCUPL, fitter options can be specified directly within the CUPL design file (.PLD) using PROPERTY statements.

The PROPERTY statement allows users to define any fitter options described in the Basic Options and Advanced Options and Strategies sections of this user guide. Examples demonstrating the use of PROPERTY statements in CUPL designs are provided below.

The syntax for a PROPERTY statement in a CUPL design is:

PROPERTY ATMEL {fitter option};

The following CUPL example illustrates the use of this statement. Note that a separate PROPERTY statement is required for each strategy, and the keyword "str" is not required in the expression.

Table 2-1. CUPL PROPERTY Statement Example

004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 033 034 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 100
    ( ) 

2.1.3. CUPL Designs Using ProChip Designer ^®

For CUPL designs, the source design file can be compiled using WinCUPL to generate a PLA netlist file. Once the PLA file is created, it can be imported into a ProChip Designer project. Users can then open the Device Fitter properties window and select the Global Parameters or Advanced options to define individual pin or MC properties. To complete the process, users select the RunFitter button to fit the design and generate both the Fitter Report file (.FIT) and the JEDEC programming file (.JED).

2.1.4. Command Line

The fitters can also be executed from the DOS command line. The command syntax shown below applies to the ATF1500 and ATF1502 devices and is identical for the ATF1504 and ATF1508 devices. A detailed description of each option is provided in FIT1500 and FIT15XX Options and Strategies.

fit1500 [-i] input_file[.tt2] {options}
Options:
-help
-o output_file_name (for *.tt3 and *.jed)
-log report_file (*.doc)
-err error_file (*.err)
-device device_name (P1500/P1500T/P1500A)
-module module_name
-preassign TRY|keep|ignore (pin preassignment options)
-silent (no message on screen)
-h2 (advanced help option)

FIT1502.EXE [-i] input_file[.tt2] {options}
Options:
-help
-o output_file_name (for *.tt3 and *.jed)
-device package_type (PLCC44/TQFP44)
-tech tech_name (ATF1502AS/ATF1502ASV/ATF1502BE)
-module module_name
-preassign TRY|keep|ignore (pin preassignment options)
-silent (no message on screen)
-h2 (advanced help option)
-has (advanced help option for AS)
-hbe (advanced help option for BE) 

3. FIT1500 and FIT15XX Options and Strategies

The FIT1500 and FIT15XX fitters support both basic and advanced options and strategies that allow users to customize the operation of the fitter to meet the design requirements. Both sets of options are discussed below.

3.1. Basic Options

[-i] Input File Name (FIT1500 and FIT15XX)

Specifies the location and name of the input netlist file (.tt2 or .edf).

fit1502 -i c:\wincupl\project\project1.tt2 -cupl

Executes the fitter from the command line and reads the project1.tt2 file from the c:\wincupl\project directory.

fit1502 -i c:\Prochip\Designs\vhdl\shift.edf -ifmt EDIF -lib aprim.lib -device 44-TQFP -tech ATF1502AS

Executes the fitter from the command line and reads the shift.edf file from the c:\Prochip\Designs\vhdI directory.

[-o] Output File Names (FIT1500 and FIT15XX)

Specifies custom output file names or output directories for the post-fit PLA and JEDEC files created by the fitter. By default, the fitter creates a post-fit PLA file [.tt3] and a JEDEC [.jed] file. These files are saved in the working directory. For example, using the command

fit1502 design -o c:\fit1502\project\project1.pla

saves the post-fit PLA file as project1.pla and the JEDEC file as project1.jed in the c:\fit1502\project subdirectory.

[-log] Fitter Report File Name (FIT1500 only)

Specifies a custom name or directory for the fitter report file. By default, the fitter generates a report file with a [.fit] extension in the working directory. This report summarizes the results of the fitting process. The contents of this file and how they can be interpreted are discussed in more detail in Interpreting the Fitter Report. Using the command

fit1500 design -log c:\fit1502\project\project1.fit

saves the fitter report as project1.fit in the c:\fit1502\project subdirectory.

[-err] Error File (FIT1500 only)

Specifies a custom name or directory for the error file, which records any errors or warnings encountered during fitting. By default, the error file [.err] is created in the working directory.

fit1500 design -err c:\fit1500\project\project1.err

Saves the error file as project1.err in the c:\fit1500\project subdirectory.

[-device] [-tech] Target Device (FIT1500 and FIT15XX)

For the FIT1500, the -device option specifies the target device type, including package type. For the FIT15XX, the -device option specifies the package type and must be used in conjunction with the -tech option to define the target device. For example, the command

fit1500 -i shift.tt2 -device P1500AT

specifies the ATF1500A 44-TQFP as the target device type. For the FIT15XX, the command

fit1502 -i shift.tt2 -device TQFP44 -tech ATF1502ASV

specifies the ATF1500A 44-TQFP as the target device type.

[-preassign TRY | keep | ignore] Preassign Pins (FIT1500 and FIT15XX)

Controls how FIT1500 and FIT15XX should handle pin or node assignments defined in the VHDL, Verilog or CUPL source file. For VHDL and Verilog designs, pin assignments are generated in a pin file (.pin) through the ProChip Designer® flow. There are three pre-assignment options available: KEEP, TRY and IGNORE. If no option is specified, the fitter defaults to TRY.

KEEP Option

Preserves all user-defined pin and node assignments. Unassigned pins and nodes are automatically assigned by the fitter. The fitting process fails if the specified pin and node pre-assignments prevent the design from fitting into the target CPLD. For example, the following command can be used:

fit1502 design.tt2 -cupl -device TQFP44 -tech ATF1502AS -preassign KEEP

When this command is executed, the fitter retains the original pin and node assignments while attempting to fit the design.tt2file.

TRY Option

Attempts to fit the design using the Keep option first. If the design fails to fit, the fitter automatically switches to Ignore. Unassigned pins and nodes are automatically assigned by the fitter. This option is used by default when no pin or node pre-assignment options are specified in the design file or on the command line.

IGNORE Option

Instructs the fitter to first attempt fitting the design using the Keep option. If the design fails to fit, the Ignore option is applied. Any pins or notes that are not pre-assigned are automatically assigned by the fitter. This option is selected by default when no pin or node pre-assignment options are specified in the design file or on the command line. For example, the following command can be used:

fit1504 design.tt2 -cupl -device TQFP44 -tech ATF1504ASV -preassign IGNORE

When this command is executed, the fitter ignores any pin or node assignments specified in the design source file while attempting to fit the design.tt2 file. Refer to Design Passes for more information about these options.

[-silent] Silent Option (FIT1500 and FIT15XX)

Prevents the result of the fitting process from being displayed on the console.

fit1502 design.tt2 -silent

[-help] Help Option (FIT1500 and FIT15XX)

Displays the basic fitter options available.

fit1502 -help

3.2. Advanced Options and Strategies

The advanced options and strategies allow users to customize the fitting process, allowing a desing to be fitted more efficiently and optimized for performance. Each option is described below.

The command

fit1502 -h2

displays all advanced fitting options and strategies available for ATF1502 devices.

The command

fit1504 -has

displays all advanced fitting options and strategies available for ATF1504AS/ASL/ASV/ASVL devices.

The command

fit1502 -hbe

displays all advanced fitting options and strategies available for ATF1502BE devices, which are no longer available.

The command

fit1500 -h2

displays all advanced fitting options and strategies available for ATF1500A/AL devices.

[-str ifmt TT | edif] Input Netlist File Format (FIT15XX only)

This option allows the user to specify the format of the input netlist file as either TT2 (PLA) or EDIF. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str ifmt TT

specifies that the input netlist file format is TT2 (PLA).

[-str lib] Library File Name for EDIF Input (FIT15XX only)

This option allows the user to specify the path and file name of the ATF15xx library file (APRIM.LIB) required for the EDIF netlist. The command

fit1502 design.edf -str ifmt EDIF -str lib C:\ATMEL_PLS_Tools\Prochip\PLDFit\aprim.lib defines the location and name of the library file as C:\ATMEL_PLS_Tools\Prochip\PLDFit\aprim.lib.

[-str MC\_power OFF | on = node\_name1, node\_name2, ...] Macrocell Reduced Power Mode (FIT15XX only)

This option allows the user to enable or disable the Macrocell Reduced Power feature and to specify the macrocells to which it applies. When enabled, macrocell power consumption is reduced by approximately 50%. The command

fit1502 design.tt2 -str MC\_power=ON

enables the Macrocell Reduced Power feature for all the macrocells in the ATF1502 device.

The command

fit1504 design.tt2 -str MC\_power=a,b

enables the Macrocell Reduced Power feature for the macrocells corresponding to signals named a and b, respectively. All remaining macrocells will have the Macrocell Reduced Power feature turned off.

[-str MC_power OFF | on = node_name1, node_name2, ...] Macrocell Reduced Power Mode (FIT15XX only)

This options allows the user to enable or disable the macrocell reduced power feature and to specify the macrocells to which it applies. When enabled, the macrocell power consumption is reduced by approximately 50%.

The command

fit1502 design.tt2 -str MC\_power=ON

enables the macrocell reduced power feature for all the macrocells in the ATF1502.

The command

fit1504 design.tt2 -str MC\_power=a,b

enables the macrocell reduced power feature for the macrocells corresponding to signals named a and b, respectively. All remaining macrocells will have the macrocell reduced power feature turned off.

[-str open\_collector OFF | on = pin\_name1, pin\_name2, ...] Open Collector Output (FIT15XX only)

This option allows users to enable or disable the open-collector output feature and to specify the output pins to which it applies.

The command

fit1502 design.tt2 -str open\_collector=ON

enables the open-collector output feature for all the output pins in the ATF1502 device.

The command

fit1502 design.tt2 -str open\_collector=ON

enables the open-collector output feature for the output signals named a and b, respectively. All remaining output pins will have the open-collector output feature turned off.

[-str power\_reset OFF | on] Power-up Reset Hysteresis (FIT15XX only)

This option allows the user to control the power reset hysteresis feature in the ATF15XX devices. When this option is set to off, the power-up reset hysteresis in the ATF15XX will be set to small. When this option is set to on, the power-up reset hysteresis in the ATF15XX will be set to large. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str power\_reset=ON

sets the power-up reset hysteresis in the ATF15XX to large.

[-strJTAG off | ON] JTAG Port (FIT15XX only)

This option allows users to control the JTAG port feature in the ATF15XX. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str JTAG=ON

enables the JTAG port feature in the ATF15XX device.

[-str TDI\_pullup OFF | on] Internal Pull-up Resistor on TDI Pin (FIT15XX only)

This option controls the internal pull-up resistor feature on the JTAG TDI pin. When set to on, the internal pull-up resistor on the TDI pin will be enabled. The JTAG port feature must be enabled when the internal pull-up resistor on the TDI pin is enabled. The command

fit1502design.tt2 -device TQFP44 -tech ATF1502AS -str JTAG=ON -str TDI\_pullup=ON

enables the internal pull-up resistor on the TDI pin.

[-str ues value] User Electronic Signature (FIT15XX only)

This option allows users to specify the value for the 16-bit User Electronic Signature (UES) to be programmed into the ATF15XX as 2 ASCII characters. The command

fit1502design.tt2 -device TQFP44 -tech ATF1502AS -str ues=01

sets the UES values to 01.

[-str no\_tff OFF | on] Do Not Use T Flip-flop (FIT15XX only)

This options prevents the fitter from using T flip-flops during logic implementation. This feature is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str no\_tff OFF

prevents the fitter from using T flip-flops in the logic implementation.

[-str tPD 5 | 7 | 10 | 15 | 20 | 25] Logic Optimization (FIT15XX only)

This options allows users to specify the speed grade of the target device. The post-fit timing simulation files generated by the fitter are based on the selected tPD value. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str tpd=10

specifies a target device speed grade of -10 (tPD = 10 ns).

[-str voltage\_level\_A 1.8 | 2.5 | 3.3] Voltage Level for I/O Bank A (FIT15XX only)

This option allows users to specify the voltage level for I/O Bank A of the target device. Post-fit timing simulation files are generated based on the specified voltage level. This option is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str voltage\_level\_A=3.3

specifies the voltage level for I/O Bank A to 3.3V.

[-str voltage\_level\_B 1.8 | 2.5 | 3.3] Voltage Level for I/O Bank B (FIT15XX only)

This option allows users to specify the voltage level for I/O Bank B of the target device. Post-fit timing simulation files are generated based on the specified voltage level. This option is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str voltage\_level\_B=3.3

specifies the voltage level for I/O Bank B to 3.3V.

[-str fast\_inlatch OFF | on = pin\_name1, pin\_name2, ...] Direct I/O Input (FIT15XX only)

This option instructs the fitter to attempt to use direct I/O inputs for the data input of flip-flops or latches, where possible. The command

fit1502 design.tt2 -str fast\_inlatch=ON

instructs the fitter to use direct I/O inputs for flip-flop or latch data inputs wherever possible.

The command

fit1504 design.tt2 -str open\_collector=a,b

instructs the fitter to use direct I/O inputs for pins a and b.

[-str schmitt\_trigger OFF | on = pin\_name1, pin\_name2, ...] Schmitt Trigger Input (FIT15XX only)

This option allows users to enable or disable the Schmitt Trigger input feature and to specify the input pins to which it applies. This feature is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -str schmitt\_trigger=ON

enables the Schmitt Trigger input feature for all input pins on the ATF1502BE device.

The command

fit1504 design.tt2 -str schmitt\_trigger=a,b

enables the Schmitt Trigger input feature for the input signals named a and b respectively. All remaining output pins will have the Schmitt Trigger input feature turned off.

[-str pull\_up OFF | on = pin\_name1, pin\_name2, ...] Pin Pull-up Resistor (FIT15XX only)

This option allows users to enable or disable the internal pull-up resistor and to specify the input or I/O pins to which it applies. This feature is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -str pull\_up=ON

enables the pin pull-up feature for all the input and I/O pins in the ATF1502BE device.

The command

fit1504 design.tt2 -str pull\_up=a,b

enables the pin pull-up feature for the pins named a and b respectively. All remaining input and I/O pins will have the pull-up feature turned off.

[-str unused\_To\_PinKeeper off | ON] Pin-keeper for Unused Pins (FIT15XX only)

This option allows users enable or disable the Pin-Keeper feature for unused input and I/O pins. This feature is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str unused\_To\_PinKeeper ON

instructs the fitter to enable the Pin-Keeper feature for all unused input and I/O pins on the ATF15xxBE device.

[-str pull\_up\_unused OFF | on] Pull-up for Unused Pins

This option allows users to enable or disable internal pull-up resistors for unused input and I/O pins. This feature is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str pull\_up\_unused ON

instructs the fitter to enable pull-ups for all unused input and I/O pins in the ATF15xxBE device.

[-str unused\_To\_Ground OFF | on] Set Unused Pins to Ground

This option allows users to configure unused input and I/O pins as additional ground pins. This feature is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str unused\_To\_Ground ON

instructs the fitter to configure all unused input and I/O pins as additional ground pins in the ATF15xxBE device.

[-str pull\_down OFF = pin\_name1, pin\_name2, ...] Pin Pull-Down Resistor (FIT15XX only)

This option allows users to enable or disable the internal pull-down resistor and to specify the input or I/O pins to which it applies. This feature is available only for ATF15xxBE designs. The command

fit1502 design.tt2 -str pull\_down=ON

enables the pin pull-down feature for all the input and I/O pins in the ATF1502BE.

The command

fit1504 design.tt2 -str pull_down=a,b

enables the pin pull-down feature for the pins named a and b respectively. All remaining input and I/O pins will have the pull-down feature turned off.

[-str GCLK\_ITD AUTO | on | off | GCLK1 | GCLK2 | GCLK3] Input Transition Detection for GCLK1/2/3 (FIT15XX only)

This option allows users to enable or disable the input transition detection feature and to specify the GCLK pin to which it applies. This feature is available only for ATF15xxASL/ASVL designs. The command

fit1502 design.tt2 -str GCLK_ITD=GCLK1

enables the input transition detection feature for GCLK1 pin on the ATF1502ASL device.

[-str Latch\_Synthesis ON | off] Latch Synthesis (FIT15XX only)

This option controls whether the fitter attempts to implement latches using logic gates. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str latch_synthesis=off

disables latch synthesis.

[-str optimize ON | off] Logic Optimization (FIT1500 and FIT15XX)

This options allows the user to control all of the fitter's logic optimization strategies. These strategies include Cascade and Foldback logic, XOR Synthesis and Node Collapsing. Logic optimization is enabled by default. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str optimize=off

disables all logic optimization and fits the design exactly as specified in the source file.

[-str cascade\_logic ON | Off = signal\_name,..., signal\_name] Cascade Logic (FIT1500 and FIT15XX)

This option allows users to control the use of cascade logic in ATF15xx/ATF1500 macrocells for implementing logic functions. This option can be enabled for either all output signals or for individual signals that are listed. These signals can represent either pins or nodes in the design. The cascade logic feature allows the user to borrow product terms from an adjacent macrocell with a small additional delay. This feature is useful for implementing high product term fan-in designs such as state machines or for optimizing a design for speed. This option is enabled by default. The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str cascade_logic = a,b

enables the cascade logic feature for signals named a and b, respectively in the source file. Cascade logic is disabled for all other signals.

The command

fit1502 design.tt2 -cupl -dev p1502c44 -str cascade_logic on

enables the cascade logic feature for all macrocells in the device.

The command

fit1502 design.tt2 -cupl -device TQFP44 -tech ATF1502AS -str cascade_logic off

disables the cascade logic feature for all macrocells in the ATF1502 device.

[-str foldback_logic ON | Off = signal_name,...,signal_name] Foldback Logic (FIT1500 and FIT15XX)

This option allows users to control whether foldback logic nodes are used in the ATF15XX/ATF1500 macrocells. This option can be enabled for all signals or limited to specific signals, which represent nodes in the design. This feature is useful for fitting additional logic into a macrocell when making design upgrades or modifications. Foldback logic is enabled by default. The command

fit1500 design.tt2 -strategy foldback_logic = a,b

enables the foldback logic nodes for signals named a and b, respectively. All other signals will have the foldback logic feature turned off.

The command

fit1502 design.tt2 -device TQFP44 -tech ATF1502AS -str foldback_logic on enables the foldback logic nodes for all macrocells in the ATF1502 device.

The command

fit1500 design.tt2 -device TQFP44 -tech ATF1502AS -str foldback_logic off

disables the foldback logic nodes for all macrocells.

[-strategy expander = node_name,...,node_name] Sharable Expander Logic (FIT1500 only)

This option allows users to define sharable expander logic equations in ATF1500 designs. It can be applied to all signals or to specific signals, which represent nodes in the design. When enabled, sharable expander logic equations are automatically converted to foldback logic nodes. Sharable expander logic equations include an implicit inversion. In contrast, foldback logic nodes in ATF1500 designs require the inversion be defined in the logic equations. For example,

Sharable Expander Equation Foldback Logic Equation

out = a & b; "Implicit Inversion out = !(a & b); "Inversion must be defined

The command

fit1500 design.tt2 -strategy expander = anode, bnode

converts the sharable expander nodes anode and bnode to foldback logic nodes. All other nodes default to foldback logic nodes. An example of how to use this strategy is shown in Hint 4 - Using Foldback Logic. This option is disabled by default.

[-strategy soft_buffer OFF | On = node_name,...,node_name] Node Collapsing (FIT1500 and FIT15XX)

This option allows users to prevent specific nodes from being collapsed by the fitter. By default, the fitter allows all nodes to be collapsed. This strategy can be enabled for either all signals or for individual signals. These signals represent nodes in the design. Preventing certain nodes from collapsing can help a design fit into the ATF15XX or ATF1500 devices. Please refer to the Hint 6 - Prevent Certain Nodes from Collapsing for more information about how to use the node collapsing feature. This option is disabled by default. The command

fit1500 design.tt2 -strategy soft_buffer = anode, bnode

prevents the fitter from collapsing nodes anode and bnode, respectively. All other nodes remain eligible for collapsing.

The command

fit1500 design.tt2 -strategy soft_buffer on

prevents all nodes defined in the design from collapsing.

[-str xor_synthesis ON | Off = signal_name,...,signal_name] XOR Synthesis (FIT1500 and FIT15XX)

This option allows users to control the use of the hardware XOR gate in ATF15xx/ATF1500 macrocells for logic synthesis. XOR synthesis can be enabled for all output signals or limited to specific signals, which may represent either pins or internal nodes. The hardware XOR gate is effective in reducing product-term usage for arithmetic logic, comparison functions and other XOR-based logic. When this option is enabled, the fitter uses the hardware XOR gate only if it produces fewer product terms than an equivalent non-XOR implementation. This option is enabled by default. The command

fit1500 design.tt2 -str xor_synthesis=a,b

enables the XOR Synthesis feature for signals named a and b, respectively. The feature is disabled for all remaining signals.

The command

fit1504 design.tt2 -cupl -device TQFP44 -tech ATF1504AS -str xor_synthesis on

enables XOR Synthesis feature for all macrocells in the ATF1504AS device.

The command

fit1500 design.tt2 -str xor_synthesis off

disables XOR Synthesis feature for all macrocells.

[-strategy dedicated_input ON | Off = pin_name,...,pin_name] Dedicated Inputs (FIT1500 only)

This option instructs the fitter to place selected input signals on the dedicated input pins of the ATF1500 device. Up to four input signals may be assigned, depending on the availability of global resources such as pin clocks, output enables, and reset signals. If dedicated inputs are explicitly defined in the design source file, those assignments override this option. This feature is enabled by default. The command

fit1500 design.tt2 -strategy dedicated_input = a,b

places the inputs a and b on any of the four dedicated input pins if they are available. Any remaining dedicated input pins are automatically assigned based on signal usage within the design.

The command

fit1500 design.tt2 -strategy dedicated_input off

disables the fitter from placing any input signals on the dedicated input pins of the ATF1500 device.

[-str output_fast On | OFF = pin_name,...,pin_name] Slew Rate Control (FIT1500 and FIT15XX)

This option allows the user to define the output slew rate for ATF15xx and ATF1500 devices. The slew rate can be defined as either fast or slow. The option may be applied to all output pins or limited to specific pins. By default, all outputs are configured for a slow slew rate, and this option is disabled. The command

fit1500 design -strategy output_fast = a,b

defines output signals a and b as fast slew rate outputs. All remaining output pins retain slow slew rates.

The command

fit1500 design.tt2 -strategy output_fast on

defines all output pins to have fast slew rates.

[-str pd1=on] [-str pd2=on] [-str sleep] Power-Down Control (FIT1500 and FIT15XX)

This option enables use of the power-down pin on ATF15xx and ATF1500 devices. This pin powers down the device to a zero-power mode. ATF15XX devices provide two such pins (PD1 or PD2), to enable this mode. ATF1500 devices use the SLEEP option for power-down control. When this feature is enabled, the macrocell associated with the PD pin is available for buried logic functions such as foldback or cascade logic. This option is disabled by default.

fit1502 design -str pd1=on

{Enables the power-down pin (PD1) on the ATF1502}

fit1500 design -strategy sleep

{Enables the power-down pin on the ATF1500A}

[-str jedec\_file = file\_name] JEDEC File (FIT1500 only)

This option allows users to specify a custom file name or directory for the generated JEDEC (.JED) file. By default, the fitter creates a JEDEC file using the design name and saves it in the working directory.

Using the command

fit1500 design.tt2 -strategy jedec_file = c:\fit1500\project\project.jed

saves the JEDEC file as project.jed in the c:\fit1500\project\ directory.

[-str vector\_file = file\_name] Vector File (FIT1500 only)

This option allows users to append a custom set of test vectors to the JEDEC file generated by the fitter. The vector file may be specified using a custom file name or directory. By default, the fitter reads a [.tmv] file from the working directory. The command

fit1500 design -strategy vector_file = c:\fit1500\project\project.vec

appends the vectors in the project.vec file to the c:\fit1500\project\ directory to the output JEDEC file design.jed.

[-str security OFF | on] Read Security (FIT1500 and FIT15XX)

This option controls the Read Security feature of ATF15xx and ATF1500 devices. When enabled, the device contents cannot be read back after programming. Disabling the Read Security feature requires a complete device erase. The command

fit1502 design.tt2 -str security=on

instructs the fitter to generate a JEDEC programming file (.JED) that enables the Read Security feature during device programming.

[-str pin\_keep OFF | on] Pin-Keeper Circuits (FIT1500 and FIT15XX)

This option allows the user to enable or disable the Pin-Keeper feature, which maintains the last known logic on an input or I/O pin when it is not actively driven. The command

fit1502 design.tt2 -str pin_keep=on

enables the Pin-Keeper feature on the ATF15XX/ATF1500 device.

[-str Verilog\_sim sdf | Verilog | OFF] Verilog Simulation Output Files (FIT15XX only)

This option allows the user to specify whether the Verilog timing simulation files should be generated or not. This includes the standard delay format (SDF) output and Verilog netlist output files. The command

fit1502 design.tt2 -str Verilog_sim=sdf

enables the generation of the SDF file for Verilog timing simulation.

[-str Vhdl\_sim sdf | vhdl | OFF] VHDL Simulation Output Files (FIT15XX only)

This option allows the user to specify whether the VHDL timing simulation files should be generated or not. This includes the standard delay format (SDF) output and VHDL netlist output files. The command

fit1502 design.tt2 -str Vhdl\_sim=sdf

enables the generation of the SDF file for VHDL timing simulation.

[-str Out\_Edif on | OFF] EDIF Netlist Output File (FIT15XX only)

This option allows the user to specify whether the EDIF netlist output file should be generated or not. The command

fit1502 design.tt2 -str Out\_Edif=OFF

disables the generation of the EDIF netlist output file.

[-str logic\_doubling on | OFF] Logic Doubling (FIT15XX only)

This option allows the user to specify whether the fitter should try to use the Logic Doubling features in the ATF15xx or not. The command

fit1502 design.tt2 -str logic\_doubling=on

allows the fitter to attempt to use the Logic Doubling features to fit the user's design.

4. The Fitting Process Flow

The fitter is a complex place-and-route software program that implements multiple options to fit a design into ATF15XX/ATF1500 devices. These options can be user-controlled or automatically selected by the fitter. For information on the number of design-pass iterations performed before the fitter determines whether a design can be successfully fit, refer to the sections Design Passes, Design Rule Check and Assign Global Input Pins. The fitting process is outlined in Figure 4-1.

Figure 4-1. Fitting Process

graph TD
    A["Design Rule Check"] --> B["Global pin assignments"]
    B --> C["Logic optimization"]
    C --> D["Control signal patching"]
    D --> E["Signal / design placement"]
    E --> F{Design fits?}
    F -->|No| G["Last design pass?"]
    F -->|Yes| H["Generate report file"]
    G --> I["Generate JEDEC and report files"]
    H --> I
    I --> J["Repeat fitting pass"]
    J --> A

4.1. Design Passes

Each attempt by the fitter to fit a design is referred to as a design pass. Complex designs may require multiple design passes to achieve a successful fit. The fitter initiates a new design pass only if the previous pass was unsuccessful. The number of design passes performed depends on the pre-assignment option specified by the user.

4.1.1. KEEP Option

When the Keep pre-assignment option is selected, the fitter performs the design passes illustrated in Figure 4-2. Any pins or nodes that are not pre-assigned in the design are automatically assigned by the fitter.

Figure 4-2. KEEP Option — Fitting Process

graph TD
    A["Pass 1\nFit with user-specified pin assignments and strategies only"] --> B{Design fits?}
    B -->|Yes| C["Generate JEDEC and report files"]
    B -->|No| D["Pass 2\nIgnore user-specified strategies\nKeep original pin assignments\nRefit design"]
    D --> E{Design fits?}
    E -->|Yes| F["Generate JEDEC and report files"]
    E -->|No| G["Generate report file"]

4.1.2. TRY Option

The TRY pre-assignment option is the default selected by the fitter when no pre-assignment option is specified by the user. The fitter performs the design passes illustrated in Figure 4-3. The first two passes are identical to those used for the KEEP pre-assignment option. The final design pass is identical to the IGNORE pre-assignment option. Any pins that are not assigned in the design are automatically assigned by the fitter.

Figure 4-3. TRY Option — Fitting Process

graph TD
    A["Pass 1\nFit with user-specified pin assignments and strategies only"] --> B{Design fits?}
    B -->|Yes| C["Generate JEDEC and report files"]
    B -->|No| D["Pass 2\nIgnore user-specified strategies where necessary\nKeep original pin assignments\nRefit design"]
    C --> E{Design fits?}
    D --> E
    E -->|Yes| F["Generate JEDEC and report files"]
    E -->|No| G["Pass 3\nIgnore user-specified pin assignments and strategies\nRe-assign pins\nRefit design"]
    F --> H{Design fits?}
    G --> H
    H -->|Yes| I["Generate JEDEC and report files"]
    H -->|No| J["Generate report file"]

4.1.3. IGNORE Option

If the IGNORE option is selected, the fitter performs the design passes illustrated in Figure 4-4.

Figure 4-4. IGNORE Option — Fitting Process

graph TD
    A["Pass 1\nKeep user-specified strategies\nIf no strategies, go to Pass 2, otherwise\nRe-assign pins\nRefit design"] --> B{Design fits?}
    B -->|Yes| C["Generate JEDEC and report files"]
    B -->|No| D["Pass 2\nIgnore user-specified strategies and pin assignments\nReassign pins\nRefit design"]
    C --> E{Design fits?}
    D --> E
    E -->|Yes| F["Generate JEDEC and report files"]
    E -->|No| G["Generate report file"]

4.2. Design Rule Check

The first step in the fitting process is a Design Rule Check. During this stage, the fitter checks for illegal pin assignments, such as assigning an output to a dedicated input pin. It also checks whether the design exceeds device limitations, including the number of product terms and registers being used and total number of buried resources needed. If the design uses more resources than are available in the ATF1500 or ATF15XX devices, the fitter fails the Design Rule Check and reports an error. In addition to validating the device resources, the Design Rule Check removes all unused signals from the design.

4.3. Assign Global Input Pins

During this fitting step, the fitter evaluates whether global resources are used in the design. Global input pins—such as clock, reset, or output enable signals—are assigned first, if defined in the design. Any remaining Global input pins are then assigned to user-specified input signals defined by the dedicated input strategy. If global input pins remain unassigned, or if a dedicated input strategy is not specified, input signals are assigned to these pins based on their frequently of use within the design.

4.4. Logic Optimization

After Global input pins are assigned, the fitter performs logic optimization to efficiently map the design logic into the ATF15XX/ATF1500 device. The logic optimization process flow is shown in Figure 4-5.

Figure 4-5. Logic Optimization Process

graph TD
    A["Optimization\n• Node collapsing\n• XOR-Synthesis"] --> B["User-specified cascade logic option?\n(Default on)"]
    B --> C["Cascade Logic\n• Determine the number of product terms needed\n• Determine macrocell resources to map cascaded logic\n• Map cascade logic to available macrocells\n• Determine remaining logic unable to be mapped"]
    C --> D{Design fits?}
    D -->|No Yes| E["End logic optimization process\nGo to next fitting process step"]
    D -->|Yes| F["User-specified foldback logic option?\n(Default on)"]
    F --> G["Foldback Logic\n• Factor out foldback logic nodes\n• Determine available macrocell resources to map foldback logic\n• Map remaining logic from previous pass to foldback nodes\n• Map any created foldback logic nodes\n• Determine remaining logic unable to be mapped"]
    G --> H{Design fits?}
    H -->|No| I["Buried Macrocell Feedback Nodes\n• Determine available macrocell resources\n• Map remaining logic from previous pass as buried macrocell feedback nodes"]
    H -->|Yes| J["End logic optimization process\nGo to next fitting process step"]
    I --> K{Design fits?}
    K -->|No Yes| L["Go to next fitter design pass"]
    K -->|Yes| M["End logic optimization process\nGo to next fitting process step"]
    L --> N["End logic optimization process\nGo to next fitting process step"]
    M --> N
    style A fill:#f9f,stroke:#333
    style N fill:#f9f,stroke:#333

4.5. Control Signal Patching

Control Signal Patching is performed when a design has multiple product term flip-flop clocks, clock enables, resets, presets or output enable logic. In this process, the fitter creates foldback or buried feedback nodes to map these inputs into the ATF15XX/ATF1500 device. This process is necessary because each ATF15XX/ATF1500 macrocell has only one product term for each of these inputs.

4.6. Signal/Design Placement

During the Signal/Design Placement step, the fitter places both pre-assigned and unassigned signals into the ATF15XX/ATF1500 device and maps the design logic using these signal placements. Pre-assigned signals are placed on the pins and nodes defined by the user, while unassigned signals are automatically placed by the fitter. Any nodes created by the fitter during the fitting process are also placed during this step.

After all signals are placed, the fitter evaluates the resources required to fit the design logic into the device and maps the design logic into the ATF15XX/ATF1500 architecture. During this mapping process, the fitter determines whether the logic is using invalid macrocell configurations, cannot fit into the available macrocells, uses incorrect register types or register control functions (i.e., Synchronous Preset) or uses too many resources in the device. If the design logic does not map into the ATF15XX/ATF1500 device, this step is repeated in a new design pass. If mapping fails during the last design pass, the fitter terminates the fitting process and reports that the design does not fit. If Signal/Design placement is successful in any design pass, the fuse-mapping process described in Fuse mapping will be performed.

4.7. Fuse mapping

Fuse Mapping is the final step in the fitting process when Signal/Design Placement completes successfully. A final verification of signal and design placement is performed to ensure correct mapping, after which the fitter generates a JEDEC file for the ATF15XX/ATF1500 device.

5. Interpreting the Fitter Report

The ATF15XX/ATF1500 fitter creates a report (log) file (*.fit) that documents the fitting process. This report file is created whether the design fits or not. If the design does not fit, the fitter reports errors in the logic file. If the design fits, a JEDEC (.JED) file is generated in addition to the report file. The Fitter Report contains the following sections:

• Initial Fitting Strategy and Properties
• Global Pin Assignments
• Input/Output Pin Pre-assignments
  • Control Signal Patching
• Floating (Unassigned) Signal Placement
  • Control Signal Assignment
• Programmed Logic
• Pin Layout and Listing
• Logic Resources Usage

Figure 5-1 shows a sample ATF1502 fitter report for the CLOCK design example and provides descriptions of the various sections within the report.
Figure 5-1. Sample Fitter Report File for the CLOCK Design Example

Atmel ATF1502 Fitter Version 1918, running Thu Jun 12 13:35:07 2025
fit1502 C:\WinCUPL\Examples\New\CLOCK\CLOCK.tt2
-CUPL
-device PLCC44
-tech ATF1502AS
-JTAG OFF
***** Initial fitting strategy and property *****
Netlist_in_file = CLOCK.tt2
Netlist_out_file = CLOCK.tt3
Jedec_file = CLOCK.jed
Vector_file = CLOCK.tmv
verilog_file = CLOCK.vt
Log_file = CLOCK.fit
Device_name = PLCC44
Tech_name = ATF1502AS
Package_type = PLCC
Preassignment = try
Security_mode = OFF
Pin-Keeper = OFF
supporter = CUPL
optimize = ON
Xor_synthesis = OFF
Foldback_logic = OFF
Cascade_logic = OFF
Output_fast = ON 

Power down pin 1 = OFF
Power down pin 2 = OFF
power_reset = OFF
JTAG = OFF
TDI pullup = OFF
TMS pullup = OFF
MC_power = OFF
Open_collector = OFF
ITDO = ON
ITD1 = ON
ITD2 = ON
Fast_inlatch = off
Latch_synthesis = off
Push_gate = on
Verilog_sim = off
VHDL_sim = off
Out_Edif = off
Logic Doubling = off
***** End of fitting strategy and property ***** 

Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF ... 

Performing global Output Enable pin assignments ...
Performing global pin assignments ... 

Final global control pins assignment (if applicable)... 

clk assigned to pin 43 

Performing input pin pre-assignments ... 

clk assigned to pin 43 

Attempt to place floating signals ... 

a is placed at pin 4 (MC 1) 

b is placed at pin 5 (MC 2) 

c is placed at pin 6 (MC 3) 

clken is placed at pin 7 (MC 4) 

y1 is placed at pin 14 (MC 10) 

y0 is placed at pin 41 (MC 17) 

y2 is placed at pin 24 (MC 32) 

The fitter keeps pre-assignments on the first design pass.

Final pin assignment for global clock input.

Pin assignment for input pins.

Pin assignment for I/O pins and macrocell assignments for buried nodes.

c b a C C C C k D 0 C 6 5 4 3 2 1 44 43 42 41 40 | clken | 7 39 |NC NC | 8 38 |NC NC | 9 37 |NC GND | 10 36 |NC NC | 11 ATF1502 35 |VCC NC | 12 44-Lead PLCC 34 |NC NC | 13 33 |NC y1 | 14 32 |NC VCC | 15 31 |NC NC | 16 30 |GND NC | 17 29 |NC N N N N G V y N N N N C C C C N C 2 C C C C| Pin layout diagram. VCC = Supply Voltage pin for the device core GND = GND pin which must be connected to ground NC = Unused I/O pins which must be unconnected on the board Universal-Interconnect-Multiplexer assignments Universal Interconnect Multiplexer (UIM) assignments for the various Logic Array Blocks (LABs). FanIn assignment for block A [3] { a, b, c, } Multiplexer assignment for block A b (MC1 P) : MUX 11 Ref (A2p) a (MC2 P) : MUX 12 Ref (A1p) c (MC3 P) : MUX 14 Ref (A3p) FanIn assignment for block B [3] { a, b, clken, } Multiplexer assignment for block B b (MC1 P) : MUX 11 Ref (A2p) clken (MC3 P) : MUX 12 Ref (A4p) a (MC2 P) : MUX 15 Ref (A1p) Creating JEDEC file C:\WinCUPL\Examples\New\CLOCK\CLOCK.jed ... PLCC44 programmed logic: The fitter generates a JEDEC (JED) file if the design fits successfully.

y1.D = !b;
y0.D = b;
y2.D = b;
y1.C = (!a & c);
y0.C = clk;
y2.C = clk;
y2.AR = a;
y2.CE = clken;
PLCC44 Pin/Node Placement:

Pin 4 = a; /* MC 1 */
Pin 5 = b; /* MC 2 */
Pin 6 = c; /* MC 3 */
Pin 7 = clken; /* MC 4 */
Pin 14 = y1; /* MC 10 */
Pin 24 = y2; /* MC 32 */
Pin 41 = y0; /* MC 17 */
Pin 43 = clk;

** Resource Usage **
DCERP Field = Summary of Allocations.

|||||
||||| _Preset [p,-] == p = PT preset, - No Preset.
|||||
||||| _Reset [g,r,-] == g= Global AR, r = PT reset, - No reset.
|||||
||||| _Clock Enable [e,-] == e = Product Term, - always enabled.
|||
||||| _Clock [c,g,-], == c = Product term, g = Global term, - No Clock.
|
| Type [C,D,L,T], == Register type C= combin, D=dff, L=latch, T=tff.
For input only = INPUT.

SO Pin Options Field = Summary of Allocations.
||
||_OpenCol [o,-] == o = Open Collector enabled, - CMOS drive.
|
| Slew [s,f] == Output Slew/Drive rate, s = slow/low, f = fast/hi drive. 

This section shows all logic equations implemented in the target device.

This section shows all final input and I/O pin assignments.

This section lists all resources available in the target device and describes the mapping of the design logic into the ATF15XX device.

MCell Pin# Oe PinDrive DCERP FBDrive DCERP Foldback CascadeOut TotPT SO
MC1 4 -- a INPUT -- -- -- 0 f-
MC2 5 -- b INPUT -- -- -- 0 f-
MC3 6 -- c INPUT -- -- -- 0 f-
MC4 7 -- clken INPUT -- -- -- 0 f-
MC5 8 -- -- -- -- 0 f-
MC6 9 -- -- -- -- 0 f-
MC7 11 -- -- -- -- 0 f-
MC8 12 -- -- -- -- 0 f-
MC9 13 -- -- -- -- 0 f-
MC10 14 on y1 Dc--- -- -- -- 2 f-
MC11 16 -- -- -- -- 0 f-
MC12 17 -- -- -- -- 0 f-
MC13 18 -- -- -- -- 0 f-
MC14 19 -- -- -- -- 0 f-
MC15 20 -- -- -- -- 0 f-
MC16 21 -- -- -- -- 0 f-
MC17 41 on y0 Dg--- -- -- -- 1 f-
MC18 40 -- -- -- -- 0 f-
MC19 39 -- -- -- -- 0 f-
MC20 38 -- -- -- -- 0 f-
MC21 37 -- -- -- -- 0 f-
MC22 36 -- -- -- -- 0 f-
MC23 34 -- -- -- -- 0 f-
MC24 33 -- -- -- -- 0 f-
MC25 32 -- -- -- -- 0 f-
MC26 31 -- -- -- -- 0 f-
MC27 29 -- -- -- -- 0 f-
MC28 28 -- -- -- -- 0 f-
MC29 27 -- -- -- -- 0 f-
MC30 26 -- -- -- -- 0 f-
MC31 25 -- -- -- -- 0 f-
MC32 24 on y2 Dger- --- --- 3 f-
MC0 2 --- --- --- 0 f-
MC0 1 --- --- --- 0 f-
MC0 44 --- --- --- 0 f-
MC0 43 clk INPUT --- --- 0 f-
Logic Array Block Macro Cells I/O Pins Foldbacks TotalPT FanIN Cascades
A: MC1 - MC16 1/16(6%) 5/16(31%) 0/16(0%) 2/80(2%) 3/40(7%) 0
B: MC17 - MC32 2/16(12%) 2/16(12%) 0/16(0%) 4/80(5%) 3/40(7%) 0
Total dedicated input used: 1/4 (25%)
Total I/O pins used 7/32 (21%)
Total Macro cells used 3/32 (9%)
Total Flip-Flop used 3/32 (9%)
Total Foldback logic used 0/32 (0%)
Total Nodes+FB/MCells 3/32 (9%)
Total cascade used 0
Total input pins 5
Total output pins 3
Total Pts 6 

This section summarizes total macrocell and logic resource utilization by the logic design.

Creating pla file C:\WinCUPL\Examples\New\CLOCK\CLOCK.tt3 with 0 inputs 0 outputs, 0 pins 0 nodes and 0 pterms...

End fitter, Design FITS

\$Device PLCC44 fits; JTAG OFF; Secure OFF

FIT1502 completed in 0.00 seconds

6. Fitter Hints

This section provides guidance on using the fitter effectively to achieve efficient design fits, optimize performance, and reduce system noise and power consumption. The following hints are discussed:

• Do Not Assign Pins
• Use Default Properties and Strategies
• Use Cascade Logic for Design Performance
• Using Foldback Logic
• Use XOR Synthesis
• Preventing Nodes from Collapsing
  • Using Slew Rate Control
  • Using the Power-Down Pin

6.1. Hint 1 - Do Not Assign Pins

Although the fitter efficiently utilizes ATF15XX/ATF1500 device resources, poorly chosen pin and node assignments can prevent a design from fitting. The fitter employs multiple pin-assignment and logic-optimization strategies to map a design into the device. Global inputs are typically assigned to control pins, such as clock, reset or output enables, to reduce product-term usage in the macrocells. I/O pins are allocated to logic only after all foldback logic nodes and cascade logic resources in the macrocells have been fully utilized. As a result, the fitter attempts to optimize the maximum amount of logic into the fewest number of macrocells and selects pin assignments to reflect this. This process ensures that the logic is allocated for the best fit into the device. Poorly chosen pin assignments impose additional restrictions on the fitting process, forcing the fitter to tailor the logic around the pin assignments.

6.2. Hint 2 - Use Default Properties and Strategies

The default properties and strategies used by the fitter are selected to achieve the best fit for the design into the ATF15XX/ATF1500 device. Users may customize properties and strategies to meet specific design requirements, as described in FIT1500 and FIT15XX Options and Strategies. However, customizing fitter behavior constrains how the design is mapped and may result in a suboptimal fit. For additional information, refer to Design Passes.

6.3. Hint 3 - Using Cascade Logic for Design Performance

If system performance is a concern, cascade logic can be used to borrow product terms from adjacent macrocells. This approach is particularly beneficial for high-performance state machines. Cascade logic incurs a much lower propagation delay than using foldback nodes or buried macrocell nodes. By default, the fitter uses cascade logic to optimize performance. If the design fails to fit, the fitter then attempts to implement logic using foldback nodes or buried macrocell feedback nodes. If output propagation delay is critical to meeting system timing requirements, the fitter can be customized to use cascade logic for specific outputs. Proper pin assignment is important to ensure that cascade logic is implemented on macrocells capable of borrowing product terms from adjacent macrocells. Each macrocell, except corner macrocells, can borrow up to five product terms from an adjacent macrocell. Multiple macrocells can be cascaded to provide up to 40 product terms for the macrocell at the bottom of the cascade chain.

6.4. Hint 4 - Using Foldback Logic

The fitter uses foldback logic as an optimization strategy to fit a design if cascade logic fails. Preventing the fitter from using foldback logic nodes may prevent a design from fitting. Allowing the fitter to use these nodes can an improve fitting efficiency and increase the likelihood of achieving a successful fit.

6.5. Hint 5 - Use XOR Synthesis

When a design includes XOR logic, enabling the XOR synthesis feature can significantly reduce the number of required product terms. This feature uses the hardware XOR gate available in the ATF15XX/ATF1500A macrocell to implement XOR logic efficiently. By default, XOR synthesis is enabled by the fitter. If this feature is disabled, XOR logic is implemented as a sum-of-products expression, which may consume a large number of product terms and potentially prevent the design from fitting into the ATF15XX/ATF1500 device. To assist the fitter, ensure that XOR synthesis is enabled, review the intermediate equations feeding XOR logic, and define these equations as nodes where appropriate.

6.6. Hint 6 - Prevent Certain Nodes from Collapsing

In some designs, it may be necessary to prevent the fitter from collapsing specific nodes. When collapsed, these nodes can generate excessive product terms, which may prevent the design from fitting into the ATF15XX/ATF1500 device. Designers can assist the fitter by explicitly defining nodes at strategic points in the design and preventing those nodes from collapsing. The following guidelines identify situations where inserting nodes may be beneficial:

• Outputs of complex intermediate combinatorial logic expressions
• Intermediate logic expressions which feed multiple inputs
• Multiple product-term register clock, reset or preset functions
• Multiple product-term output enables

6.7. Hint 7- Using Slew Rate Control

The ATF15XX/ATF1500 supports per-macrocell output slew rate control, allowing designers to tailor output switching characteristics to system timing requirements. Slower slew rates can reduce system noise and are the default setting applied by the fitter. If specific outputs must interface with higher-speed devices or if overall performance optimization is required, individual macrocell outputs can be configured to use a fast slew rate.

6.8. Hint 8 - Using the Power-Down Pin

The power-down pin allows the ATF15XX device to be externally placed into a zero-power mode. By default, the fitter disables the power-down pin, making it available for use as a logic pin. If minimizing power consumption is a key design requirement, enabling the power-down pin allows the device to be powered down when system conditions permit. This capability enables designers to customize power usage to meet system needs. For example, the ATF15XX can be powered down when all inputs are idle and powered back up when input activity is expected.

7. Revision History

Revision A (May 2026)

Initial release of this document.

Microchip Information

Trademarks

The “Microchip” name and logo, the “M” logo, and other names, logos, and brands are registered and unregistered trademarks of Microchip Technology Incorporated or its affiliates and/or subsidiaries in the United States and/or other countries (“Microchip Trademarks”). Information regarding Microchip Trademarks can be found at https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.

ISBN: 979-8-3371-3094-1

Legal Notice

This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/design-help/client-support-services.

THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.

IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION.

Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip products:

• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
• Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip products are strictly prohibited and may violate the Digital Millennium Copyright Act.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable". Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products.

Product Page Links

ATF1500A, ATF1500AL, ATF1502AS, ATF1502ASL, ATF1502ASV, ATF1504AS, ATF1504ASL, ATF1504ASV, ATF1504ASVL, ATF1508AS, ATF1508ASL, ATF1508ASV, ATF1508ASVL