MD1822 - Unspecified Microchip - Free user manual and instructions

USER MANUAL MD1822 Microchip

High-Speed 4-Channel MOSFET Driver with Two Inverting and Two Non-Inverting Outputs

Features

• Mixed Inversion MOSFET Driver
• 6 ns Rise and Fall Time
• 2A Peak Output Source-and-Sink Current
• 1.8V to 5V Input CMOS Compatible
• 5V to 10V Total Supply Voltage
- Smart Logic Threshold
- Low-Jitter Design
• Four Matched Channels
• Drives Two P-Channel and Two N-Channel MOSFETs
• Outputs can swing below Ground
- Low-Inductance, Quad-Flat No-Lead Package
• High-Performance, Thermally Enhanced Packaging

Applications

• Medical Ultrasound Imaging
• Piezoelectric Transducer Drivers
• Non-Destructive Testing
• PIN Diode Driver
• CCD Clock Driver/Buffer
• High-Speed Level Translator

General Description

The MD1822 is a high-speed, four-channel MOSFET driver designed to drive high-voltage P-channel and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high-output current for a capacitive load. The high-speed input stage of the MD1822 can operate from a 1.8V to 5V logic interface with an optimum operating input signal range of 1.8V to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation.

The output stage of the MD1822 has separate power connections, enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and -5V, and the output L and H levels may be varied anywhere over the range of -5V to +5V. The output stage is capable of peak currents of up to ±2A, depending on the supply voltages used and load capacitance present. The PE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. (See Figure 3-1.) Second, when PE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair.

Package Type

16-lead QFN (Top view) 1 See Table 2-1 for pin information.

Functional Block Diagrams

graph TD
    PE["PE"] --> A["AND Gate"]
    INA["INA"] --> A
    INB["INB"] --> B["AND Gate"]
    INC["INC"] --> C["AND Gate"]
    IND["IND"] --> D["AND Gate"]
    A --> OUTA["OUTA"]
    B --> OUTB["OUTB"]
    C --> OUTC["OUTC"]
    D --> OUTD["OUTD"]
    GND["GND"] --> A
    GND --> B
    GND --> C
    GND --> D
    VDD["VDD"] --> A
    VDD --> B
    VDD --> C
    VDD --> D
    VH["VH"] --> A
    VH --> B
    VH --> C
    VH --> D

graph TD
    subgraph MD1822
        PE["PE"] --> LevelShifter1["Level Shifter"]
        INA["INA"] --> LevelShifter2["Level Shifter"]
        INB["INB"] --> LevelShifter3["Level Shifter"]
        INC["INC"] --> LevelShifter4["Level Shifter"]
        IND["IND"] --> LevelShifter5["Level Shifter"]
    end

    subgraph VDD
        VSS["VSS"] --> AND1["AND"]
        VDD["VDD"] --> AND2["AND"]
        VSS --> INV1["VH"]
        VSS --> INV2["VH"]
        VSS --> INV3["VH"]
        VSS --> INV4["VH"]
        VSS --> INV5["VH"]
        VSS --> INV6["VH"]
        VSS --> INV7["VH"]
        VSS --> INV8["VH"]
        VSS --> INV9["VH"]
        VSS --> INV10["VH"]
        VSS --> INV11["VH"]
        VSS --> INV12["VH"]
        VSS --> INV13["VH"]
        VSS --> INV14["VH"]
        VSS --> INV15["VH"]
        VSS --> INV16["VH"]
        VSS --> INV17["VH"]
        VSS --> INV18["VH"]
        VSS --> INV19["VH"]
        VSS --> INV20["VH"]
        VSS --> INV21["VH"]
        VSS --> INV22["VH"]
        VSS --> INV23["VH"]
        VSS --> INV24["VH"]
        VSS --> INV25["VH"]
        VSS --> INV26["VH"]
        VSS --> INV27["VH"]
        VSS --> INV28["VH"]
        VSS --> INV29["VH"]
        VSS --> INV30["VH"]
        VSS --> INV31["VH"]
        VSS --> INV32["VH"]
        VSS --> INV33["VH"]
        VSS --> INV34["VH"]
        VSS --> INV35["VH"]
        VSS --> INV36["VH"]
        VSS --> INV37["VH"]
        VSS --> INV38["VH"]
        VSS --> INV39["VH"]
        VSS --> INV40["VH"]
        VSS --> INV41["VH"]
        VSS --> INV42["VH"]
        VSS --> INV43["VH"]
        VSS --> INV44["VH"]
        VSS --> INV45["VH"]
        VSS --> INV46["VH"]
        VSS --> INV47["VH"]
        VSS --> INV48["VH"]
        VSS --> INV49["VH"]
        VSS --> INV50["VH"]
        VSS --> INV51["VH"]
        VSS --> INV52["VH"]
        VSS --> INV53["VH"]
        VSS --> INV54["VH"]
        VSS --> INV55["VH"]
        VSS --> INV56["VH"]
        VSS --> INV57["VH"]
        VSS --> INV58["VH"]
        VSS --> INV59["VH"]
        VSS --> INV60["VH"]
        VSS --> INV61["VH"]
        VSS --> INV62["VH"]
        VSS --> INV63["VH"]
        VSS --> INV64["VH"]
        VSS --> INV65["VH"]
        VSS --> INV66["VH"]
        VSS --> INV67["VH"]
        VSS --> INV68["VH"]
        VSS --> INV69["VH"]
        VSS --> INV70["VH"]
        VSS --> INV71["VH"]
        VSS --> INV72["VH"]
        VSS --> INV73["VH"]
        VSS --> INV74["VH"]
        VSS --> INV75["VH"]
        VSS --> INV76["VH"]
        VSS --> INV77["VH"]
        VSS --> INV78["VH"]
        VSS --> INV79["VH"]
        VSS --> INV80["VH"]
        VSS --> INV81["VH"]
        VSS --> INV82["VH"]
        VSS --> INV83["VH"]
        VSS --> INV84["VH"]
        VSS --> INV85["VH"]
        VSS --> INV86["VH"]
        VSS --> INV87["VH"]
        VSS --> INV88["VH"]
        VSS --> INV89["VH"]
        VSS --> INV90["VH"]
        VSS --> INV91["VH"]
        VSS --> INV92["VH"]
        VSS --> INV93["VH"]
        VSS --> INV94["VH"]
        VSS --> INV95["VH"]
        VSS --> INV96["VH"]
        VSS --> INV97["VH"]
        VSS --> INV98["VH"]
        VSS --> INV99["VH"]

    subgraph Inputs
    PE
    INA
    INB
    INC
    IND
    end

    subgraph Outputs
    VDD
    VH
    OUTA
    OUTB
    OUTC
    OUTD
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GNG
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GND
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNG
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC
    GNC

Typical Application Circuit

3.3V CMOS Logic Inputs +3.3V +10V 0.1µF +10V 0.47µF MD1822 PE VDD VH INA OUTA 10nF +100V 0.47µF PIN INB OUTB 10nF -100V 0.47µF NIN DMP INC OUTC GND VSS VL IND OUTD 10nF HVout

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†

Logic Supply Voltage, VDD-VSS	-0.5V to +12.5V
Output High Supply Voltage, VH	V-0.5V to VDD+0.5V
Output Low Supply Voltage, VL	VSS-0.5V to VH+0.5V
Low-Side Supply Voltage, VSS	-6V to +0.5V
Logic Input Levels	VSS-0.5V to GND +5.5V
Maximum Junction Temperature, TJ	+125°C
Operating Ambient Temperature, TA	-20°C to +85°C
Storage Temperature, TS	-65°C to +150°C
Power Dissipation (Thermal Resistance, θJA=55 °C/W) (Note 2):
16-lead QFN	2.2W
ESD Rating (Note 1)	ESD Sensitive

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note 1: Device is ESD sensitive. Handling precautions are recommended.
2: Mounted on a 1 oz. four-layer 3" x 4" PCB

DC ELECTRICAL CHARACTERISTICS

Electrical Specifications: V_H = V_DD = 10V, V_L = V_SS = GND = 0V, V_PE = 3.3V, T_A = 25°C
Parameter	Sym.	Min.	Typ.	Max.	Unit	Conditions
Logic Supply Voltage	V_DD-V_SS	4.75	—	11.5	V	4V ≤ V_DD ≤ 11.5V
Low-Side Supply Voltage	V_SS	-5.5	—	0	V
Output High Supply Voltage	V_H	V_SS+2	—	V_DD	V
Output Low Supply Voltage	V_L	V_SS	—	V_DD-4	V
V_DD Quiescent Current	I_DDQ	—	60		μA	No input transitions, PE = 0
V_H Quiescent Current	I_HQ	—	2	—	μA
V_DD Quiescent Current	I_DDQ	—	1	—	mA	No input transitions, PE = 1
V_H Quiescent Current	I_HQ	—	2	—	μA
V_DD Average Current I	_DD	—	4	—	mA	One channel on at 5 MHz, no load
V_H Average Current	I_H	—	10	—	mA
Input Logic Voltage High	V_IH	V_PE-0.3	—	V_PE	V	For logic inputs INA, INB, INC, and IND
Input Logic Voltage Low	V_IL	0	—	0.3	V
Input Logic Current High	I_IH	—	—	1	μA
Input Logic Current Low	I_L	—	—	1	μA
PE Input logic Voltage High	V_IH	1.7	3.3	5.25	V	For logic input PE
PE Input Logic Voltage Low	V_IL	0	—	0.3	V
PE Input Impedance to GND	R_IN\_PE	100	—	—	kΩ
Logic Input Capacitance	C_IN	—	5	10	pF	I_SINK = 50 mA
Output Sink Resistance	R_SINK	—	1.5	—	Ω	I_SOURCE = 50 mA
Output Source Resistance	R_SOURCE	—	2	—	Ω
Peak Output Sink Current	I_SINK	—	2	—	A
Peak Output Source Current	I_SOURCE	—	2	—	A

AC ELECTRICAL CHARACTERISTICS

Electrical Specifications: V_H = V_DD = 10V, V_L = V_SS = GND = 0V, V_PE = 3.3V, T_A = 25°C unless otherwise indicated.
Parameter	Sym.	Min.	Typ.	Max.	Unit	Conditions
Input or PE Rise and Fall Time t	irf	— —	10 ns			Logic input edge speed requirement
Propagation Delay when Output is from Low to High	t_PLH	— 6.5	— ns			C_LOAD = 1000 pF (see Timing Diagram), input signal rise/fall time 2 ns
Propagation Delay when Output is from High to Low	t_PHL	— 6.5	— ns
Output Rise Time t	r	— 7	—	ns
Output Fall Time	t_f	— 7	—	ns
Rise and Fall Time Matching	|t_r - t_f|	— 1	—	ns		For each channel
Propagation Low to High and High to Low Matching	|t_PLH - t_PHL|	— 1	— ns
Propagation Delay Matching	t_dm	—	±2	—	ns	Device to device delay match
PE On Time	t_PE-ON	— —	5	μs	V	_PE = 1.7V - 5.25V, V_DD = 7.5V - 11.5V, -20°C - 85°C
PE Off-Time	t_PE-OFF	— —	4	μs

TEMPERATURE SPECIFICATIONS

Parameter	Sym.	Min.	Typ.	Max.	Units	Conditions
TEMPERATURE RANGE
Maximum Junction Temperature	T_J	—	—	+125	°C
Operating Ambient Temperature	T_A	-20	—	+85	°C
Storage Temperature	T_S	-65	—	+150	°C
PACKAGE THERMAL RESISTANCE
16-lead QFN	_JA	— 55	— °C/W

Timing Diagram

TABLE 1-1: TRUTH FUNCTION TABLE

Logic Input Output
PE INA INB OUTA OUTB
H L H V			H	V_H
H L L V			H	V_L
H H H V			L	V_H
H H L V			L	V_L
L	X X V		H	V_L
PE	INC	IND	OUTC	OUTD
H L H V			H	V_H
H L L V			H	V_L
H H H V			L	V_H
H H L V			L	V_L
L	X X V		H	V_L

2.0 PIN DESCRIPTION

The details on the pins of MD1822 are listed on Table 2-1. See Package Type for the location of pins.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number	Pin Name Description
1 INB Logic input
2 VDD High-side supply voltage
3 VSS		Low-side supply voltage. VSS is also connected to the IC substrate. It is required to connect to the most negative potential of voltage supplies.
4 INC Logic input
5 IND Logic input
6	GND	Logic input ground reference
7	VL	Supply voltage for N-channel output stage
8	OUTC	Output driver
9	OUTD	Output driver
10, 11	VH	Supply voltage for P-channel output stage
12	OUTA Output driver
13	OUTB Output driver
14	VL	Supply voltage for N-channel output stage
15	PE	Power enable logic input. When PE is high, it sets the input logic threshold. When PE is low, all outputs are at default state (See Table 1-1.) and the IC is in Standby mode.
16	INA Logic input
Substrate		The IC substrate is internally connected to the thermal pad. The thermal pad and VSS must be connected externally.

3.0 APPLICATION INFORMATION

For proper operation of the MD1822, low-inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB, INC, IND and PE pins should be connected to a logic source with a swing of GND to PE, where PE is from 1.8V to 5V. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1822 is capable of operating up to 100 MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result in capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the V_SS and V_L pins should have low-inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection V_DD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the powerleads.

FIGURE 3-1: VTH/VPE Graph.

MD1822 Delay vs Temperature

MD1822 t, & t vs Temperature

MD1822 Delay vs V_DD

MD1822 t_r & t_T vs V_DD

FIGURE 3-2: Rise/Fall times, propagation delay vs. VDD voltage and Temperature.

The voltages of V_H and V_L decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1 F may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace

width to reduce inductance. Surface-mount components are highly recommended. Since the output impedance of this driver is very low, in some cases, it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will reduce the output voltage slew rate at the terminals of a capacitive load.

Make sure that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.8V, even small coupled voltages may cause problems. The use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

16-lead QFN

XXXXX XYWW NNN

Example

182 2815 232

Legend: XX...X Product Code or Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week '01')NNN Alphanumeric traceability codeePb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator (e3) can be found on the outer packaging for this package.

Note:

In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.

16-Lead QFN Package Outline (K6)

3.00x3.00mm body, 1.00mm height (max), 0.50mm pitch

16 D 1 Note 1 (Index Area D/2 x E/2) E

Top View

D2 16 Note 1 (Index Area D/2 x E/2) 1 E2 b View B

Bottom View

A A1 θ A3 Seating Plane

Side View

Note 2 L1 Note 3 L

View B

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

Notes:

1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier, an embedded metal marker, or a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.

Symbol		A	A1	A3	b	D	D2	E	E2	e	L	L1	θ
Dimension (mm)	MIN	0.80	0.00	0.20 REF	0.18	2.85*	1.50	2.85*	1.50	0.50 BSC	0.20^†	0.00	0^
	NOM	0.90	0.02		0.25	3.00	1.65	3.00	1.65		0.30^†	-	-
	MAX	1.00	0.05		0.30	3.15*	1.80	3.15*	1.80		0.45	0.15	14^

JEDEC Registration MO-220, Variation VEED-4, Issue K, June 2006
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.

Drawings not to scale.

NOTES:

APPENDIX A: REVISION HISTORY

Revision A (October 2018)

• Converted Supertex Doc# DSFP-MD1822 to Microchip DS20005706A
• Changed the package marking format
• Changed the quantity of the K6 package from 3000/Reel to 3300/Reel
• Made minor text changes throughout the document

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

PART NO. Device XX Package Options - X Environmental - X Media Type

Device: MD1822 = High-Speed 4-Channel MOSFET Driver

with Two Inverting and Two Non-Inverting Outputs

Package: K6 = 16-lead (3x3) VQFN

Environmental: G = Lead (Pb)-free/RoHS-compliant Package

Media Type: (blank) = 3300/Reel for a K6 Package

Example:

a) MD1822K6-G: High-Speed 4-Channel MOSFET Driver with Two Inverting and Two Non-Inverting Outputs, 16-lead (3x3) VQFN, 3300/Reel

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