ATSAMA5D24 - Carte d'évaluation Microchip - Free user manual and instructions

USER MANUAL ATSAMA5D24 Microchip

SAMA5D2C XULT User's Guide

Introduction

Blue printed circuit board with various electronic components and connectors (no readable text or symbols)

This user's guide introduces the Microchip SAMA5D2C Xplained Ultra evaluation kit (SAMA5D2C-XULT kit) and describes the development and debugging capabilities for applications running on the SAMA5D2 Arm® Cortex®-A5-based microprocessor unit (MPU). The SAMA5D2C-XULT kit supports the following part numbers:

• ATSAMA5D21C
• ATSAMA5D22C
• ATSAMA5D23C
• ATSAMA5D24C
• ATSAMA5D26C
• ATSAMA5D27C
• ATSAMA5D28C

Table of Contents

Introduction....1

1. Kit Contents....3
2. Evaluation Kit Specifications....4

2.1. Electrostatic Warning....4
2.2. Power Supply Warning....4

1. Board Power-Up....5
2. Sample Code and Technical Support....6
3. Hardware Overview....7

5.1. Introduction....7
5.2. Equipment List....7
5.3. Board Features....7

1. Board Components....9

6.1. Board Overview....9
6.2. Connectors On Board....10
6.3. Function Blocks....10
6.4. PIO Usage and Interface Connectors....21
6.5. PIO Usage on Expansion Connectors....41

1. Board Schematics....55
2. Errata....70

8.1. NRST....70
8.2. nLBO....70
8.3. R63....70
8.4. R100/R105....70

1. Revision History....71

The Microchip Website....72
Product Change Notification Service....72
Customer Support....72
Microchip Devices Code Protection Feature....72
Legal Notice....73
Trademarks....73
Quality Management System....74
Worldwide Sales and Service....75

1. Kit Contents

The SAMA5D2C Xplained Ultra evaluation kit includes:

• One SAMA5D2C-XULT board
• One Micro-AB type USB cable

2. Evaluation Kit Specifications

Table 2-1. Evaluation Kit Specifications

Characteristic Specifications
Board SAMA5D2C-XULT
Part Number ATSAMA5D2C-XULT
Board Supply Voltage USB and/or Battery powered
Temperature Operating	0°C to +70°C
	Storage -40°C to +85°C
Relative Humidity 0 to 90% (non-condensing)
Main Board Dimensions (L x W x H) 135 × 88 × 20 mm
Board Identification SAMA5D2 XPLAINED ULTRA

2.1 Electrostatic Warning

ESD-Sensitive Electronic Equipment!

The evaluation kit is shipped in a protective anti-static package. The board system must not be subject to high electrostatic potentials.

We recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touching the component pins or any other metallic element on the board.

2.2 Power Supply Warning

Hardware Power Supply Limitation

Powering the board with voltages higher than 5 VCC (e.g., the 12 VCC power adapters from other kits such as Arduino kits) may damage the board.

Hardware Power Budget

Using the USB as the main power source (max. 500 mA) is acceptable only with the use of the on-board peripherals and low-power LCD extension.

When external peripheral or add-on boards need to be powered, we recommend the use of an external power adapter connected to the USB Micro-AB connectors (can provide up to 1.2A on the 3.3V node).

3. Board Power-Up

Three sources are available to power-up the SAMA5D2C-XULT board:

• USB-powered through the USB Micro-AB connector (J23 - default configuration)
• Powered through the USB Micro-AB connector on the Embedded Debugger (EDBG) interface (J14)
• Powered through a rechargeable battery Li-polymer 3.7V connected to J3 or J4

Unlike Arduino Uno boards, the SAMA5D2C-XULT board runs at 3.3V. The maximum voltage that the I/O pins can tolerate is 3.3V. Providing higher voltages (e.g., 5V) to an I/O pin could damage the board.

The sequence for the initial power-up of the board is the following:

1. Unpack the board, taking care to avoid electrostatic discharge.
2. Connect the USB Micro-AB cable to the connector J23 (or J14).
3. Connect the other end of the cable to a free USB port of your PC.

Table 3-1. Electrical Characteristics

Parameter Value
Input voltage 5 VCC
Maximum input voltage (limits) 6 VCC
Maximum DC 3.3V current available 1.2A
I/O voltage 3.3V only

4. Sample Code and Technical Support

After boot up, you can run sample code or your own application on the evaluation kit. Sample code and technical support is available on www.microchip.com. In particular, the software package (example source code and drivers) can be found on the "SAMA5D2 Software Package" page of our website.

Linux® software and demos can be found on www.at91.com/linux4sam/bin/view/Linux4SAM/.

Make sure that the latest software version is downloaded before starting your evaluation. For more information, go to www.at91.com/linux4sam/bin/view/Linux4SAM/.

5. Hardware Overview

5.1 Introduction

The SAMA5D2C-XULT kit is a full-featured evaluation platform for the SAMA5D2 series ARM-based microprocessor units (MPU). It allows users to extensively evaluate, prototype and create application-specific designs.

5.2 Equipment List

The SAMA5D2C-XULT board is based on the integration of an ARM Cortex-A5-based microprocessor with external memory, one Ethernet physical layer transceiver, one SD/MMC interface, one host USB port and one device USB port, one 24-bit RGB LCD and debug interfaces.

Seven headers, compatible with Arduino R3 (Uno, Due) and two Xplained headers are available for various shield connections.

5.3 Board Features

Table 5-1. Board Specifications

Characteristics Specifications
Dimensions (L x W x H)	135 x 88 x 20 mm
Processor SAMA5D27C (289-ball BGA package), 14x14 mm body, 0.8 mm ball pitch
Oscillators MPU, EDBG: 12 MHz crystalRTC: 32.768 kHzPHY: 25 MHz
Main memory 2 x DDR3L SDRAM 2 Gbit - 16 Mbit x 16 x 8 banks (total 4 Gbit = 512 Mbyte)1 x eMMC NAND Flash 4 Gbit
Accessory memories One Serial EEPROM SPIOne QSPI Serial FlashOne EEPROM with MAC Address and Serial Number
SD/MMC One 4-bit SD card connector
USB One USB Host with power switchOne Micro-AB USB device
Display One LCD interface connector, LCD TFT Controller with overlay, alpha-blending, rotation, scaling and color space conversion
Image sensor One ISC interface and connector
Ethernet One Ethernet PHY (RMII 10/100 MHz)
Debug port One JTAG interface connectorOne EDBG interface with CDCOne serial debug console interface (3.3V level)
Expansion connector Arduino R3 compatible set of connectorsXPRO set of connectors
......continued
Characteristics Specifications
Board supply voltage 5V from USBOn-board power regulation by PMICExternal battery-powered capability
Battery On-board PowerCap
User interface Reset, wake-up and user configurable push buttonsOne tri-color user LED (red, green, blue)

6. Board Components

6.1 Board Overview

The fully-featured SAMA5D2C-XULT board integrates multiple peripherals and interface connectors as shown in the figure below.

Figure 6-1. SAMA5D2C-XULT Board Overview

WWW.ATMEL.COM BOOT_DIS V5 V5 D23 D25 D27 D29 D30 D31 D33 D35 D37 D38 D40 D41 D43 D45 D47 D49 D51 D53 GND DIGITAL P/IOBU CANRX1 CANTX1 C42 A12 R160 R161 R162 R163 R164 R165 R166 R167 R168 R169 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R180 R181 R182 R183 R184 R185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195 R196 R197 R198 R199 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 SAMA5D2 X_PLAINED CLASS D R71 STAT_VBAT POWER 3V3 RST 3V3 5V GND NC A0 A1 A2 A3 A4 A5 A6 A7 CANRX0 CANTX0 VDDCORE REB LED RGB LED RSDI 3V3 LP RST 3V3 5V GND RSDI 3V3 LP RST 3V3 5V GND RSDI 3V3 LP RST 3V3 5V GND RSDI 3V3 LP RST 3V3 5V GND RSDI 3V3 LP RST 3V3 5V GND RSDI 3V3 LP RST 3V3 5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.5V GND RSDI 0.

6.1.1 Default Jumper Settings

The board overview shows the default jumper settings. Blue jumpers are configuration items. Red jumpers are current measurement points. The table below describes the functionality of the jumpers.

Table 6-1. SAMA5D2C-XULT Jumper Settings

Jumper	Default	Function
JP1	OPEN	Disable EDBG
JP2	OPEN	Disable Debug
JP3	CLOSE	VDD_3V3_LP current measurement
JP4	CLOSE	VDDCORE current measurement
JP5	CLOSE	VDDISC + VDDIOP0/1/2 current measurement
JP6	CLOSE	VDDBU current measurement
JP7	CLOSE	VDDIODDR_MPU current measurement
JP8	CLOSE	VDD_5V_IN current measurement
......continued
Jumper Default Function
JP9 OPEN Disable	CS of SPI, QSPI and eMMC memories

6.2 Connectors On Board

The table below describes the interface connectors on the SAMA5D2C-XULT board.

Table 6-2. SAMA5D2C-XULT Board Interface Connectors

Connector Interfaces to
J23 USB-A Device. Supports USB device using a type Micro-AB connector
J13 USB Host B. Supports USB host using a type A connector
J1 Serial DBGU (3.3V level)
J11 JTAG, 10-pin IDC connector
J14 EDBG USB connector
J15 USB-C	TM (not populated)
J6 Ethernet
J2 Expansion connector with all LCD controller signals for display module connection (QTouch®, TFT LCD display with touchscreen and backlight)
J19 SDHCI SD/MMC connector
J3, J4 Battery connectors
J12 Tamper connector (not populated)
J7, J8, J9,J16, J17, J20,J21, J22	Expansion connectors with Arduino R3 compatible PIO signals
J24, J25, J26 Xplained Pro Expansion connectors
J10 EDBG JTAG (not populated)
J18 ISC interface
J5 Class-D amplifier output

6.3 Function Blocks

6.3.1 Processor

The SAMA5D2 Series is a high-performance, power-efficient MPU based on the ARM Cortex-A5 processor. Refer to the SAMA5D2 Series data sheet for more information.

6.3.2 Power Supply Topology and Power Distribution

6.3.2.1 Power Supplies

Detailed information on the device power supplies is provided in the tables "SAMA5D2 Power Supplies" and "Power Supply Connections" in the SAMA5D2 Series data sheet.

Figure 6-2. Processor Power Lines Supplies

VDDCORE (1V2) C28 C27 C143 C31 C108 C119 C29 C132 C30 C122 C137 10uF 10uF 100nF 100nF 100nF 100nF 100nF 100nF VDDIODR (1V35) C70 C71 C60 C104 C66 C102 C101 C114 C105 C84 C97 10uF 10uF 100nF 100nF 100nF 100nF 100nF VDDBU (3V3) VDDBU C134 100nF VDDANA (3V3) VDDANA C144 100nF C136 100nF VDDIOP0 VDDIOP1 VDDIOP2 C135 C131 C107 C103 100nF 100nF 100nF 100nF VDDHSC VDDFUSE C118 VDDHSC VDDFUSE C116 100nF [6V2](2V1) C111 100nF VDDAudiopll (3V3) VDDAudiopll C148 4.7uF C140 100nF VDDUTMIC (1V2) VDDUTMIC C147 C133 4.7uF 100nF VDDUTMII VDDSDHC (3V3) VDDUTMII VDDSDHC C125 100nF C110 100nF VDDPLLA VDDOSC VDDISC R131 R269 1R 1% C45 C128 4.7uF 4.7uF VDDPLLA VDDPLLA R269 C128 4.7uF 4.7uF (3V3) VDDOSC VDDISC C138 100nF

VDDCORE (1V2) D7 D9 F3 K13 N5 N9 VDDCORE 1 VDDCORE 2 VDDCORE 3 VDDCORE 4 VDDCORE 5 VDDCORE 6 VDDDDR_1 VDDDDR 2 VDDDDR 3 VDDDDR 4 VDDDDR 5 VDDDDR 6 VDDDDR 7 VDDBU VDDANA (3V3) K3 L5 VDDIOPC (3V3) E6 F7 VDDIOP1 (3V3) N13 R14 VDDIOP2 (3V3) F10 VDDHSIC (1V2) R9 VDDFUSE (2V5) M12 VDDAUDIOP-1 (3V3) T3 VDDUTMIC (1V2) P7 VDDUTMII (3V3) P8 VDDSDHC (3V3 or 1V8) P11 VDDPLLA (1V2) U4 VDDOSC (3V3) T7 VDDISC (3V3) F4 VDDCORE 1 GNDCORE 1 GNDCORE 2 GNDCORE 3 GNDCORE 4 GNDCORE 5 GNDCORE 6 GNDDDR_1 GNDDDR 2 GNDDDR 3 GNDDDR 4 GNDDDR 5 GNDDDR 6 GNDDDR 7 GNDBU GNDBANA 1 GNDBANA 2 GNDIOP0 1 GNDIOP0 2 GNDIOP1 1 GNDIOP1 2 GNDIOP2 GNDOPLL GNDAUDIOPLL GNDAUDIOPLL GNDUTMIC GNDUTMIC GNDUTMII GNDUSMMC GNDUSMMC GNDPLLA GNDOSC GNDISC VDDIOP0 1 VDDIOP0 2 VDDIOP1 1 VDDIOP1 2 VDDIOP2 VDDHSC GNDPLL VDDHSC GNDPLL VDDFUSE GNDPLL VDDAUDIOPLL GNDAUDIOPLL VDDUTMIC GNDUTMIC GNDUTMII GNDUTMII GNDUSMMC GNDUSMMC GNDPLLA GNDOSC GNDISC VDDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNDPLL A GNGUTMII CNA5027-CU

6.3.2.2 Power-Up and Power-Down Considerations

Power-up and power-down considerations are described in section "Power Considerations" of the SAMA5D2 Series data sheet.

The power-up sequence provided in the SAMA5D2 Series data sheet must be respected for reliable operation.

6.3.2.3 ACT8945A Power Management IC

The ACT8945A is a complete, cost-effective and highly-efficient ActivePMU ^™ power management solution, optimized to provide a single-chip power solution and voltage sequencing for SAMA5D2/SAMA5D3/SAMA5D4 and SAM9 series MPUs. It also meets the control requirements of these devices.

The ACT8945A features three step-down DC-DC converters and four low-noise, low-dropout linear regulators along with a complete battery charging solution featuring the advanced ActivePath™ system-power selection function.

Refer to the ACT8945A data sheet at www.active-semi.com/ for more details.

The three DC-DC converters utilize a high efficiency, fixed-frequency (2 MHz), current-mode PWM control architecture that requires a minimum number of external components. Two DC-DC converters are capable of

supplying up to 1100 mA of output current, while the third supports up to 1200 mA. All four low-dropout linear regulators are high performance, low-noise regulators that supply up to 320 mA of output current.

Figure 6-3. Board Power Management

Electrical schematic diagram of a power supply circuit with multiple components and labeled traces for wake-up reset and voltage regulation.

Note: Occasional board start-up problems occurred when powered from a USB source with a weak VBUS level below 4.8V. To avoid the voltage drop and resulting start-up problems, production boards were assembled with a 0 Ω resistor in place of the Schottky diode D9 shown here.

6.3.2.3.1 Supply Group Configuration

The ACT8945A provides:

• All power supplies required by the SAMA5D2 device:
- 1.2V VDDCORE, VDDPLLA, VDDUTMIC, VDDHSIC
-1.35V VDDIODDR
-2.0V VDDBU
- 3.3V VDDIOP, VDDISC
- 1.8V or 3.3V VDDSDHC (= VDDSDMMC)
-2.5V VDDFUSE
- 3.3V VDDOSC, VDDUTMII, VDDANA, VDDAUDIOPLL

• Power supplies to external chips on the main board:

-2.5V VDDLED

-4.8V VSYS_5V

6.3.2.4 Power Boost 5V

To generate a true 5V voltage from the PMIC output (4.8V typical), a FAN48610 low-power boost regulator is integrated into the design. This feeds the 5V USB host and the 5V LCD.

Figure 6-4. Power Boost 5V

VSYS_5V VDDB_5V U22 VIN VOUT1 A1 A2 L27 0.47uH PGND1 C1 C2 SW1 PGND2 AGND SW2 C3 B1 B2 B3 EN FAN48610 R34510K C180 10uF C181 22uF

6.3.2.5 Input Power Options

There are several power options for the SAMA5D2C-XULT board.

USB-powered operation is the default configuration, where the USB device port is connected to a PC or a 5V DC supply. The USB supply is sufficient to power the board in most applications. It is important to note that when the USB supply is used, the USB-B Host port has limited power. If USB Host port is required for the application, it is recommended that an external DC supply be used.

The figure below provides the schematics of power options.

Figure 6-5. Input Powering Scheme

EDBG_USB_VBUS_5V[14] R187 10K R186 10K USBA_VBUS_5V[10] 8 IN1 STAT VSNS OUT EN ILIM IN2 GND TPS2113 1 7 4 5 JP8 Header 1X2 JPR8 Jumper VDD_5V_IN 1 2 R185 390R 1% C59 C60 C58 10uF 10uF 100nF

Note: USB-powered operation eliminates additional wires and batteries. It is the preferred mode of operation for any project that requires only a 5V source at up to 500 mA.

6.3.2.6 Battery Supply Source

The ACT8945A features an advanced battery charger that incorporates the ActivePath architecture for system power selection. This combination of circuits provides a complete, advanced battery-management system that automatically selects the best available input supply, manages charge current to ensure system power availability, and provides a complete, high accuracy ( ±0.5% ), thermally regulated, full-featured single-cell linear Li+ charger.

The ActivePath circuitry monitors the state of the input supply, the battery, and the system, and automatically reconfigures itself to optimize the power system. If a valid input supply is present, ActivePath powers the system from the input while charging the battery in parallel. This allows the battery to charge as quickly as possible, while supplying the system. If a valid input supply is not present, ActivePath powers the system from the battery. Finally, if the input is present and the system current requirement exceeds the capability of the input supply, ActivePath allows system power to be drawn from both the battery and the input supply.

Figure 6-6. Battery Powering Scheme

LM2 ACT8846AQJ405-T 33 CHGIN 21 ACIN 20 LSI 23 ISET REFBP 22 CHOLEV nRS10 nIRQ nPBSTAT 27 R27 2 R16 100k 1% 11 R17 100k 1% 12 R29 100k 1% 13 R30 0.5V R31 0.5V R41 DN4(0K) VSEL 25 VSEL 26 VPSYS_5V VPSYS_10uF C163 C164 C178 C167 VSYS_5V C166 C167 VSYS_0V D1 FDP VBAT C18 J5 1x3Pin (See note 3) OUT1 SW1 39 OUT1 SW2 36 OUT2 SW3 15 OUT3 (a See note 3) DNP(Header 1X2 2.00MM)

Notes:

1. Refer to errata NRST.
2. If the battery does not have a pack embedded thermistor (i.e., battery temperature monitoring), the TH pin should be connected to ground => short J3 pins 2 and 3.
3. If no battery is connected on connector J3 or J4, it is recommended that the charging function be disabled in the ACT8945 chip. To do so, write the SUSCHG bit to '1' in APCH register (REG 0x71, SUSCHG = 1).

6.3.2.6.1 Charger Input Interrupts

To facilitate input supply detection and eliminate the size and cost of external detection circuitry, the charger has the ability to generate interrupts based upon the status of the input supply. This function is capable of generating an interrupt when the input is connected, disconnected, or both, when the charger state machine transitions.

6.3.2.6.2 Charge Status Indicator

The charger provides a charge-status indicator output, nSTAT. nSTAT is an open-drain output which sinks current when the charger is in an active-charging state, and is high-Z otherwise. nSTAT features an internal 8 mA current limit, and is capable of directly driving an LED (D1).

6.3.2.6.3 Precision Voltage Detector

The low battery input (LBI) connects to one input of a precision voltage comparator, which can be used to monitor a system voltage such as the battery voltage. An external resistive-divider network can be used to set voltage monitoring thresholds. The output of the comparator is present at the open-drain low battery indicator output (nLBO) and connected to the red LED D1.

Table 6-3. PIOs Used to Control the Battery Charger

PIO Function
PA12 CHGLEV: Charge Current Selection Input
PB13 nIRQ: Open-Drain Interrupt Output. nIRQ is asserted any time an unmasked fault condition exists or a charger interrupt occurs.
PC8	nLBO: Low Battery Indicator Output. nLBO is asserted low whenever the voltage at LBI is lower than1.2V; it is high-Z otherwise.

Figure 6-7. Battery Connector J3 and Optional J4

WWW.ATMEL.COM VXPRO EXT1 F1_TXO F1_RXO XPRO POWER BOOT_DIS RESET WAKE UP EDBG-USB A5-JTAGED66-JTG CLASS D SAMA5D2 X PLAINED ULTRA Atmel® SMART™ VBAT DEBUG_DIS PB_USER BP1 LED3G_DIS R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100

Table 6-4. Battery J3 Signal Descriptions

Pin Mnemonic Signal Description
1	VBAT	Battery I/O (exploitation and charging). Connect this pin directly to the battery anode (+ terminal)
2	GND	Common ground
3	TH	Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 102 μA (typical) current internally.

6.3.2.7 Backup Power Supply

The SAMA5D2C-XULT board requires a power source to permanently power the backup part of the SAMA5D2 device (refer to the SAMA5D2 Series data sheet). A super capacitor sustains such permanent power to VDDBU when all system power sources are off.

Figure 6-8. VDDBU Powering Scheme Option

VDD_3V3 D5 RB160M-60TR R280 100R 1% 1 2 D6 BAT54C 3 JPR6 Jumper JP6 Header 1X2 VDDBU C42 0.2F/3.3V C44 DNP(1uF) C46 100nF R139 DNP(2.2K) (Super)-Capacitor energy storage Populate R if no Super Cap

6.3.2.8 Power Supply Control

In the ACT8945A, three DC-DC converters (1.8V, 1.2V, 3.3V) and two LDO outputs are available.

All ACT8945A outputs can be controlled by the TWI interface through software.

The three DC-DC outputs can be enabled or disabled by the SAMA5D2 SHDN output:

• SHDN = 0: The DC-DC output is disabled.
• SHDN = 1: The DC-DC output is enabled.

Two push buttons are also available:

• Wake-up push button: When pressed, the ACT8945A power outputs are restarted if the ACT8945A is in Shutdown mode.
• Reset push button: When pressed, the ACT8945A transfers the reset signal to the MPU.

6.3.3 Reset Circuitry

The reset sources for the SAMA5D2C-XULT board are:

• Power-on Reset from the Power Management Unit (PMIC)
- Push button reset BP3
- External reset from Arduino connectors
• JTAG or EDBG reset from an in-circuit emulator

Figure 6-9. Reset/Wake-up and Shutdown Control

VSY5_5V R8 68K R15 10CK VSYS_5V R23 100R 1% 19 nPGSTAT nLBO SDA SCL 27 26 SW2 34 R30.0R 25 VSEL 15 OUT3 17 Q2 BSS138 Q1 BSS138 R13 48.9K 1% 10 PWRHLD Q3 BSS138 R14 48.9K 1% 9 nPBIN FPREN GNDIA GNDIP/2 GNDIPJ EXPAD 19 37 14 47 R19 OR Tsc Switch R12 100K R9 1K C10 100nF SHONDT WAKE UP RESET

6.3.4 Clock Circuitry

The SAMA5D2C-XULT board includes four clock sources:

• Two clocks are alternatives for the SAMA5D2 processor (12 MHz, 32 kHz)
  • One crystal oscillator used for the Ethernet RMII chip (25 MHz)
  • One crystal oscillator used for the EDBG (12 MHz)

Figure 6-10. Clock Circuitry

R138 DNR(1M) XIN XOUT Y4 1 2 3 4 C47 27pF 12MHz CL=15pF C45 27pF

R103 DNP(1M) XOUT32 32.768KHz CL=12.5pF XIN32 C41 22pF Y3 4 1 3 2 C40 22pF

C34 22pF 2 1 Y2 3 4 C35 22pF 25MHz CL=20pF ETH_XI R64 DNP(1M) ETH_XO

6.3.5 Memory

6.3.5.1 Memory Organization

The SAMA5D2 features a DDR/SDR memory interface and an External Bus Interface (EBI) to allow interfacing to a wide range of external memories and to almost any kind of parallel peripheral.

This section describes the memory devices that equip the SAMA5D2C-XULT board.

6.3.5.2 DDR3/SDRAM

Two DDR3L/SDRAM (MT41H128M16JT-125-K - 2 Gbit = 16 Mbit x 16 x 8 banks) are used as main system memory and total 4 Gbit of SDRAM on the board. The memory bus is 32 bits wide and operates with a frequency of up to 166 MHz.

Figure 6-11. DDR3L

One specific analog input, DDR_CAL, is used to calibrate all DDR I/Os.

Figure 6-12. DDR Signals and CAL Analog Input

The Secure Digital Multimedia Card (SDMMC) Controller supports the Embedded MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification

One MTFC4GACAJCN-4M 4 Gb eMMC is connected to the processor through the SDMMC0 port.

Table 6-5. SDMMC Reference Documents

Name Link
SD Host Controller Simplified Specification V3.00 www.sdcard.org
SDIO Simplified Specification V3.00 www.sdcard.org
Physical Layer Simplified Specification V3.01 www.sdcard.org
Embedded MultiMedia Card (e.MMC) Electrical Standard 4.51 www.jedec.org

Figure 6-13. eMMC

47K pull down on SDHC0_CMD_PA1 close to MPU. 39R on SDHC0_CK_PA0 close to MPU. Impedance match of CLK/CMD/DAT[7:0] 50R IN=0: S1 Closed IN=1: S2 Closed SCHC0_VDDSEL_PA11 R225 10K R21LOR GND S2 D IN U13 ADG849 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 VDD_3V3 C65 1uF C79 100nF C65 1uF C79 100nF

6.3.5.5 CS Disable

The SAMA5D2 device boots according to the following sequence:

1. SD CARD connected on SDHC1
2. eMMC connected on SDHC0
3. Serial Flash connected on SPI0_IOSET1 (Chip Select 0: NPCS0)
4. Optional QSPI Flash connected on QSPI0_IOSET3 (Chip Select 0: CS0)

In this sequence, the first device found with bootable contents is selected as the boot source. The others are disregarded. (see Note below)

An on-board jumper (JP9) controls the selection (CS#) of the on-board bootable memory components (eMMC and Serial Flash) using a non-inverting 3-state buffer.

Figure 6-14. CS Disable

QSPI0_CS_PA23(7) JPR9 Header 1X2 JPR9 Jumper BOOT_DIS SP0_NPC50_PA17(7) R226 10K U15 VCC 5 4 C63 100nF R218 10K QSPI0_CS QSPI Flash CS VDD_3V3 R230 10K SDHC0_CD_PA13 [T] eMMC Flash CS Q6 BSS138 R227_100R_1% U14 VCC 5 4 C62 100nF R217 10K SP10_CS0_PA17 SPI Flash CS NL17SZ126DFT2G NCL17SZ126DFT2G

The rule of operation is:

• JP9 = OFF (default) → enable normal boot from serial Flash memories mounted on board
• JP9 = ON → booting from optional serial Flash memories is disabled

Refer to the SAMA5D2 Series data sheet for more information on standard boot strategies and sequencing.

Note: The errata in the SAMA5D2 data sheet state that booting from SD/MMC devices is nondeterministic. In order to have a known behavior regardless of SD/MMC data contents, we recommend SDMMC0/SDMMC1 boot bits be disabled in the Boot Configuration Word fuse.

6.3.6 Additional Memories

6.3.6.1 Serial Flash

The SAMA5D2 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial serial Flash.

The four main signals used in the SPI are Clock, Data In, Data Out, and Chip Select. The SPI is a serial interface similar to the bus interface but with three main differences:

• It operates at a higher speed.
• Transmit and receive data lines are separate.
• Device access is chip select-based instead of address-based.

Figure 6-15. Serial Flash

SPI0_MOSI_PA15 SPI0_MISO_PA16 SPI0_SPCK_PA14 SPI0_CS0_PA17 5 2 6 1 SI SQ SCK CS U9 VCC WP HOLD GND AT25DF321A 8 3 7 4 VDD_3V3 C53 100nF

6.3.6.2 QSPI Serial Flash

The SAMA5D2 provides two Quad Serial Peripheral Interfaces (QSPI). One port is used to interface with the optional on-board QSPI serial Flash.

The Quad SPI Interface (QSPI) is a synchronous serial data link that provides communication with external devices in Master mode.

The QSPI can be used in SPI mode to interface to serial peripherals (such as ADCs, DACs, LCD controllers, CAN controllers and sensors), or in Serial Memory mode to interface to serial Flash memories.

The QSPI allows the system to execute code directly from a serial Flash memory (XIP) without code shadowing to RAM. The serial Flash memory mapping is seen in the system as other memories (ROM, SRAM, DRAM, embedded Flash memory, etc.).

With the support of the Quad SPI protocol, the QSPI allows the system to use high-performance serial Flash memories which are small and inexpensive, in place of larger and more expensive parallel Flash memories.

Figure 6-16. QSPI Serial Flash

VDD_3V3 [7] QSPI0_IC0_PA24 5 S/SIO0 VCC 8 [7] QSPI0_IC1_PA25 2 SO/SIO1 GND 4 [7] QSPI0_IC2_PA26 3 SIO2 CSW 1 QSPI0_CS [7] QSPI0_IC3_PA27 7 SIO3 5CLK 6 QSPI0_SCK_PA22 [7] U10 MIX25L2587JGME-09G

6.3.6.3 Serial EEPROM with Unique MAC Address

The SAMA5D2C-XULT board embeds one Microchip AT24MAC402/602 EEPROM using a TWI1 interface.

The AT24MAC402/602 provides 2048 bits of Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM) organized as 256 words of eight bits each and is accessed via an I²C-compatible (2-wire) serial interface. In addition, the AT24MAC402/602 incorporates an easy and inexpensive method to obtain a globally unique MAC or EUI address (EUI-48 or EUI-64).

The EUI-48/64 addresses can be assigned as the actual physical address of a system hardware device or node, or it can be assigned to a software instance. These addresses are factory-programmed by Microchip and guaranteed unique. They are permanently write-protected in an extended memory block located outside of the standard 2-Kbit memory array.

In addition, the AT24MAC402/602 provides the value-added feature of a factory-programmed, also guaranteed unique 128-bit serial number located in the extended memory block (same area as the EUI address values).

The EEPROM device is also used as a “software label” to store board information such as chip type, manufacturer name and production date, using the last two 16-byte blocks in memory. To preserve the ease of board identification by software, the information contained in these blocks should not be modified.

Figure 6-17. EEPROM

VDD_3V3 VDD_3V3 R320 R31910K EEMROM_WP DNP(10K) R316 OR U18 A0 VCC 8 C161 100nF 2 A1 WP 7 EEPROM_WP 3 A2 SCL 6 EEPROM_TWCK1_PD5 [8] 4 GND SDA 5 EEPROM_TWD1_PD4 [8] AT24MAC402-MAHM-T

6.4 PIO Usage and Interface Connectors

6.4.1 Secure Digital Multimedia Card Interface

6.4.1.1 Secure Digital Multimedia Card Controller (SDMMC)

The SAMA5D2C-XULT board has two SDMMC interfaces that support the MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification.

• SDMMC0 interface is connected to the eMMC.
• SDMMC1 Interface based on a 7-pin interface (clock, command, 4-bit data, power lines).

6.4.1.2 SDMMC1 Card Connector

A standard MMC/SD card connector, connected to SDMMC1, is mounted on the top side of the board. It includes a card detection switch.

Figure 6-18. SDMMC1

VDD_3V3 R245 R241 R209 R1928K R1896K VDD_3V3 R214 8R C64 10uF C75 100nF SDHC1_CD_PA30[7] (MCI CD) MCH DA1 (MCI DA0) (MCI CK) MCH1_CMD_PA28[4] (MCI CDA) (MCI DA3) (MCI DA2) MCH1_DAT1_PA19[4] (MCI DA10_PA18[4] MCH1_CK_PA22[7] (MCI CK) MCH1_DAT3_PA21[4] (MCI DA2) MCH1_DAT2_PA20[4] 8 7 6 5 4 3 2 1 9 J19 16 15 14 (SDHC1_WP) 13 12 11 10 VDD_3V3

Note: Refer to details on SDcard boot in CS Disable.

Standard SD Socket J19

WWW.ATMEL.COM BOOT_DIS XPRO EXT1 XPRO EXT2 A5-USB-A SCL0 SDA0 AREF GND VDDIODDR F1_TXD F4_RXD F0_TXD F0_RXD F3_TXD F3_RXD SDA1 SQL1 D22 D23 D24 D25 D26 D27 D29 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 GND DIGITAL P10BU CANRX1 CANTX1 PI0BU QOL OSC R120 127 R120 127 R120 127 R120 127 R120 127 R120 127 R120 127 R120 127 R120 127 R120 127 R120 127 R120 127

Table 6-6. Standard SD Socket J19 Signal Descriptions

Pin	Mnemonic	PIO	Signal Description
1	DAT3	PA21	Data Bit 3
2	CDA	PA28	Command Line
3	GND	-	Common ground
4	VCC	-	Supply Voltage 3.3V
......continued
Pin Mnemonic PIO Signal Description
5 CLK PA22 Clock / Command Line
6 CD PA30 Card Detect
7 DAT0 PA18 Data Bit 0
8 DAT1 PA19 Data Bit 1
9 DAT2 PA20 Data Bit 2
10 GND – Common ground

6.4.2 Communication Interfaces

The SAMA5D2C-XULT board is equipped with GMAC and USB Host/Device communication interfaces.

6.4.2.1 Ethernet 10/100 (GMAC) Port

The SAMA5D2C-XULT board contains a MICREL PHY device (KSZ8081) operating at 10/100 Mb/s. The board supports RMII interface modes. The Ethernet interface consists of two pairs of low-voltage differential pair signals designated from GRX± and GTX± plus control signals for link activity indicators. These signals can be used to connect to a 10/100 Base-T RJ45 connector integrated on the SAMA5D2C-XULT board.

Additionally, for monitoring and control purposes, LED functionality is carried on the RJ45 connectors to indicate activity, link, and speed status information.

For more information about the Ethernet controller device, refer to the MICREL KSZ8081RN controller data sheet.

Figure 6-19. Ethernet (GMAC)

Ethernet 10Base-T/100Base-TX U3 VDDA 250 C21 C24 C25 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 U3

Figure 6-20. ETH RJ45 Connector J6

WWW.ATMEL.COM BOOT_DIS XPRO EXT1 F1 TXD F1 RXD XPRO EXT2 V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D38 D40 D41 D43 D45 D47 D49 D51 D53 GND SMMC Atmel® SMART™ SAMA5D2 X PLAINED SAMSUNG VDD 3V3 VDD 3V2 LP VDD CORE RGB LED LED R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 RB_VBAT_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_1_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_2_3

Table 6-7. ETH RJ45 Connector Signal Descriptions

Pin	Mnemonic	Signal Description
1	TX+	Transmit
2	TX-	Transmit
3	RX+	Receive
4	Decoupling capacitor	-
5	Decoupling capacitor	-
6	RX-	Receive
7	NC	-
8	EARTH / GND	Common ground
9	ACT LED	LED activity
10	ACT LED	LED activity
11	LINK LED	LED link connection
12	LINK LED	LED link connection
13	EARTH / GND	Common ground
14	EARTH / GND	Common ground
15	NC	-
16	NC	-

6.4.2.2 USB Host/Device A, B

The SAMA5D2C-XULT board features three USB communication ports:

• USB-B Host High- and Full-speed Interface

- One USB host type A connector

• USB-A Device Interface

- One USB device standard Micro-AB connector. This port has a VBUS detection function made through the resistor ladder R183 and R184.

• UBC-C High-speed Host Port

- One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface. This port is connected to a single 2-pin jumper.

Figure 6-21. USB-B Host & USB-A Device Interface

USB-AUSB-B R183,100K C57 20pF R184 200K USBA_VBUS_5V [4] USBA_VBUS_5V_PA31 [7] USBA_DM [8] USBA_DP [9] J23 MicroUSB AB Connector EARTH USB A

5 SH1 VBUS DM DP GND A SH2 1 2 3 4 USB6_VBUS_5V USB8_DM[9] USB8_DP[9] J13 Single USB Type A 6 EARTH_USB_B

The USB-B Host port is equipped with 500 mA high-side power switch for self-powered and bus-powered applications.

Figure 6-22. USB Power Switch

USBB_VBUS_5V C156 100nF C157 10uF L21 180ohm at 100MHz 2 8 U16 OUT_2 EN OUT_1 FLG IN_2 GND IN_1 NC VDDB_5V C155 100nF 7 5 SP2525A-1EN-L EN: Active High USBB_EN5V_PB10 [7] USBB_OVCUR_PA29 [7] R301 10K

6.4.3 USB-A Micro-AB Connector J23

Figure 6-23. USB-A Connector J23

WWW.ATMEL.COM XPRO EXT1 F1_TXD F1_RXD XPRO EXT2 J46 BOOT_DIS VDDIODDR SDMMOCLn VDDI R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100 VDDI-3V3 VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP VDDI-3V3 LP CLASS D: EDBG_DIS R TPI T2 R S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S CTS TXD RXD HCC RTS GND SAMA5D2 X_PLAINED

6.4.4 USB-B Type B Connector J13

The USB-B host port A (J13) features a VBUS insert detection function through the ladder-type resistors R26 and R27.

Figure 6-24. USB B Connector J13

XPRO EXT1 F1_TXD F1_RXD XPRO EXT2 WWW.ATMEL.COM BOOT_DIS V5 V5 D23 D25 D27 D29 D31 D33 D35 D36 D37 D38 D40 D42 D43 D45 D47 D49 D51 D52 GND DIGITAL Atmel® SMART™ SAMA5D2 X PLAINED ULTRA CLASS D VDD_3VS STAT VBAT POWER VDD_3VS LP RST 3VS GND NC A1 A2 A3 A4 A5 A6 A7 VDDCORE - VBAT - RGB LED - LCD & DEBUG DIS PB_USER DEBUG LEDG_DIS AD-USB-A A5-USB-A RESET WAKE UP EDBG-USB VDDIODDR SDMMC0n1 RIG RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO

Table 6-8. USB-A & USB-B Connector Signal Descriptions

Pin	Mnemonic	Signal Description
1	VBUS	5V power
2	DM	Data minus
3	DP	Data plus
4	ID	On-the-go identification
5	GND	Common ground

6.4.5 LCD TFT Interface

6.4.5.1 LCD

The SAMA5D2C-XULT board provides 18 bits of data and control signals to the LCD interface. Other signals are used to control the LCD and are available on connector J2: TWI, SPI, two GPIOs for interrupt, 1-Wire and power supply lines.

6.4.5.2 LCD Expansion Header

J2 is a 1.27mm pitch 50-pin header. It gives access to the LCD signals.

Figure 6-25. LCD Expansion Header Interface Schematic

VDDB_GV VDD_3V3 R36 R347 NRSTI401234 R40 OR OR LCD_PWN_PC26[8] LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29[8] LCD_PWN_PC26[8] LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29[8] LCD_PWN_PC26[8] LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29(8) LCD_PWN_PC26[8] LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29[8] LCD_PWN_PC26[8] LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29 LCD_PWN_PC26[8] LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29 LCD_PWN_PC26[8] LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29 LCD_LCDPWN LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29 LCD_LCDPWN LCD_IRQ_P86[7] LCD_IRQ1_PB7[7] LCD_TWCK1_PD6[7] LCD_TWD1_PD4[8] LCD_DISP_PC29 LCD_LCDPWN LCD_IRQ_P86[7] DNP(POR) 22R 22R 22R R39 R38 R37 R36 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 NPN(POR) 50 Ph FPC Connector 50 Ph FPC Connector

6.4.5.3 LCD Power

In order to operate correctly out of the processor with various LCD modules, two voltage lines are available: 3.3V and 5 VCC (default), both selected by 0R resistors R335 and R347.

Figure 6-26. LCD Power

VDDB_5V VDD_3V3 R336 DNP(0R) R347 0R NRST-19.12-14-7 R40 0R LCD J2 50 49 48 47 46 45

6.4.5.4 LCD Connector J2

Figure 6-27. LCD Connector J2

WWW.ATMEL.COM BOOT_DIS V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 GND J5 SDMMC1 Atmel® SMART™ SAMA5D2 X PLAINED ULTRA DEBUG_DIS DEBUG DBVCC1806-6VD PBJUSER PB_USER LCD LCC RUB VDD_3V3 VDD_3V3_LP VDD_3V3_P VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP VDD_3V3_LP

Table 6-9. LCD Connector J2 Signal Descriptions

Pin	Signal	PIO	Signal	RGB Interface Function	Alternate
1	ID_SYS	PB0/ ID00	ID	Extension module identification	EDBG_ID_01
2	-	GND	GND	GND	-
3	-	-	-	-	-
4	-	-	-	-	-
5	LCDDAT2	PC10	D2	Data line	-
6	LCDDAT3	PC11	D3	Data line	-
7	-	GND	GND	GND	-
8	LCDDAT4	PC12	D4	Data line	-
9	LCDDAT5	PC13	D5	Data line	-
10	LCDDAT6	PC14	D6	Data line	-
11	LCDDAT7	PC15	D7	Data line	-
12	-	GND	GND	GND	-
13	-	-	-	-	-
14	-	-	-	-	-
15	LCDDAT10	PC16	D10	Data line	-
Pin Signal PIO Signal RGB Interface Function Alternate
16 LCDDAT11 PC17 D11 Data line -
17 - GND GND GND -
18 LCDDAT12 PC18 D12			Data line -
19 LCDDAT13 PC19 D13			Data line -
20 LCDDAT14 PC20 D14			Data line -
21 LCDDAT15 PC21 D15			Data line -
22 - GND GND GND -
23 - - -			-	-
24 - - -			-	-
25 LCDDAT18 PC22 D18			Data line -
26 LCDDAT19 PC23 D19			Data line -
27 - GND GND GND -
28 LCDDAT20 PC24 D20			Data line -
29 LCDDAT21 PC25 D21			Data line -
30 LCDDAT22 PE26	D22		Data line -
31 LCDDAT23 PE27	D23		Data line -
32 - GND GND GND -
33	LCDPCK	PD0	PCLK	Pixel clock	-
34	LCDVSYNC	PC30	VSYNC/CS	Vertical synchronization	-
35	LCDHSYNC	PC31	HSYNC/WE	Horizontal synchronization	-
36	LCDDEN	PD1	DATA_ENABLE/RE	Data enable	-
37	SPI1_SPCK	PC1	SPI_SCK	-	AD3/YM PD22
38	SPI1_MOSI	PC2	SPI_MOSI	-	AD2/YP PD21
39	SPI1_MISO	PC3	SPI_MISO	-	AD1/XM PD20
40	SPI1_NPCS0	PC4	SPI_CS	-	AD0/XP PD19
41	LCDDISP	PA29	ENABLE	Display enable signal	-
42	TWD1	PD4	TWI_SDA	I2C data line (maXTouch®)	-
43	TWCK1	PD5	TWI_SCL	I2C clock line (maXTouch)	-
44	GPIO	PB7	IRQ1	maXTouch interrupt line	-
45	GPIO	PB8	IRQ2	Interrupt line for other I2C devices	-
46 LCDPWM PC28 PWM Backlight control -
47	RESET	-	RESET	Reset for both display and maXTouch	-
48	Main_5V/3V3	VCC	VCC	3.3V or 5V supply (0R)	-
49	Main_5V/3V3	VCC	VCC	3.3V or 5V supply (0R)	-
50 GND GND GND GND -

6.4.6 ISC

The Image Sensor Controller (ISC) system manages incoming data from a parallel or serial csi-2 based CMOS/CCD sensor. It supports a single active interface. It supports the ITU-R BT 656/1120 422 protocol with a data width of 8 bits or 10 bits and raw Bayer format. The internal image processor includes adjustable white balance, color filter array interpolation, color correction, gamma correction, 12-bit to 10-bit compression, programmable color space conversion, horizontal and vertical chrominance subsampling module.

Figure 6-28. ISC J18

WWW.ATMEL.COM BOOT_DIS V5 V5 D23 D25 D27 D29 D31 D33 D35 D07 D38 D40 D42 D44 D46 D48 D50 D52 GND DIGITAL Atmel® SMART™ SAMA5D2 X PLAINED SAMS-DIS® LEDG_DIS® EVB_GND RESET WAKE UP A5-JTAGEDBO-ITAG R00 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100

Table 6-10. ISC J18 Signal Descriptions

Pin	Mnemonic	PIO	Signal Description
1	3V3	-	ISC Power Supply
2	GND	-	Ground
3	3V3	-	ISC Power Supply
4	GND	-	Ground
5	ISC_RST	PB11	Reset ISC module
6	ISC_PWD	PB12	Power Down module
7	TWCK1	PD5	TWI Clock
8	TWD1	PD4	TWI Data
9	GND	-	Ground
10	ISC_MCK	PC7	ISC Master Clock
11	GND	-	Ground
12	ISC_VSYNC	PC5	ISC Vertical Synchronization
Pin Mnemonic PIO Signal Description
13 GND – Ground
14 ISC_HSYNC PC6 ISC Horizontal Synchronization
15 GND – Ground
16 ISC_PCK PC4 Clock
17 GND – Ground
18 ISC_D4 PB30 Image data D0
19 ISC_D5 PB31 Data D1
20 ISC_D6 PC0 Data D2
21 ISC_D7 PC1 Data D3
22 ISC_D8 PC2 Data D4
23 ISC_D9 PC3 Data D5
24 ISC_D10 PB24 Data D6
25 ISC_D11 PB25 Data D7
26 ISC_D0 PB26 RFU
27 ISC_D1 PB27 RFU
28 ISC_D2 PB28 RFU
29 ISC_D3 PB29 RFU
30 GND – Ground

The connector ISC J18 has been laid out to be compatible with previous evaluation kits and existing extensions in 8-bit modes. Hence, the 8-bit image data [7:0] are aligned with ISC_D[11:4] in the table above. Refer to the SAMA5D2 Series data sheet for an in-depth description of the ISC bussing scheme. A summary is also provided below.

The table below shows how ISC_DATA[11:0] is routed to image data D[11:0] in relation to the bit mode.

Table 6-11. ISC Interface - ISC_DATA to Image Data

Interface 12-bit 11-bit	10-bit 9-bit	8-bit
isc_data[11](MSB)	D[11]	D[10]	D[9]	D[8]	D[7]
isc_data[10]	D[10]	D[9]	D[8]	D[7]	D[6]
isc_data[9]	D[9]	D[8]	D[7]	D[6]	D[5]
isc_data[8]	D[8]	D[7]	D[6]	D[5]	D[4]
isc_data[7]	D[7]	D[6]	D[5]	D[4]	D[3]
isc_data[6]	D[6]	D[5]	D[4]	D[3]	D[2]
isc_data[5]	D[5]	D[4]	D[3]	D[2]	D[1]
isc_data[4]	D[4]	D[3]	D[2]	D[1]	D[0]
isc_data[3]	D[3]	D[2]	D[1]	D[0]	Not Used

......continued
Interface 12-bit 11-bit 10-bit 9-bit 8-bit
isc_data[2] D[2] D[1] D[0] Not Used Not Used
isc_data[1] D[1] D[0] Not Used Not Used Not Used
isc_data[0] D[0] Not Used Not Used Not Used Not Used

Figure 6-29. ISC J18 Header

ISC VDD_3V3 R130 0R J18 1 3 5 7 9 11 13 15 17 2 4 6 8 10 R259 39R 12 R251 39R 14 R246 39R 16 R239 39R 18 R228 22R 20 R223 22R 22 R221 22R 24 R215 22R 26 R207 22R 28 R190 22R 30 ISC_TWD1_PD4 [8] ISC_MCK/EXP_PC7 [8,15] ISC_VSYNC/EXP_PC5 [8,15] ISC_HSYNC/EXP_PC6 [8,15] ISC_PCK/SPI1_NPCS0_PC4 [8,10,15] ISC_D4/EXP_PB30 [7,15] ISC_D6/EXP/XPRO_PC0 [8,15] ISC_D8/SPI1_MOSI_PC2 [8,10,15] ISC_D10/EXP_PB24 [7,15] ISC_D0/EXP_PB26 [7,15] ISC_D2/EXP/XPRO_PB20 [7,15] ISC_D3/EXP/XPRO_PB29 [7,15] ISC D5/EXP/XPRO_PB31 [8,10,15] ISC_D7/SPI1_SPCK_PC1 [8,10,15] ISC_D9/SPI1_MISO_PC3 [7,15] ISC_D11/EXP_PB25 [7,15] ISC_D1/EXP_PB27 [7,15] ISC_D3/EXP/XPRO_PB29 Header 2X15

6.4.7 Audio Class D Amplifier

The Audio Class D Amplifier (CLASSD) is a digital input, Pulse Width Modulated (PWM) output stereo Class D amplifier. It features a high-quality interpolation filter embedding a digitally controlled gain, an equalizer and a de-emphasis filter.

On its input side, the CLASSD is compatible with most common audio data rates. On the output side, its PWM output can drive either:

• high-impedance single-ended or differential output loads (Audio DAC application) or,
  • external MOSFETs through an integrated non-overlapping circuit (Class D power amplifier application).

Figure 6-30. Audio PWM Class D MOSFET Mono Amplifier

VSY5 5W R62 UR R312 D7 1N4148W C29 10uF C33 10uF C38 10uF C32 10uF R71 0R 7] CLASSD_R0_PB1 7] CLASSD_R1_PB2 R311 22R C158 10nF R315 22R R313 U17 DMC2400UV R318 D8 1N4148W 5 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10K [7] CLASSD_R2_PB3 [7] CLASSD_R3_PB4 R322 22R C159 10nF R324 22R R323 U19 DMC2400UV R325 22R R324 R326 22R R325 J5 1 L25 Right P 2 Right N 3 4 180ohm at 100MHz 1 L26 2 Right P 180ohm at 100MHz

CLASSD Output Connector J5

WWW.ATMEL.COM XPRO EXT1 F1_TXD F1_RXD P2 BOOT_DIS V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 GND Atmel® SMART™ SAMA5D2 X PLAINED ULTRA DEBUG_DIS P2 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 RESET WAKE UP EDBG-USB A5-JTAGED66-JTAG3 CLASS D EDBG_DIS 10 11 12 13 14 15 16 17 18 19 20 21 SOMMO.CI11 SDMMCO.II 13 14 15 16 17 18 19 20 21 VDDIODDR HSC HSC P0 VDDBU CANRX1 CANTX1 P/O BU DIGITAL DIGITAL VDDIODDR SDMMCO.II 13 14 15 16 17 18 19 20 21 VDDIODDR SDMMCO.II 13 14 15 16 17 18 19 20 21

Table 6-12. CLASSD Output Connector J5 Signal Descriptions

Pin Mnemonic	Signal Description
1	VSYS_5V	Power
2	GND	GND
3	OUTPUT RIGHT P	Positive Level
4	OUTPUT RIGHT N	Negative Level

6.4.8 Tamper Interface

The SAMA5D2C-XULT board features eight tamper pins for static or dynamic intrusion detections, UART reception, and two analog pins for comparison.

For information on intrusion detection for SAMA5D23 and SAMA5D28, refer to the document "SAMA5D2 Security Module", document no. 44036. This document is available under Non-Disclosure Agreement (NDA).

Contact a Microchip sales representative for further details.

Figure 6-31. Tamper Pin Connector J12

PIOBU0 R76 330R PIOBU2 R77 330R PIOBU4 R78 330R PIOBU6 R79 330R RXD R80 0R J12 2 R132 330R 4 R133 330R 6 R134 330R 8 R135 330R 10 R136 0R R81 0R 11 12 13 14 R1370R ACNACP DNP(Header 2X7) VDD 5V IN R100 10K R123 100R 1% ACP R105 47K VDD 5V IN R152 1K (1.24V) R146 100R 1% ACN C51 130nF U7 TLV431A 2 1 R155 0R R158 DNP(0R)

6.4.9 Tamper Connector

Figure 6-32. Tamper Connector J12

WWW.ATMEL.COM BOOT_DIS XPRO Power XPRO EXT1 25 F1_TXD F1_RXD XPRO EXT2 45 P0 VDDIODDR SDMMCOLI VDDI R120H17 R120H13 R107H16 R102H11 700 2.5V RESET WAKE UP L13 EDBG-JUB EDBG-JTAG A5-JTAG CLASS D R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100 VDD_3V3 LP VDD_3V3 LP RST 3V3 5V GND GND NC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 CANRX0 CANTX0 VDDCORE REB LED LCD P2 DEBUG_DIS DEBUG SAMA5D2 X PLAINED LATMEL® SMART™

Table 6-13. Tamper Connector J12 Signal Descriptions

Signal	Pin No.		Signal
PIOBU0	1	2	PIOBU1
PIOBU2	3	4	PIOBU3
PIOBU4	5	6	PIOBU5
......continued
Signal Pin No. Signal
PIOBU6 7 8 PIOBU7
RXD 9 10 NC
GND 11 12 GND
ACP 13 14 ACN

6.4.10 RGB LED

There is one RGB LED on the SAMA5D2C-XULT board; it can be controlled by the user. The three LED cathodes are controlled via GPIO PWM pins.

Figure 6-33. RGB LED Indicators

graph LR
    A["LED_RED_PB6[7"]] --> B["R326"]
    C["LED_GREEN_PB5[7"]] --> D["R325"]
    E["LED_BLUE_PB0[7"]] --> F["R328"]
    B --> G["470R 1"]
    D --> H["470R 4"]
    F --> I["470R 3"]
    G --> J["D2"]
    H --> J
    I --> J
    J --> K["Anode"]
    K --> L["VDD LED"]
    style J fill:#f9f,stroke:#333

6.4.11 Push Button Switches

The SAMA5D2C-XULT board features three push buttons:

• One board Reset button (BP3) connected to the PMIC ACT8945A. When pressed and released, it causes a Power-on Reset of the board.
• One wake-up push button connected to the PMIC ACT8945A, used to exit the processor from Low-power mode (BP2).
  • One User momentary push button (BP1).

Figure 6-34. User Push Buttons (BP1)

[7] USER_PB_PB9 BP1 Tact Switch

6.4.12 Debug Interfaces

The SAMA5D2C-XULT board includes a JTAG, a Debug serial COM port and an EDBG interface port, to provide debug level access to the SAMA5D2.

6.4.12.1 Debug JTAG

A 10-pin JTAG header is provided on the SAMA5D2C-XULT board to facilitate the software development and debugging by using various JTAG emulators. The interface signals have a voltage level of 3.3V.

Figure 6-35. JTAG Interface

VDD_3V3 R104 100K R75 100K R74 100K JTAG_TCK_PD14 R99 DNP(0R) JTAG_TCK_PD14 [8] JTAG_TDO_PD16 [8] JTAG_TDI_PD15 [8] NRST [4,9,10,12,14,15] JTAG_TMS_PD17 [8] JTAG_TCK_PD14 [8] JTAG_TDO_PD16 [8] Header 2X5

Figure 6-36. JTAG J11

WWW.ATMEL.COM BOOT_DIS XPRO EXT1 F1_TXD F1_RXD XPRO EXT2 J95 P3 RESET VDDIODDR SDMMCO11 R128 R124 R100 R105 R71 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125 R126 R127 R128 R129 R130 R131 R132 R133 R134 R135 R136 R137 R138 R139 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R150 R151 R152 GND

Table 6-14. JTAG/ICE Connector J11 Signal Descriptions

Pin	Mnemonic	Signal Description
1	VTref. 3.3V power	This is the target reference voltage (main 3.3V).
2	TMS TEST MODE SELECT	JTAG mode set input into target CPU
3	GND	Common ground
4	TCK TEST CLOCK – Output timing signal, for synchronizing test logic and control register access	JTAG clock signal into target CPU
5	GND	Common ground
6	TDO JTAG TEST DATA OUTPUT – Serial data input from the target	JTAG data output from target CPU
......continued
Pin	Mnemonic Signal Description
7	RTCK – Input Return test clock signal from the target	Some targets having too slow of a system clock must synchronize the JTAG inputs to internal clocks. In present case such synchronization is unneeded and TCK merely looped back into RTCK.
8	TDI TEST DATA INPUT – Serial data output line, sampled on the rising edge of the TCK signal	JTAG data input into target CPU
9	GND Common ground
10	nSRST RESET Active-low reset signal. Target CPU reset signal.

6.4.12.2 Serial Console Port

The SAMA5D2C-XULT board has a dedicated serial port for debugging, which is accessible through the 6-pin male header J1. Various interfaces can be used as USB/Serial DBGU port bridge, such as FTDI TTL-232R USB to TTL serial cable or basic breakout board for the RS232/USB converter.

Figure 6-37. Debug Com Port for Console

VDD_3V3 C177 100nF DBGU_OE U21 VCC 5 DBGU_TXD 2 3 GND NL17SZ128DFT2G VDD_3V3 C170 100nF DBGU_LRXD1_PD2[RDS] U20 5 VCC 4 DBGU_CE 2 GND 3 DBGU_RXD NL17SZ128DFT2G TP27 SMD R336 DNEUR DBGU_CTS TP28 SMD R344 DNEUR DBGU_RTS

VDD_3V3 R527(DN168K) R33888K R29488K (UL4040)V(168K) DNP105(R441) DNP106(R342) VSYS_5V DBGU_CTS DBGU_XO DBGU_RXO DBGU_RTS J1 1 2 3 4 5 6 Header 1X6 VDD_3V3 R340 10K DBGU_OE JPN Header 1X2 JPR2 Jumper DBGU_DIS

A jumper (JP2) is available to disable the Debug communication interface.

R341 and R342 are optional (not implemented) resistors that can be used for power selection. Power can be delivered either by the SAMA5D2C-XULT board or by the debug interface tool. To avoid malfunction between the debug interface (e.g., FTDI) and the on-board power system, ensure that the selected voltage level corresponds to application requirements. The console baud rate is set to 115200 by default.

Figure 6-38. DEBUG Connector J1

WWW.ATMEL.COM V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D38 D40 D42 D44 D46 D48 D50 D52 GND DIGITAL Atmel® SMART™ SAMA5D2 X PLAINED DEBUG_DIS PB_USER SP1 DEBUG VDDIODDR SDMMC011 RESET A5-JTAGED66-JTG EDBG-USB CLASS D RST VDD 3V3 RST VDD 3V3 LP RST VDD CORE VBAT LEDG_DIS TP1 T2 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49 Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73 Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97 Q98 Q99 Q100 VDDI-XIN VDDI-XIN_IN VDDI-XIN_IN VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT VDDI-XIN_OUT WAVE UP Q10 Q11 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100

Table 6-15. DEBUG Connector J1 Signal Descriptions

Pin Mnemonic	PIO	Signal Description
1	CTS	RFU	Handshake input
2	TXD1 (Transmitted Data)	PD3	RS232 serial data output signal
3	RXD1 (Received Data)	PD2	RS232 serial data input signal
4	Power	-	5V/3.3V (selected by resistors)
5	RTS	RFU	Handshake output
6	GND	-	Common ground

When using a console connected to the DEBUG interface J1, the jumper JP2 DEBUG_DIS should be OFF.

6.4.13 Embedded Debugger (EDBG) Interface

The Embedded Debugger (EDBG) ^(1) is an intuitive plug-and-play solution which adds full programming and debugging support to embedded hardware kits containing Microchip microcontrollers and microprocessors. It enables seamless integration between the target hardware and the Atmel Studio front end.

In addition to the Virtual COM port which provides a UART bridge to the target device, the EDBG provides a Data Gateway Interface, through which the target device and host PC can communicate, facilitating high-level application debugging, monitoring, graphing and logging of system information in real-time.

The EDBG is based on the AT32UC3A4256J high-performance low-power 32-bit AVR microcontroller running at up to 60 MHz. The device includes an on-chip USB 2.0 high-speed hardware module with dedicated DMA channels, making it ideal for data communications.

By default, the EDBG is in Reset state and not usable. To use the EDBG interface, remove the jumper JP1. To avoid any conflicts with the debug signals, do not use the JTAG and EDBG at the same time.

Figure 6-39. EDBG Interface

Circuit schematic diagram of an EDBG-based power supply with labeled components and connections

6.4.14 CDC Debug Interface

This feature is enabled only if pin J9 (RESET_N) of the microcontroller is not tied to ground. The pin is normally pulled high and controlled by jumper JP1.

• Jumper JP1 not installed: The CDC device is enabled.
• Jumper JP1 installed: The CDC device is disabled.

The default baud rate CDC is 57600 (57600/N/8/1).

When using a console with the EDBG-CDC, the jumper JP2 DEBUG_DIS should be ON.

6.4.15 EDBG USB Type Micro-AB

Figure 6-40. EDBG USB Type Micro-AB Connector J14

SAMA5D2 X PLAINED WWW.ATMEL.COM BOOT_DIS VDD-3V3 VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP VDD-3V3_LP

Table 6-16. USB Connector J14 Signal Descriptions

Pin	Mnemonic	Signal Description
1	VBUS	5V power
2	DM	Data minus
3	DP	Data plus
4	ID	On-the-go identification (not connected)
5	GND	Common ground

6.5 PIO Usage on Expansion Connectors

6.5.1 Arduino Connectors

Five 8-pin, one 6-pin, one 10-pin and one 36-pin headers (J7, J8, J9, J16, J17, J20, J21, J22) are provided on the SAMA5D2C-XULT board to enable the PIO connection of various expansion cards. These headers' physical and electrical implementation match the Arduino R3 extension ("shields") system.

Due to I/O multiplexing, different signals can be provided on each pin.

Figure 6-41. Expansion Boards Connectors

5V_EXT_INP J17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 R206 22R R207 DNP(22R) R208 OR R209 OR R210 OR R211 OR R212 OR R213 OR R214 OR R215 OR R216 OR R217 RNP(0R) R218 RNP(0R) R219 RNP(0R) R220 RNP(0R) R221 RNP(0R) R222 RNP(0R) R223 RNP(0R) R224 RNP(0R) R225 RNP(0R) R226 RNP(0R) R227 RNP(0R) R228 RNP(0R) R229 RNP(0R) R230 RNP(0R) R231 RNP(0R) R232 RNP(0R) R233 RNP(0R) R234 RNP(0R) R235 RNP(0R) R236 RNP(0R) R237 RNP(0R) R238 RNP(0R) R239 RNP(0R) R240 RNP(0R) R241 RNP(0R) R242 RNP(0R) R243 RNP(0R) R244 RNP(0R) R245 RNP(0R) R246 RNP(0R) R247 RNP(0R) R248 RNP(0R) R249 RNP(0R) R250 RNP(0R) R251 RNP(0R) NRSST 100Ω 1% R261 Socket 2X19 EXP_PA8[8] EXP_PA1[7] ISC_DS/EXP_XPRO_PB31 ISC_DS/EXP_XPRO_PB37 ISC_DS/EXP_XPRO_PB39 ISC_DS/EXP_XPRO_PB31 ISC_DS/SPX_SPCK_PC1 EXP_PAZ[7] ISC_DS/EXP_XPRO_PB38 ISC_DS/EXP_XPRO_PB39 ISC_DS/EXP_XPRO_PC1 EXP_PAZ[7] ISC_DS/EXP_MISO_PC3 [8,10] ISC_DS/EXP_MISO_PC4 [8,10] ISC_DS/EXP_MISO_PC5 [8,10] ISC_DS/EXP_MISO_PC6 [8,10] ISC_DS/EXP_MISO_PC7 [8,10] ISC_DS/EXP_MISO_PC8 [8,10] ISC_DS/EXP_MISO_PC9 [8,10] ISC_DS/EXP_MISO_PC10 [8,10] ISC_DS/EXP_MISO_PC11 [8,10] ISC_DS/EXP_MISO_PC12 [8,10] ISC_DS/EXP_MISO_PC13 [8,10] ISC_DS/EXP_MISO_PC14 [8,10] ISC_DS/EXP_MISO_PC15 [8,10] ISC_DS/EXP_MISO_PC16 [8,10] ISC_DS/EXP_MISO_PC17 [8,10] ISC_DS/EXP_MISO_PC18 [8,10] ISC_DS/EXP_MISO_PC19 [8,10] ISC_DS/EXP_MISO_PC20 [8,10] ISC_DS/EXP_MISO_PC21 [8,10] ISC_DS/EXP_MISO_PC22 [8,10] ISC_DS/EXP_MISO_PC23 [8,10] ISC_DS/EXP_MISO_PC24 [8,10] ISC_DS/EXP_MISO_PC25 [8,10] ISC_DS/EXP_MISO_PC26 [8,10] ISC_DS/EXP_MISO_PC27 [8,10] ISC_DS/EXP_MISO_PC28 [8,10] ISC_DS/EXP_MISO_PC30 [8,10] ISC_DS/EXP_MISO_PC31 [8,10] ISC_DS/EXP_MISO_PC32 [8,10] ISC_DS/EXP_MISO_PC33 [8,10] ISC_DS/EXP_MISO_PC34 [8,10] ISC_DS/EXP_MISO_PC35 [8,10] ISC_DS/EXP_MISO_PC36 [8,10] ISC_DS/EXP_MISO_PC37 [8,10] ISC_DS/EXP_MISO_PC38 [8,10] ISC_DS/EXP_MISO_PC39 [8,10] ISC_DS/EXP_MISO_PC40 [8,10] ISC_DS/EXP_MISO_PC41 [8,10] ISC_DS/EXP_MISO_PC42 [8,10] ISC_DS/EXP_MISO_PC43 [8,10] ISC_DS/EXP_MISO_PC44 [8,10] ISC_DS/EXP_MISO_PC45 [8,10] ISC_DS/EXP_MISO_PC46 [8,10] ISC_DS/EXP_MISO_PC47 [8,10] ISC_DS/EXP_MISO_PC48 [8,10] ISC_DS/EXP_MISO_PC49 [8,10] ISC_DS/EXP_MISO_PC50 [8,10] S VDD_3V3 5V EXT_INP DND(POR) R244 DND(POR) R245 DND(POR) R246 DND(POR) R247 DND(POR) R248 DND(POR) R249 DND(POR) R250 DND(POR) R251 DND(POR) R252 DND(POR) R253 DND(POR) R254 DND(POR) R255 DND(POR) R256 DND(POR) R257 DND(POR) R258 DND(POR) R259 DND(POR) R260 DND(POR) R261 Header 2X3 [8.16] EXP_XPRO_PD27 SPIT_MISO DLP 5V EXT_INP EDBG_SP_MISO[4] DLP 5V EXT_INP [8.16] EXP_XPRO_PD26 SPIT_SPCK_SPD LDSN 5V EXT_INP EDBG_SP_SCK[4] DLP 5V EXT_INP NRST 100Ω 1% R261

6.5.1.1 Functions Available Through the Arduino Headers

The multiplexing of the SAMA5D27 I/Os (standard parallel I/O and up to three peripheral functions per pin) makes it possible to route alternate signals via Arduino extension headers. To enable these signals, SAMA5D27 PIO multiplexing must be properly configured. For more details, refer to Board Schematics and the section PIO Controller (PIO) in the SAMA5D2 Series data sheet.

The tables below, together with the connector schematics, provide the alternate signals available for use with Arduino connectors.

Figure 6-42. J7 Connector

WWW.ATMEL.COM VDDIODDR RESET WAKE UP EDBG-USB A5-JTAGED66-JTG CLASS D VDD 3V0 SAMA5D2 X PLAINED Atmel® SMART™ VBAT DEBUG_DIS PB_USER DBG_DIS LED8Q_DIS Ethy Levels 13V LEVELS CTB RXO VCCRDS GND GPIOBU CANRX1 CANTX1 PDCBU HSC DIGITAL VDDIODDR SDMMC011 VDDIODDR F4-TXD F4-RXD F0-TXD F0-RXD F3-TXD F3-RXD SDM SQ1 D22 D24 D26 D28 D30 D32 D34 D36 D38 D40 D42 D44 D46 D48 D50 D52 GND V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 GND IC R30 A5-USB-B SDMMC1 ATmel®

Table 6-17. J7 Connector Signals

Pin No. Signal	Function
1	VBAT	NC
2	3V3	(IOREF)
3	RST	-
4	3V3	-
5	5V	-
6	GND	-
7	GND	-
8	VIN	NC

Figure 6-43. J8 Connector

WWW.ATMEL.COM XPRO-EXT1 F1_TXD F1_RXD XPRO-EXT2 BOOT_DIS A5-USB-A RESET WAKE UP EDBG-USB A5-JTAGEDBG-JTAG CLASS D SAMA5D2 X PLAINED ULTRA Atmel® SMART™ VBAT DEBUG_DIS PB_USER BP1 LEDG_DIS R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 VDD_3V3 LP VDD_3V3 LP VDD_CORE RGB_LED RGB_LED LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GN LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GND LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNG LED_GNS

Table 6-18. J8 Connector Signals

Pin		SAMA5D27 PIO Muxing Alternates
No. Type
1	PA16	SPI0_MISO	TD1	QSPI0_IO0	I2SWS1	FLEXCOM3_IO4	D11	-
2	PD19	PCK0	TWD1	URXD2	-	I2SCK0	ISC_D11	AD0
3	PD20	TIOA2	TWCK1	UTXD2	-	I2SMCK0	ISC_PCK	AD1
4	PD23	URXD2	-	FLEXCOM4_IO3	-	I2SDO0	ISC_FIELD	AD4
5	PD21	TIOB2	TWD0	FLEXCOM4_IO1	-	I2SWS0	ISC_VSYNC	AD2
6	PD22	TCLK2	TWCK0	FLEXCOM4_IO2	-	I2SDI0	ISC_HSYNC	AD3
7	PD24	UTXD2	-	FLEXCOM4_IO4	-	-	-	AD5
8	PD30	SPI1_NPCS2	TMS	FLEXCOM2_O1	TIOB3	TWCK0	-	AD11

Figure 6-44. J9 Connector

WWW.ATMEL.COM XPRO EXT1 F1_TXD F1_RXD XPRO EXT2 BOOT_DIS RESET SDMMC017 VDDIODDR WAKE UP EDBG-USB A5-JTAGEDBG-JTAG CLASS D SAMA5D2 X PLAINED Atmel® SMART™ CAMR-X CANRX1 CANTX1 PINBU P311 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 GND CANTX1 CANRX1 CANTX1 PINBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBUU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU PINDBU

Table 6-19. J9 Connector Signals

Pin		SAMA5D27 PIO Muxing Alternates
No. Type
1	PA19	SPI0_NPCS2	RF1	QSPI0_IO3	TIOA0	SDHC1_DAT1	D14
2	PA17	SPI0_NPCS0	RD1	QSPI0_IO1	I2SDI1	FLEXCOM3_O1	D12
3	PA18	SPI0_NPCS1	RK1	QSPI0_IO2	I2SDO1	SDHC1_DAT0	D13
4	PC8	LCDDEN	NANDRDY	FIQ	PCK0	UTXD1	ISC_FIELD
5	PC27	LCDDAT23	GTX3	PCK1	CANRX1	TWD0	A16
6	PC26	LCDDAT22	-	GTX2	CANTX1	-	A15
7	PC11	LCDDAT3	GTXEN	ISC_D2	TCLK4	CANRX0	A0/NBS0
8	PC10	LCDDAT2	GTXCK	ISC_D1	TIOB4	CANTX0	-

Figure 6-45. J20 Connector

WWW.ATMEL.COM V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D39 D41 D43 D45 D47 D49 D51 D53 GND SDMMC1 A5-USB-8 R3 SAMS Atmel® SMART™ SAMA5D2 X PLAINED ULTRA DEBUG_DIS DEBUG DBG_DIS EDBG_DIS CLASS D R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 RPDDBUTX10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

Table 6-20. J20 Connector Signals

Pin		SAMA5D27 PIO Muxing Alternates
No. Type
10	PC0	LCDDAT21	A23	FLEXCOM0_O1	TWCK0	-	ISC_D6
9	PB31	LCDDAT20	A20	FLEXCOM0_IO4	TWD0	-	ISC_D5
8	AREF	-	-	-	-	-	-
7	GND	-	-	-	-	-	-
6	PD25	SPI1_SPCK		FLEXCOM4_O1	-	-	AD6
5	PD27	SPI1_MISO	TCK	FLEXCOM2_IO2	-	-	AD8
4	PD26	SPI1_MOSI	-	FLEXCOM2_IO1	-	-	AD7
3	PD28	SPI1_NPCS0	TDI	FLEXCOM2_IO3	-	-	AD9
2	PB5	TCLK2	D10	PWMH2	QSPI1_SCK	PTCPORT5	GTSUCOMP
1	PB6	TIOA2	D11	PWML2	QSPI1_CS	PTCPORT6	GTXER

Figure 6-46. J21 Connector

WWW.ATMEL.COM XPRO EXT1 F1_TXD F1_RXD XPRO EXT2 BOOT_DIS A5 USB-A RESET WAKE UP EDBG-USB A5-JTAGEDBG-JTAG CLASS D SAMS-DIS SAMAS-D2 X PLAINED ALTR DEBUG DBG_DIS R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 VDDIODDR SDMMC011 H126V12 H126V13 H126V14 H126V15 H126V16 H126V17 H126V18 H126V19 H126V20 H126V21 H126V22 H126V23 H126V24 H126V25 H126V26 H126V27 H126V28 H126V29 H126V30 H126V31 H126V32 H126V33 H126V34 H126V35 H126V36 H126V37 H126V38 H126V39 H126V40 H126V41 H126V42 H126V43 H126V44 H126V45 H126V46 H126V47 H126V48 H126V49 H126V50 H126V51 H126V52 H126V53 H126V54 H126V55 H126V56 H126V57 H126V58 H126V59 H126V60 H126V61 H126V62 H126V63 H126V64 H126V65 H126V66 H126V67 H126V68 H126V69 H126V70 H126V71 H126V72 H126V73 H126V74 H126V75 H126V76 H126V77 H126V78 H126V79 H126V80 H126V81 H126V82 H126V83 H126V84 H126V85 H126V86 H126V87 H126V88 H126V89 H126V90 H126V91 H126V92 H126V93 H126V94 H126V95 H126V96 H126V97 H126V98 H126V99 H126V100 H126V101 H126V102 H126V103 H126V104 H126V105 H126V106 H126V107 H126V108 H126V109 H126V110 H126V111 H126V112 H126V113 H126V114 H126V115 H126V116 H126V117 H126V118 H126V119 H126V120 H126V121 H126V122 H126V123 H126V124 H126V125 H126V126 H126V127 H126V128 H126V129 H126V130 H126V131 H126V132 H126V133 H126V134 H126V135 H126V136 H126V137 H126V138 H126V139 H126V140 H126V141 H126V142 H126V143 H126V144 H126V145 H126V146 H126V147 H126V148 H126V149 H126V150 H126V151 H126VBNDLEDLDDPDDLEDDEBUG_DISEHEPB_USERBP

Table 6-21. J21 Connector Signals

Pin		SAMA5D27 PIO Muxing Alternates
No. Type
1	PB9	TIOA3	D14	PWMFI1	QSPI1_IO2	-	GCOL
2	PA19	SPI0_NPCS2	RF1	QSPI0_IO3	TIOA0	SDHC1_DAT1	D14
3	PA20	SPI0_NPCS3	-	-	TIOB0	SDHC1_DAT2	D15
4	PD29	SPI1_NPCS1	TDO	FLEXCOM2_IO4	TIOA3	TWD0	AD10
5	PB10	TIOB3	D15	PWMEXTRG1	QSPI1_IO3	-	GRX2
6	PA21	IRQ	PCK2		TCLK0	SDHC1_DAT3	NANDRDY
7	PD12	TIOB1	FLEXCOM4_IO0	UTMI_LS1	GRXER	ISC_D5	ISC_D0
8	PD13	TCLK1	FLEXCOM4_IO1	UTMI_CRDCPSEL0	GRX0	ISC_D6	ISC_D1

Figure 6-47. J22 Connector

WWW.ATMEL.COM V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D38 D40 D41 D43 D45 D46 D48 D50 D51 D53 GND Atmel® SMART™ SAMA5D2 X PLAINED ULTRA DEBUG_DIS PB_USER BP1 DEBUG CTB RXO VOUTRDS GND VDDIODDR RESET A5-JTAGED66-JTG EDBG-USB CLASS D VDD 3V3 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R100

Table 6-22. J22 Connector Signals

Pin		SAMA5D27 PIO Muxing Alternates
No. Type
1	PA24	FLEXCOM1_IO0	D2	TDO	SPI1_MISO	-	QSPI0_IO0
2	PA23	FLEXCOM1_IO1	D1	TDI	SPI1_MOSI	-	QSPI0_CS
3	PB28	LCDDAT17	A17	FLEXCOM0_IO0	TIOA5	-	ISC_D2
4	PB29	LCDDAT18	A18	FLEXCOM0_IO1	TIOB5	-	ISC_D3
5	PB23	LCDDAT12	A12	RD0	TIOB2	FLEXCOM3_IO1	GMDIO
6	PB22	LCDDAT11	A11	TD0	TIOA2	FLEXCOM3_IO2	GMDC
7	PD4	TWD1	URXD2	-	GCOL	ISC_D10	NCS0
8	PD5	TWCK1	UTXD2	-	GRX2	ISC_D9	NCS1

Figure 6-48. J17 Connector

WWW.ATMEL.COM BOOT_DIS XPRO-EXT1 F1_TXD F1_RXD XPRO-EXT2 VDDIODDR SDMMC017 RESET WAKE UP EDBG-USB A5-JTAGEDBG-JTAG CLASS D SAMA5D2 X PLAINED ULTRA Atmel® SMART™ VBAT DEBUG_DIS DEBUG CTB ROD VOLTREUS 6x6D 3.9Y LEVELS

Table 6-23. J17 Connector Signals

Pin		SAMA5D27 PIO Muxing Alternates
No. Type
1	5V	-	-	-	-	-	-
2	5V	-	-	-	-	-	-
3	PD6	TCK	PCK1	-	GRX3	ISC_D8	NCS2
4	PA14	SPI0_SPCK	TK1	QSPI0_SCK	I2SMCK1	FLEXCOM3_IO3	D9
5	PA15	SPI0_MOSI	TF1	QSPI0_CS	I2SCK1	FLEXCOM3_IO1	D10
6	PB30	LCDDAT19	A19	FLEXCOM0_IO3	TCLK5	-	ISC_D4
7	PB31	LCDDAT20	A20	FLEXCOM0_IO4	TWD0	-	ISC_D5
8	PC0	LCDDAT21	A23	FLEXCOM0_O1	TWCK0	-	ISC_D6
9	PB20	LCDDAT9	A9	TK0	TIOB3	PCK1	GTX0
10	PB21	LCDDAT10	A10	TF0	TCLK3	FLEXCOM3_IO3	GTX1
11	PB27	LCDDAT16	A16	UTXD0	PDMCLK0	-	ISC_D1
12	PB26	LCDDAT15	A15	URXD0	PDMDAT0	-	ISC_D0
13	PB29	LCDDAT18	A18	FLEXCOM0_IO1	TIOB5	-	ISC_D3
14	PB28	LCDDAT17	A17	FLEXCOM0_IO0	TIOA5	-	ISC_D2
15	PB31	LCDDAT20	A20	FLEXCOM0_IO4	TWD0	-	ISC_D5
16	PB30	LCDDAT19	A19	FLEXCOM0_IO3	TCLK5	-	ISC_D4
Pin SAMA5D27 PIO Muxing Alternates
No. Type
17 PC1 LCDDAT22 A24 CANTX0 SPI1_SPCK I2SCK0 ISC_D7
18 PC0 LCDDAT21 A23 FLEXCOM0_O1 TWCK0 - ISC_D6
19 PA22 FLEXCOM1_IO3 D0 TCK		SPI1_SPCK SDHC1_CK QSPI0_SCK
20 PA25 FLEXCOM1_IO4 D3 TMS		SPI1_NPCS0 - QSPI0_IO1
21 PA26 FLEXCOM1_O1 D4 NTRST		SPI1_NPCS1 - QSPI0_IO2
22	PC3	LCDPWM	NWAIT	TIOA1	SPI1_MISO	I2SWS0	ISC_D9
23	PC2	LCDDAT23	A25	CANRX0	SPI1_MOSI	I2SMCK0	ISC_D8
24	PC6	LCDHSYNC	NCS1	TWD1	SPI1_NPCS2		ISC_HSYNC
25	PC5	LCDVSYNC	NCS0	TCLK1	SPI1_NPCS1	I2SDO0	ISC_VSYNC
26	PC4	LCDDISP	NWR1/NBS1	TIOB1	SPI1_NPCS0	I2SDI0	ISC_PCK
27	PB11	LCDDAT0	A0/NBS0	URXD3	PDMDAT0	-	GRX3
28	PB12	LCDDAT1	A1	UTXD3	PDMCLK0	-	GTX2
29	PC7	LCDPCK	NCS2	TWCK1	SPI1_NPCS3	URXD1	ISC_MCK
30 PB25	LCDDAT14 A14 RF0		- FLEXCOM3_IO1 ISC_D11
31	PB24	LCDDAT13	A13	RK0	TCLK2	FLEXCOM3_IO4	ISC_D10
32	PC8	LCDDEN	NANDRDY	FIQ	PCK0	UTXD1	ISC_FIELD
33	PD31	ADTRG	NTRST	IRQ	TCLK3	PCK0	-
34 PC26	LCDDAT22 - GTX2		CANTX1		A15
35 GND	----
36 GND	----

Figure 6-49. J16 Connector

WWW.ATMEL.COM V5 V5 D23 D25 D27 D29 D31 D33 D35 D37 D38 D40 D42 D44 D46 D48 D50 D52 GND DIGITAL Atmel® SMART™ SAMA5D2 X PLAINED DEBUG_DIS PB_USER BP1 DBG_DIS EDBG_DIS CLASS D RESET WAKE UP A5-JTAGED66-JTG VDDIODDR SDMMC011 H126R112 R126R113 H126R114 H126R115 H126R116 H126R117 H126R118 H126R119 H126R120 H126R121 H126R122 H126R123 H126R124 H126R125 H126R126 H126R127 H126R128 H126R129 H126R130 H126R131 H126R132 H126R133 H126R134 H126R135 H126R136 H126R137 H126R138 H126R139 H126R140 H126R141 H126R142 H126R143 H126R144 H126R145 H126R146 H126R147 H126R148 H126R149 H126R150 H126R151 H126R152 H126R153 H126R154 H126R155 H126R156 H126R157 H126R158 H126R159 H126R160 H126R161 H126R162 H126R163 H126R164 H126R165 H126R166 H126R167 H126R168 H126R169 H126R170 H126R171 H126R172 H126R173 H126R174 H126R175 H126R176 H126R177 H126R178 H126R179 H126R180 H126R181 H126R182 H126R183 H126R184 H126R185 H126R186 H126R187 H126R188 H126R189 H126R190 H126R191 H126R192 H126R193 H126R194 H126R195 H126R196 H126R197 H126R198 H126R199 H126R200

Table 6-24. J16 Connector Signals

Pin		SAMA5D27 PIO Muxing Alternates
No. Type
1	PD27	SPI1_MISO	TCK	FLEXCOM2_IO2	-	-	AD8
2	POWER (1)	-	-	-	-	-	-
3	PD25	SPI1_SPCK	-	FLEXCOM4_O1	-	-	AD6
4	PD26	SPI1_MOSI	-	FLEXCOM2_IO1	-	-	AD7
5	nRST	-	-	-	-	-	-
6	GND	-	-	-	-	-	-

Note: 5V/3.3V selected by resistors

6.5.2 XPRO

The SAMA5D2C-XULT board features three connectors to interface with standard Xplained PRO extensions.

Figure 6-50. XPRO Connectors Schematics

XPRO Power 5V_EXT_INP J24 1 2 3 4 VDD_3V3VSYS_5V DNP(Header 2X2) XPRO EXT1 EDBG_ID_02[14] XPRO_PD1[8] EXPXPRO_PD136[10] FXPXXPRO_FB57[11] EXPXPRO_PD139[15] ISC_D6/EXPXPRO_FB316[16] EXPXPRO_PA23[15] EXPXPRO_TD23[16] EXPXPRO_FD276[18] J25 ID ADC(-) GPIO PWM(-) IROGPIO TWI_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19 20 4 ADC(-) GPIO PWM(-) IROSSA TWT_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19 4 ADC(-) GPIO PWM(-) IROSSA TWT_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19 4 ADC(-) GPIO PWM(-) IROSSA TWT_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19 4 ADC(-) GPIO PWM(-) IROSSA TIW_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19 4 ADC(-) GPIO PWM(-) IROSSA TWT_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19 4 ADC(-) GPIO PWM(-) IROSSA TWT_SDA UART_RX SPI_SS_A SPI_MISO 10 SP_SST_BIGPIO TV_T_SC UART_TX SPI_MCSI SPI_SCK SPI_SCK 14 LART_TX SPI_MCSI SPI_SCK 15 LART_TX SPI_MCSI SPI_SCK 16 LART_TX SPI_MCSI SPI_SCK 17 LART_TX SPI_MCSI SPI_SCK 18 LART_TX SPI_MCSI SPI_SCK 20 VDD_3V3 EXPGXPRO_PD12[8.16] EXPGXPRO_PD18[8] EXPGXPRO_P910[7.15] EXPGXPRO_P229[8.16] EXPGXPRO_P24[7.15] EXPGXPRO_P26[8.15] EXPGXPRO_P25[8.15] XPRO EXT2 EDBG_ID_53[14] XPRO_PD7[8] XPRO_PD8[8] EXPXPRO_FB57[10] EXPXPRO_PD216[16] ISC_D2/EXPXPRO_FB286[10.40] ISC_D2/EXPXPRO_FB296[10.45] EXPXPRO_FD276[18] EXPXPRO_FD276[18] J26 ID ADC(-) GPIO PWM(-) IROGPIO TWI_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19 4 ADC(-) GPIO PWM(-) IROSSA TWT_SDA UART_RX SPI_SS_A SPI_MISO 13 15 17 19

The standard extension headers include common signals.

Figure 6-51. XPRO Connectors

XPRO POWER XPRO EXT1 7 5 4 3 2 1 0 14 F1 TXD 15 F1 RXD 16 17 XPRO EXT2 18 19 20 21 WWW.ATMEL.COM BOOT_DIS RESET SCL0 SDA0 GND VDDIODDR R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 GND DIGITAL HSC VDDBU CANEX1 CANTX1 CLASS D R15 VDD_3V3 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 GND Atmel® SMART™ SAMA5D2 X PLAINED ULTRA EDBG_DIS TF1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TIP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TPP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TFP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTP1T2 TTFIPTN B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B3B B5

Table 6-25. XPRO Power Connector J24 Signal Descriptions

Signal	Pin No.		Signal
EXP_5V	1	2	GND
......continued
Signal Pin No. Signal
VDD_5V 3 4 VSYS_3V3

Table 6-26. XPRO EXT1 Connector J25 Signal Descriptions

Pin XPRO Signal SAMA5D27 PIO Muxing Alternates
No. Type
1 - EDBG_ID_02 ----
2 GND ---		----
3	PD11	ADC(+)	TIOA1	PCK2	UTMI_LS0	GRXDV	ISI_D4	ISI_MCK	PTCCOL0
4	PD12	ADC(-)	TIOB1	FLEXCOM4_IO0	UTMI_LS1	GRXER	ISI_D5	ISI_D4	PTCCOL1
5	PD13	GPIO	TCLK1	FLEXCOM4_IO1	UTMI_CDRCPSEL0	GRX0	ISI_D6	ISI_D5	PTCCOL2
6	PD18	GPIO	NTRST	-	-	GMDIO	ISI_FIELD	ISI_D10	PTCCOL7
7	PB9	PWM(+)	TIOA3	D14	PWMFI1	QSPI1_IO2	-	GCOL	-
8	PB10	PWM(-)	TIOB3	D15	PWMEXTRG1	QSPI1_IO3	-	GRX2	-
9	PD13	IRQ/GPIO	TCLK1	FLEXCOM4_IO2	UTMI_CDRCPSEL0	GRX0	ISI_D6	ISI_D5	PTCCOL2
10	PD29	SPI_SS_B/GPIO	SPI1_NPCS1	TDO	FLEXCOM2_IO4	TIOA3	TWD0	-	AD10
11	PB31	TWI_SDA	LCDDAT20	A20	FLEXCOM0_IO4	TWD0	-	ISI_D5	-
12	PC0	TWI_SCL	LCDDAT21	A23	FLEXCOM0_O1	TWCK0	-	ISI_D6	-
13	PA23	UART_RX	FLEXCOM1_IO2	D1	TDI	SPI1_MOSI	-	QSPI0_CS	-
14	PA24	UART_TX	FLEXCOM1_IO1	D2	TDO	SPI1_MISO	-	QSPI0_IO0	-
15	PD28	SPI_SS_A	SPI1_NPCS0	TDI	FLEXCOM2_IO3	-	-	-	AD9
16	PD26	SPI_MOSI	SPI1_MOSI	-	FLEXCOM2_IO1	-	-	-	AD7
17	PD27	SPI_MISO	SPI1_MISO	TCK	FLEXCOM2_IO2	-	-	-	AD8
18	PD25	SPI_SCK	SPI1_SPCK	-	FLEXCOM4_O1	-	-	-	AD6
19	GND ---		-	----
20	3V3	--	----

Table 6-27. XPRO EXT2 Connector J26 Signal Descriptions

Pin		XPRO Signal	SAMA5D27 PIO Muxing Alternates
No.	Type
1	-	EDBG_ID_03	-	-	-	-	-	-	-
2	GND	-	-	-	-	-	-	-	-
3	PD7	ADC(+)	TDI	-	UTMI_RXVAL	GTX2	ISI_D0	NWR1/NBS1	PTCROW4
4	PD8	ADC(-)	TDO	-	UTMI_RXERR	GTX3	ISI_D1	NANDRDY	PTCROW5
5	PD9	GPIO	TMS	-	UTMI_RXACT	GTXCK	ISI_D2	-	PTCROW6
6	PD10	GPIO	NTRST	-	UTMI_HDIS	GTXEN	ISI_D3	-	PTCROW7
7	PB5	PWM(+)	TCLK2	D10	PWMH2	QSPI1_SCK	PTCPORT5	GTSUCOMP	-
8	PB6	PWM(-)	TIOA2	D11	PWML2	QSPI1_CS	PTCPORT6	GTXER	-
Pin XPRO Signal SAMA5D27 PIO Muxing Alternates
No. Type
9 PA21 IRQ/GPIO IRQ PCK2 - TCLK0 SDHC1_DAT3 NANDRDY -
10	PD28	SPI_SS_B/GPIO	SPI1_NPCS0	TDI	FLEXCOM2_IO3	-	-	-	AD9
11	PB28	TWI_SDA	LCDDAT17	A17	FLEXCOM0_IO1	TIOA5	-	ISI_D2	-
12	PB29	TWI_SCL	LCDDAT18	A18	FLEXCOM0_IO2	TIOB5	-	ISI_D3	-
13	PB29	UART_RX	LCDDAT18	A18	FLEXCOM0_IO2	TIOB5	-	ISI_D3	-
14	PB28	UART_TX	LCDDAT17	A17	FLEXCOM0_IO1	TIOA5	-	ISI_D2	-
15	PD29	SPI_SS_A	SPI1_NPCS1	TDO	FLEXCOM2_IO4	TIOA3	TWD0	-	AD10
16	PD26	SPI_MOSI	SPI1_MOSI	-	FLEXCOM2_IO1	-	-	-	AD7
17	PD27	SPI_MISO	SPI1_MISO	TCK	FLEXCOM2_IO2	-	-	-	AD8
18	PD25	SPI_SCK	SPI1_SPCK	-	FLEXCOM4_O1	-	-	-	AD6
19	GND	-	-	-	-	-	-	-	-
20	3V3	-	-	-	-	-	-	-	-

7. Board Schematics

This section contains the following schematics:

• Block Diagram
• PIO Muxing Table
• Power Supply
• SAMA5D27 – Power
• SAMA5D27 - DDR3
  • SAMA5D27 – PIOA and PIOB
  • SAMA5D27 – PIOC and PIOD
• SAMA5D27 – SYS, Tamper, and Debug
• USB, ISC, and LCD
• Serial Flash, LEDS, Push Button and ClassD
• Ethernet
• SD and eMMC
  • EDBG
• Expansion and XPRO Connectors

Important: Design Reuse Recommendation

In case the memory or PIO busses go to multiple destinations, series resistors must be added. These resistors must be located at the beginning of each branch, as close as possible to the MPU.

In case these connections are point-to-point, the branch resistors found in the following schematics can be removed.

In all cases, it is recommended to always perform routing simulation to check signal integrity prior to PCB manufacturing.

Figure 7-1. Block Diagram

graph TD
    A["Microchip"] -->|10/11 21 teeth| B["32Gb eMMC Flash"]
    A -->|21 teeth| C["4Gb DDR3 SDRAM"]
    A -->|21 teeth| D["32Gb eMMC Flash"]
    A -->|21 teeth| E["4Gb DDR3 SDRAM"]
    A -->|21 teeth| F["32Gb eMMC Flash"]
    A -->|21 teeth| G["4Gb DDR3 SDRAM"]
    A -->|21 teeth| H["32Gb eMMC Flash"]
    A -->|21 teeth| I["4Gb DDR3 SDRAM"]
    A -->|21 teeth| J["32Gb eMMC Flash"]
    A -->|21 teeth| K["4Gb DDR3 SDRAM"]
    A -->|21 teeth| L["32Gb eMMC Flash"]
    A -->|21 teeth| M["4Gb DDR3 SDRAM"]
    A -->|21 teeth| N["32Gb eMMC Flash"]
    A -->|21 teeth| O["4Gb DDR3 SDRAM"]
    A -->|21 teeth| P["32Gb eMMC Flash"]
    A -->|21 teeth| Q["4Gb DDR3 SDRAM"]
    A -->|21 teeth| R["32Gb eMMC Flash"]
    A -->|21 teeth| S["4Gb DDR3 SDRAM"]
    A -->|21 teeth| T["32Gb eMMC Flash"]
    A -->|21 teeth| U["4Gb DDR3 SDRAM"]
    A -->|21 teeth| V["32Gb eMMC Flash"]
    A -->|21 teeth| W["4Gb DDR3 SDRAM"]
    A -->|21 teeth| X["32Gb eMMC Flash"]
    A -->|21 teeth| Y["4Gb DDR3 SDRAM"]
    A -->|21 teeth| Z["32Gb eMMC Flash"]
    A -->|21 teeth| AA["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AB["32Gb eMMC Flash"]
    A -->|21 teeth| AC["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AD["32Gb eMMC Flash"]
    A -->|21 teeth| AE["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AF["32Gb eMMC Flash"]
    A -->|21 teeth| AG["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AH["32Gb eMMC Flash"]
    A -->|21 teeth| AI["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AJ["32Gb eMMC Flash"]
    A -->|21 teeth| AK["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AL["32Gb eMMC Flash"]
    A -->|21 teeth| AM["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AN["32Gb eMMC Flash"]
    A -->|21 teeth| AO["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AP["32Gb eMMC Flash"]
    A -->|21 teeth| AQ["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AR["32Gb eMMC Flash"]
    A -->|21 teeth| AS["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AT["32Gb eMMC Flash"]
    A -->|21 teeth| AU["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AV["32Gb eMMC Flash"]
    A -->|21 teeth| AW["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AX["32Gb eMMC Flash"]
    A -->|21 teeth| AY["4Gb DDR3 SDRAM"]
    A -->|21 teeth| AZ["32Gb eMMC Flash"]
    A -->|21 teeth| BA["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BB["32Gb eMMC Flash"]
    A -->|21 teeth| BC["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BD["32Gb eMMC Flash"]
    A -->|21 teeth| BE["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BF["32Gb eMMC Flash"]
    A -->|21 teeth| BG["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BH["32Gb eMMC Flash"]
    A -->|21 teeth| BI["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BJ["32Gb eMMC Flash"]
    A -->|21 teeth| BK["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BL["32Gb eMMC Flash"]
    A -->|21 teeth| BM["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BN["32Gb eMMC Flash"]
    A -->|21 teeth| BO["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BP["32Gb eMMC Flash"]
    A -->|21 teeth| BQ["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BR["32Gb eMMC Flash"]
    A -->|21 teeth| BS["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BT["32Gb eMMC Flash"]
    A -->|21 teeth| BU["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BV["32Gb eMMC Flash"]
    A -->|21 teeth| BW["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BX["32Gb eMMC Flash"]
    A -->|21 teeth| BY["4Gb DDR3 SDRAM"]
    A -->|21 teeth| BZ["32Gb eMMC Flash"]
    A -->|21 teeth| CA["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CB["32Gb eMMC Flash"]
    A -->|21 teeth| CC["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CD["32Gb eMMC Flash"]
    A -->|21 teeth| CE["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CF["32Gb eMMC Flash"]
    A -->|21 teeth| CG["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CH["32Gb eMMC Flash"]
    A -->|21 teeth| CI["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CJ["32Gb eMMC Flash"]
    A -->|21 teeth| CK["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CL["32Gb eMMC Flash"]
    A -->|21 teeth| CM["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CN["32Gb eMMC Flash"]
    A -->|21 teeth| CO["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CP["32Gb eMMC Flash"]
    A -->|21 teeth| COB["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CPB["32Gb eMMC Flash"]
    A -->|21 teeth| CPC["32Gb eMMC Flash"]
    A -->|21 teeth| CPD["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CPE["32Gb eMMC Flash"]
    A -->|21 teeth| CPF["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CPG["32Gb eMMC Flash"]
    A -->|21 teeth| CPH["4Gb DDR3 SDRAM"]
    A -->|21 teeth| CPI["32Gb eMMC Flash"]
    A -->|21 teeth| CPJ["4Gb DDR3 SDRAM"]

Board Schematics

SAMAD2C XULT

Figure 7-2. PIO Muxing Table
PIO Muxing & Jumper setting

LCD
ID_SYS	1
GND	2
KC	3
KC	4
LCDDAT2	5
LCDDAT3	6
GND	7
LCDDAT4	9
LCDDAT5	9
LCDDAT6	10
LCDDAT7	11
GND	12
KC	13
KC	14
LCDDAT10	15
LCDDAT11	16
GND	17
LCDDAT12	18
LCDDAT13	19
LCDDAT14	20
LCDDAT15	21
GND	22
KC	23
KC	24
LCDDAT16	25
LCDDAT19	26
GND	27
LCDDAT20	28
LCDDAT21	29
LCDDAT22	30
LCDDAT23	31
GND	32
LCDDPK	33
LCDSYNC	34
LCDSYNC	35
LCDDEN	36
SPTI_SPCK/AD1_XP	37
SPTI_MOSFAD1_XM	38
SPTI_MISOFAD2_TP	39
SPTI_NPCSDAD3_YM	40
LCDDISP	41
TWDT	42
TWCKT	43
IRQ1	44
IRQ2	45
TCIPPWM	46
MRST	47
VCC	48
VCC	49
GND	50

PIOA		PIQA		PIOB		PIOB		PIOC	EASURGASUEGASURGASURGASU
PA0	SDHCB_CX	PA18	SPID_MISOEXP	P00	LED_BLUE/CO_ID	P016	ETH_GRXIV	PC4	ISC_DMS/EXPPRO
PA1	SDHCB_CMD	PA17	SPID_CS/DEXP	P61	CLASSID_R3	PB17	ETH_GRER	PC1	ISC_DTS/IMP_SPICK/EXP
PA2	SDHCB_DAT0	PA18	SDHCT_DAT/DEXP	P62	CLASSID_R1	PB18	ETH_GRX0	PC2	ISC_DSS/P1_MOS/EXP
PA3	SDHCB_DAT1	PA19	SDHCT_DAT/DEXP	P63	CLASSID_R2	PB19	ETH_GRX1	PC3	ISC_DSS/P1_MISO/EXP
PA4	SDHCB_DAT2	PA20	SDHCT_DAT/DEXP	P64	CLASSID_R3	PB20	ETH GTX/EXP	PC4	ISC_PCK/SPIN_NPCS/EXP
PA5	SDHCB_DAT3	PA21	SDHCT_DAT/DEXP/PRO	P65	LED_GREEN/EXP/PRO	P021	ETH GTX/EXP	PC5	ISC_VSYNC/EXP
PA6	SDHCB_DAT4	PA22	SDHCT_OK/GSPII_SCK/EXP	P66	LED_RED/EXP/PRO	P022	ETH_GM/EXP	PC6	ISC_LSYNC/EXP
PA7	SDHCB_DAT5	PA23	QSPII_CS/EXP/PRO	P67	LCD_IRQ1	P023	ETH_CAND/EXP	PC7	ISC_MCK/EXP
PA8	SDHCB_DAT6	PA24	QSPII_ON/DEXP/PRO	P68	LCD_IRQ2	P024	ISC_DTX/EXP	PC8	PMIC_LO/EXP
PA9	SDHCB_DAT7	PA25	QSPII_OT/EXP	P69	USER_FB/EXP/PRO	P025	ISC_OTI/EXP	PC9	ETH_INT
PA10	SDHCB_RSTN	PA26	QSPII_TO/EXP	P610	USBB_EN/S/EXP/PRO	P026	ISC_DXE/EXP	PC10	LCD_DAT/DEXP
	SDHCB_MOUSEH	PA27	QSPII_IO3	P611	ISC_RST/EXP	P027	AMC_DTEXP	PC11	LCD_DAT/DEXP
PA12	PMIC_CHGEFV	PA28	SDHCT_CMD	P612	ISC_PWD/EXP	P028	ISC_C2/EXP/PRO	PC12	LCD_DAT4
PA13	SDHCB_CD	PA29	USBB_DVCUR	P613	PMIC_IRQ	P029	ISC_C3/EXP/PRO	PC13	LCD_DAT5
PA14	SPID_SPICK/EXP	PA30	SDHCT_CD	P614	ETH_CTX/CK	P030	ISC_C4/EXP	PC14	LCD_DAT6
PA15	SPID_MOS/EXP	PA31	USBA_VBUS_Detection	P615	LTH_ISTEN	P031	ISC_C6/EXP/PRO	PC15	LCD_DAT7

PIOC		PIOD		PIOD	EGASUEGASUEGASO
PC16	LCO_DAT10	PD0	LCD_FCK	PD16	JTAG_TDO
PC17	LCO_DAT11	PD1	LCD_DLN	PD17	JTAG_INS
PC18	LCO_DAT12	PD2	DEGU_CRXOH	PD18	XPRO
PC19	LCO_DAT13	PD3	DEGU_UTXD1	PD19	LCD_XPIEXP
PC20	LCO_DAT14	PD4	LCODEPMSCEXP TWD1	PD20	LCD_XMEXP
PC21	LCO_DAT15	PD5	LCODEPMSCEXP TWCK1	PD21	LCD_YMPVRC_TWCKEXP
PC22	LCO_DAT16	PD6	EXP	PD22	LCD_YMPVRC_TWCKEXP
PC23	LCO_DAT19	PD7	XPRO	PD23	EXP
PC24	LCO_DAT20	PD8	XPRO	PD24	EXP
PC25	LCO_DAT21	PD9	XPRO	PD25	EXPXPRO
PC26	LCO_DAT22/DX2	PD10	XPRO	PD26	EXPXPRO
PC27	LCO_DAT23/DX2	PD11	XPRO	PD27	EXPXPRO
PC28	LCO_PWM	PD12	EXPXPRO	PD28	EXPXPRO
PC29	LCO_DISP	PD13	EXPXPRO	PD29	EXPXPRO
PC30	LCO_VSYNC	PD14	JTAG_TCK	PD30	EXP
PC31	LCO_HSYNC	PD15	JTAG_TDI	PD31	EXP

JUMPER DESCRIPTION
PART	DEFAULT	FUNCTION
JP1	OPEN	Disable LDGS
JP2	OPEN	Disable Debug
JP3	CLOSE	IVDD_SV_LP Measurement
JP4	CLOSE	IVDDCORE Measurement
JP5	CLOSE	IVDDISC-VDDIOPVIZ Measurement
JP6	CLOSE	IVDDRU Measurement
JP7	CLOSE	IVDDIOUR_MPU Measurement
JP8	CLOSE	IVDD_BV_IN Measurement
JP9	OPEN	Disable CS of SP/SDSP/SMMHC Memory

MROCHIP GAMAZONE-NOFT PDL Molding	R12	HD/AT	PN	Pin 16	3.0X	32" 55" X8
	E	RD/CT	PN	20" 12"	3.0X	30" 00" X8
	E	HD/CT	PN	Pin 14	3.0X	32" 55" X8
	E	RD/CT	PN	Pin 16	3.0X	30" 00" X8
	A	RD/CT	Pin 2	Pin 14	3.0X	32" 55" X8
	A	HD/CT	Pin 2	Pin 14	3.0X	32" 55" X8
	B12	HD/CT	Pin 2	Pin 14	DATE	DATE
	R11	1/1			D1	3/15

Board Schematics

Figure 7-3. Power Supply

Board Schematics
SAMAD2C XULT

Figure 7-4. SAMA5D27 - Power

POWER TEST POINTS VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VOCER 10kΩ, VAC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/DC/NC VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) VOCER 10kΩ (5.2) (5.2) VOCER 10kΩ (5.2) (5.2) VOCER 10kΩ (5.2) (5.2) VOCER 10kΩ (5.2) (5.2) VOCER 10kΩ (5.2) (5.2) VOCER 10kΩ (5.2) (5.2) VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ VOCER 48kΩ AOSO-6492 capacitors close to the Pin of VODO***

Board Schematics
SAMAD2C XULT

Figure 7-5. SAMA5D27 - DDR3

100 ohms differential trace impedance Routing top or bottom 100 ohms differential trace impedance Routing up or bottom 100 ohms differential trace impedance Routing up or bottom 100 ohms differential trace impedance Routing up or bottom 100 ohms differential trace impedance Routing up or bottom 100 ohms differential trace impedance Routing up or bottom 100 ohms differential trace impedance Routing up or bottom 100 ohms differential trace impedance

Board Schematics

SAMAD2C XULT

Figure 7-6. SAMA5D27 - PIOA and PIOB

S202 S212 S222 S232 S242 S252 S262 S272 S282 S292 S302 S312 S322 S332 S342 S352 S362 S372 S382 S392 S402 S412 S422 S432 S442 S452 S462 S472 S482 S492 S502 S512 S522 S532 S542 S552 S562 S572 S582 S592 S602 S612 S622 S632 S642 S652 S662 S672 S682 S692 S702 S712 S722 S732 S742 S752 S762 S772 S782 S792 S802 S812 S822 S832 S842 S852 S862 S872 S882 S892 S902 S912 S922 S932 S942 S952 S962 S972 S982 S992 S1002

B102 B103 B104 B105 B106 B107 B108 B109 B110 B110 B111 B112 B112 B113 B114 B114 B115 B116 B116 B117 B118 B118 B119 B120 B120 B121 B122 B122 B123 B124 B124 B125 B126 B126 B127 B128 B128 B129 B130 B130 B131 B132 B132 B133 B134 B134 B135 B136 B136 B137 B138 B138 B139 B140 B140 B141 B142 B142 B143 B144 B144 B145 B146 B146 B147 B148 B148 B149 B150 B150 B151 B152 B152 B153 B154 B154 B155 B156 B156 B157 B158 B158 B159 B160 B160 B161 B162 B162 B163 B164 B164 B165 B166 B166 B167 B168 B168 B169 B170 B170 B171 B172 B172 B173 B174 B174 B175 B176 B176 B177 B178 B178 B179 B180 B180 B181 B182 B182 B183 B184 B184 B185 B186 B186 B187 B188 B188 B189 B190 B190 B191 B192 B192 B193 B194 B194 B195 B196 B196 B197 B198 B198 B200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200 A200

38R on PAZZ close to MPU.

15 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

B01 B12 B23 B02 B12 B24 B03 B12 B25 B04 B12 B26 B05 B12 B27 B06 B12 B28 B07 B12 B29 B08 B12 B30 B09 B12 B31 B10 B12 B32 B11 B12 B33 B12 B12 B34 B13 B12 B35 B14 B12 B36 B15 B12 B37 B16 B12 B38 B17 B12 B39 B18 B12 B40 B19 B12 B41 B20 B12 B42 B21 B12 B43 B22 B12 B44 B23 B12 B45 B24 B12 B46 B25 B12 B47 B26 B12 B48 B27 B12 B49 B28 B12 B50 B29 B12 B51 B30 B12 B52 B31 B12 B53 B32 B12 B54 B33 B12 B55 B34 B12 B56 B35 B12 B57 B36 B12 B58 B37 B12 B59 B38 B12 B60 B39 B12 B61 B40 B12 B62 B41 B12 B63 B42 B12 B64 B43 B12 B65 B44 B12 B66 B45 B12 B67 B46 B12 B68 B47 B12 B69 B48 B12 B70 B49 B12 B71 B50 B12 B72 B51 B12 B73 B52 B12 B74 B53 B12 B75 B54 B12 B76 B55 B12 B77 B56 B12 B78 B57 B12 B79 B58 B12 B80 B59 B12 B81 B60 B12 B82 B61 B12 B83 B62 B12 B84 B63 B12 B85 B64 B12 B86 B65 B12 B87 B66 B12 B88 B67 B12 B89 B68 B12 B90 B69 B12 B91 B70 B12 B92 B71 B12 B93 B72 B12 B94 B73 B12 B95 B74 B12 B96 B75 B12 B97 B76 B12 B98 B77 B12 B99 B78 A07A F08 D09 E0D

MICROCHIP	31	NO. (2)	PWR	8000 10	300	3000000
			2000	8000 10	300	3000000
			4000	8000 10	300	3000000
	A	R###	200	7000 10	300	3000000
	A	R###	300	7000 10	300	3000000
	A	R###	400	7000 10	300	3000000
	BVI			500	500	DATOMY
	R###	119			D1	7/5

Board Schematics

SAMAD2C XULT

Figure 7-7. SAMA5D27 - PIOC and PIOD

Figure 7-8. SAMA5D27 - SYS, Tamper, and Debug

SYS Routing up or bottom Routing USB Max trace length mismatch between USB signals unit should be no audio than 3.5mm 80 ohms differentials trace Impedance Routing HSIC Routing HSIC Reise to Sound JTAG DEBUG MICROCHIP D1 1/15

Board Schematics
SAMAD2C XULT

Figure 7-9. USB, ISC, and LCD

ISC LCD USB A USB C USB B Through Holes MICROCHIP SAMSUNG KINT 1.14 D1 10/15

Board Schematics
SAMAD2C XULT

Figure 7-10. Serial Flash, LEDS, Push Button and ClassD

Figure 7-11. Ethernet

100 ohms differential trace impedance Routing top or bottom Ethernet 10Base-T/100Base-TX U5 DCBCAST_21T TX4 RCC VDD_102 VDDA_203 VDDA_204 VDDA_205 VDDA_206 VDDA_207 VDDA_208 VDDA_209 VDDA_210 VDDA_211 VDDA_212 VDDA_213 VDDA_214 VDDA_215 VDDA_216 VDDA_217 VDDA_218 VDDA_219 VDDA_220 VDDA_221 VDDA_222 VDDA_223 VDDA_224 VDDA_225 VDDA_226 VDDA_227 VDDA_228 VDDA_229 VDDA_230 VDDA_231 VDDA_232 VDDA_233 VDDA_234 VDDA_235 VDDA_236 VDDA_237 VDDA_238 VDDA_239 VDDA_240 VDDA_241 VDDA_242 VDDA_243 VDDA_244 VDDA_245 VDDA_246 VDDA_247 VDDA_248 VDDA_249 VDDA_250 VDDA_251 VDDA_252 VDDA_253 VDDA_254 VDDA_255 VDDA_256 VDDA_257 VDDA_258 VDDA_259 VDDA_260 VDDA_261 VDDA_262 VDDA_263 VDDA_264 VDDA_265 VDDA_266 VDDA_267 VDDA_268 VDDA_269 VDDA_270 VDDA_271 VDDA_272 VDDA_273 VDDA_274 VDDA_275 VDDA_276 VDDA_277 VDDA_278 VDDA_279 VDDA_280 VDDA_281 VDDA_282 VDDA_283 VDDA_284 VDDA_285 VDDA_286 VDDA_287 VDDA_288 VDDA_289 VDDA_290 VDDA_291 VDDA_292 VDDA_293 VDDA_294 VDDA_295 VDDA_296 VDDA_297 VDDA_298 VDDA_299 VDDA_300 ECCOS-TP-B All the Exchangers of Base: PTF_ADECA_pctc=1.0 - 3.0 - 1. CNC-PLT_PHOT/RCC=1.0 - 3.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 1.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 4.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 5.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 7.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PhOT/RCC=1.5 / VCC-PLT_PHOT/RCC=1.5 / VCC-PLT_PhOT/RCC=1.5 / VCC-PLT_PhOT/RCC=1,5 / VCC-PLT_PHOT/RCC=1,5 / VCC-PLT_PHOT/RCC=1,5 / VCC-PLT_PHOT/RCC=1,5 / VCC-PLT_PHOT/RCC=1,5 / VCC-PLT_PHOT/RCC=1,5 / VCC-PLT_PHOT/RCC=1,5 / VCC-PLT_PHOT/RCC=1,5 / Vcc-PLT_PHOT/RCC=1,5 / Vcc-PLT_PHOT/RCC=1,5 / Vcc-PLT_PHOT/RCC=1,5 / Vcc-PLT_PHOT/RCC=1,5 / Vcc-PLT_PHOT/RCC=1,5 / Vcc-PLT_PHOT/RCC=1,5 / Vcc-PLT_PHOT/RCC=3,5 / Vcc-PLT_PHOT/RCC=3,5 / Vcc-PLT_PHOT/RCC=3,5 / Vcc-PLT_PHOT/RCC=3,5 / Vcc-PLT_PHOT/RCC=3,5 / Vcc-PLT_PHOT/RCC=3,5 / Vcc-PLT_PHOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=3,5 / Vcc-PLT_PhOT/RCC=4,5 / Vcc-PLT_PhOT/RCC=4,5 / Vcc-PLT_PhOT/RCC=4,5 / Vcc-PLT_PhOT/RCC=4,5 / Vcc-PLT_PhOT/RCC=4,5 / Vcc-PLT_PhOT/RCC=4,5 / Vcc-PLT_PhOT/RCC=4,5 / Vcc-PLT_PpHOT/RCC=4,5 / Vcc-PLT_PpHOT/RCC=4,5 / Vcc-PLT_PpHOT/RCC=4,5 / Vcc-PLT_PpHOT/RCC=4,5 / Vcc-PLT_PpHOT/RCC=4,5 / Vcc-PLT_PpHOT/RCC=4,5 / Vcc-PLT_PpHOT/RCC=-3,5 / Vcc-PLT_PpHOT/RCC=-3,5 / Vcc-PLT_PpHOT/RCC=-3,5 / Vcc-PLT_PpHOT/RCC=-3,5 / Vcc-PLT_PpHOT/RCC=-3,5 / Vcc-PLT_PpHOT/RCC=-3,5 / Vcc-PLT_PpHOT/RCC=-3,5 / AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = AUC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC = BAC

Board Schematics

SAMAD2C XULT

Figure 7-12. SD and eMMC

SD/MMCPlus CARD INTERFACE - SDHC1 47K pull down on SDHC0 OVD PA1 close to MPU. 3RR on SDHC0 CK PA3 close to MPU. Incremental match of CLVC/CMD (DAI[7:30] 30R) eMMC - SDHC0 MicroCHIP SINAMATOSC-251T D1 13 15 VCCB 262 VCCB 263 VCCB 264 VCCB 265 VCCB 266 VCCB 267 VCCB 268 VCCB 269 VCCB 270 VCCB 271 VCCB 272 VCCB 273 VCCB 274 VCCB 275 VCCB 276 VCCB 277 VCCB 278 VCCB 279 VCCB 280 VCCB 281 VCCB 282 VCCB 283 VCCB 284 VCCB 285 VCCB 286 VCCB 287 VCCB 288 VCCB 289 VCCB 290 VCCB 291 VCCB 292 VCCB 293 VCCB 294 VCCB 295 VCCB 296 VCCB 297 VCCB 298 VCCB 299 VCCB 300 VCCB 301 VCCB 302 VCCB 303 VCCB 304 VCCB 305 VCCB 306 VCCB 307 VCCB 308 VCCB 309 VCCB 310 VCCB 311 VCCB 312 VCCB 313 VCCB 314 VCCB 315 VCCB 316 VCCB 317 VCCB 318 VCCB 319 VCCB 320 VCCB 321 VCCB 322 VCCB 323 VCCB 324 VCCB 325 VCCB 326 VCCB 327 VCCB 328 VCCB 329 VCCB 330 VCCB 331 VCCB 332 VCCB 333 VCCB 334 VCCB 335 VCCB 336 VCCB 337 VCCB 338 VCCB 339 VCCB 340 VCCB 341 VCCB 342 VCCB 343 VCCB 344 VCCB 345 VCCB 346 VCCB 347 VCCB 348 VCCB 349 VCCB 350 VCCB 351 VCCB 352 VCCB 353 VCCB 354 VCCB 355 VCCB 356 VCCB 357 VCCB 358 VCCB 359 VCCB 360 VCCB 361 VCCB 362 VCCB 363 VCCB 364 VCCB 365 VCCB 366 VCCB 367 VCCB 368 VCCB 369 VCCB 370 VCCB 371 VCCB 372 VCCB 373 VCCB 374 VCCB 375 VCCB 376 VCCB 377 VCCB 378 VCCB 379 VCCB 380 VCCB 381 VCCB 382 VCCB 383 VCCB 384 VCCB 385 VCCB 386 VCCB 387 VCCB 388 VCCB 389 VCCB 390 VCCB 391 VCCB 392 VCCB 393 VCCB 394 VCCB 395 VCCB 396 VCCB 397 VCCB 398 VCCB 399 VCCB 400

Board Schematics
SAMAD2C XULT

Figure 7-13. EDBG

EDBG_TWI EDBG JTAG MICROCHIP SAMSUNG-KILT D1 14/15

Board Schematics

SAMAD2C XULT

Figure 7-14. Expansion and XPRO Connectors

Expansion Boards Connectors XPRO Power XPRO EXT1 XPRO EXT2 Sv Ext 8.0 Sv Ext 7.5 Sv Ext 6.5 Sv Ext 5.5 Sv Ext 4.5 Sv Ext 3.5 Sv Ext 2.5 Sv Ext 1.5 Sv Ext 0.5 Sv Ext 0.1 Sv Ext 0.05 Sv Ext 0.01 Sv Ext 0.005 Sv Ext 0.001 Sv Ext 0.0005 Sv Ext 0.0001 Sv Ext 0.00005 Sv Ext 0.00001 Sv Ext 0.000005 Sv Ext 0.000001 Sv Ext 0.0000005 Sv Ext 0.0000001 Sv Ext 0.00000005 Sv Ext 0.00000001 Sv Ext 0.000000005 Sv Ext 0.000000001 Sv Ext 0.0000000005 Sv Ext 0.0000000001 Sv Ext 0.00000000005 Sv Ext 9.5 Sv Ext 8.5 Sv Ext 7.5 Sv Ext 6.5 Sv Ext 5.5 Sv Ext 4.5 Sv Ext 3.5 Sv Ext 2.5 Sv Ext 1.5 Sv Ext 0.5 Sv Ext 0.1 Sv Ext 0.05 Sv Ext 0.01 Sv Ext 9.5 Sv Ext 8.5 Sv Ext 7.5 Sv Ext 6.5 Sv Ext 5.5 Sv Ext 4.5 Sv Ext 3.5 Sv Ext 2.5 Sv Ext 1.5 Sv Ext 0.5 Sv Ext 9.5 Sv Ext 8.5 Sv Ext 7.5 Sv Ext 6.5 Sv Ext 5.5 Sv Ext 4.5 Sv Ext 3.5 Sv Ext 2.5 Sv Ext 1.5 Sv Ext 9.5 Sv Ext 8.5 Sv Ext 7.5 Sv Ext 6.5 Sv Ext 5.5 Sv Ext 4.5 Sv Ext 3.5 Sv Ext 2.5 Sv Ext 1.5 Sv Ext 9.5 Sv Ext 8.5 Sv Ext 7.5 DIN:1, DIN:2, DIN:3, DIN:4, DIN:5, DIN:6, DIN:7, DIN:8, DIN:9, DIN:10, DIN:11, DIN:12, DIN:13, DIN:14, DIN:15, DIN:16, DIN:17, DIN:18, DIN:19, DIN:20, DIN:21, DIN:22, DIN:23, DIN:24, DIN:25, DIN:26, DIN:27, DIN:28, DIN:29, DIN:30, DIN:31, DIN:32, DIN:33, DIN:34, DIN:35, DIN:36, DIN:37, DIN:38, DIN:39, DIN:40, DIN:41, DIN:42, DIN:43, DIN:44, DIN:45, DIN:46, DIN:47, DIN:48, DIN:49, DIN:50, DIN:51, DIN:52, DIN:53, DIN:54, DIN:55, DIN:56, DIN:57, DIN:58, DIN:59, DIN:60, DIN:61, DIN:62, DIN:63, DIN:64, DIN:65, DIN:66, DIN:67, DIN:68, DIN:69, DIN:70, DIN:71, DIN:72, DIN:73, DIN:74, DIN:75, DIN:76, DIN:77, DIN:78, DIN:79, DIN:80, DIN:81, DIN:82, DIN:83, DIN:84, DIN:85, DIN:86, DIN:87, DIN:88, DIN:89, DIN:90, DIN:91, DIN:92, DIN:93, DIN:94, DIN:95, DIN:96, DIN:97, DIN:98, DIN:99, DIN:100

Board Schematics
SAMAD2C XULT

8. Errata

8.1 NRST

Issue: Pullup R6 is connected to VDD_3V3

Workaround: Connect pullup R6 to VDDBU.

8.2 nLBO

Issue: No pullup on nLBO

Workaround: Add pullup 10K to nLBO output.

8.3 R63

Issue: Incorrect R63 resistance in schematic "EDBG"

Workaround: Correct the resistance to 47R.

8.4 R100/R105

Issue: The values of resistors R100/R105 (mounted as a resistive divider on VDD_5V_IN) are swapped. This results in:

• a leakage current path is created from VDD_5V_IN to VDDDU through the ACP pin, and
• the ACP pin is biased around 4V instead of 0.88V, therefore the voltage detection between ACP and CAN does not work

Workaround: Swap R100 and R105.

9. Revision History

Table 9-1. Rev. E - 08/2020

Changes

Updated PD12 and PD13 in XPRO EXT1 Connector J25 Signal Descriptions and J21 Connector Signals.

Table 9-2. Rev. D - 05/2019

Changes

Updated 7. Board Schematics: all schematics regenerated.

Table 9-3. Rev. C - 10/2018

Changes

Document title modified to SAMA5D2C XULT User's Guide (was SAMA5D2 (Rev. C) Xplained Ultra Evaluation Kit User's Guide)

Updated Figure 6-10.

Changed eMMC reference in section eMMC.

All schematics regenerated.

Added R100/R105 in section Errata.

Table 9-4. Rev. B - 12/2017

Changes

Updated SAMA5D27 – PIOA and PIOB.

Removed Declaration of Conformity.

Table 9-5. Rev. A - 10/2017

Changes

First issue.

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