MIC2126 - Electronic component Microchip - Free user manual and instructions

USER MANUAL MIC2126 Microchip

28V Synchronous Buck Controllers Featuring Adaptive ON-Time Control

Features

• Hyper Speed Control Architecture Enables:
- High delta V operation ( V_IN = 28V and V_OUT = 0.6V )
- Any Capacitor™ stable
• 4.5V to 28V Input Voltage
- Adjustable Output Voltage from 0.6V to 24V
• 200 kHz to 750 kHz Programmable Switching Frequency
• HyperLight Load ^® (MIC2125)
• Hyper Speed Control ^® (MIC2126)
- Enable Input and Power Good Output
• Built-in 5V Regulator for Single-Supply Operation
- Programmable current limit and "hiccup" mode short-circuit protection
- 7 ms internal soft-start, internal compensation, and thermal shutdown
• Supports Safe Start-Up into a Prebiased Output
- - 40^ C to + 125^ C Junction Temperature Range
• Available in 16-pin, 3 mm × 3 mm QFN Package

Applications

• Networking/Telecom Equipment
- Base Stations, Servers
• Distributed Power Systems
- Industrial Power Supplies

General Description

The MIC2125 and MIC2126 are constant-frequency synchronous buck controllers featuring a unique adaptive ON-time control architecture. The MIC2125/6 operate over an input voltage range from 4.5V to 28V and can be used to supply load current up to 25A. The output voltage is adjustable down to 0.6V with a guaranteed accuracy of ±1%. The device operates with programmable switching frequency from 200 kHz to 750 kHz.

HyperLight Load ^® architecture provides the same high efficiency and ultra-fast transient response as the Hyper Speed Control ^® architecture under medium to heavy loads. It also maintains high efficiency under light load conditions by transitioning to variable frequency, discontinuous conduction mode operation.

The MIC2125/6 offer a full suite of features to ensure protection of the IC during fault conditions. These include undervoltage lockout to ensure proper operation under power-sag conditions, internal soft-start to reduce inrush current, "hiccup" mode short-circuit protection, and thermal shutdown.

Package Type

MIC2125/6 16-Pin 3 mm x 3 mm QFN (ML) VIN EN PG FB 16 15 14 13 VDD 1 PVDD 2 ILIM 3 DL 4 EP 17 12 AGND 11 NC 10 OVP 9 BST 5 6 7 8 PGND FREQ DH SW

Typical Application Circuit

MIC2125/6 3x3 QFN PVDD VDD AGND EN PG VOUT 56.2kΩ 10kΩ OVP FB FREQ VIN BST DH SW DL PGND ILIM 1.2kΩ 0.1μF 0.72μH 90.9kΩ 0.1μF 2.26kΩ 4.7μF 2.2μF ×3 470pF 10kΩ 470μF VOUT TO 28V VOUT 3.3V/20A

Functional Block Diagram

MIC2125/26 PVDD VDD LDO VDD LVLO MODIFIED TOUT FIXED TON ESTIMATE VIN FREQ BST HSD DH Q1 0.1μF SW PVDD LSD DL Q3 POND CL DETECTION ILIM OVP Vpp 0.6V THERMAL SHUTDOWN COMP COMPENSATION g,EA 8% Vpp 0.6V AGND VDD 49.9kΩ PG EN EN 4.7μF R19 R20 2.2μF x2 220μF 0.72μH R1 10kΩ 470pF 100μF 470μF 3.3V/20A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

V_IN -0.3V to +30V
V_DD, P_VDD -0.3V to +6V
V_SW , V_FREQ , V_ILIM , V_EN -0.3V to ( V_IN + 0.3V )
V_BST to V_SW ...... -0.3V to 6V
V_BST -0.3V to 36V
V_PG -0.3V to (V_DD + 0.3V)
V_FB -0.3V to (V_DD + 0.3V)
P_GND to A_GND -0.3V to +0.3V
ESD Rating ^(1) 2 kV

Operating Ratings ‡

Supply Voltage ( V_IN ) 4.5V to 28V

V_SW , V_FREQ , V_ILIM , V_EN ....0V to V_IN

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.

‡ Notice: The device is not guaranteed to function outside its operating ratings.

Note 1: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 kΩ in series with 100 pF.

TABLE 1-1: ELECTRICAL CHARACTERISTICS

Electrical Characteristics: V_IN = 12V, V_OUT = 1.2V, V_BST - V_SW = 5V; T_A = 25°C , unless noted. Bold values indicate -40°C ≤ T_J ≤ +125°C. (Note 1).
Parameters Min. Typ.	Max. Units	Conditions
Power Supply Input
Input Voltage Range ( V_IN ) (Note 2)	4.5 — 5	5 V	V		_DD = V_IN
	4.5 — 28	—
Quiescent Supply Current (MIC2125)	—	3	4	0	750 FB = 1.5μA V
Quiescent Supply Current (MIC2126)	—	1.1	3	mA	V_FB = 1.5V
Shutdown Supply Current	—	0.1	5	μA	SW unconnected, V_EN = 0V
V_DD Supply
V_DD Output Voltage	4.8	5.2	5.4	V	V_IN = 7V to 28V, I_DD = 10mA
V_DD UVLO Threshold	3.7	4.2	4.5		V_DD rising
V_DD UVLO Hysteresis	—	400	—	mV	—
Load Regulation	0.6	2	3.6	%	I_DD = 0 to 40 mA
Reference
Feedback Reference Voltage	0.597	0.6	0.603	V	T_J = 25°C (±0.5%)
	0.594	0.6	0.606		-40°C ≤ T_J ≤ +125°C (±1%)
FB Bias Current	—	0.01	0.5	μA	V_FB = 0.6V
Enable Control
EN Logic Level High	1.6	—	—	V	—
EN Logic Level Low	—	—	0.6		—
EN Hysteresis	—	120	—	mV	—
EN Bias Current	—	6	30	μA	V_EN = 12V
Oscillator
Switching Frequency	—	750	—	kHz	V_FREQ = V_IN
	—	3	7	5	—
Maximum Duty Cycle	—	85	—	%	—
Minimum Duty Cycle	—0	—		V	_FREQ = 50% × V_IN
Minimum On-Time	—	100	—	ns	—
Minimum Off-Time	150	220	300		—
Soft-Start
Soft-Start Time	—	7	—	ms	—
Short-Circuit Protection and OVP
Current-Limit Comparator Offset	-15	-47	mV	V	_FB = 0.6V
Current-Limit Source Current	32	36	40	μA	V_FB = 0.6V

Note 1: Specification for packaged product only.
2: The application is fully functional at low V_DD (supply of the control section) if the external MOSFETs have low voltage V_TH .

TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: V_IN = 12V, V_OUT = 1.2V, V_BST - V_SW = 5V; T_A = 25°C , unless noted. Bold values indicate -40°C ≤ T_J ≤ +125°C. (Note 1).
Parameters	Min.	Typ.	Max.	Units	Conditions
Overvoltage Protection Threshold	— 0.62	— V —
FET Drivers
DH, DL Output Low Voltage —	— 0.1 V	I			_SINK = 10 mA
DH, DL Output High Voltage V	_PVDD-0.1 or V_BST-0.1	—	—		I_SOURCE = 10 mA
DH On-Resistance, High State	— 2.5 — Ω	—
DH On-Resistance, Low State	— 1.6 — —
DL On-Resistance, High State	— 1.9 — —
DL On-Resistance, Low State	—	0.55 —	—
SW, BST Leakage Current —	— 50			μA —
Power Good (PG)
PG Threshold Voltage	85	89	95	% V_OUT	Sweep V_FB from low to high
PG Hysteresis	—	6	— Sweep V		_FB from high to low
PG Delay Time	—	80	—	μs	Sweep V_FB from low to high
PG Low Voltage	—	60	200	mV	V_FB < 90% × V_NOM, I_PG = 1 mA
Thermal Protection
Overtemperature Shutdown	—	150	—	°C	T_J Rising
Overtemperature Shutdown Hysteresis	—	15	—	°C	—

Note 1: Specification for packaged product only.
2: The application is fully functional at low V_DD (supply of the control section) if the external MOSFETs have low voltage V_TH .

TEMPERATURE SPECIFICATIONS

Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Junction Operating Temperature T	J	-40 —	+125 °C	Note 1
Storage Temperature Range T	S	-65 —	+150 °C —
Junction Temperature	TJ	—	— +150 °C —
Lead Temperature	—	—	—	+260	°C	Soldering, 10s
Package Thermal Resistances
Thermal Resistance 3 mm x 3 mm QFN-16LD	_JA	—	50.8	—	°C/W	—
	_JC	—	25.3	—	°C/W	—

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., T_A , T_J , _JA ). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

FIGURE 2-1: V IN Operating Supply Current vs. Input Voltage (MIC2125).

FIGURE 2-4: V IN Shutdown Current vs. Input Voltage (MIC2125).

FIGURE 2-2: Feedback Voltage vs. Input Voltage (MIC2125).

FIGURE 2-5: Switching Frequency vs. Input Voltage.

FIGURE 2-3: Output Voltage vs. Input Voltage (MIC2125).

FIGURE 2-6: Switching Frequency vs. Temperature (MIC2126).

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

FIGURE 2-7: V _DD Voltage vs. Input Voltage (MIC2125).

FIGURE 2-10: V IN Operating Supply Current vs. Temperature (MIC2125).

FIGURE 2-8: Enable Threshold vs. Input Voltage (MIC2125).

FIGURE 2-11: Feedback Voltage vs. Temperature (MIC2125).

FIGURE 2-9: Output Peak Current Limit vs. Input Voltage (MIC2125).

FIGURE 2-12: Load Regulation vs. Temperature (MIC2125).

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

FIGURE 2-13: V IN Shutdown Current vs. Temperature (MIC2125).

FIGURE 2-16: EN Bias Current vs. Temperature (MIC2125)

FIGURE 2-14: V _DD UVLO Threshold vs. Temperature (MIC2125).

FIGURE 2-17: V _DD Voltage vs. Temperature (MIC2125)

FIGURE 2-15: Enable Threshold vs. Temperature (MIC2125).

FIGURE 2-18: Current-Limit Source Current vs. Temperature (MIC2125).

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

*Note: For Case Temperature graphs: The temperature measurement was taken at the hottest point on the MIC2125/6 case mounted on a 5 square inch PCBn. Actual results will depend upon the size of the PCB, ambient temperature and proximity to other heat emitting components.

FIGURE 2-19: Line Regulation vs. Temperature (MIC2125).

FIGURE 2-22: Output Regulation vs. Input Voltage (MIC2125).

FIGURE 2-20: Feedback Voltage vs. Output Current (MIC2125).

FIGURE 2-23: Case Temperature* vs. Output Current (MIC2125).

FIGURE 2-21: Line Regulation vs. Output Current (MIC2125).

FIGURE 2-24: Case Temperature* vs. Output Current (MIC2125).

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

*Note: For Case Temperature graphs: The temperature measurement was taken at the hottest point on the MIC2125/6 case mounted on a 5 square inch PCBn. Actual results will depend upon the size of the PCB, ambient temperature and proximity to other heat emitting components.

FIGURE 2-25: Case Temperature* vs. Output Current (MIC2125).

FIGURE 2-28: Efficiency (V IN = 18V) vs. Output Current (MIC2125).

FIGURE 2-26: Efficiency (V IN = 5V) vs. Output Current (MIC2125).

FIGURE 2-29: Efficiency (V IN = 5V) vs. Output Current (MIC2126).

FIGURE 2-27: Efficiency (V IN = 12V) vs. Output Current (MIC2125).

FIGURE 2-30: Efficiency (V IN = 12V) vs. Output Current (MIC2126).

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

FIGURE 2-31: Efficiency (V IN = 18V) vs. Output Current (MIC2126).

FIGURE 2-34: MIC2125 V IN Start-Up with Prebiased Output.

FIGURE 2-32: V IN Soft Turn-On.

FIGURE 2-35: Enable Turn-On/Turn-Off.

FIGURE 2-33: V IN Soft Turn-Off.

FIGURE 2-36: Enable Turn-On Delay and Rise Time.

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

FIGURE 2-37: Enable Turn-Off Delay and Fall Time.

FIGURE 2-40: Enabled into Short.

FIGURE 2-38: Enable Thresholds.

FIGURE 2-41: Power-Up into Short-Circuit.

FIGURE 2-39: Enable Turn-On Delay and Rise Time.

FIGURE 2-42: Output Peak Current-Limit Threshold.

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

FIGURE 2-43: Short-Circuit.

FIGURE 2-46: Transient Response.

FIGURE 2-44: Output Recovery from Short-Circuit.

FIGURE 2-47: MIC2125 Switching Waveform, I_OUT = 0A .

FIGURE 2-45: Output Recovery from Thermal Shutdown.

FIGURE 2-48: MIC2125 Switching Waveform, I_OUT = 0.1A .

Note: Unless otherwise noted, V_IN = 12V , FREQ = 350 kHz.

FIGURE 2-49: Switching Waveform, I OUT = 10A.

FIGURE 2-52: MIC2125 Switching Waveform, I_OUT = 0.1A .

FIGURE 2-50: Switching Waveform, I OUT = 20A.

FIGURE 2-53: Power Good at V IN Soft Turn-On.

FIGURE 2-51: MIC2125 Switching Waveform, I_OUT = 0A .

FIGURE 2-54: Power Good at V IN Soft Turn-Off.

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin Number Symbol Description
1	V_DD	Internal Linear regulator output. Connect a 4.7 μF ceramic capacitor from V_DD to A_GND for decoupling. In the applications where V_IN < +5.5V , V_DD should be tied to V_IN to by-pass the linear regulator.
2	P_VDD	5V supply input for the low-side N-channel MOSFET driver, which can be tied to V_DD externally. A 4.7 μF ceramic capacitor from P_VDD to P_GND is recommended for decoupling.
3	I_LIM	Current limit setting input. Connect a resistor from SW to I_LIM to set the overcurrent threshold for the converter.
4 DL Low-side gate driver output. The DL driving voltage swings from ground to V DD
5	P_GND	Power ground. P_GND is the return path for the low side gate driver. Connect P_GND pin to the source of low-side N-Channel external MOSFET.
6 FREQ Switching frequency adjust input. Connect FREQ to the mid-point of an external resistor divider from V_IN to GND to program the switching frequency. Tie to V_IN to operate at 750 kHz frequency.
7 DH High-side gate driver output. The DH driving voltage is floating on the switch node voltage ( V_SW ).
8	SW	Switch node and current-sense input. Connect the SW pin to the switch node of the buck converter. The SW pin also senses the current by monitoring the voltage across the low-side MOSFET during OFF time. In order to sense the current accurately, connect the low-side MOSFET drain to the SW pin using a Kelvin connection.
9	BST	Bootstrap Capacitor Input. Connect a ceramic capacitor with a minimum value of 0.1 μF from BST to SW.
10	OVP Output Overvoltage Protection Input. Connect to the mid-point of an external resistive divider from the V_OUT to GND to program overvoltage limit. Connect to A_GND if the output overvoltage protection is not required.
11	NC No connect.
12	A_GND	Analog Ground. Connect A_GND to the exposed pad.
13	FB Feedback input. Input to the transconductance amplifier of the control loop. The FB pin is regulated to 0.6V. A resistor divider connecting the feedback to the output is used to set the desired output voltage.
14	PG	Open-drain Power good output. Pull-up with an external pull-up resistor to V_DD or to an external power rail.
15	EN Enable input. A logic signal to enable or disable the buck converter operation. Logic-high enables the device; logic-low shuts down the regulator. In disable mode, the V_DD supply current for the device is minimized to 0.1 μA typically. Do not pull-up EN pin to V_DD/P_VDD .
16	V_IN	Supply voltage input. The V_IN operating voltage range is from 4.5V to 28V. A 1 μF ceramic capacitor from V_IN to A_GND is required for decoupling.
17	EP Exposed Pad. Connect the exposed pad to the A GND copper plane to improve the thermal performance.

4.0 FUNCTIONAL DESCRIPTION

The MIC2125 and MIC2126 are adaptive on-time synchronous buck controllers built for high input voltage to low output voltage applications. They are designed to operate over a wide input voltage range from 4.5V to 28V and their output is adjustable with an external resistive divider. An adaptive ON-time control scheme is employed to obtain a constant switching frequency and to simplify the control compensation. Overcurrent protection is implemented when sensing low-side MOSFET's R_DS(ON) . The device features internal soft-start, enable, UVLO, and thermal shutdown.

4.1 Theory of Operation

The MIC2125/6 Functional Block Diagram appears on page two. The output voltage is sensed by the MIC2125/6 feedback pin (FB), and is compared to a 0.6V reference voltage ( V_REF ) at the low gain transconductance error amplifier ( g_m ). Figure 4-1 shows the MIC2125/6 control loop timing during steady-state operation. When the feedback voltage decreases and the amplifier output is below 0.6V, the comparator triggers and generates an ON-time period. The ON-time period is predetermined by the fixed t_ON estimator circuitry value from Equation 4-1:

EQUATION 4-1:

$$ t _ {O N E S T I M A T E D (} = \frac {V _ {O U T}}{V _ {I N} \times f _ {S W}} $$

Where:

$$ V _ {\text { OUT }} $$

$$ V _ {I N} $$

$$ f _ {S W} $$

Output Voltage

Power Stage Input Voltage

Switching Frequency

At the end of the ON-time, the internal high-side driver turns off the high-side MOSFET and the low-side driver turns on the low-side MOSFET. The OFF-time depends upon the feedback voltage. When the feedback voltage decreases and the output of the g_m amplifier is below 0.6V, the ON-time period is triggered and the OFF-time period ends. If the OFF-time period determined by the feedback voltage is less than the minimum OFF-time t_OFF(min) , which is about 220 ns, the MIC2125/6 control logic applies the t_OFF(min) instead. t_OFF(min) is required to maintain enough energy in the boost capacitor ( C_BST ) to drive the high-side MOSFET.

The maximum duty cycle is obtained from the 220 ns t_OFF(MIN) :

EQUATION 4-2:

$$ D _ {M A X} \quad \frac {t _ {S} - t _ {O F F M I N (}}{t _ {S}} \quad 1 - \frac {2 2 0 n s}{t _ {S}} $$

Where:

$$ t _ {S} \quad 1 / f _ {S W} $$

It is not recommended to use MIC2125/6 with an OFF-time close to t_OFF(MIN) during steady-state operation.

The adaptive ON-time control scheme results in a constant switching frequency in the MIC2125/6. The actual ON-time and resulting switching frequency varies with the different rising and falling times of the external MOSFETs. Also, the minimum t_ON results in a lower switching frequency in high V_IN to V_OUT applications.

FIGURE 4-1: MIC2125/6 Control Loop Timing

Figure 4-2 shows the operation of the MIC2125/6 during load transient. The output voltage drops due to a sudden increase in load, which results in the V_FB falling below V_REF . This causes the comparator to trigger an ON-time period. At the end of the ON-time, a minimum OFF-time t_OFF(min) is generated to charge C_BST if the feedback voltage is still below V_REP . The next ON-time is triggered immediately after the t_OFF(min) due to the low feedback voltage. This operation results in higher switching frequency during load transients. The switching frequency returns to the nominal set frequency once the output stabilizes at new load current level. The output recovery time is fast and the output voltage deviation is small in MIC2125/6 converter due to the varying duty cycle and switching frequency.

FIGURE 4-2: MIC2125/6 Load Transient Response

Unlike true current-mode control, the MIC2125/6 uses the output voltage ripple to trigger an ON-time period. In order to meet the stability requirements, the MIC2125/6 feedback voltage ripple should be in phase with the inductor current ripple and large enough to be sensed by the g_m amplifier. The recommended feedback voltage ripple is 20 mV \~ 100 mV over the full input voltage range. If a low-ESR output capacitor is selected, then the feedback voltage ripple may be too small to be sensed by the g_m amplifier. Also, the output voltage ripple and the feedback voltage ripple are not necessarily in phase with the inductor current ripple if the ESR of the output capacitor is very low. For these applications, ripple injection is required to ensure proper operation. Refer to the Ripple Injection section under Application Information for details about the ripple injection technique.

4.2 Discontinuous Conduction Mode (MIC2125 Only)

The MIC2125 operates in discontinuous conduction mode at light load. The MIC2125 has a zero crossing comparator (ZC detection) that monitors the inductor current by sensing the voltage drop across the low-side MOSFET during its ON-time. If the V_FB > 0.6V and the inductor current goes slightly negative, the MIC2125 turns off both the high-side and low-side MOSFETs. During this period, the efficiency is optimized by shutting down all the non-essential circuits and the load current is supplied by the output capacitor. The control circuitry wakes up when the feedback voltage falls below V_REF and triggers a t_ON pulse. Figure 4-3 shows the control loop timing in discontinuous conduction mode.

FIGURE 4-3: MIC2125 Control Loop Timing (Discontinuous Conduction Mode)

The typical no load supply current during discontinuous conduction mode is only about 340 A, allowing the MIC2125 to achieve high efficiency at light load operation.

4.3 Soft-Start

Soft-start reduces the power supply inrush current at startup by controlling the output voltage rise time. The MIC2125/6 implements an internal digital soft-start by ramping up the reference voltage V_REF from 0 to 100% in about 7 ms. Once the soft-start is completed, the related circuitry is disabled to reduce the current consumption.

4.4 Current Limit

The MIC2125/6 uses the low-side MOSFET R_DS(ON) to sense the inductor current.

CONTROL LOGIC TIMER SOFT-START CL DETECTION VIN DH Q1 SW DL Q3 PGND ILIM ICL CCL L RCL COUT

FIGURE 4-4: MIC2125/6 Current-Limiting Circuit
In each switching cycle of the MIC2125/6 converter, the inductor current is sensed by monitoring the voltage across the low-side MOSFET during the OFF period. An internal current source of 36 A generates a voltage across the external resistor R_CL . The I_LIM pin voltage V_(ILIM) is the sum of the voltage across the low side MOSFET and the voltage across the resistor ( V_CL ). The sensed voltage V_(ILIM) is compared with the power ground ( P_GND ) after a blanking time of 150 ns.
If the absolute value of the voltage drop across the low side MOSFET is greater than V_CL , the current limit event is triggered. Eight consecutive current limit events triggers hiccup mode. The hiccup sequence, including the soft-start, reduces the stress on the switching FETs and protects the load and supply from severe short conditions.
The current limit can be programmed by using Equation 4-3.

EQUATION 4-3:

R_CL = (I_CLIM + _PP × 0.5) R_DSON(-) × V_OFFSETI_CL
Where:
I_CLIM	Desired Current Limit
_PP	Inductor Current Peak-to-Peak
R_DS(ON)	On-Resistance of Low-Side Power MOSFET
V_OFFSET	Current-Limit Comparator Offset (Typical Value is -4 mV per Table 1-1)
I_CL	Current-Limit Source Current (Typical Value is 36 μA, per Table 1-1)

Because MOSFET R_DS(ON) varies from 30% to 40% with temperature, it is recommended to add a 50% margin to I_CL in the previous equation to avoid false current limiting due to increased MOSFET junction temperature rise. It is also recommended to connect the SW pin directly to the drain of the low-side MOSFET to accurately sense the MOSFET's R_DS(ON) .

4.5 Negative Current Limit (MIC2126 Only)

The MIC2126 implements negative current limit by sensing the SW voltage when the low-side FET is off. If the SW node voltage exceeds 12 mV typical, the device turns off the low-side FET until the next ON-time event is triggered. The negative current limit value is given by Equation 4-4.

EQUATION 4-4:

$$ I _ {N L I M} = \frac {1 2 m V}{R _ {D S O N (\quad)}} $$

Where:

$$ \begin{array}{c c} I _ {N L I M} & \text { Negative Current Limit } \ R _ {D S (O N)} & \text { On - Resistance of Low - Side Power } \ & \text { MOSFET } \end{array} $$

4.6 MOSFET Gate Drive

The MIC2125/6 high-side drive circuit is designed to switch an N-Channel MOSFET. Figure 4-1 shows a bootstrap circuit, consisting of a PMOS switch and C_BST . This circuit supplies energy to the high-side drive circuit. Capacitor C_BST is charged while the low-side MOSFET is on and the voltage on the SW pin is approximately 0V. When the high-side MOSFET driver is turned on, energy from C_BST is used to turn the MOSFET on. If the bias current of the high-side driver is less than 10 mA, a 0.1 μF capacitor is sufficient to hold the gate voltage within minimal droop, (i.e., _BST = 10 mA × 3.33 μs/0.1 μF = 333 mV ). A small resistor, RG in series with C_BST , can be used to slow down the turn-on time of the high-side N-channel MOSFET.

4.7 Overvoltage Protection

The MIC2125/6 includes the OVP feature to protect the load from overshoots due to input transients and output short to a high voltage. When the overvoltage condition is triggered, the converter turns off immediately to allow the output voltage to discharge. The MIC2125/6 power should be recycled to enable it again.

5.0 APPLICATION INFORMATION

5.1 Setting the Switching Frequency

The MIC2125/6 are adjustable-frequency, synchronous buck controllers featuring a unique adaptive ON-time control architecture. The switching frequency can be adjusted between 200 kHz and 750 kHz by changing the resistor divider network consisting of R19 and R20.

MIC2125/26 VDD/PVDD AGND VDD 5V 4.7µF VIN 2.2µF x3 R19 R20 VIN FREQ PGND

FIGURE 5-1: Switching Frequency Adjustment.

Equation 5-1 gives the estimated switching frequency.

EQUATION 5-1:

fSW(ADJ) fO×R20/R19R20+ Where: fO Switching Frequency when R19 is 100 kΩ and R20 is open. fO is typically 750 kHz.

For more precise setting, it is recommended to use Figure 5-2.

FIGURE 5-2: Switching Frequency vs. R20

5.2 MOSFET Selection

Voltage rating, on-resistance, and total gate charge are important parameters for MOSFET selection.

The voltage rating for the high-side and low-side MOSFETs are essentially equal to the power stage input voltage V_IN . A safety factor of 30% should be added to the V_IN(MAX) while selecting the voltage rating of the MOSFETs to account for voltage spikes due to circuit parasitic elements.

The power dissipated in the MOSFETs is the sum of conduction losses ( P_CONDUCTION ) and switching losses ( P_AC ).

EQUATION 5-2:

$$ P _ {S W} = P _ {C O N D U C T I O N} + P _ {A C} $$

EQUATION 5-3:

$$ P _ {C O N D U C T I O N} = I _ {S W (R M S)} ^ {2} \times R _ {D S (O N)} $$

Where:

$$ \begin{array}{l} R _ {D S (O N)} \quad \text { On - Resistance of the MOSFET } \ I _ {S W (R M S)} \quad R M S \text { current of the MOSFET } \ \end{array} $$

The total high-side MOSFET switching loss is:

EQUATION 5-4:

$$ P _ {A C} = 0. 5 \times V _ {I N} \times I _ {L O A D} \times (t _ {R} + t _ {F}) \times f _ {S W} $$

Where:

$$ \begin{array}{l} t _ {R} / t _ {F} \quad \text { Switching Transition Times } \ I _ {\text {LOAD}} \quad \text {Load Current} \ f _ {S W} \quad \text { Switching Frequency } \ \end{array} $$

Turn-on and turn-off transition times can be approximated by:

EQUATION 5-5:

$$ t _ {R} = \frac {Q _ {S W (H S)} \times \left(R _ {I I S D (P U L L - U P)} + R _ {H S (G A T E)}\right)}{V _ {D D} - V _ {T H}} $$

EQUATION 5-6:

$$ t _ {F} = \frac {Q _ {S W H S (\quad)} R _ {H S D P U L L U P - (\quad + (R _ {H S G A T E (\quad)})}}{V _ {T H}} $$

Where:

$$ R _ {H S D (P U L L - U P)} $$

High-Side Gate Driver Pull-Up Resistance

$$ R _ {H S D (P U L L - D O W N)} $$

High-Side Gate Driver Pull-Down Resistance

$$ R _ {H S (G A T E)} $$

High-Side MOSFET Gate Resistance

$$ Q _ {S W (H S)} $$

Switching Gate Charge of the High-Side MOSFET

$$ V _ {T H} $$

Gate Threshold Voltage

The high-side MOSFET switching losses increase with the switching frequency and the input voltage. The low-side MOSFET switching losses are negligible and can be ignored for these calculations.

5.3 Inductor Selection

Inductance value, saturation, and RMS currents are required to select the output inductor. The input and output voltages and the inductance value determine the peak-to-peak inductor ripple current. Larger peak-to-peak ripple current increases the power dissipation in the inductor and MOSFETs. Larger output ripple current also requires more output capacitance to smooth out the larger ripple current. Smaller peak-to-peak ripple current requires a larger inductance value and therefore a larger and more expensive inductor.

A good compromise between size, loss, and cost is to set the inductor ripple current to be equal to 40% of the maximum output current.

The inductance value is calculated by Equation 5-7.

EQUATION 5-7:

$$ L = \frac {V _ {O U T} V _ {I N M A X (} \times (V _ {O U T})}{V _ {I N M A X (} \times f _ {S W} \times 0 . 4 \times I _ {O U T M A X (}} \quad) $$

Where:

f_SW

Switching Frequency

0.4

Ratio of AC Ripple Current to DC Output Current

$$ V _ {\text { IN(MAX) }} $$

Maximum Power Stage Input Voltage

The peak-to-peak inductor current ripple is:

EQUATION 5-8:

$$ \Delta I _ {L (P P)} = \frac {V _ {O U T} - V _ {I N M A X (\times (V _ {O U T})}}{V _ {I N M A X (\times f _ {S W} \times L}} $$

The peak inductor current is equal to the average output current plus one half of the peak-to-peak inductor current ripple.

EQUATION 5-9:

$$ I _ {L P K (\quad)} I _ {\overline {{{O}}} U T M A X (\quad)} 0, \Delta k _ {L (P P)} $$

The saturation current rating is given by:

EQUATION 5-10:

$$ I _ {L (S A T)} = \frac {(R _ {C L} \times I _ {C L}) - V _ {O F F S E T}}{R _ {D S (O N)}} $$

Where:

$$ R _ {C L} $$

Current-Limit Resistor

$$ I _ {C L} $$

Current-Limit Source Current

$$ V _ {\text { OFFSET }} $$

Current-Limit Comparator Offset

$$ R _ {D S (O N)} $$

On-Resistance of Low-Side Power MOSFET

The RMS inductor current is used to calculate the I^2R losses in the inductor.

EQUATION 5-11:

$$ I _ {L (R M S)} = \sqrt {I _ {O U T M A X (\quad^ {2} + \frac {\Delta I _ {L (P P)} ^ {2}}{1 2})}} $$

Maximizing efficiency requires the proper selection of core material and minimizing the winding resistance. The high-frequency operation of the MIC2125/6 requires the use of ferrite materials. Lower cost iron powder cores may be used, but the increase in core loss reduces the efficiency of the power supply. This is especially noticeable at low output power. The winding resistance decreases efficiency at the higher output current levels. The winding resistance must be minimized, although this usually comes at the expense of a larger inductor. The power dissipated in the inductor is equal to the sum of the core and copper losses. At higher output loads, the core losses are usually insignificant and can be ignored. At lower output currents, the core losses can be significant. Core loss information is usually available from the magnetics vendor.

The amount of copper loss in the inductor is calculated by Equation 5-12:

EQUATION 5-12:

$$ P _ {I N D U C T O R (C U)} = I _ {L (R M S)} ^ {2} \times R _ {W I N D I N G} $$

5.4 Output Capacitor Selection

The type of the output capacitor is usually determined by its equivalent series resistance (ESR). Voltage and RMS current capability are two other important factors for selecting the output capacitor. Recommended capacitor types are ceramic, tantalum, low-ESR aluminum electrolytic, OS-CON, and POSCAP. The output capacitor's ESR is usually the main cause of the output ripple. The output capacitor ESR also affects the control loop from a stability point of view. The maximum value of ESR is calculated by Equation 5-13.

EQUATION 5-13:

$$ E S R _ {C _ {O U T}} \leq \frac {\Delta V _ {O U T P P (})}{\Delta J _ {L P P (})} $$

Where:

$$ \begin{array}{l l} \Delta V _ {\text { OUT(PP) }} & \text { Peak - to - Peak Output Voltage Ripple } \ \Delta I _ {\text { L(PP) }} & \text { Peak - to - Peak Inductor Current Ripple } \end{array} $$

The required output capacitance is calculated in Equation 5-14.

EQUATION 5-14:

$$ C _ {O U T} = \frac {\Delta I _ {L P P (\quad)}}{\Delta V _ {\mathcal {G} U T P P (\quad)} ^ {f} \times_ {S W} 8 \times} $$

Where:

$$ \begin{array}{l l} \mathrm{C} _ {\text {OUT}} & \text {Output Capacitance Value} \ \mathrm{f} _ {\text {SW}} & \text {Switching Frequency} \end{array} $$

As described in the Theory of Operation subsection of the Functional Description, the MIC2125/26 requires at least 20 mV peak-to-peak ripple at the FB pin to ensure that the g_m amplifier and the comparator behave properly. Also, the output voltage ripple should be in phase with the inductor current. Therefore, the output voltage ripple caused by the output capacitors value should be much smaller than the ripple caused by the output capacitor ESR. If low-ESR capacitors, such as ceramic capacitors, are selected as the output capacitors, a ripple injection method should be applied to provide the enough feedback voltage ripple. Refer to the Ripple Injection subsection for details.

The voltage rating of the capacitor should be twice the output voltage for a tantalum and 20% greater for aluminum electrolytic or OS-CON. The output capacitor RMS current is calculated in Equation 5-15.

EQUATION 5-15:

$$ I _ {C _ {O U T R M S (}} = \frac {\Delta I _ {L P P}}{\sqrt {1 2}} (\quad) $$

The power dissipated in the output capacitor is:

EQUATION 5-16:

$$ P _ {D I S S C O U T} = I _ {\text { GOUT(RMS) }} ^ {2} \times E S R _ {C O U T} $$

5.5 Input Capacitor Selection

The input capacitor reduces peak current drawn from the power supply and reduces noise and voltage ripple on the input. The input voltage ripple depends on the input capacitance and ESR. The input capacitance and ESR values are calculated by using Equation 5-17 and Equation 5-18.

EQUATION 5-17:

$$ C _ {I N} = \frac {I _ {O U T} \times D \times (1 - D)}{\eta \times \Delta V _ {I N (C)} \times f _ {S W}} $$

Where:

$$ \begin{array}{c c} I _ {O U T} & \text { Load Current } \ \eta & \text { Power Conversion Efficiency } \ \Delta V _ {I N (C)} & \text { Input Ripple Due to Capacitance Value } \end{array} $$

EQUATION 5-18:

$$ E S R _ {C I N} = \frac {\Delta V _ {I N (E S R)}}{I _ {L (P K)}} $$

Where:

$$ \begin{array}{l l} \Delta V _ {I N (E S R)} & \text {Input Ripple Due to Capacitor ESR} \ & \text {Value} \ L _ {(P K)} & \text {Peak Inductor Current} \end{array} $$

The input capacitor should be qualified for ripple current rating and voltage rating. The RMS value of the input capacitor current is determined at the maximum output current. Assuming the peak-to-peak inductor current ripple is low:

EQUATION 5-19:

$$ I _ {C I N (R M S)} \approx I _ {O U T (M A X)} \times \sqrt {D \times (1 - D)} $$

The power dissipated in the input capacitor is:

EQUATION 5-20:

$$ P _ {D I S S (C I N)} = I _ {C I N (R M S)} ^ {2} \times E S R _ {C I N} $$

5.6 Output Voltage Setting

The MIC2125/26 requires two resistors to set the output voltage, as shown in Figure 5-3.

gm AMP - + VREF - FB R1 R2

FIGURE 5-3: Voltage-Divider Configuration.

The output voltage is determined by Equation 5-21:

EQUATION 5-21:

	V_OUT	V_FB × = (1 + 1R2)
Where:
V_FB	0.6V

A typical value of R1 can be in the range of 3 kΩ and 15 kΩ. If R1 is too large, it may allow noise to be introduced into the voltage feedback loop. If R1 is too small in value, it will decrease the efficiency of the power supply, especially at light loads. Once R1 is selected, R2 can be calculated using Equation 5-22.

EQUATION 5-22:

$$ R 2 = \frac {V _ {F B} R 1 \times}{V _ {O U T} - V _ {F B}} $$

5.7 Output Overvoltage Limit Setting

The output overvoltage limit should be typically 20% higher than the nominal output voltage. Set the OVP limit by connecting a resistor divider from the output to ground as shown in Figure 5-4.

+ - VREF OVP R1 R2

FIGURE 5-4: OVP Voltage-Divider Configuration.

Choose R2 in the range of 10 kΩ to 49.9 kΩ and calculate R1 using Equation 5-23.

EQUATION 5-23:

$$ R 1 R \geqslant \left[ \frac {V _ {O V P}}{0 . 6} - 1 \right] $$

5.8 Ripple Injection

The V_FB ripple required for proper operation of the MIC2125/6 g_m amplifier and comparator is 20 mV to 100 mV. However, the output voltage ripple is generally designed as 1% to 2% of the output voltage. For low output voltages, such as a 1V, the output voltage ripple is only 10 mV to 20 mV, and the feedback voltage ripple is less than 20 mV. If the feedback voltage ripple is so small that the g_m amplifier and comparator cannot sense it, then the MIC2125/6 loses control and the output voltage is not regulated. In order to have sufficient V_FB ripple, a ripple injection method should be applied for low output voltage ripple applications.

The applications are divided into three situations according to the amount of the feedback voltage ripple:

- Enough ripple at the feedback voltage due to the large ESR of the output capacitors (Figure 5-5). The converter is stable without any ripple injection.

MIC2125/26 SW L FB R1 COUT ESR R2

FIGURE 5-5: Enough Ripple at FB.

The feedback voltage ripple is:

EQUATION 5-24:

$$ \Delta V _ {F B P P (\quad)} \frac {R 2}{\bar {R} 1 R 2 +} \times E \delta R _ {C _ {O U T}} \quad \Delta \times_ {L P P (\quad)} $$

Where:

I_L(PP) Peak-to-Peak Value of the Inductor Current Ripple

- Inadequate ripple at the feedback voltage due to the small ESR of the output capacitors.

The output voltage ripple is fed into the FB pin through a feed-forward capacitor, C_ff in this situation, as shown in Figure 5-7. The typical C_ff value is between 1 nF and 100 nF.

MIC2125/26 SW L FB R1 Cff COUT R2 ESR

FIGURE 5-6: Inadequate Ripple at FB.

With the feed-forward capacitor, the feedback voltage ripple is very close to the output voltage ripple.

EQUATION 5-25:

$$ \Delta V _ {F B P P (\quad)} E \mathbf {S} R \quad \Delta k _ {L P P (\quad)} $$

- Virtually no ripple at the FB pin voltage due to the very low ESR of the output capacitors.

Therefore, additional ripple is injected into the FB pin from the switching node SW via a resistor R_INJ and a capacitor C_INJ , as shown in Figure 5-7.

MIC2125/26 SW L C_INJ FB R_INJ R1 C_fH C_OUT ESR

FIGURE 5-7: Invisible Ripple at FB.

The process of sizing the ripple injection resistor and capacitors is as follows.

• S e I e_IN as 100 nF, which can be considered as short for a wide range of the frequencies.
• S e I e_ff to feeC all output ripples into the feedback pin. Typical choice of C_ff is 0.47 nF to 47 nF, if R1 and R2 are in the kΩ range. The C_ff value can be calculated using Equation 5-26:

EQUATION 5-26:

$$ C _ {f f} \gg \frac {1}{R _ {P}} \times \left(\frac {t _ {S} \times V _ {I N} \times D \times (1 - D)}{\left(V _ {I N} \times D \times (1 - D)\right) - \Delta V _ {F B P P (}}\right) $$

Where:

V_IN Power Stage Input Voltage

D Duty Cycle t_S 1/ f_SW R_P (R1//R2// R_IN ) F_B(PP) Feedback Rip

- S e l eINS according to Equation 5-27.

EQUATION 5-27:

$$ R _ {I N J} = \frac {1}{C _ {f f}} \times \left(\frac {V _ {I N} \times D \times (1 - D)}{\Delta V _ {F B P P} (\times f _ {S W})}\right) $$

6.0 PCB LAYOUT GUIDELINES

PCB layout is critical to achieve reliable, stable and efficient performance. The following guidelines should be followed to ensure proper operation of the MIC2125/26 converter.

6.1 IC

• The ceramic bypass capacitors which are connected to the V_DD and P_VDD pins must be located right at the IC. Use wide traces to connect to the V_DD , P_VDD and A_GND , P_GND pins respectively.
• The signal ground pin (A_GND) must be connected directly to the ground planes.
• Place the IC close to the point-of-load (POL).
• Signal and power grounds should be kept separate and connected at only one location.

6.2 Input Capacitor

• Place the input ceramic capacitors as close as possible to the MOSFETs.
• Place several vias to the ground plane close to the input capacitor ground terminal.

6.3 Inductor

• Keep the inductor connection to the switch node (SW) short.
• Do not route any digital lines underneath or close to the inductor.
• Keep the switch node (SW) away from the feedback (FB) pin.
• The SW pin should be connected directly to the drain of the low-side MOSFET to accurately sense the voltage across the low-side MOSFET.

6.4 Output Capacitor

• Use a copper plane to connect the output capacitor ground terminal to the input capacitor ground terminal.
• The feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. Sensing a long high-current load trace can degrade the DC load regulation.

6.5 MOSFETs

• MOSFET gate drive traces must be short. The ground plane should be the connection between the MOSFET source and P_GND .
• Choose a low-side MOSFET with a high C_GS/C_GD ratio and a low internal gate resistance to minimize the effect of d_v/d_t inducted turn-on.
• Use a 4.5V V _GS rated MOSFET. Its higher gate threshold voltage is more immune to glitches than a 2.5V or 3.3V rated MOSFET.

For more information about the Evaluation board layout, please contact Microchip sales.

7.0 PACKAGING INFORMATION

16-Lead QFN 3 mm x 3 mm Package Outline and Recommended Land Pattern

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

TITLE

16 LEAD QFN 3x3mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN

DRAWING # QFN33-16LD-PL-1 UNIT MM

PIN 1 DOT BY MARKING 3.0000±0.050 1 2 3.0000±0.050

TOP VIEW NOTE 1, 2, 3

1.5500±0.050 Exp.DAP PIN #1 IDENTIFICATION CHAMFER 0.300 X 45° 0.5000 BSC 0.2300±0.050 1.5500±0.050 Exp.DAP 1.5000 Ref.

BOTTOM VIEW NOTE 1, 2, 3

0.850±0.050 0.000-0.050 0.2030±0.025

SIDE VIEW NOTE: 1, 2, 3

NOTE:

1. MAX PACKAGE WARPAGE IS 0.05 MM
2. MAX ALLOWABLE BURR [S 0.076 MM IN ALL DIRECTIONS
3. PIN #1 IS ON TOP WILL BE LASER MARKED
4. RED CIRCLE IN LAND PATTERN INDICATE THERMAL VIA. SIZE SHOULD BE 0.30-0.35 MM
   IN DIAMETER AND SHOULD BE CONNECTED TO GND FOR MAX THERMAL PERFORMANCE
5. GREEN RECTANGLES (SHADED AREA) indicate SOLDER STENCIL OPENING ON EXPOSED
   PAD AREA. SIZE SHOULD BE 0.60×0.60 MM IN SIZE, 0.20 MM SPACING.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

POD-Land Pattern drawing # QFN33-16LD-PL-1

RECOMMENDED LAND PATTERN NOTE: 4, 5

Geometric diagram with green hatched squares arranged around a central square, no text or symbols present

STACKED-UP

0.48±0.02 0.80±0.02 0.23±0.02 1.60±0.02 2.24±0.02 3.20±0.02 0.50 BSC 1.60±0.02 2.24±0.02 3.20±0.02

EXPOSED METAL TRACE

0.70±0.02 0.40±0.02 0.10±0.02 0.23±0.02 1.40±0.02 2.24±0.02 3.04±0.02 2.24±0.02 3.04±0.02

Revision A (November 2015)

• Original Conversion of this Document.

Revision B (December 2015)

- Corrected the erroneous listing of the MIC2126 example with a 64LD package. Replaced with correct 16LD package information.

NOTES:

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Device: MIC2125: 28V, Synchronous Buck Controller featuring Adaptive On-Time Control with HyperLight Load MIC2126: 28V, Synchronous Buck Controller featuring Adaptive On-Time Control with HyperSpeed Control

Temperature: Y = -40^ to +125^

Package: ML = 16-Pin 3 mm x 3 mm QFN

Examples:

a) MIC2125YML: 28V, Synchronous Buck

Controller featuring Adaptive On-Time Control with HyperLight Load, -40°C to +125°C junction temperature range, 16LD QFN

b) MIC2126YML: 28V, Synchronous Buck Controller featuring Adaptive On-Time Control with Hyper Speed Control, -40°C to +125°C junction temperature range, 16LD QFN

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

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